[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-12 Thread Freddy, Ye via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3fc1fe8db830: [X86] Support -march=rocketlake (authored by 
FreddyYe).

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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -653,8 +653,7 @@
   list SKLAdditionalFeatures = [FeatureAES,
   FeatureXSAVEC,
   FeatureXSAVES,
-  FeatureCLFLUSHOPT,
-  FeatureSGX];
+  FeatureCLFLUSHOPT];
   list SKLTuning = [FeatureHasFastGather,
   FeatureMacroFusion,
   FeatureSlow3OpsLEA,
@@ -754,7 +753,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureCLWB,
   FeatureMOVDIRI,
@@ -764,7 +763,7 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -846,8 +845,7 @@
 
   // Goldmont Plus
   list GLPAdditionalFeatures = [FeaturePTWRITE,
-  FeatureRDPID,
-  FeatureSGX];
+  FeatureRDPID];
   list GLPTuning = [FeatureUseGLMDivSqrtCosts,
   FeatureSlowTwoMemOps,
   FeatureSlowLEA,
@@ -1308,6 +1306,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
Index: llvm/lib/Support/X86TargetParser.cpp
===
--- llvm/lib/Support/X86TargetParser.cpp
+++ llvm/lib/Support/X86TargetParser.cpp
@@ -194,6 +194,7 @@
 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
 FeatureVAES | FeatureVPCLMULQDQ;
+constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
 constexpr FeatureBitset FeaturesICLServer =

[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-12 Thread Kan Shengchen via Phabricator via cfe-commits 
skan accepted this revision.
skan added inline comments.



Comment at: llvm/lib/Support/X86TargetParser.cpp:176
 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
 FeatureXSAVES | FeatureSGX;
 // SkylakeServer inherits all SkylakeClient features except SGX.

craig.topper wrote:
> skan wrote:
> > Shouldn't the FeatureSGX be removed here?
> That would change the frontend behavior which would require a wider 
> discussion. My suggestion was only to change the backend behavior since there 
> was nothing testable with llc anyway.
Okay, it makes sense to me.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-12 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Support/X86TargetParser.cpp:176
 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
 FeatureXSAVES | FeatureSGX;
 // SkylakeServer inherits all SkylakeClient features except SGX.

skan wrote:
> Shouldn't the FeatureSGX be removed here?
That would change the frontend behavior which would require a wider discussion. 
My suggestion was only to change the backend behavior since there was nothing 
testable with llc anyway.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-12 Thread Kan Shengchen via Phabricator via cfe-commits 
skan added inline comments.



Comment at: llvm/lib/Support/X86TargetParser.cpp:176
 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
 FeatureXSAVES | FeatureSGX;
 // SkylakeServer inherits all SkylakeClient features except SGX.

Shouldn't the FeatureSGX be removed here?



Comment at: llvm/lib/Support/X86TargetParser.cpp:180
 constexpr FeatureBitset FeaturesSkylakeServer =
 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |

Remove `~FeatureSGX` here?



Comment at: llvm/lib/Support/X86TargetParser.cpp:197
 FeatureVAES | FeatureVPCLMULQDQ;
+constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
 constexpr FeatureBitset FeaturesICLServer =

Remove `~FeatureSGX` here?


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-12 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-12 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added a comment.

Hi @MaskRay, @craig.topper, @skan, reviewers, I've addressed your comments. Any 
more concerns?


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 336738.
FreddyYe added a comment.

rebase


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -653,8 +653,7 @@
   list SKLAdditionalFeatures = [FeatureAES,
   FeatureXSAVEC,
   FeatureXSAVES,
-  FeatureCLFLUSHOPT,
-  FeatureSGX];
+  FeatureCLFLUSHOPT];
   list SKLTuning = [FeatureHasFastGather,
   FeatureMacroFusion,
   FeatureSlow3OpsLEA,
@@ -754,7 +753,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureCLWB,
   FeatureMOVDIRI,
@@ -764,7 +763,7 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -846,8 +845,7 @@
 
   // Goldmont Plus
   list GLPAdditionalFeatures = [FeaturePTWRITE,
-  FeatureRDPID,
-  FeatureSGX];
+  FeatureRDPID];
   list GLPTuning = [FeatureUseGLMDivSqrtCosts,
   FeatureSlowTwoMemOps,
   FeatureSlowLEA,
@@ -1308,6 +1306,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
Index: llvm/lib/Support/X86TargetParser.cpp
===
--- llvm/lib/Support/X86TargetParser.cpp
+++ llvm/lib/Support/X86TargetParser.cpp
@@ -194,6 +194,7 @@
 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
 FeatureVAES | FeatureVPCLMULQDQ;
+constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
 constexpr FeatureBitset FeaturesICLServer =
 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
 constexpr FeatureBitset FeaturesTigerlake =
@@ -356,6 +357,8 @@
   {

[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added a comment.

In D100085#2682080 , @craig.topper 
wrote:

> Thanks. I also found this 
> https://github.com/gcc-mirror/gcc/commit/c422e5f81f42a0fc197f0715f4fcd81f1be90bff
>can you create a new patch to do the same for llvm/clang and rebase this 
> patch on top of it.

OK, I'll create it.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added a comment.

Thanks. I also found this 
https://github.com/gcc-mirror/gcc/commit/c422e5f81f42a0fc197f0715f4fcd81f1be90bff
   can you create a new patch to do the same for llvm/clang and rebase this 
patch on top of it.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:742
   FeatureGFNI,
   FeatureCLWB,
   FeatureRDPID,

craig.topper wrote:
> FreddyYe wrote:
> > craig.topper wrote:
> > > FreddyYe wrote:
> > > > craig.topper wrote:
> > > > > I'm not sure that rocketlake has CLWB. Can you double check that? 
> > > > > It's not listed in the cpuinfo dump on the 11700K that I found with a 
> > > > > google search here 
> > > > > https://www.pugetsystems.com/labs/hpc/Intel-Rocket-Lake-Compute-Performance-Results-HPL-HPCG-NAMD-and-Numpy-2116/
> > > > For now I have only an icelake-client machine and found that CLWB is 
> > > > not there, too. Guess I can do that modification in this patch? 
> > > > Rocketlake may probably lose CLWB. I'll double check.
> > > What’s the model number for you ice lake client CPU?
> > It is 0x7e. And I've double checked that rkl also hasn't CLWB.
> Sorry I meant the marketing name like "Intel® Core™ i7-1065G7"
It is `Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz`


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:742
   FeatureGFNI,
   FeatureCLWB,
   FeatureRDPID,

FreddyYe wrote:
> craig.topper wrote:
> > FreddyYe wrote:
> > > craig.topper wrote:
> > > > I'm not sure that rocketlake has CLWB. Can you double check that? It's 
> > > > not listed in the cpuinfo dump on the 11700K that I found with a google 
> > > > search here 
> > > > https://www.pugetsystems.com/labs/hpc/Intel-Rocket-Lake-Compute-Performance-Results-HPL-HPCG-NAMD-and-Numpy-2116/
> > > For now I have only an icelake-client machine and found that CLWB is not 
> > > there, too. Guess I can do that modification in this patch? Rocketlake 
> > > may probably lose CLWB. I'll double check.
> > What’s the model number for you ice lake client CPU?
> It is 0x7e. And I've double checked that rkl also hasn't CLWB.
Sorry I meant the marketing name like "Intel® Core™ i7-1065G7"


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:742
   FeatureGFNI,
   FeatureCLWB,
   FeatureRDPID,

craig.topper wrote:
> FreddyYe wrote:
> > craig.topper wrote:
> > > I'm not sure that rocketlake has CLWB. Can you double check that? It's 
> > > not listed in the cpuinfo dump on the 11700K that I found with a google 
> > > search here 
> > > https://www.pugetsystems.com/labs/hpc/Intel-Rocket-Lake-Compute-Performance-Results-HPL-HPCG-NAMD-and-Numpy-2116/
> > For now I have only an icelake-client machine and found that CLWB is not 
> > there, too. Guess I can do that modification in this patch? Rocketlake may 
> > probably lose CLWB. I'll double check.
> What’s the model number for you ice lake client CPU?
It is 0x7e. And I've double checked that rkl also hasn't CLWB.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:742
   FeatureGFNI,
   FeatureCLWB,
   FeatureRDPID,

FreddyYe wrote:
> craig.topper wrote:
> > I'm not sure that rocketlake has CLWB. Can you double check that? It's not 
> > listed in the cpuinfo dump on the 11700K that I found with a google search 
> > here 
> > https://www.pugetsystems.com/labs/hpc/Intel-Rocket-Lake-Compute-Performance-Results-HPL-HPCG-NAMD-and-Numpy-2116/
> For now I have only an icelake-client machine and found that CLWB is not 
> there, too. Guess I can do that modification in this patch? Rocketlake may 
> probably lose CLWB. I'll double check.
What’s the model number for you ice lake client CPU?


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-11 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:742
   FeatureGFNI,
   FeatureCLWB,
   FeatureRDPID,

craig.topper wrote:
> I'm not sure that rocketlake has CLWB. Can you double check that? It's not 
> listed in the cpuinfo dump on the 11700K that I found with a google search 
> here 
> https://www.pugetsystems.com/labs/hpc/Intel-Rocket-Lake-Compute-Performance-Results-HPL-HPCG-NAMD-and-Numpy-2116/
For now I have only an icelake-client machine and found that CLWB is not there, 
too. Guess I can do that modification in this patch? Rocketlake may probably 
lose CLWB. I'll double check.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-09 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:742
   FeatureGFNI,
   FeatureCLWB,
   FeatureRDPID,

I'm not sure that rocketlake has CLWB. Can you double check that? It's not 
listed in the cpuinfo dump on the 11700K that I found with a google search here 
https://www.pugetsystems.com/labs/hpc/Intel-Rocket-Lake-Compute-Performance-Results-HPL-HPCG-NAMD-and-Numpy-2116/


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added a comment.

Hi @craig.topper and @skan , THX for review! I tested that deleting sgx indeed 
leads to not generating "+sgx" in 'target-features', didn't know before:)

  '+sgx' is not a recognized feature for this target (ignoring feature)  


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 336303.
FreddyYe added a comment.

revert clang-format and revert deleting FeatureSGX def.


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -653,8 +653,7 @@
   list SKLAdditionalFeatures = [FeatureAES,
   FeatureXSAVEC,
   FeatureXSAVES,
-  FeatureCLFLUSHOPT,
-  FeatureSGX];
+  FeatureCLFLUSHOPT];
   list SKLTuning = [FeatureHasFastGather,
   FeatureMacroFusion,
   FeatureSlow3OpsLEA,
@@ -754,7 +753,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureMOVDIRI,
   FeatureMOVDIR64B,
@@ -763,7 +762,7 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -845,8 +844,7 @@
 
   // Goldmont Plus
   list GLPAdditionalFeatures = [FeaturePTWRITE,
-  FeatureRDPID,
-  FeatureSGX];
+  FeatureRDPID];
   list GLPTuning = [FeatureUseGLMDivSqrtCosts,
   FeatureSlowTwoMemOps,
   FeatureSlowLEA,
@@ -1307,6 +1305,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
Index: llvm/lib/Support/X86TargetParser.cpp
===
--- llvm/lib/Support/X86TargetParser.cpp
+++ llvm/lib/Support/X86TargetParser.cpp
@@ -194,6 +194,7 @@
 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
+constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
 constexpr FeatureBitset FeaturesICLServer =
 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
 constexpr FeatureBitset

[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 336301.
FreddyYe added a comment.

cancel the clang-format in constexpr ProcInfo Processors[] = {}


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -268,8 +268,6 @@
  "Pad short functions">;
 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
   "Invalidate Process-Context Identifier">;
-def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
-  "Enable Software Guard Extensions">;
 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
   "Flush A Cache Line Optimized">;
 def FeatureCLWB: SubtargetFeature<"clwb", "HasCLWB", "true",
@@ -653,8 +651,7 @@
   list SKLAdditionalFeatures = [FeatureAES,
   FeatureXSAVEC,
   FeatureXSAVES,
-  FeatureCLFLUSHOPT,
-  FeatureSGX];
+  FeatureCLFLUSHOPT];
   list SKLTuning = [FeatureHasFastGather,
   FeatureMacroFusion,
   FeatureSlow3OpsLEA,
@@ -754,7 +751,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureMOVDIRI,
   FeatureMOVDIR64B,
@@ -763,7 +760,7 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -845,8 +842,7 @@
 
   // Goldmont Plus
   list GLPAdditionalFeatures = [FeaturePTWRITE,
-  FeatureRDPID,
-  FeatureSGX];
+  FeatureRDPID];
   list GLPTuning = [FeatureUseGLMDivSqrtCosts,
   FeatureSlowTwoMemOps,
   FeatureSlowLEA,
@@ -1307,6 +1303,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
Index:

[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:271-273
-def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
-  "Enable Software Guard Extensions">;
 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",

skan wrote:
> craig.topper wrote:
> > Clang still puts it in target-features attribute so you can’t delete this 
> > or you’ll get a warning that the feature doesn’t exist.
> If you delete the definition of FeatureSGX, you need to remove the related 
> code in X86Subtarget.h too.  BTW, I don't think "there are no IR intrinsics 
> for a feature" is a good reason to remove a feature.
I only said to remove it from the CPUs because for  llc -march=skylake it 
doesn’t matter if we enable SGX because there’s nothing you can test from llc.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Kan Shengchen via Phabricator via cfe-commits 
skan added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:271-273
-def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
-  "Enable Software Guard Extensions">;
 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",

craig.topper wrote:
> Clang still puts it in target-features attribute so you can’t delete this or 
> you’ll get a warning that the feature doesn’t exist.
If you delete the definition of FeatureSGX, you need to remove the related code 
in X86Subtarget.h too.  BTW, I don't think "there are no IR intrinsics for a 
feature" is a good reason to remove a feature.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:271
   "Invalidate Process-Context Identifier">;
-def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
-  "Enable Software Guard Extensions">;

Clang still puts it in target-features attribute so you can’t delete this or 
you’ll get a warning that the feature doesn’t exist.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Kan Shengchen via Phabricator via cfe-commits 
skan added inline comments.



Comment at: llvm/lib/Support/X86TargetParser.cpp:293-301
+// Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
+{{""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B},
+// i386-generation processors.
+{{"i386"}, CK_i386, ~0U, FeatureX87},
+// i486-generation processors.
+{{"i486"}, CK_i486, ~0U, FeatureX87},
+{{"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX},

It's not correct to format here in this patch and do not mix tab with space.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 336295.
FreddyYe added a comment.

delete FeatureSGX in the backend since there are no IR intrinsics for SGX.


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -268,8 +268,6 @@
  "Pad short functions">;
 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
   "Invalidate Process-Context Identifier">;
-def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
-  "Enable Software Guard Extensions">;
 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
   "Flush A Cache Line Optimized">;
 def FeatureCLWB: SubtargetFeature<"clwb", "HasCLWB", "true",
@@ -653,8 +651,7 @@
   list SKLAdditionalFeatures = [FeatureAES,
   FeatureXSAVEC,
   FeatureXSAVES,
-  FeatureCLFLUSHOPT,
-  FeatureSGX];
+  FeatureCLFLUSHOPT];
   list SKLTuning = [FeatureHasFastGather,
   FeatureMacroFusion,
   FeatureSlow3OpsLEA,
@@ -754,7 +751,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureMOVDIRI,
   FeatureMOVDIR64B,
@@ -763,7 +760,7 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -845,8 +842,7 @@
 
   // Goldmont Plus
   list GLPAdditionalFeatures = [FeaturePTWRITE,
-  FeatureRDPID,
-  FeatureSGX];
+  FeatureRDPID];
   list GLPTuning = [FeatureUseGLMDivSqrtCosts,
   FeatureSlowTwoMemOps,
   FeatureSlowLEA,
@@ -1307,6 +1303,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
Index:

[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:767
+  // Rocketlake
+  list RKLAdditionalFeatures = [FeatureAES,
+  FeatureXSAVEC,

craig.topper wrote:
> FreddyYe wrote:
> > craig.topper wrote:
> > > Is this list this long because SKL includes SGX but RKL doesn't?
> > Yes. And I don't know any simple ways to exclude SGX here, any suggestions?
> Nothing pretty. Guess it depends on if SGX is going to not appear in more 
> future CPUs or if this is a one off case. If it's going to continue then we 
> could remove it from the inheritance and just give it to SKL, ICL, CNL, etc. 
> individually.
> 
> Or we could just not default SGX on for any CPU. It's probably not all that 
> useful in the backend anyway. Clang will put it in the target-feature 
> attribute anyway. Having it in the backend feature lists doesn't really do 
> anything since I don't think we have any IR intrinsics for SGX.
Agree. Like we did in https://reviews.llvm.org/D88006. SGX is also not useful 
in the backend.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:790
+  FeatureFSRM];
+  list RKLTuning = ICLTuning;
+  list RKLFeatures =

RKSimon wrote:
> Using ICLTuning suggests we should still be avoiding 512-bit ops 
> (FeaturePrefer256Bit) - is this still true for RKL (or anything past CNL...)?
> 
> I posted PR48336 but never got any response, but from what others have 
> reported (Travis Downs, Phoronix etc) its mainly a power issue these days, 
> not a perf issue due to big freq drops.
We need more tests on such as SPEC to see whether we can default enable 
FeaturePrefer512bit.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:767
+  // Rocketlake
+  list RKLAdditionalFeatures = [FeatureAES,
+  FeatureXSAVEC,

FreddyYe wrote:
> craig.topper wrote:
> > Is this list this long because SKL includes SGX but RKL doesn't?
> Yes. And I don't know any simple ways to exclude SGX here, any suggestions?
Nothing pretty. Guess it depends on if SGX is going to not appear in more 
future CPUs or if this is a one off case. If it's going to continue then we 
could remove it from the inheritance and just give it to SKL, ICL, CNL, etc. 
individually.

Or we could just not default SGX on for any CPU. It's probably not all that 
useful in the backend anyway. Clang will put it in the target-feature attribute 
anyway. Having it in the backend feature lists doesn't really do anything since 
I don't think we have any IR intrinsics for SGX.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added a comment.

Hi @MaskRay , I tried to refactor the test file by assembling the common 
CHECKs. But I found it will lead to too many check-prefixes ine one RUN line. 
For example,

  // RUN: %clang -march=c3 -m32 -E -dM %s -o - 2>&1 \
  // RUN: -target i386-unknown-linux \
  // RUN:   | FileCheck -match-full-lines %s 
-check-prefixes=CHECK_I386_M32C,CHECK_I486_M32C,CHECK_I486_M32S,CHECK_PENTIUM_MMX_M32S,CHECK_WINCHIP2_M32S
  
  // CHECK_WINCHIP2_M32S: #define __3dNOW__ 1
  // CHECK_PENTIUM_MMX_M32S:#define __MMX__ 1
  // CHECK_WINCHIP_C6_M32S: #define __MMX__ 1
  // CHECK_I386_M32C: #define __i386 1
  // CHECK_I386_M32C: #define __i386__ 1
  // CHECK_I486_M32C: #define __i486 1
  // CHECK_I486_M32C: #define __i486__ 1
  // CHECK_I586_M32C: #define __i586 1
  // CHECK_I586_M32C: #define __i586__ 1
  // CHECK_I586_M32C: #define __pentium 1
  // CHECK_I586_M32C: #define __pentium__ 1
  // CHECK_PENTIUM_MMX_M32S:  #define __pentium_mmx__ 1
  // CHECK_I386_M32S: #define __tune_i386__ 1
  // CHECK_I486_M32S: #define __tune_i486__ 1
  // CHECK_PENTIUM_MMX_M32S:  #define __tune_pentium_mmx__ 1
  // CHECK_I386_M32C: #define i386 1

And that CPU is still a very old CPU. It is easy to imagine how long for 
example skylake's RUN line is. Generally speaking, X86's ISA evolution between 
different chips is not very clear. So this refactoring work is beyond my ETA. I 
uploaded a new version to reuse the most similar CHECKS. Does that look good to 
you?


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 336133.
FreddyYe added a comment.
Herald added a subscriber: jfb.

update lit test and clang-format


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -754,7 +754,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureMOVDIRI,
   FeatureMOVDIR64B,
@@ -763,7 +763,35 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Rocketlake
+  list RKLAdditionalFeatures = [FeatureAES,
+  FeatureXSAVEC,
+  FeatureXSAVES,
+  FeatureCLFLUSHOPT,
+  FeatureAVX512,
+  FeatureCDI,
+  FeatureDQI,
+  FeatureBWI,
+  FeatureVLX,
+  FeaturePKU,
+  FeatureVBMI,
+  FeatureIFMA,
+  FeatureSHA,
+  FeatureBITALG,
+  FeatureVAES,
+  FeatureVBMI2,
+  FeatureVNNI,
+  FeatureVPCLMULQDQ,
+  FeatureVPOPCNTDQ,
+  FeatureGFNI,
+  FeatureCLWB,
+  FeatureRDPID,
+  FeatureFSRM];
+  list RKLTuning = ICLTuning;
+  list RKLFeatures =
+!listconcat(BDWFeatures, RKLAdditionalFeatures);
+
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -1307,6 +1335,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.RKLFeatures, ProcessorFeatures.RKLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
Index:

[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Simon Pilgrim via Phabricator via cfe-commits 
RKSimon added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:790
+  FeatureFSRM];
+  list RKLTuning = ICLTuning;
+  list RKLFeatures =

Using ICLTuning suggests we should still be avoiding 512-bit ops 
(FeaturePrefer256Bit) - is this still true for RKL (or anything past CNL...)?

I posted PR48336 but never got any response, but from what others have reported 
(Travis Downs, Phoronix etc) its mainly a power issue these days, not a perf 
issue due to big freq drops.


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added a comment.

In D100085#2675965 , @MaskRay wrote:

> In D100085#2675919 , @FreddyYe 
> wrote:
>
>> Hi @MaskRay, I tried to refactor, but met some difficulties. Since these 
>> defines are dictionary ordered, a new #define may insert into a common 
>> CHECK. So it is difficult to let different RUN share common CHECKs.
>
> Check prefixes of the same kind do not need to be contiguous.
>
>   // A:
>   // B:
>   // A:

I see. And It works. And I'll update. And thank you!


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay added a comment.

In D100085#2675919 , @FreddyYe wrote:

> Hi @MaskRay, I tried to refactor, but met some difficulties. Since these 
> defines are dictionary ordered, a new #define may insert into a common CHECK. 
> So it is difficult to let different RUN share common CHECKs.

Check prefixes of the same kind do not need to be contiguous.

  // A:
  // B:
  // A:


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added a comment.

Hi @MaskRay, I tried to refactor, but met some difficulties. Since these 
defines are dictionary ordered, a new #define may insert into a common CHECK. 
So it is difficult to let different RUN share common CHECKs.

  // RUN: %clang -march=pentium-mmx -m32 -E -dM %s -o - 2>&1 \
  // RUN: -target i386-unknown-linux \
  // RUN:   | FileCheck -match-full-lines %s 
-check-prefixes=CHECK_I386_M32,CHECK_I586_M32,CHECK_PENTIUM_MMX_M32
  
  // CHECK_I386_M32: #define __i386 1
  // CHECK_I386_M32: #define __i386__ 1
  // CHECK_I386_M32: #define i386 1
  
  // CHECK_I586_M32: #define __i586 1
  // CHECK_I586_M32: #define __i586__ 1
  // CHECK_I586_M32: #define __pentium 1
  // CHECK_I586_M32: #define __pentium__ 1
  // CHECK_I586_M32: #define __tune_i586__ 1
  // CHECK_I586_M32: #define __tune_pentium__ 1
  
  // CHECK_PENTIUM_MMX_M32: #define __MMX__ 1
  // CHECK_PENTIUM_MMX_M32: #define __pentium_mmx__ 1
  // CHECK_PENTIUM_MMX_M32: #define __tune_pentium_mmx__ 1

The example above will destroy the original order of the define list. Do you 
have some good suggestions?


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-08 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 336007.
FreddyYe added a comment.

Updating according to comments. Test refactoring not done.


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -754,7 +754,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureMOVDIRI,
   FeatureMOVDIR64B,
@@ -763,7 +763,35 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Rocketlake
+  list RKLAdditionalFeatures = [FeatureAES,
+  FeatureXSAVEC,
+  FeatureXSAVES,
+  FeatureCLFLUSHOPT,
+  FeatureAVX512,
+  FeatureCDI,
+  FeatureDQI,
+  FeatureBWI,
+  FeatureVLX,
+  FeaturePKU,
+  FeatureVBMI,
+  FeatureIFMA,
+  FeatureSHA,
+  FeatureBITALG,
+  FeatureVAES,
+  FeatureVBMI2,
+  FeatureVNNI,
+  FeatureVPCLMULQDQ,
+  FeatureVPOPCNTDQ,
+  FeatureGFNI,
+  FeatureCLWB,
+  FeatureRDPID,
+  FeatureFSRM];
+  list RKLTuning = ICLTuning;
+  list RKLFeatures =
+!listconcat(BDWFeatures, RKLAdditionalFeatures);
+
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -1307,6 +1335,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.RKLFeatures, ProcessorFeatures.RKLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
Index:

[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-07 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added a comment.

THX for review!




Comment at: clang/test/Preprocessor/predefined-arch-macros.c:1396
 
+// RUN: %clang -march=rocketlake -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \

MaskRay wrote:
> The file may need some refactoring first. You can let RUN lines share some 
> common check prefixes, instead of adding a bunch of defines for every new 
> processor.
> 
> ```
> // CHECK_X86_64_V2: ...
> // CHECK_X86_64_V2: ...
> // CHECK_X86_64_V3: ...
> // CHECK_PROCESSOR1_M32:
> // CHECK_PROCESSOR1_M64:
> // CHECK_PROCESSOR2_M32:
> // CHECK_PROCESSOR2_M64:
> ```
I agree. I'll do it



Comment at: compiler-rt/lib/builtins/cpu_model.c:101
   INTEL_COREI7_ALDERLAKE,
+  INTEL_COREI7_ROCKETLAKE,
   AMDFAM19H_ZNVER3,

craig.topper wrote:
> This order is defined by libgcc. We can't insert in the middle unless ZNVER3 
> was in the wrong place
> 
> Why this not referenced in the switch the select subtype?
This is a mistake. I'll modify. And reference is missing in two switch. I'll 
add.



Comment at: llvm/lib/Target/X86/X86.td:767
+  // Rocketlake
+  list RKLAdditionalFeatures = [FeatureAES,
+  FeatureXSAVEC,

craig.topper wrote:
> Is this list this long because SKL includes SGX but RKL doesn't?
Yes. And I don't know any simple ways to exclude SGX here, any suggestions?


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-07 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: compiler-rt/lib/builtins/cpu_model.c:101
   INTEL_COREI7_ALDERLAKE,
+  INTEL_COREI7_ROCKETLAKE,
   AMDFAM19H_ZNVER3,

This order is defined by libgcc. We can't insert in the middle unless ZNVER3 
was in the wrong place

Why this not referenced in the switch the select subtype?



Comment at: llvm/lib/Target/X86/X86.td:767
+  // Rocketlake
+  list RKLAdditionalFeatures = [FeatureAES,
+  FeatureXSAVEC,

Is this list this long because SKL includes SGX but RKL doesn't?


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-07 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay added inline comments.



Comment at: clang/test/Preprocessor/predefined-arch-macros.c:1396
 
+// RUN: %clang -march=rocketlake -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \

The file may need some refactoring first. You can let RUN lines share some 
common check prefixes, instead of adding a bunch of defines for every new 
processor.

```
// CHECK_X86_64_V2: ...
// CHECK_X86_64_V2: ...
// CHECK_X86_64_V3: ...
// CHECK_PROCESSOR1_M32:
// CHECK_PROCESSOR1_M64:
// CHECK_PROCESSOR2_M32:
// CHECK_PROCESSOR2_M64:
```


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[PATCH] D100085: [X86] Support -march=rocketlake

2021-04-07 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe created this revision.
Herald added subscribers: dexonsmith, pengfei, hiraditya.
FreddyYe requested review of this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

Repository:
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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -754,7 +754,7 @@
   list ICXFeatures =
 !listconcat(ICLFeatures, ICXAdditionalFeatures);
 
-  //Tigerlake
+  // Tigerlake
   list TGLAdditionalFeatures = [FeatureVP2INTERSECT,
   FeatureMOVDIRI,
   FeatureMOVDIR64B,
@@ -763,7 +763,35 @@
   list TGLFeatures =
 !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
-  //Sapphirerapids
+  // Rocketlake
+  list RKLAdditionalFeatures = [FeatureAES,
+  FeatureXSAVEC,
+  FeatureXSAVES,
+  FeatureCLFLUSHOPT,
+  FeatureAVX512,
+  FeatureCDI,
+  FeatureDQI,
+  FeatureBWI,
+  FeatureVLX,
+  FeaturePKU,
+  FeatureVBMI,
+  FeatureIFMA,
+  FeatureSHA,
+  FeatureBITALG,
+  FeatureVAES,
+  FeatureVBMI2,
+  FeatureVNNI,
+  FeatureVPCLMULQDQ,
+  FeatureVPOPCNTDQ,
+  FeatureGFNI,
+  FeatureCLWB,
+  FeatureRDPID,
+  FeatureFSRM];
+  list RKLTuning = ICLTuning;
+  list RKLFeatures =
+!listconcat(BDWFeatures, RKLAdditionalFeatures);
+
+  // Sapphirerapids
   list SPRAdditionalFeatures = [FeatureAMXTILE,
   FeatureAMXINT8,
   FeatureAMXBF16,
@@ -1307,6 +1335,8 @@
 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ProcessorFeatures.RKLFeatures, ProcessorFeatures.RKLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake",