[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6101d720cb49: [RISCV] Relax rules for ordering s/z/x 
prefixed extensions in ISA naming strings (authored by asb).

Changed prior to commit:
  https://reviews.llvm.org/D149246?vs=517106=534930#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-arch.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -811,9 +811,9 @@
   // Parse the ISA string containing non-standard user-level
   // extensions, standard supervisor-level extensions and
   // non-standard supervisor-level extensions.
-  // These extensions start with 'z', 's', 'x' prefixes, follow a
-  // canonical order, might have a version number (major, minor)
-  // and are separated by a single underscore '_'.
+  // These extensions start with 'z', 's', 'x' prefixes, might have a version
+  // number (major, minor) and are separated by a single underscore '_'. We do
+  // not enforce a canonical order for them.
   // Set the hardware features for the extensions that are supported.
 
   // Multi-letter extensions are seperated by a single underscore
@@ -822,9 +822,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -844,18 +841,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -40,6 +40,8 @@
   users migrate build systems so as not to rely on this.
 * Allowing CSRs to be named without gating on specific extensions.  This
   applies to all CSR names, not just those in zicsr, zicntr, and zihpm.
+* The ordering of ``z*``, ``s*``, and ``x*`` prefixed extension names is not
+  enforced in user-specified ISA naming strings (e.g. ``-march``).
 
 We are actively deciding not to support multiple specification revisions
 at this time. We acknowledge a likely future need, but actively defer the
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -323,8 +323,7 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
 // RV32-X-ORDER: error: invalid arch name 'rv32ixdef_sabc',
-// RV32-X-ORDER: standard supervisor-level extension not given
-// RV32-X-ORDER: in canonical order 'sabc'
+// RV32-X-ORDER  

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.
Herald added a subscriber: wangpc.

All feedback so far has been positive and this has two LGTMs, but I also 
recognise this patch has been left for a while. Heads up that I intend to 
commit this towards the end of the working day Monday UK time unless anyone has 
any objections / concerns.


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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.

I am really happy to see this happen, binutils has relaxed for a while in more 
relaxed way[1] - only require must start with `rv[32|64][e|i|g]`, personally I 
would like to relax the order at all like binutils did for GCC, but I don't 
want to disturb that before making sure clang will going same way - otherwise 
just making more incomparable.

The order is kind of not friendly for user, I don't believe how many people 
remember the right order between `z*` extension in short time - even after read 
the RISC-V ISA spec.

[1] https://sourceware.org/pipermail/binutils/2022-December/125267.html


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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Conor Dooley via Phabricator via cfe-commits]

ConchuOD added a comment.

Perhaps redundant now that Palmer has commented, an opinion was solicited from 
me so here I am, pretty much copy-pasting from elsewhere:

IMO, alignment with gcc is helpful, permissiveness is better.
Given "canonical order" can, and has, change(d) in the past I think it's good 
to insulate against it happening again.
Conjuring up march is bad enough as things stand w/ availability with given 
toolchain versions, especially in situations where different toolchain 
components are mixed between various versions llvm and gnu stuff. 
Having to do special handing of different versions of gcc/clang whenever we do 
actually need to add Sfoo or Xfoo sounds like another layer of misery I would 
love to avoid.
Although it looks like we'll probably have to do some Makefile dance around 
older gcc/clang versions but at least going forward it'd be the same.


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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Palmer Dabbelt via Phabricator via cfe-commits]

palmer-dabbelt added a comment.

IDK about the specifics here, but I think in general being more permissive on 
ISA string parsing is the way to go.  The rules have changed so many times it's 
not really viable to follow them, so we're sort of just stuck with a bunch of 
historally-driven implementation-specific behavior.

I've got a TODO floating around somewhere to document what GCC accepts, but 
it's super clunky and I get tired every time I try and look...


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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

I generally think this is a good idea.  I'd ask you add this to RISCVUsage 
under "The current known variances from the specification are", and mention it 
at the next sync up call, but otherwise, I think we should proceed with this.

LGTM once the above are done.


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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 517106.
asb added a comment.

Add missing doc comment update.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -756,9 +756,9 @@
   // Parse the ISA string containing non-standard user-level
   // extensions, standard supervisor-level extensions and
   // non-standard supervisor-level extensions.
-  // These extensions start with 'z', 's', 'x' prefixes, follow a
-  // canonical order, might have a version number (major, minor)
-  // and are separated by a single underscore '_'.
+  // These extensions start with 'z', 's', 'x' prefixes, might have a version
+  // number (major, minor) and are separated by a single underscore '_'. We do
+  // not enforce a canonical order for them.
   // Set the hardware features for the extensions that are supported.
 
   // Multi-letter extensions are seperated by a single underscore
@@ -767,9 +767,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -789,18 +786,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -333,8 +333,7 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
 // RV32-X-ORDER: error: invalid arch name 'rv32ixdef_sabc',
-// RV32-X-ORDER: standard supervisor-level extension not given
-// RV32-X-ORDER: in canonical order 'sabc'
+// RV32-X-ORDER  unsupported non-standard user-level extension 'xdef'
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixabc_xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XDUP %s
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -422,6 +422,9 @@
 - Fixed incorrect ABI lowering of ``_Float16`` in the case of structs
   containing ``_Float16`` that are eligible for passing via GPR+FPR or
   FPR+FPR.
+- The rules for ordering of extensions in ``-march`` strings were relaxed. A
+  canonical ordering is no longer enforced on ``z*``, ``s*``, and ``x*``
+  prefixed extensions.
 
 CUDA/HIP Language Changes
 ^
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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 517105.

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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -767,9 +767,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -789,18 +786,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -333,8 +333,7 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
 // RV32-X-ORDER: error: invalid arch name 'rv32ixdef_sabc',
-// RV32-X-ORDER: standard supervisor-level extension not given
-// RV32-X-ORDER: in canonical order 'sabc'
+// RV32-X-ORDER  unsupported non-standard user-level extension 'xdef'
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixabc_xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XDUP %s
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -422,6 +422,9 @@
 - Fixed incorrect ABI lowering of ``_Float16`` in the case of structs
   containing ``_Float16`` that are eligible for passing via GPR+FPR or
   FPR+FPR.
+- The rules for ordering of extensions in ``-march`` strings were relaxed. A
+  canonical ordering is no longer enforced on ``z*``, ``s*``, and ``x*``
+  prefixed extensions.
 
 CUDA/HIP Language Changes
 ^


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* 

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
asb added reviewers: reames, kito-cheng, craig.topper, jrtc27, joshua-arch1.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, 
hiraditya, arichardson.
Herald added a project: All.
asb requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

This was discussed somewhat in D148315 . As 
it stands, we require in RISCVISAInfo::parseArchString (used for e.g. `-march` 
parsing in Clang) that extensions are given in the order of z, then s, then x 
prefixed extensions (after the standard single-letter extensions). However, we 
recently (in D148315 ) moved to that order 
from z/x/s as the canonical ordering was changed in the spec. In addition, 
recent GCC seems to require z* extensions before s*.

My recollection of the history here is that we thought keeping `-march` as 
close to the rules for ISA naming strings as possible would simplify things, as 
there's an existing spec to point to. My feeling is that now we've had 
incompatible changes, and an incompatibility with GCC there's no real benefit 
to sticking to this restriction, and it risks making it much more painful than 
it needs to be to copy a `-march=` string between GCC and Clang.

This patch actually removes all ordering restrictions so you can freely mix 
x/s/z extensions. Arguably this is more freedom than we want to allow, on the 
other hand it might be less hassle for build systems assembling their arch 
strings.

To be very explicit, this doesn't change our behaviour when emitting a 
canonically ordered extension string (e.g. in build attributes). We of course 
sort according to the canonical order (as we understand it) in that case.


Repository:
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Files:
  clang/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -767,9 +767,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -789,18 +786,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -422,6 +422,9 @@
 - Fixed incorrect ABI lowering of ``_Float16`` in the case of structs
   containing ``_Float16`` that are eligible for passing via GPR+FPR or
   FPR+FPR.
+- The