Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-26 Thread James Y Knight via cfe-commits 
jyknight added a comment.

ping again.


http://reviews.llvm.org/D17933



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Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-08 Thread James Y Knight via cfe-commits 
jyknight added a comment.

ping.


http://reviews.llvm.org/D17933



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Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-04 Thread James Y Knight via cfe-commits 
jyknight updated this revision to Diff 52587.
jyknight marked 2 inline comments as done.
jyknight added a comment.

review fixes


http://reviews.llvm.org/D17933

Files:
  lib/Basic/Targets.cpp
  lib/Frontend/InitPreprocessor.cpp
  test/CodeGen/atomic-ops.c
  test/CodeGen/ms-volatile.c
  test/CodeGenCXX/atomicinit.cpp
  test/OpenMP/atomic_capture_codegen.cpp
  test/OpenMP/atomic_read_codegen.c
  test/OpenMP/atomic_update_codegen.cpp
  test/OpenMP/atomic_write_codegen.c
  test/Preprocessor/arm-target-features.c
  test/Preprocessor/init.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/predefined-macros.c
  test/Preprocessor/x86_target_features.c
  test/Sema/atomic-ops.c

Index: test/Sema/atomic-ops.c
===
--- test/Sema/atomic-ops.c
+++ test/Sema/atomic-ops.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -target-cpu i686 -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
@@ -502,5 +502,3 @@
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_acq_rel, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_seq_cst, memory_order_relaxed);
 }
-
-
Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -291,8 +291,13 @@
 
 // NOTBM-NOT: #define __TBM__ 1
 
-// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s
+// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16-386 %s
 
+// MCX16-386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+
+// RUN: %clang -target x86_64-unknown-unknown -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s
+
+// MCX16: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
 
 // RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=PRFCHW %s
Index: test/Preprocessor/predefined-macros.c
===
--- test/Preprocessor/predefined-macros.c
+++ test/Preprocessor/predefined-macros.c
@@ -102,47 +102,117 @@
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i386 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I386
 // CHECK-SYNC_CAS_I386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP
+// CHECK-SYNC_CAS_I386-NOT: __GCC_ATOMIC_{{.*}}_LOCK_FREE 2
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i486 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I486
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 //
+
+// FIXME: The value of LLONG_LOCK_FREE on i586 is wrong: clang is
+// using the alignment of "long long" (only 32bit for a 64bit value)
+// to disqualify it from being lock free. But the semantics of this
+// define are supposed to tell you if "_Atomic long long" is lock free
+// -- and it is.
+
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i586 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I586
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+//

Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-04 Thread James Y Knight via cfe-commits 
jyknight added a comment.

Done and done.


http://reviews.llvm.org/D17933



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Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-04 Thread Daniel Sanders via cfe-commits 
dsanders added a subscriber: dsanders.


Comment at: test/Preprocessor/init.c:3295
@@ +3294,3 @@
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// MIPSN32BE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16

I've just noticed that we only check the '__GCC_*' macros for the 64-bit ABI's 
(N32/N64). I'm not sure why the 32-bit (O32) checks are missing.

The O32 cases are the same as N32 except that `__GCC_ATOMIC_LLONG_LOCK_FREE` is 
1 and `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8` is not defined.
Could you add:
  // MIPS32LE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
  // MIPS32LE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
  // MIPS32LE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
  // MIPS32LE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
  // MIPS32LE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
  // MIPS32LE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
  // MIPS32LE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
  // MIPS32LE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
  // MIPS32LE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
and the same for the MIPS32BE case?


http://reviews.llvm.org/D17933



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Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-03 Thread David Majnemer via cfe-commits 
majnemer added a subscriber: majnemer.


Comment at: lib/Basic/Targets.cpp:2565-2577
@@ -2569,1 +2564,15 @@
+
+  void setAtomic() {
+if (getTriple().getArch() == llvm::Triple::x86_64) {
+  if (HasCX16)
+MaxAtomicInlineWidth = 128;
+  else
+MaxAtomicInlineWidth = 64;
+} else if (CPU >= CK_i586)
+  MaxAtomicInlineWidth = 64;
+else if (CPU >= CK_i486)
+  MaxAtomicInlineWidth = 32;
+else
+  MaxAtomicInlineWidth = 0;
+  }
 };

Might be easier to read if we go from increasing strength:

```
void setAtomic() {
  MaxAtomicInlineWidth = 0;
  if (CPU >= CK_i486)
MaxAtomicInlineWidth = 32;
  if (CPU >= CK_i586)
MaxAtomicInlineWidth = 64;
  if (getTriple().getArch() == llvm::Triple::x86_64) {
MaxAtomicInlineWidth = 64;
if (HasCX16)
  MaxAtomicInlineWidth = 128;
  }
}
```

Either works for me.


http://reviews.llvm.org/D17933



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Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-01 Thread James Y Knight via cfe-commits 
jyknight updated this revision to Diff 52430.
jyknight added a comment.

Review tweaks.


http://reviews.llvm.org/D17933

Files:
  lib/Basic/Targets.cpp
  lib/Frontend/InitPreprocessor.cpp
  test/CodeGen/atomic-ops.c
  test/CodeGen/ms-volatile.c
  test/CodeGenCXX/atomicinit.cpp
  test/OpenMP/atomic_capture_codegen.cpp
  test/OpenMP/atomic_read_codegen.c
  test/OpenMP/atomic_update_codegen.cpp
  test/OpenMP/atomic_write_codegen.c
  test/Preprocessor/arm-target-features.c
  test/Preprocessor/init.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/predefined-macros.c
  test/Preprocessor/x86_target_features.c
  test/Sema/atomic-ops.c

Index: test/Sema/atomic-ops.c
===
--- test/Sema/atomic-ops.c
+++ test/Sema/atomic-ops.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -target-cpu i686 -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
@@ -502,5 +502,3 @@
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_acq_rel, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_seq_cst, memory_order_relaxed);
 }
-
-
Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -291,8 +291,13 @@
 
 // NOTBM-NOT: #define __TBM__ 1
 
-// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s
+// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16-386 %s
 
+// MCX16-386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+
+// RUN: %clang -target x86_64-unknown-unknown -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s
+
+// MCX16: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
 
 // RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=PRFCHW %s
Index: test/Preprocessor/predefined-macros.c
===
--- test/Preprocessor/predefined-macros.c
+++ test/Preprocessor/predefined-macros.c
@@ -102,47 +102,117 @@
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i386 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I386
 // CHECK-SYNC_CAS_I386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP
+// CHECK-SYNC_CAS_I386-NOT: __GCC_ATOMIC_{{.*}}_LOCK_FREE 2
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i486 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I486
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 //
+
+// FIXME: The value of LLONG_LOCK_FREE on i586 is wrong: clang is
+// using the alignment of "long long" (only 32bit for a 64bit value)
+// to disqualify it from being lock free. But the semantics of this
+// define are supposed to tell you if "_Atomic long long" is lock free
+// -- and it is.
+
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i586 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I586
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define

Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-04-01 Thread James Y Knight via cfe-commits 
jyknight marked an inline comment as done.


Comment at: test/CodeGen/atomic-ops.c:1
@@ -1,2 +1,2 @@
-// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map 
-triple=i686-apple-darwin9 | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map 
-triple=i686-apple-darwin9 -target-cpu i686 | FileCheck %s
 // REQUIRES: x86-registered-target

rsmith wrote:
> Why do you need a -target-cpu i686 in addition to the i686 triple?
The Driver code is what's responsible for parsing the default target cpu out of 
the triple. So if you invoke CC1 yourself, and don't pass -target-cpu, it 
treats i686-* triples as still targeting i386.


Comment at: test/Preprocessor/arm-target-features.c:108-118
@@ -107,2 +107,13 @@
 // V8M_BASELINE-NOT: __ARM_FP 0x{{.*}}
-// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+// V8M_BASELINE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// V8M_BASELINE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// V8M_BASELINE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// V8M_BASELINE: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1

rsmith wrote:
> Maybe drop the #define on these lines for consistency with the surrounding 
> tests?
Did the inverse (cleaned up the surrounding lines) in r265187.


Comment at: test/Preprocessor/init.c:3295
@@ -3292,1 +3294,3 @@
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
 // MIPSN32BE: #define __GNUC_MINOR__ 2

rsmith wrote:
> Can you add a `MIPSN32BE-NOT: ` for the 16 byte form? Likewise for the below 
> cases.
Done here and everywhere.


http://reviews.llvm.org/D17933



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Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-03-31 Thread Richard Smith via cfe-commits 
rsmith added a subscriber: rsmith.


Comment at: lib/Basic/Targets.cpp:4080
@@ -4079,1 +4079,3 @@
+// x86-64 has atomics up to 16 bytes, when the HasCX16 target
+// feature is enabled, 64 otherwise.
 MaxAtomicPromoteWidth = 128;

... where by 64, you mean 8, right? :)


Comment at: test/CodeGen/atomic-ops.c:1
@@ -1,2 +1,2 @@
-// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map 
-triple=i686-apple-darwin9 | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map 
-triple=i686-apple-darwin9 -target-cpu i686 | FileCheck %s
 // REQUIRES: x86-registered-target

Why do you need a -target-cpu i686 in addition to the i686 triple?


Comment at: test/Preprocessor/arm-target-features.c:108-118
@@ -107,2 +107,13 @@
 // V8M_BASELINE-NOT: __ARM_FP 0x{{.*}}
-// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+// V8M_BASELINE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// V8M_BASELINE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// V8M_BASELINE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// V8M_BASELINE: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1

Maybe drop the #define on these lines for consistency with the surrounding 
tests?


Comment at: test/Preprocessor/init.c:3295
@@ -3292,1 +3294,3 @@
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
 // MIPSN32BE: #define __GNUC_MINOR__ 2

Can you add a `MIPSN32BE-NOT: ` for the 16 byte form? Likewise for the below 
cases.


http://reviews.llvm.org/D17933



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Re: [PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-03-31 Thread James Y Knight via cfe-commits 
jyknight added a comment.

Ping.


http://reviews.llvm.org/D17933



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[PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

2016-03-07 Thread James Y Knight via cfe-commits 
jyknight created this revision.
jyknight added a reviewer: t.p.northover.
jyknight added a subscriber: cfe-commits.
Herald added subscribers: dschuff, jfb, aemerson.

Also, remove all the manual definition of
__GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros. Instead, define it based on
MaxAtomicInlineWidth, just like the __GCC_ATOMIC_*_LOCK_FREE macros.

Previously, the __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* defines had been
computed separately, and *were* being set appropriately for older x86
targets, while MaxAtomicInlineWidth was not.

(Note the one FIXME comment: __GCC_ATOMIC_LLONG_LOCK_FREE is (still) set
improperly for i586, due to checking alignment where it ought not to.)

Test changes of note:

A few test invocations of clang -cc1 needed to have a "-target-cpu i686"
argument added -- the Driver would do so automatically based on the
"i686" in the triple, but in the tests cases cc1 invocations, it was
missing.

Some of the OpenMP tests needed a "-target-cpu core2" added: they were
assuming that cmpxchg16b was available, even though it's not in the base
x86_64 architecture.

An ARM test was asserting that V8M doesn't have
__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1. This was wrong: V8M *does* support
atomic operations.

http://reviews.llvm.org/D17933

Files:
  lib/Basic/Targets.cpp
  lib/Frontend/InitPreprocessor.cpp
  test/CodeGen/atomic-ops.c
  test/CodeGen/ms-volatile.c
  test/CodeGenCXX/atomicinit.cpp
  test/OpenMP/atomic_capture_codegen.cpp
  test/OpenMP/atomic_read_codegen.c
  test/OpenMP/atomic_update_codegen.cpp
  test/OpenMP/atomic_write_codegen.c
  test/Preprocessor/arm-target-features.c
  test/Preprocessor/init.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/predefined-macros.c
  test/Preprocessor/x86_target_features.c
  test/Sema/atomic-ops.c

Index: test/Sema/atomic-ops.c
===
--- test/Sema/atomic-ops.c
+++ test/Sema/atomic-ops.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -target-cpu i686 -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
@@ -499,5 +499,3 @@
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_acq_rel, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_seq_cst, memory_order_relaxed);
 }
-
-
Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -291,8 +291,13 @@
 
 // NOTBM-NOT: #define __TBM__ 1
 
-// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck --check-prefix=MCX16 %s
+// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck --check-prefix=MCX16-386 %s
 
+// MCX16-386-NOT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
+
+// RUN: %clang -target x86_64-unknown-unknown -mcx16 -x c -E -dM -o - %s | FileCheck --check-prefix=MCX16 %s
+
+// MCX16: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
 
 // RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck --check-prefix=PRFCHW %s
Index: test/Preprocessor/predefined-macros.c
===
--- test/Preprocessor/predefined-macros.c
+++ test/Preprocessor/predefined-macros.c
@@ -102,45 +102,110 @@
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i386 \
 // RUN:   | FileCheck %s --check-prefix=CHECK-SYNC_CAS_I386
 // CHECK-SYNC_CAS_I386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP
+// CHECK-SYNC_CAS_I386-NOT: __GCC_ATOMIC_{{.*}}_LOCK_FREE 2
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i486 \
 // RUN:   | FileCheck %s --check-prefix=CHECK-SYNC_CAS_I486
-// CHECK-SYNC_CAS_I486: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
-// CHECK-SYNC_CAS_I486: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
-// CHECK-SYNC_CAS_I486: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+// CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+//