subject:"\[PATCH\] D62686\: \[RISCV\] Add support for save\/restore of callee\-saved registers via libcalls"

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-02-11 Thread Lewis Revill via Phabricator via cfe-commits

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG07f7c00208b3: [RISCV] Add support for save/restore of 
callee-saved registers via libcalls (authored by lewis-revill).

Changed prior to commit:
  https://reviews.llvm.org/D62686?vs=242723=243978#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-02-11 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added a comment.

Since the DebugInfo fix has been accepted, I'm looking to get this patch and 
that fix committed shortly if there are no problems caused by rebasing.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-02-05 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 242723.
lewis-revill added a comment.

Rebased


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+;

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-15 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added a comment.

In D62686#1820816 , @apazos wrote:

> Lewis, your latest patch looks good, we just had another run with no new 
> failures. But we know it will have issues with -g. So I think we should not 
> merge it yet. Do you have a version of the patch that creates the labels for 
> the compiler-generated save/restore lib calls, so that this optimization does 
> not depend on D71593 ? We could merge that 
> version then, and when D71593  is accepted, 
> you just have to rework/remove the label generation part of the patch.

I don't expect that would be possible without making changes to generic code 
anyway. Removing the framesetup flag from the libcalls when generating them 
would allow labels to be produced, but that would require making modifications 
to the logic of this patch which relies on the libcalls being annotated as such.

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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-14 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Lewis, your latest patch looks good, we just had another run with no new 
failures. But we know it will have issues with -g. So I think we should not 
merge it yet. Do you have a version of the patch that creates the labels for 
the compiler-generated save/restore lib calls, so that this optimization does 
not depend on D71593 ? We could merge that 
version then, and when D71593  is accepted, 
you just have to rework/remove the label generation part of the patch.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-14 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added a comment.

Should I wait for the comments to be resolved on D71593 
 before I commit this patch? Ideally if this 
patch makes it into a release then that bug fix should be there too.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-13 Thread Pengxuan Zheng via Phabricator via cfe-commits

pzheng added a comment.

In D62686#1816681 , @lewis-revill 
wrote:

> Fix .cfi_offset signedness error.


Thanks, @lewis-revill. It looks correct now.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-13 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added a comment.

In D62686#1808041 , @apazos wrote:

> Lewis, is the patch final? It would be good to merge it before the 10.0 
> release branch creation on Jan 15th


I would say so now.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-13 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 237620.
lewis-revill added a comment.

Fix .cfi_offset signedness error.


Repository:
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+;

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-13 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added a comment.

In D62686#1815158 , @pzheng wrote:

> I see the following .cfi_offset directives generated using @shiva0217's test 
> case. Any idea why the offset for ra is 536870908?
>
>   callt0, __riscv_save_0
>   .cfi_def_cfa_offset 16
>   .cfi_offset ra, 536870908
>   


Hmm I see this too I'll look into it.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-10 Thread Pengxuan Zheng via Phabricator via cfe-commits

pzheng added a comment.

I see the following .cfi_offset directives generated using @shiva0217's test 
case. Any idea why the offset for ra is 536870908?

  callt0, __riscv_save_0
  .cfi_def_cfa_offset 16
  .cfi_offset ra, 536870908




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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-01-07 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Lewis, is the patch final? It would be good to merge it before the 10.0 release 
branch creation on Jan 15th


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-20 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 234853.
lewis-revill added a comment.

Added .cfi_offset directives for registers saved by libcalls.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-20 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 234842.
lewis-revill added a comment.

Fixed existing .cfi_offset offsets. Since these are frame-pointer based they 
also need to account for the libcall stack adjustment.

Currently working on adding .cfi_offset instructions for the registers saved by 
the libcall.


Repository:
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0,

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-16 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 234091.
lewis-revill added a comment.

Rebased and addressed StackSize vs RealStackSize error.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-16 Thread James Clarke via Phabricator via cfe-commits

jrtc27 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:668
+.setMIFlag(MachineInstr::FrameSetup);
+
+// Add registers spilled in libcall as liveins.

lewis-revill wrote:
> shiva0217 wrote:
> > GCC will generate stack adjustment and GPR callee saved CFIs for the save 
> > libcalls. Should we do the same?
> I'm not familiar with the use of the CFI offset stuff, though just to be 
> sure, you're saying that in addition to the manually-added `.cfi_offset`s in 
> the libcalls themselves we would want to add them in our frame too?
Yes. The CFI use is completely ignorant of any control flow. It goes to the 
start of the function, and walks forward, executing every `.cfi_*` directive 
until reaching the current point in the code. Since the libcalls (and thus 
their CFI directives) are not inline in the function, they are completely 
invisible to the CFI machinery. Thus, their side-effects must be duplicated 
straight after the calls to them.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-16 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill marked an inline comment as done.
lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:289
   unsigned CFIIndex = MF.addFrameInst(
   MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
   BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))

shiva0217 wrote:
> Should the -StackSize be -RealStackSize?
Looks like it, good catch.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:668
+.setMIFlag(MachineInstr::FrameSetup);
+
+// Add registers spilled in libcall as liveins.

shiva0217 wrote:
> GCC will generate stack adjustment and GPR callee saved CFIs for the save 
> libcalls. Should we do the same?
I'm not familiar with the use of the CFI offset stuff, though just to be sure, 
you're saying that in addition to the manually-added `.cfi_offset`s in the 
libcalls themselves we would want to add them in our frame too?


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-16 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill marked an inline comment as done.
lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:667
+.addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
+.setMIFlag(MachineInstr::FrameSetup);
+

shiva0217 wrote:
> There is a case may trigger an assertion when compile with -O3 -g 
> -msave-restore if the libcall has FrameSetup flag.
>   int main(int a, char* argv[]) {
> exit(0);
> return 0;
>   }
Think I've found the cause of this. When 'DIFlagAllCallsDescribed' is set for 
the module LLVM attempts to provide call entry info DIEs for all calls, 
//including// this one that has been added by us. One detail of this is 
attempting to calculate the return PC value or offset for the call using a 
label that was assumed to be inserted after the call instruction.

However, while the attempt to add the call entry info doesn't check for the 
FrameSetup flag, the label was never inserted, since that code //does// check 
for the flag. Adding the missing check to avoid adding call entry info for 
calls marked as FrameSetup fixed this issue.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-09 Thread Shiva Chen via Phabricator via cfe-commits

shiva0217 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:289
   unsigned CFIIndex = MF.addFrameInst(
   MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
   BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))

Should the -StackSize be -RealStackSize?



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:667
+.addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
+.setMIFlag(MachineInstr::FrameSetup);
+

There is a case may trigger an assertion when compile with -O3 -g 
-msave-restore if the libcall has FrameSetup flag.
  int main(int a, char* argv[]) {
exit(0);
return 0;
  }



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:668
+.setMIFlag(MachineInstr::FrameSetup);
+
+// Add registers spilled in libcall as liveins.

GCC will generate stack adjustment and GPR callee saved CFIs for the save 
libcalls. Should we do the same?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.h:40
 
+  bool hasReservedSpillSlot(const MachineFunction , unsigned Reg,
+int ) const override;

An alternative of defining hasReservedSpillSlot could be set SaveRegs for the 
registers will be pushed by the libcalls in determineCalleeSaves. So the 
StackSize calculation will take the callee saved registers will be pushed by 
the libcalls into account.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-07 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 232702.
lewis-revill added a comment.

Rebased.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-12-03 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Lewis, try rebasing it, not applying cleanly nor https://reviews.llvm.org/D62190


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-11-15 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:278
   // Add CFI directives for callee-saved registers.
-  const std::vector  = MFI.getCalleeSavedInfo();
-  // Iterate over list of callee-saved registers and emit .cfi_restore
-  // directives.
-  for (const auto  : CSI) {
-Register Reg = Entry.getReg();
-unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
-nullptr, RI->getDwarfRegNum(Reg, true)));
-BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-.addCFIIndex(CFIIndex);
+  if (!CSI.empty()) {
+// Iterate over list of callee-saved registers and emit .cfi_restore

pzheng wrote:
> lewis-revill wrote:
> > lenary wrote:
> > > Nit: You shouldn't need this `if` statement - the for loop just won't 
> > > execute if CSI is empty, surely.
> > Good catch, thanks!
> Any chance this comment from @lenary is missed?
It appears this CFI code was removed since I last rebased.
But yes, just for posterity I did miss this comment!


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-11-15 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 229485.
lewis-revill added a comment.

Rebased


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+;

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-11-14 Thread Pengxuan Zheng via Phabricator via cfe-commits

pzheng added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:278
   // Add CFI directives for callee-saved registers.
-  const std::vector  = MFI.getCalleeSavedInfo();
-  // Iterate over list of callee-saved registers and emit .cfi_restore
-  // directives.
-  for (const auto  : CSI) {
-Register Reg = Entry.getReg();
-unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
-nullptr, RI->getDwarfRegNum(Reg, true)));
-BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-.addCFIIndex(CFIIndex);
+  if (!CSI.empty()) {
+// Iterate over list of callee-saved registers and emit .cfi_restore

lewis-revill wrote:
> lenary wrote:
> > Nit: You shouldn't need this `if` statement - the for loop just won't 
> > execute if CSI is empty, surely.
> Good catch, thanks!
Any chance this comment from @lenary is missed?


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-11-01 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 227512.
lewis-revill added a comment.
Herald added a subscriber: sameer.abuasal.

Rebased and merged D68644  into this patch - 
this patch already assumes shrink wrapping support anyway.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-23 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 226166.
lewis-revill added a comment.

Rebase on top of shrink wrapping patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+; RV64I-SR: call t0, __riscv_save_11
+; RV64I-SR: tail __riscv_restore_11
+;
+; RV32I-FP-SR-LABEL: callee_saved1:
+; RV32I-FP-SR: call t0, __riscv_save_11
+; RV32I-FP-SR: tail __riscv_restore_11
+;
+; RV64I-FP-SR-LABEL: callee_saved1:
+; RV64I-FP-SR: call t0, __riscv_save_11
+; RV64I-FP-SR: tail __riscv_restore_11
+  %val = load [24 x i32], [24 x i32]* @var1
+  store volatile [24 x i32] %val, [24 x i32]* @var1
+  ret void
+}
+
+define void @callee_saved2() nounwind {
+; RV32I-LABEL: callee_saved2:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved2:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved2:
+; RV32I-SR: call t0, __riscv_save_12
+; RV32I-SR: tail __riscv_restore_12
+;
+; RV64I-SR-LABEL: callee_saved2:
+; RV64I-SR: call t0, __riscv_save_12
+; RV64I-SR: tail __riscv_restore_12
+;
+; RV32I-FP-SR-LABEL: callee_saved2:
+; RV32I-FP-SR: call t0, __riscv_save_12
+; RV32I-FP-SR: tail __riscv_restore_12
+;
+; RV64I-FP-SR-LABEL: callee_saved2:
+; RV64I-FP-SR: call t0, __riscv_save_12
+; RV64I-FP-SR: tail __riscv_restore_12
+  %val = load [30 x i32], [30 x i32]* @var2
+  store volatile [30 x i32] %val, [30 x i32]* @var2
+  ret void
+}
+
+; Check that floating point callee saved registers are still manually saved and
+; restored.
+
+define void @callee_saved_fp() nounwind {
+; RV32I-LABEL: callee_saved_fp:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved_fp:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved_fp:
+; RV32I-SR: call t0, __riscv_save_7
+; RV32I-SR: tail __riscv_restore_7
+;
+; RV64I-SR-LABEL: callee_saved_fp:
+; RV64I-SR: call t0, __riscv_save_7
+; RV64I-SR: tail __riscv_restore_7
+;
+;

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-16 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Thanks Lewis, the runs are looking good, no failures, and good code size 
savings (average 3%)


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-16 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 225230.
lewis-revill added a comment.

Disable the save/restore optimization when a function contains tail calls. 
Address various miscellaneous concerns with the patch. Update tests to include 
less redundant code when checking cases where save/restore libcalls are not 
used.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+; RV64I-SR: call t0, __riscv_save_11
+; RV64I-SR: tail __riscv_restore_11
+;
+; RV32I-FP-SR-LABEL: callee_saved1:
+; RV32I-FP-SR: call t0, __riscv_save_11
+; RV32I-FP-SR: tail __riscv_restore_11
+;
+; RV64I-FP-SR-LABEL: callee_saved1:
+; RV64I-FP-SR: call t0, __riscv_save_11
+; RV64I-FP-SR: tail __riscv_restore_11
+  %val = load [24 x i32], [24 x i32]* @var1
+  store volatile [24 x i32] %val, [24 x i32]* @var1
+  ret void
+}
+
+define void @callee_saved2() nounwind {
+; RV32I-LABEL: callee_saved2:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved2:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved2:
+; RV32I-SR: call t0, __riscv_save_12
+; RV32I-SR: tail __riscv_restore_12
+;
+; RV64I-SR-LABEL: callee_saved2:
+; RV64I-SR: call t0, __riscv_save_12
+; RV64I-SR: tail __riscv_restore_12
+;
+; RV32I-FP-SR-LABEL: callee_saved2:
+; RV32I-FP-SR: call t0, __riscv_save_12
+; RV32I-FP-SR: tail __riscv_restore_12
+;
+; RV64I-FP-SR-LABEL: callee_saved2:
+; RV64I-FP-SR: call t0, __riscv_save_12
+; RV64I-FP-SR: tail __riscv_restore_12
+  %val = load [30 x i32], [30 x i32]* @var2
+  store volatile [30 x i32] %val, [30 x i32]* @var2
+  ret void
+}
+
+; Check that floating point callee saved registers are still manually saved and
+; restored.
+
+define void @callee_saved_fp() nounwind {
+; RV32I-LABEL: callee_saved_fp:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved_fp:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved_fp:
+; RV32I-SR: call

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-15 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.



> Is it worth trying to disallow tail call optimization completely if this flag 
> is enabled? I'm not sure what GCC does exactly. but this seems to be the 
> behaviour.

I had reported above that I have already run that test:  with 
"-fno-optimize-sibling-calls -msave-restore", i.e., disabling tail calls when 
m-save-restore is enabled.

But it seems a better solution is to optimistically apply -msave-restore when 
there are no tail calls of any type in a function,  instead of disabling tail 
calls completed. Let tail call optimization prevail over msave-restore. No LLVM 
target is disabling tail calls.

So you can update the patch according to this solution plan.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-15 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added inline comments.



Comment at: llvm/test/CodeGen/RISCV/saverestore.ll:348
+
+; Check that functions with varargs do not use save/restore code
+

luismarques wrote:
> Maybe for these tests just put a -NOT check that __riscv_save_ isn't called?
Thanks, I realise it makes much more sense to do this for all the other 
'non-save-restore' checks too, since they don't actually check any save/restore 
behaviour.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-15 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill added a comment.

In D62686#1708792 , @apazos wrote:

> Yes Eli thanks for pointing out  there are more scenarios that can fail.
>  It looks like the best solution is to permit both flags on, but then bail 
> out from doing this transformation if there is any type of tail call already 
> in the function.
>  This way we avoid messing with reverting tail calls back to regular calls.


Is it worth trying to disallow tail call optimization completely if this flag 
is enabled? I'm not sure what GCC does exactly. but this seems to be the 
behaviour.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-14 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Yes Eli thanks for pointing out  there are more scenarios that can fail.
It looks like the best solution is to permit both flags on, but then bail out 
from doing this transformation if there is any type of tail call already in the 
function.
This way we avoid messing with reverting tail calls back to regular calls.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-14 Thread Eli Friedman via Phabricator via cfe-commits

efriedma added a comment.

> Bug2: test case provided above. Please Lewis take a look at how this case can 
> be fixed.

Isn't the issue just that the code is checking for PseudoTAIL, and not 
PseudoTAILIndirect?



What happens if a tail call has more than 8 arguments?

What happens for a musttail call?  A tailcc call?  (Not sure if either of those 
are actually supported on RISCV at the moment?)


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-14 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Here is the bugpoint-reduced test case for the SPEC failure when enabling 
-msave-restore and allowing tail calls:

Run the command llc test.ll -mattr=+save-restore -o out.s

You will see the code generated is wrong:

  tail__riscv_restore_2
   jr  a5

target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-linux-gnu"

%struct.1_s = type { i8*, i8*, i8*}
%struct.2_s = type { i8*, i8*, i8*}

declare dso_local void @test2() local_unnamed_addr
declare dso_local i32 @test3(%struct.2_s* nonnull %a, %struct.1_s** %b) 
local_unnamed_addr

define dso_local void @test1(%struct.2_s* %a, %struct.1_s** %b) 
local_unnamed_addr  {
entry:

  br i1 undef, label %if.end2, label %if.then

if.then:  ; preds = %entry

  tail call void @test2()
  br label %if.end2

if.end2:  ; preds = %if.then, %entry

  %call3 = tail call i32 null(%struct.2_s* nonnull %a, %struct.1_s** %b)
  ret void

}

To summarize the issues we have detected so far:

1. Bug1: When transforming a tail call back into a regular call, the 
transformation is not correctly preserving the original call's return values.

I fixed this by conservatively adding RegState::Implicit definitions for each 
possible integer and FP return registers, when defining the riscv_restore tail 
call.

2. Bug2: test case provided above. Please Lewis take a look at how this case 
can be fixed.

3. I have also run the tests with "-fno-optimize-sibling-calls -msave-restore", 
i.e., disabling tail calls when m-save-restore is enabled.

With this config, issues (1) and (2) do not happen.
There is some loss in code size savings when using fno-optimize-sibling-calls.
But still we see code size savings benefit from -msave-restore.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-13 Thread Luís Marques via Phabricator via cfe-commits

luismarques added a comment.

The priority for this patch is to address the issues reported by @apazos but 
after that please check the clang-format output. There are some cases in this 
patch where it might make sense to use a different formatting than clang-format 
indicates, but the remaining should be addressed.

@apazos Have you considered tweaking the patch code to not do a tail call, just 
to check if that's what's causing the remaining failures? I'm not sure if 
that's too hard, but it could eventually be easier than drilling into the 
failing cases.




Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:27
+// registers.
+static int getLibCallID(const MachineFunction ,
+const std::vector ) {

The return value isn't used as just an opaque index, it also reflects the frame 
size and is used for that purpose. The function comment should probably reflect 
that.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:34
+
+  unsigned MaxReg = 0;
+  for (auto  : CSI)

Use `Register` and `RISCV::NoRegister`. (You'll have to use `MaxReg.id()` 
instead in the call to `max`).



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:36
+  for (auto  : CSI)
+if (CS.getFrameIdx() < 0)
+  MaxReg = std::max(MaxReg, CS.getReg());

Might be worth adding a small comment explaining how this serves as a filters 
for the registers we are interested in. Or point to a later relevant comment?



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:39
+
+  if (MaxReg == 0)
+return -1;

Ditto `NoRegister`.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:66
+const std::vector ) {
+  static const char *const spillLibCalls[] = {
+"__riscv_save_0",

Check LLVM naming convention capitalization. Ditto other vars here.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:93
+  const std::vector ) {
+  static const char *const restoreLibCalls[] = {
+"__riscv_restore_0",

Check LLVM naming convention capitalization. Ditto other vars here.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:190
 
+static std::vector
+getNonLibcallCSI(const std::vector ) {

This could probably use `SmallVector`.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:706
+  for (auto  : reverse(NonLibcallCSI)) {
+unsigned Reg = CS.getReg();
+const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

Ditto `Register`.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:95
+// by save/restore libcalls.
+static const std::map FixedCSRFIMap = {
+  {/*ra*/  RISCV::X1,   -1},

Use `IndexedMap` instead?



Comment at: llvm/test/CodeGen/RISCV/saverestore.ll:348
+
+; Check that functions with varargs do not use save/restore code
+

Maybe for these tests just put a -NOT check that __riscv_save_ isn't called?


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-08 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 223855.
lewis-revill added a comment.

Rebased to fix conflicts with recent split SP adjustments


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,640 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I: addi sp, sp, -32
+; RV32I-NEXT:sw s0, 28(sp)
+; RV32I-NEXT:sw s1, 24(sp)
+; RV32I-NEXT:sw s2, 20(sp)
+; RV32I-NEXT:sw s3, 16(sp)
+; RV32I-NEXT:sw s4, 12(sp)
+; RV32I: lw s4, 12(sp)
+; RV32I-NEXT:lw s3, 16(sp)
+; RV32I-NEXT:lw s2, 20(sp)
+; RV32I-NEXT:lw s1, 24(sp)
+; RV32I-NEXT:lw s0, 28(sp)
+; RV32I-NEXT:addi sp, sp, 32
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I: addi sp, sp, -48
+; RV64I-NEXT:sd s0, 40(sp)
+; RV64I-NEXT:sd s1, 32(sp)
+; RV64I-NEXT:sd s2, 24(sp)
+; RV64I-NEXT:sd s3, 16(sp)
+; RV64I: ld s4, 8(sp)
+; RV64I-NEXT:ld s3, 16(sp)
+; RV64I-NEXT:ld s2, 24(sp)
+; RV64I-NEXT:ld s1, 32(sp)
+; RV64I-NEXT:ld s0, 40(sp)
+; RV64I-NEXT:addi sp, sp, 48
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I: addi sp, sp, -48
+; RV32I-NEXT:sw s0, 44(sp)
+; RV32I-NEXT:sw s1, 40(sp)
+; RV32I-NEXT:sw s2, 36(sp)
+; RV32I-NEXT:sw s3, 32(sp)
+; RV32I-NEXT:sw s4, 28(sp)
+; RV32I-NEXT:sw s5, 24(sp)
+; RV32I-NEXT:sw s6, 20(sp)
+; RV32I-NEXT:sw s7, 16(sp)
+; RV32I-NEXT:sw s8, 12(sp)
+; RV32I-NEXT:sw s9, 8(sp)
+; RV32I-NEXT:sw s10, 4(sp)
+; RV32I: lw s10, 4(sp)
+; RV32I-NEXT:lw s9, 8(sp)
+; RV32I-NEXT:lw s8, 12(sp)
+; RV32I-NEXT:lw s7, 16(sp)
+; RV32I-NEXT:lw s6, 20(sp)
+; RV32I-NEXT:lw s5, 24(sp)
+; RV32I-NEXT:lw s4, 28(sp)
+; RV32I-NEXT:lw s3, 32(sp)
+; RV32I-NEXT:lw s2, 36(sp)
+; RV32I-NEXT:lw s1, 40(sp)
+; RV32I-NEXT:lw s0, 44(sp)
+; RV32I-NEXT:addi sp, sp, 48
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I: addi sp, sp, -96
+; RV64I-NEXT:sd s0, 88(sp)
+; RV64I-NEXT:sd s1, 80(sp)
+; RV64I-NEXT:sd s2, 72(sp)
+; RV64I-NEXT:sd s3, 64(sp)
+; RV64I-NEXT:sd s4, 56(sp)
+; RV64I-NEXT:sd s5, 48(sp)
+; RV64I-NEXT:sd s6, 40(sp)
+; RV64I-NEXT:sd s7, 32(sp)
+; RV64I-NEXT:sd s8, 24(sp)
+; RV64I-NEXT:sd s9, 16(sp)
+; RV64I-NEXT:sd s10, 8(sp)
+; RV64I: ld s10, 8(sp)
+; RV64I-NEXT:ld s9, 16(sp)
+; RV64I-NEXT:ld s8, 24(sp)
+; RV64I-NEXT:ld s7, 32(sp)
+; RV64I-NEXT:ld s6, 40(sp)
+; RV64I-NEXT:ld s5, 48(sp)
+; RV64I-NEXT:ld s4, 56(sp)
+; RV64I-NEXT:ld s3, 64(sp)
+; RV64I-NEXT:ld s2, 72(sp)
+; RV64I-NEXT:ld s1, 80(sp)
+; RV64I-NEXT:ld s0, 88(sp)
+; RV64I-NEXT:addi sp, sp, 96
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR:

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-03 Thread Ana Pazos via Phabricator via cfe-commits

apazos added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:631
+  MachineBasicBlock::iterator NewMI =
+  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALL))
+  .add(MI->getOperand(0));

apazos wrote:
> Where are we making sure the PseudoCALL result in a0 is alive through the 
> riscv_restore call?
I did not find any other target that transforms a tail call back into a regular 
call.

The issue with doing this is that we don't have info about the return value of 
the original call.

If anyone knows how to do it, please give me some pointers.

I tried to fix this problem by adding implicit operands to  the riscv_restore 
tail call that are all the possible return value registers:
BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))
.addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
-.setMIFlag(MachineInstr::FrameDestroy);
+.setMIFlag(MachineInstr::FrameDestroy)
+.addReg(RISCV::X10, RegState::Implicit)
+.addReg(RISCV::X11, RegState::Implicit)
+.addReg(RISCV::F10_F, RegState::Implicit)
+.addReg(RISCV::F11_F, RegState::Implicit)

With this change, some perennial tests now pass.

But there are still failures to be analyzed in SPEC.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-02 Thread Ana Pazos via Phabricator via cfe-commits

apazos added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:631
+  MachineBasicBlock::iterator NewMI =
+  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALL))
+  .add(MI->getOperand(0));

Where are we making sure the PseudoCALL result in a0 is alive through the 
riscv_restore call?


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-02 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Lewis, with this patch we see less failures. But still some tests in SPEC and 
perennial test suites are failing.

Pengxuan and I are trying to triage the failures.

Here is what we see in one of the failed tests:

Code right before rologue/Epilogue Insertion & Frame Finalization:

  %call39 = tail call i32 @somefunction()
  ret i32 %call39

Code after Prologue/Epilogue Insertion & Frame Finalization:

  PseudoCALL target-flags() @somefunction, implicit-def $x1, implicit 
$x2
  $x10 = frame-destroy LUI 1
  $x10 = frame-destroy ADDI killed $x10, -1712
  $x2 = frame-destroy ADD $x2, killed $x10
  CFI_INSTRUCTION def_cfa_offset 0
  frame-destroy PseudoTAIL target-flags() &__riscv_restore_12, 
implicit $x2

x10 is the return value and it is being overwritten.

Is this patch self contained? Or does it depend on another patch under review?

For the tests that are passing, I see better code size reduction with C 
extension enabled (testing RV32IMAC) than with the machine outliner.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-01 Thread Ana Pazos via Phabricator via cfe-commits

apazos added a comment.

Thanks for the patch update. I will launch some new correctness runs.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-10-01 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 222612.
lewis-revill added a comment.

Rewrote logic to calculate stack sizes, frame indexes and frame pointer 
offsets. This was necessary to take into account the fact that the save/restore 
lib calls are essentially an opaque section of the stack that is inserted at 
the beginning of the frame, after positive offset objects such as fixed stack 
arguments, but before additional callee saved registers (IE FP registers) and 
negative offset (dynamic) objects. So calculations of the actual offsets of 
these objects must be adjusted accordingly for the stack to function correctly.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,640 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I: addi sp, sp, -32
+; RV32I-NEXT:sw s0, 28(sp)
+; RV32I-NEXT:sw s1, 24(sp)
+; RV32I-NEXT:sw s2, 20(sp)
+; RV32I-NEXT:sw s3, 16(sp)
+; RV32I-NEXT:sw s4, 12(sp)
+; RV32I: lw s4, 12(sp)
+; RV32I-NEXT:lw s3, 16(sp)
+; RV32I-NEXT:lw s2, 20(sp)
+; RV32I-NEXT:lw s1, 24(sp)
+; RV32I-NEXT:lw s0, 28(sp)
+; RV32I-NEXT:addi sp, sp, 32
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I: addi sp, sp, -48
+; RV64I-NEXT:sd s0, 40(sp)
+; RV64I-NEXT:sd s1, 32(sp)
+; RV64I-NEXT:sd s2, 24(sp)
+; RV64I-NEXT:sd s3, 16(sp)
+; RV64I: ld s4, 8(sp)
+; RV64I-NEXT:ld s3, 16(sp)
+; RV64I-NEXT:ld s2, 24(sp)
+; RV64I-NEXT:ld s1, 32(sp)
+; RV64I-NEXT:ld s0, 40(sp)
+; RV64I-NEXT:addi sp, sp, 48
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I: addi sp, sp, -48
+; RV32I-NEXT:sw s0, 44(sp)
+; RV32I-NEXT:sw s1, 40(sp)
+; RV32I-NEXT:sw s2, 36(sp)
+; RV32I-NEXT:sw s3, 32(sp)
+; RV32I-NEXT:sw s4, 28(sp)
+; RV32I-NEXT:sw s5, 24(sp)
+; RV32I-NEXT:sw s6, 20(sp)
+; RV32I-NEXT:sw s7, 16(sp)
+; RV32I-NEXT:sw s8, 12(sp)
+; RV32I-NEXT:sw s9, 8(sp)
+; RV32I-NEXT:sw s10, 4(sp)
+; RV32I: lw s10, 4(sp)
+; RV32I-NEXT:lw s9, 8(sp)
+; RV32I-NEXT:lw s8, 12(sp)
+; RV32I-NEXT:lw s7, 16(sp)
+; RV32I-NEXT:lw s6, 20(sp)
+; RV32I-NEXT:lw s5, 24(sp)
+; RV32I-NEXT:lw s4, 28(sp)
+; RV32I-NEXT:lw s3, 32(sp)
+; RV32I-NEXT:lw s2, 36(sp)
+; RV32I-NEXT:lw s1, 40(sp)
+; RV32I-NEXT:lw s0, 44(sp)
+; RV32I-NEXT:addi sp, sp, 48
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I: addi sp, sp, -96
+; RV64I-NEXT:sd s0, 88(sp)
+; RV64I-NEXT:sd s1, 80(sp)
+; RV64I-NEXT:sd s2, 72(sp)
+; RV64I-NEXT:sd s3, 64(sp)
+; RV64I-NEXT:sd s4, 56(sp)
+; RV64I-NEXT:sd s5, 48(sp)
+; RV64I-NEXT:sd s6, 40(sp)
+; RV64I-NEXT:sd s7, 32(sp)
+; RV64I-NEXT:sd s8, 24(sp)
+; RV64I-NEXT:sd s9, 16(sp)
+; RV64I-NEXT:sd s10, 8(sp)
+; RV64I: ld

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-09-23 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill planned changes to this revision.
lewis-revill added a comment.

It seems like the regressions I'm seeing are due to the fact that calculating 
offsets for fixed objects at the top of the frame didn't account for extra 
stack size adjustment from the libcalls. I'm trying to find a neat way around 
this without breaking other calculations.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-09-19 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill marked an inline comment as done.
lewis-revill added a comment.

In D62686#1675347 , @lenary wrote:

> We discussed this in the RISC-V meeting on 19 Sept 2019. @apazos says there 
> are some SPEC failures in both 2006 and 2017, which would be good to triage.

I've uncovered some execution failures in our annotated GCC testsuite as well, 
so I will look into those as a starting point.

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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-09-19 Thread Sam Elliott via Phabricator via cfe-commits

lenary added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:72
 
+def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
+  "true", "Enable save/restore.">;

lewis-revill wrote:
> lenary wrote:
> > Given the clang option defaults to false, I think it should here too, to 
> > avoid confusion in other frontends.
> This is simply a case of a confusing parameter of the SubtargetFeature class.
> 
> SubtargetFeature interprets this "true" string as 'Value the attribute to be 
> set to by feature'. IE: when the feature is enabled, what value should the 
> corresponding RISCVSubtarget variable be set to? Rather than a default value 
> for that variable.
Ah, apologies for the confusion.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-09-19 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill marked 2 inline comments as done.
lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:72
 
+def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
+  "true", "Enable save/restore.">;

lenary wrote:
> Given the clang option defaults to false, I think it should here too, to 
> avoid confusion in other frontends.
This is simply a case of a confusing parameter of the SubtargetFeature class.

SubtargetFeature interprets this "true" string as 'Value the attribute to be 
set to by feature'. IE: when the feature is enabled, what value should the 
corresponding RISCVSubtarget variable be set to? Rather than a default value 
for that variable.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:278
   // Add CFI directives for callee-saved registers.
-  const std::vector  = MFI.getCalleeSavedInfo();
-  // Iterate over list of callee-saved registers and emit .cfi_restore
-  // directives.
-  for (const auto  : CSI) {
-Register Reg = Entry.getReg();
-unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
-nullptr, RI->getDwarfRegNum(Reg, true)));
-BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-.addCFIIndex(CFIIndex);
+  if (!CSI.empty()) {
+// Iterate over list of callee-saved registers and emit .cfi_restore

lenary wrote:
> Nit: You shouldn't need this `if` statement - the for loop just won't execute 
> if CSI is empty, surely.
Good catch, thanks!


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-09-19 Thread Sam Elliott via Phabricator via cfe-commits

lenary added a comment.

Two nits, that I wanted to submit before the meeting, but didn't get around to.




Comment at: llvm/lib/Target/RISCV/RISCV.td:72
 
+def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
+  "true", "Enable save/restore.">;

Given the clang option defaults to false, I think it should here too, to avoid 
confusion in other frontends.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:278
   // Add CFI directives for callee-saved registers.
-  const std::vector  = MFI.getCalleeSavedInfo();
-  // Iterate over list of callee-saved registers and emit .cfi_restore
-  // directives.
-  for (const auto  : CSI) {
-Register Reg = Entry.getReg();
-unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
-nullptr, RI->getDwarfRegNum(Reg, true)));
-BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-.addCFIIndex(CFIIndex);
+  if (!CSI.empty()) {
+// Iterate over list of callee-saved registers and emit .cfi_restore

Nit: You shouldn't need this `if` statement - the for loop just won't execute 
if CSI is empty, surely.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-09-19 Thread Sam Elliott via Phabricator via cfe-commits

lenary added a comment.

We discussed this in the RISC-V meeting on 19 Sept 2019. @apazos says there are 
some SPEC failures in both 2006 and 2017, which would be good to triage.


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

2019-09-18 Thread Lewis Revill via Phabricator via cfe-commits

lewis-revill updated this revision to Diff 220677.
lewis-revill added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Replace internal -mllvm option with target feature enabled through the clang 
frontend using -msave-restore.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,640 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I: addi sp, sp, -32
+; RV32I-NEXT:sw s0, 28(sp)
+; RV32I-NEXT:sw s1, 24(sp)
+; RV32I-NEXT:sw s2, 20(sp)
+; RV32I-NEXT:sw s3, 16(sp)
+; RV32I-NEXT:sw s4, 12(sp)
+; RV32I: lw s4, 12(sp)
+; RV32I-NEXT:lw s3, 16(sp)
+; RV32I-NEXT:lw s2, 20(sp)
+; RV32I-NEXT:lw s1, 24(sp)
+; RV32I-NEXT:lw s0, 28(sp)
+; RV32I-NEXT:addi sp, sp, 32
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I: addi sp, sp, -48
+; RV64I-NEXT:sd s0, 40(sp)
+; RV64I-NEXT:sd s1, 32(sp)
+; RV64I-NEXT:sd s2, 24(sp)
+; RV64I-NEXT:sd s3, 16(sp)
+; RV64I: ld s4, 8(sp)
+; RV64I-NEXT:ld s3, 16(sp)
+; RV64I-NEXT:ld s2, 24(sp)
+; RV64I-NEXT:ld s1, 32(sp)
+; RV64I-NEXT:ld s0, 40(sp)
+; RV64I-NEXT:addi sp, sp, 48
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I: addi sp, sp, -48
+; RV32I-NEXT:sw s0, 44(sp)
+; RV32I-NEXT:sw s1, 40(sp)
+; RV32I-NEXT:sw s2, 36(sp)
+; RV32I-NEXT:sw s3, 32(sp)
+; RV32I-NEXT:sw s4, 28(sp)
+; RV32I-NEXT:sw s5, 24(sp)
+; RV32I-NEXT:sw s6, 20(sp)
+; RV32I-NEXT:sw s7, 16(sp)
+; RV32I-NEXT:sw s8, 12(sp)
+; RV32I-NEXT:sw s9, 8(sp)
+; RV32I-NEXT:sw s10, 4(sp)
+; RV32I: lw s10, 4(sp)
+; RV32I-NEXT:lw s9, 8(sp)
+; RV32I-NEXT:lw s8, 12(sp)
+; RV32I-NEXT:lw s7, 16(sp)
+; RV32I-NEXT:lw s6, 20(sp)
+; RV32I-NEXT:lw s5, 24(sp)
+; RV32I-NEXT:lw s4, 28(sp)
+; RV32I-NEXT:lw s3, 32(sp)
+; RV32I-NEXT:lw s2, 36(sp)
+; RV32I-NEXT:lw s1, 40(sp)
+; RV32I-NEXT:lw s0, 44(sp)
+; RV32I-NEXT:addi sp, sp, 48
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I: addi sp, sp, -96
+; RV64I-NEXT:sd s0, 88(sp)
+; RV64I-NEXT:sd s1, 80(sp)
+; RV64I-NEXT:sd s2, 72(sp)
+; RV64I-NEXT:sd s3, 64(sp)
+; RV64I-NEXT:sd s4, 56(sp)
+; RV64I-NEXT:sd s5, 48(sp)
+; RV64I-NEXT:sd s6, 40(sp)
+; RV64I-NEXT:sd s7, 32(sp)
+; RV64I-NEXT:sd s8, 24(sp)
+; RV64I-NEXT:sd s9, 16(sp)
+; RV64I-NEXT:sd s10, 8(sp)
+; RV64I: ld s10, 8(sp)
+; RV64I-NEXT:ld s9, 16(sp)
+; RV64I-NEXT:ld s8, 24(sp)
+; RV64I-NEXT:ld s7, 32(sp)
+; RV64I-NEXT:ld s6, 40(sp)
+; RV64I-NEXT:ld s5, 48(sp)
+; RV64I-NEXT:ld s4, 56(sp)
+; RV64I-NEXT:ld s3, 64(sp)
+; RV64I-NEXT:ld s2, 72(sp)
+; RV64I-NEXT:ld s1, 80(sp)
+; RV64I-NEXT:ld s0, 88(sp)
+; RV64I-NEXT:addi sp, sp, 96
+;

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