[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2368bf52cd77: [PowerPC] Add support for -mcpu=pwr10 in both 
clang and llvm (authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80020/new/

https://reviews.llvm.org/D80020

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
 
 ; CHECK-NOT: is not a recognized processor for this target
 ; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
   if (CacheLineSize.getNumOccurrences() > 0)
 return CacheLineSize;
 
-  // On P7, P8 or P9 we have a cache line size of 128.
+  // Starting with P7 we have a cache line size of 128.
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
   // For P7 and P8, floating-point instructions have a 6-cycle latency and
   // there are two execution units, so unroll by 12x for latency hiding.
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+  // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
 
 namespace PPC {
   // -m directive values.
-  enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
-  };
+enum {
+  DIR_NONE,
+  DIR_32,
+  DIR_440,
+  DIR_601,
+  DIR_602,
+  DIR_603,
+  DIR_7400,
+  DIR_750,
+  DIR_970,
+  DIR_A2,
+  DIR_E500,
+  DIR_E500mc,
+  DIR_E5500,
+  DIR_PWR3,
+  DIR_PWR4,
+  DIR_PWR5,
+  DIR_PWR5X,
+  DIR_PWR6,
+  DIR_PWR6X,
+  DIR_PWR7,
+  DIR_PWR8,
+  DIR_PWR9,
+  DIR_PWR10,
+  DIR_PWR_FUTURE,
+  DIR_64
+};
 }
 
 class GlobalValue;
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ 

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 266548.
lei added a comment.

fix up rebase issue after revert


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80020/new/

https://reviews.llvm.org/D80020

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
 
 ; CHECK-NOT: is not a recognized processor for this target
 ; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
   if (CacheLineSize.getNumOccurrences() > 0)
 return CacheLineSize;
 
-  // On P7, P8 or P9 we have a cache line size of 128.
+  // Starting with P7 we have a cache line size of 128.
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
   // For P7 and P8, floating-point instructions have a 6-cycle latency and
   // there are two execution units, so unroll by 12x for latency hiding.
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+  // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
 
 namespace PPC {
   // -m directive values.
-  enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
-  };
+enum {
+  DIR_NONE,
+  DIR_32,
+  DIR_440,
+  DIR_601,
+  DIR_602,
+  DIR_603,
+  DIR_7400,
+  DIR_750,
+  DIR_970,
+  DIR_A2,
+  DIR_E500,
+  DIR_E500mc,
+  DIR_E5500,
+  DIR_PWR3,
+  DIR_PWR4,
+  DIR_PWR5,
+  DIR_PWR5X,
+  DIR_PWR6,
+  DIR_PWR6X,
+  DIR_PWR7,
+  DIR_PWR8,
+  DIR_PWR9,
+  DIR_PWR10,
+  DIR_PWR_FUTURE,
+  DIR_64
+};
 }
 
 class GlobalValue;
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6 +115,7 @@
   HasAddiLoadFusion = false;
   HasAddisLoadFusion = false;
   IsISA3_0 = 

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 266533.
lei added a comment.

rebased


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80020/new/

https://reviews.llvm.org/D80020

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h


Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -176,6 +176,7 @@
  StringRef CPU,
  const std::vector ) const override;
 
+  void addP10SpecificFeatures(llvm::StringMap ) const;
   void addFutureSpecificFeatures(llvm::StringMap ) const;
 
   bool handleTargetFeatures(std::vector ,
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -325,6 +325,13 @@
 .Case("e500", true)
 .Default(false);
 
+  // Power10 includes all the same features as Power9 plus any features 
specific
+  // to the Power10 core.
+  if (CPU == "pwr10" || CPU == "power10") {
+initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+addP10SpecificFeatures(Features);
+  }
+
   // Future CPU should include all of the features of Power 10 as well as any
   // additional features (yet to be determined) specific to it.
   if (CPU == "future") {
@@ -345,6 +352,13 @@
   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
 }
 
+// Add any Power10 specific features.
+void PPCTargetInfo::addP10SpecificFeatures(
+llvm::StringMap ) const {
+  Features["htm"] = false; // HTM was removed for P10.
+  return;
+}
+
 // Add features specific to the "Future" CPU.
 void PPCTargetInfo::addFutureSpecificFeatures(
 llvm::StringMap ) const {


Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -176,6 +176,7 @@
  StringRef CPU,
  const std::vector ) const override;
 
+  void addP10SpecificFeatures(llvm::StringMap ) const;
   void addFutureSpecificFeatures(llvm::StringMap ) const;
 
   bool handleTargetFeatures(std::vector ,
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -325,6 +325,13 @@
 .Case("e500", true)
 .Default(false);
 
+  // Power10 includes all the same features as Power9 plus any features specific
+  // to the Power10 core.
+  if (CPU == "pwr10" || CPU == "power10") {
+initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+addP10SpecificFeatures(Features);
+  }
+
   // Future CPU should include all of the features of Power 10 as well as any
   // additional features (yet to be determined) specific to it.
   if (CPU == "future") {
@@ -345,6 +352,13 @@
   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
 }
 
+// Add any Power10 specific features.
+void PPCTargetInfo::addP10SpecificFeatures(
+llvm::StringMap ) const {
+  Features["htm"] = false; // HTM was removed for P10.
+  return;
+}
+
 // Add features specific to the "Future" CPU.
 void PPCTargetInfo::addFutureSpecificFeatures(
 llvm::StringMap ) const {
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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Amy Kwan via Phabricator via cfe-commits]

amyk accepted this revision.
amyk added a comment.

This LGTM.


Repository:
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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision.
stefanp added a comment.

LGTM


Repository:
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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 266321.
lei added a comment.

change how we generate p10 feature list.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80020/new/

https://reviews.llvm.org/D80020

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
 
 ; CHECK-NOT: is not a recognized processor for this target
 ; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
   if (CacheLineSize.getNumOccurrences() > 0)
 return CacheLineSize;
 
-  // On P7, P8 or P9 we have a cache line size of 128.
+  // Starting with P7 we have a cache line size of 128.
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
   // For P7 and P8, floating-point instructions have a 6-cycle latency and
   // there are two execution units, so unroll by 12x for latency hiding.
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+  // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
 
 namespace PPC {
   // -m directive values.
-  enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
-  };
+enum {
+  DIR_NONE,
+  DIR_32,
+  DIR_440,
+  DIR_601,
+  DIR_602,
+  DIR_603,
+  DIR_7400,
+  DIR_750,
+  DIR_970,
+  DIR_A2,
+  DIR_E500,
+  DIR_E500mc,
+  DIR_E5500,
+  DIR_PWR3,
+  DIR_PWR4,
+  DIR_PWR5,
+  DIR_PWR5X,
+  DIR_PWR6,
+  DIR_PWR6X,
+  DIR_PWR7,
+  DIR_PWR8,
+  DIR_PWR9,
+  DIR_PWR10,
+  DIR_PWR_FUTURE,
+  DIR_64
+};
 }
 
 class GlobalValue;
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6 +115,7 @@
   HasAddiLoadFusion = false;
   HasAddisLoadFusion = false;
   

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7eb666b1556b: [PowerPC] Add support for -mcpu=pwr10 in both 
clang and llvm (authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80020/new/

https://reviews.llvm.org/D80020

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
 
 ; CHECK-NOT: is not a recognized processor for this target
 ; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
   if (CacheLineSize.getNumOccurrences() > 0)
 return CacheLineSize;
 
-  // On P7, P8 or P9 we have a cache line size of 128.
+  // Starting with P7 we have a cache line size of 128.
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
   // For P7 and P8, floating-point instructions have a 6-cycle latency and
   // there are two execution units, so unroll by 12x for latency hiding.
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+  // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
 
 namespace PPC {
   // -m directive values.
-  enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
-  };
+enum {
+  DIR_NONE,
+  DIR_32,
+  DIR_440,
+  DIR_601,
+  DIR_602,
+  DIR_603,
+  DIR_7400,
+  DIR_750,
+  DIR_970,
+  DIR_A2,
+  DIR_E500,
+  DIR_E500mc,
+  DIR_E5500,
+  DIR_PWR3,
+  DIR_PWR4,
+  DIR_PWR5,
+  DIR_PWR5X,
+  DIR_PWR6,
+  DIR_PWR6X,
+  DIR_PWR7,
+  DIR_PWR8,
+  DIR_PWR9,
+  DIR_PWR10,
+  DIR_PWR_FUTURE,
+  DIR_64
+};
 }
 
 class GlobalValue;
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ 

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 266283.
lei added a comment.

update as per reviewers comments


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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
 
 ; CHECK-NOT: is not a recognized processor for this target
 ; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
   if (CacheLineSize.getNumOccurrences() > 0)
 return CacheLineSize;
 
-  // On P7, P8 or P9 we have a cache line size of 128.
+  // Starting with P7 we have a cache line size of 128.
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
   // For P7 and P8, floating-point instructions have a 6-cycle latency and
   // there are two execution units, so unroll by 12x for latency hiding.
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+  // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
 
 namespace PPC {
   // -m directive values.
-  enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
-  };
+enum {
+  DIR_NONE,
+  DIR_32,
+  DIR_440,
+  DIR_601,
+  DIR_602,
+  DIR_603,
+  DIR_7400,
+  DIR_750,
+  DIR_970,
+  DIR_A2,
+  DIR_E500,
+  DIR_E500mc,
+  DIR_E5500,
+  DIR_PWR3,
+  DIR_PWR4,
+  DIR_PWR5,
+  DIR_PWR5X,
+  DIR_PWR6,
+  DIR_PWR6X,
+  DIR_PWR7,
+  DIR_PWR8,
+  DIR_PWR9,
+  DIR_PWR10,
+  DIR_PWR_FUTURE,
+  DIR_64
+};
 }
 
 class GlobalValue;
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6 +115,7 @@
   HasAddiLoadFusion = false;
   HasAddisLoadFusion = false;
   IsISA3_0 = 

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Amy Kwan via Phabricator via cfe-commits]

amyk accepted this revision.
amyk added a comment.

I think this looks good aside from the comments I had.




Comment at: llvm/lib/Target/PowerPC/PPCSubtarget.h:142
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;

Missing `IsISA3_1 = false;` in PPCSubtarget.cpp.


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp accepted this revision.
stefanp added a comment.

LGTM


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM aside from a couple of minor nits.




Comment at: clang/lib/Basic/Targets/PPC.cpp:319
 .Case("ppc64le", true)
+.Case("pwr10", true)
 .Case("pwr9", true)

Please remove this since HTM was removed in P10.



Comment at: clang/test/Preprocessor/init-ppc64.c:644
+// PPCPOWER10:#define _ARCH_PWR7 1
+// PPCPOWER10:#define _ARCH_PWR9 1
+//

I am not sure what the story is with not checking for `_ARCH_PWR8` for the P9 
test, but I don't think we need to continue that precedent.


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Amy Kwan via Phabricator via cfe-commits]

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp:653
 
   // On P7, P8 or P9 we have a cache line size of 128.
   unsigned Directive = ST->getCPUDirective();

Should this comment be updated to include P10 as well?


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Victor Huang via Phabricator via cfe-commits]

NeHuang marked an inline comment as done.
NeHuang added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:339
 
   if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
   llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {

lei wrote:
> NeHuang wrote:
> > I think we also need to check for `ArchDefinePwr10` and `ArchDefineFuture` 
> > based on the comment  "// We have __float128 on PPC but not power 9 and 
> > above."
> > 
> > `!(ArchDefs & ArchDefinePwr9)` -> `!(ArchDefs & (ArchDefinePwr9 | 
> > ArchDefinePwr10 | ArchDefineFuture))`
> I would think this would be redundant since `-mcpu=pwr10` also defines 
> `ArchDefinePwr9` ...
Yeah. That makes sense. Thanks for the explanation!


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:339
 
   if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
   llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {

NeHuang wrote:
> I think we also need to check for `ArchDefinePwr10` and `ArchDefineFuture` 
> based on the comment  "// We have __float128 on PPC but not power 9 and 
> above."
> 
> `!(ArchDefs & ArchDefinePwr9)` -> `!(ArchDefs & (ArchDefinePwr9 | 
> ArchDefinePwr10 | ArchDefineFuture))`
I would think this would be redundant since `-mcpu=pwr10` also defines 
`ArchDefinePwr9` ...



Comment at: llvm/lib/Target/PowerPC/PPC.td:211
+ "true",
+ "Enable instructions added in ISA 3.1.">;
 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", 
"true",

steven.zhang wrote:
> Nit: no ending dot.
That's needed to indicate the end of the sentence.  Similar to line 208.


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 266073.
lei marked 7 inline comments as done.
lei added a comment.

address review comments


Repository:
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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
 
 ; CHECK-NOT: is not a recognized processor for this target
 ; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -654,7 +654,8 @@
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -688,7 +689,8 @@
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
 
 namespace PPC {
   // -m directive values.
-  enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
-  };
+enum {
+  DIR_NONE,
+  DIR_32,
+  DIR_440,
+  DIR_601,
+  DIR_602,
+  DIR_603,
+  DIR_7400,
+  DIR_750,
+  DIR_970,
+  DIR_A2,
+  DIR_E500,
+  DIR_E500mc,
+  DIR_E5500,
+  DIR_PWR3,
+  DIR_PWR4,
+  DIR_PWR5,
+  DIR_PWR5X,
+  DIR_PWR6,
+  DIR_PWR6X,
+  DIR_PWR7,
+  DIR_PWR8,
+  DIR_PWR9,
+  DIR_PWR10,
+  DIR_PWR_FUTURE,
+  DIR_64
+};
 }
 
 class GlobalValue;
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1305,6 +1305,7 @@
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
+  case PPC::DIR_PWR10:
   case PPC::DIR_PWR_FUTURE:
 setPrefLoopAlignment(Align(16));
 setPrefFunctionAlignment(Align(16));
@@ -14912,6 +14913,7 @@
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
+  case PPC::DIR_PWR10:
   case PPC::DIR_PWR_FUTURE: {
 if (!ML)
   break;
@@ -16101,6 +16103,7 @@
   // vector7   2  2
   return true;
 case PPC::DIR_PWR9:
+case 

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:339
 
   if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
   llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {

I think we also need to check for `ArchDefinePwr10` and `ArchDefineFuture` 
based on the comment  "// We have __float128 on PPC but not power 9 and above."

`!(ArchDefs & ArchDefinePwr9)` -> `!(ArchDefs & (ArchDefinePwr9 | 
ArchDefinePwr10 | ArchDefineFuture))`


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Stefan Pintilie via Phabricator via cfe-commits]

stefanp added a comment.

Most of my comments are related to the fact that we are now inserting P10 
 between P9  and 
Future and so a few things need to change for the Future code to sit on top of 
P10  now.




Comment at: clang/test/Preprocessor/init-ppc64.c:652
 // PPCFUTURE:#define _ARCH_PPCSQ 1
 // PPCFUTURE:#define _ARCH_PWR4 1
 // PPCFUTURE:#define _ARCH_PWR5 1

Since we are adding P10 between P9 and Future we should add another line here:
```
PPCFUTURE:#define _ARCH_PWR10 1
```



Comment at: llvm/lib/Target/PowerPC/PPC.td:340
+  list P10SpecificFeatures =
+[FeaturePrefixInstrs, FeaturePCRelativeMemops];
+  list P10InheritableFeatures =

I think these can be moved up to `P10AdditionalFeatures`. That way everything 
on P10 is now inheritable by future and we don't have to specify anything for 
`FutureSpecificFeatures`.



Comment at: llvm/lib/Target/PowerPC/PPC.td:351
   list FutureSpecificFeatures =
 [FeaturePrefixInstrs, FeaturePCRelativeMemops];
   list FutureInheritableFeatures =

These features are now no longer `FutureSpecificFeatures` I would think that 
they would now be part of Power10 and should be inherited by future CPU. 



Comment at: llvm/test/CodeGen/PowerPC/check-cpu.ll:11
 
 ; Test mcpu=future that should be recognized on PowerPC.
 

nit:
We should probably update this comment too.


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Qing Shan Zhang via Phabricator via cfe-commits]

steven.zhang added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:272
 .Default(false);
 
   Features["qpx"] = (CPU == "a2q");

Do we miss to define this macro ?
```
 __POWER10_VECTOR__
```



Comment at: llvm/lib/Target/PowerPC/PPC.td:211
+ "true",
+ "Enable instructions added in ISA 3.1.">;
 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", 
"true",

Nit: no ending dot.


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Qing Shan Zhang via Phabricator via cfe-commits]

steven.zhang added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:272
 .Default(false);
 
   Features["qpx"] = (CPU == "a2q");

steven.zhang wrote:
> Do we miss to define this macro ?
> ```
>  __POWER10_VECTOR__
> ```
Well, pls ignore this comments as that macro should be added when p10 vector 
feature is added.


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Amy Kwan via Phabricator via cfe-commits]

amyk added a comment.

I believe we're also missing `IsISA3_1 = false;` in `PPCSubtarget.cpp`.




Comment at: llvm/lib/Target/PowerPC/PPC.td:338
+  // still exist with the exception of those we know are Power9 specific.
+  list P10AdditionalFeatures = [DirectivePwr10];
+  list P10SpecificFeatures =

Are we missing `FeatureISA3_1` in `P10AdditionalFeatures`?


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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 264303.
lei retitled this revision from " [PowerPC] Add support for -mcpu=pwr10 in both 
clang and llvm" to "[PowerPC] Add support for -mcpu=pwr10 in both clang and 
llvm".
lei added a comment.

missed a file


Repository:
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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,6 +2,10 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
 ; Test mcpu=future that should be recognized on PowerPC.
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -654,7 +654,8 @@
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -688,7 +689,8 @@
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
 
 namespace PPC {
   // -m directive values.
-  enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
-  };
+enum {
+  DIR_NONE,
+  DIR_32,
+  DIR_440,
+  DIR_601,
+  DIR_602,
+  DIR_603,
+  DIR_7400,
+  DIR_750,
+  DIR_970,
+  DIR_A2,
+  DIR_E500,
+  DIR_E500mc,
+  DIR_E5500,
+  DIR_PWR3,
+  DIR_PWR4,
+  DIR_PWR5,
+  DIR_PWR5X,
+  DIR_PWR6,
+  DIR_PWR6X,
+  DIR_PWR7,
+  DIR_PWR8,
+  DIR_PWR9,
+  DIR_PWR10,
+  DIR_PWR_FUTURE,
+  DIR_64
+};
 }
 
 class GlobalValue;
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1305,6 +1305,7 @@
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
+  case PPC::DIR_PWR10:
   case PPC::DIR_PWR_FUTURE:
 setPrefLoopAlignment(Align(16));
 setPrefFunctionAlignment(Align(16));
@@ -14896,6 +14897,7 @@
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
+  case PPC::DIR_PWR10:
   case PPC::DIR_PWR_FUTURE: {
 if (!ML)
   break;
@@ -16085,6 +16087,7 @@
   // vector7   2  2
   return true;
 case PPC::DIR_PWR9:
+case PPC::DIR_PWR10:
 

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 264301.
lei added a comment.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

Add support in llvm.


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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Arch/PPC.cpp
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/init-ppc64.c
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/check-cpu.ll

Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,6 +2,10 @@
 ; RUN: -mcpu=future < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
 
 
 ; Test mcpu=future that should be recognized on PowerPC.
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -654,7 +654,8 @@
   unsigned Directive = ST->getCPUDirective();
   // Assume that Future CPU has the same cache line size as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 128;
 
   // On other processors return a default of 64 bytes.
@@ -688,7 +689,8 @@
   // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
   // Assume that future is the same as the others.
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
-  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+  Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+  Directive == PPC::DIR_PWR_FUTURE)
 return 12;
 
   // For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -57,6 +57,7 @@
 DIR_PWR7,
 DIR_PWR8,
 DIR_PWR9,
+DIR_PWR10,
 DIR_PWR_FUTURE,
 DIR_64
   };
@@ -138,6 +139,7 @@
   bool HasAddiLoadFusion;
   bool HasAddisLoadFusion;
   bool IsISA3_0;
+  bool IsISA3_1;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
+  bool isISA3_1() const { return IsISA3_1; }
   bool useLongCalls() const { return UseLongCalls; }
   bool hasFusion() const { return HasFusion; }
   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1305,6 +1305,7 @@
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
+  case PPC::DIR_PWR10:
   case PPC::DIR_PWR_FUTURE:
 setPrefLoopAlignment(Align(16));
 setPrefFunctionAlignment(Align(16));
@@ -14896,6 +14897,7 @@
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
+  case PPC::DIR_PWR10:
   case PPC::DIR_PWR_FUTURE: {
 if (!ML)
   break;
@@ -16085,6 +16087,7 @@
   // vector7   2  2
   return true;
 case PPC::DIR_PWR9:
+case PPC::DIR_PWR10:
 case PPC::DIR_PWR_FUTURE:
   //  typemul addshl
   // scalar5   2  2
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -51,6 +51,7 @@
 def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
 def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
 def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
+def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
 def DirectivePwrFuture
 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
 
@@ -205,6 +206,9 @@
 def FeatureISA3_0 :