[PATCH] D80723: [PowerPC] Convert vec_splats functions to macros

2020-06-07 Thread Qing Shan Zhang via Phabricator via cfe-commits 
steven.zhang added a comment.

It LGTM now except one comment on the test. And it seems that, we still have 
many other builtins implementation that didn't use the _Generic.




Comment at: clang/test/CodeGen/ppc-emmintrin.c:1
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target

So, why this line of comments is removed ? It seems that, the old test was 
generated by the script while the new one isn't. I expect both should generate 
by script. 


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[PATCH] D80723: [PowerPC] Convert vec_splats functions to macros

2020-05-31 Thread Colin Samples via Phabricator via cfe-commits 
vddvss updated this revision to Diff 267529.
vddvss marked an inline comment as done.
vddvss added a comment.

Updated revision to address @steven.zhang's good suggestion on the test case.

This also does `clang-format` on `altivec.h` to address the harbormaster 
failure, although I am inclined to do `/* clang-format off */`, since it is a 
lot less readable after running `clang-format`.


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Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/ppc-emmintrin.c
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/CodeGen/ppc-pmmintrin.c
  clang/test/CodeGen/ppc-smmintrin.c
  clang/test/CodeGen/ppc-tmmintrin.c
  clang/test/CodeGen/ppc-xmmintrin.c
  clang/test/CodeGen/pr44276.c

Index: clang/test/CodeGen/pr44276.c
===
--- /dev/null
+++ clang/test/CodeGen/pr44276.c
@@ -0,0 +1,22 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr8 %s -verify
+// expected-no-diagnostics
+
+// Check that this compiles
+
+#include 
+
+void test() {
+  static vector unsigned char a = vec_splats('1');
+  static vector signed char b = vec_splats((signed char)'1');
+  static vector unsigned short c = vec_splats((unsigned short)1U);
+  static vector signed short d = vec_splats((short)1);
+  static vector unsigned int e = vec_splats(1U);
+  static vector signed int f = vec_splats(1);
+  static vector float g = vec_splats(1.0f);
+  static vector unsigned long long h = vec_splats(1ULL);
+  static vector signed long long i = vec_splats(1LL);
+  static vector double j = vec_splats(1.0);
+  static vector unsigned __int128 k = vec_splats((__int128)1);
+  static vector signed __int128 l = vec_splats((__int128)1);
+}
Index: clang/test/CodeGen/ppc-xmmintrin.c
===
--- clang/test/CodeGen/ppc-xmmintrin.c
+++ clang/test/CodeGen/ppc-xmmintrin.c
@@ -1,4 +1,3 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
@@ -66,11 +65,13 @@
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG25:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG25]])
+// CHECK-NEXT: [[REG26A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG25]], i32 0
+// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG26A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG28]])
+// CHECK-NEXT: [[REG29A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG28]], i32 0
+// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG29A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG29]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG30]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
@@ -86,11 +87,13 @@
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG37]])
+// CHECK-NEXT: [[REG38A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG37]], i32 0
+// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG38A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG39:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG38]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG39]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG40:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG40]])
+// CHECK-NEXT: [[REG41A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG40]], i32 0
+// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG41A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64>

[PATCH] D80723: [PowerPC] Convert vec_splats functions to macros

2020-05-28 Thread Qing Shan Zhang via Phabricator via cfe-commits 
steven.zhang added inline comments.



Comment at: clang/lib/Headers/altivec.h:13670
+  )
+#elif defined(__VSX__)
+#define vec_splats(N) \

vddvss wrote:
> steven.zhang wrote:
> > I am not sure if this is by intention. It is not semantics the same with 
> > this change. Before the change, if VSX is off, and POWER8_VECTOR && 
> > __powerpc64__ is on, vector signed/unsigned long long, signed/unsigned 
> > __int128 is not a valid candidate of vec_splats. But with this patch, they 
> > are.
> No intention to change semantics. But AFICT, we throw an error if 
> POWER8_VECTOR is on and VSX is off: 
> https://github.com/llvm/llvm-project/blob/master/clang/lib/Basic/Targets/PPC.cpp#L222
Hmm, we are making assumption that, POWER8_VECTOR enables the VSX, and it is 
true. Thank you for pointing out this.



Comment at: clang/test/CodeGen/pr44276.c:3
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-unknown -mcpu=pwr8 %s 
-o - | FileCheck %s
+

The assembly output is not your test point. How about doing it as this:
```
// RUN: %clang_cc1 -S -emit-llvm -triple powerpc64-unknown-unknown -target-cpu 
pwr8 %s
// expected-no-diagnostics
```


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[PATCH] D80723: [PowerPC] Convert vec_splats functions to macros

2020-05-28 Thread Colin Samples via Phabricator via cfe-commits 
vddvss added inline comments.



Comment at: clang/lib/Headers/altivec.h:13670
+  )
+#elif defined(__VSX__)
+#define vec_splats(N) \

steven.zhang wrote:
> I am not sure if this is by intention. It is not semantics the same with this 
> change. Before the change, if VSX is off, and POWER8_VECTOR && __powerpc64__ 
> is on, vector signed/unsigned long long, signed/unsigned __int128 is not a 
> valid candidate of vec_splats. But with this patch, they are.
No intention to change semantics. But AFICT, we throw an error if POWER8_VECTOR 
is on and VSX is off: 
https://github.com/llvm/llvm-project/blob/master/clang/lib/Basic/Targets/PPC.cpp#L222


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[PATCH] D80723: [PowerPC] Convert vec_splats functions to macros

2020-05-28 Thread Qing Shan Zhang via Phabricator via cfe-commits 
steven.zhang added inline comments.



Comment at: clang/lib/Headers/altivec.h:13670
+  )
+#elif defined(__VSX__)
+#define vec_splats(N) \

I am not sure if this is by intention. It is not semantics the same with this 
change. Before the change, if VSX is off, and POWER8_VECTOR && __powerpc64__ is 
on, vector signed/unsigned long long, signed/unsigned __int128 is not a valid 
candidate of vec_splats. But with this patch, they are.


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[PATCH] D80723: [PowerPC] Convert vec_splats functions to macros

2020-05-28 Thread Colin Samples via Phabricator via cfe-commits 
vddvss created this revision.
vddvss added reviewers: nemanjai, PowerPC.
Herald added subscribers: cfe-commits, shchenz, kbarton.
Herald added a project: clang.

This commit converts the `vec_splats` functions in altivec.h to macros, solving 
an issue where `vec_splats` calls could not assign to variables of static 
storage duration, such as:

  static vector int x = vec_splats(1);

Since `vec_splats` was implemented as a function, code such as in this example 

 would result in a compile-time error in `clang`. This differs from `gcc`, 
which allows this construct.

This updates tests accordingly, and fixes PR44276 and PR44455. Sorry for the 
delay in getting this to you.


Repository:
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https://reviews.llvm.org/D80723

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/ppc-emmintrin.c
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/CodeGen/ppc-pmmintrin.c
  clang/test/CodeGen/ppc-smmintrin.c
  clang/test/CodeGen/ppc-tmmintrin.c
  clang/test/CodeGen/ppc-xmmintrin.c
  clang/test/CodeGen/pr44276.c

Index: clang/test/CodeGen/pr44276.c
===
--- /dev/null
+++ clang/test/CodeGen/pr44276.c
@@ -0,0 +1,26 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-unknown -mcpu=pwr8 %s -o - | FileCheck %s
+
+// Check that this compiles
+
+#include 
+
+// CHECK-LABEL: @test(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret void
+//
+void test() {
+  static vector unsigned char a = vec_splats('1');
+  static vector signed char b = vec_splats((signed char)'1');
+  static vector unsigned short c = vec_splats(1U);
+  static vector signed short d = vec_splats(1);
+  static vector unsigned int e = vec_splats(1U);
+  static vector signed int f = vec_splats(1);
+  static vector float g = vec_splats(1.0f);
+  static vector unsigned long long h = vec_splats(1ULL);
+  static vector signed long long i = vec_splats(1LL);
+  static vector double j = vec_splats(1.0);
+  static vector unsigned __int128 k = vec_splats((__int128)1);
+  static vector signed __int128 l = vec_splats((__int128)1);
+}
Index: clang/test/CodeGen/ppc-xmmintrin.c
===
--- clang/test/CodeGen/ppc-xmmintrin.c
+++ clang/test/CodeGen/ppc-xmmintrin.c
@@ -1,4 +1,3 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
@@ -66,11 +65,13 @@
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG25:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG25]])
+// CHECK-NEXT: [[REG26A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG25]], i32 0
+// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG26A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG28]])
+// CHECK-NEXT: [[REG29A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG28]], i32 0
+// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG29A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG29]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG30]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
@@ -86,11 +87,13 @@
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG37]])
+// CHECK-NEXT: [[REG38A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG37]], i32 0
+// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG38A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG39:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG38]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG39]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align