[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
This revision was automatically updated to reflect the committed changes.
Closed by commit rG93b99728b167: [AArch64] Add pipeline model for
HiSilicons TSV110 (authored by Elvina).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D89972/new/
https://reviews.llvm.org/D89972
Files:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64SchedTSV110.td
llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -20,6 +20,7 @@
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=tsv110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -7,6 +7,7 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=tsv110 < %s | FileCheck %s
; Make sure that inst-combine fuses the multiply add in the addressing mode of
; the load.
Index: llvm/lib/Target/AArch64/AArch64SchedTSV110.td
===
--- /dev/null
+++ llvm/lib/Target/AArch64/AArch64SchedTSV110.td
@@ -0,0 +1,745 @@
+//==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the machine model for Huawei TSV110 to support
+// instruction scheduling and other instruction cost heuristics.
+//
+//===--===//
+
+// ===-===//
+// The following definitions describe the simpler per-operand machine model.
+// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
+
+// Huawei TSV110 scheduling machine model.
+def TSV110Model : SchedMachineModel {
+ let IssueWidth= 4; // 4 micro-ops dispatched per cycle.
+ let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
+ let LoopMicroOpBufferSize = 16;
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
+ let CompleteModel = 1;
+
+ list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+PAUnsupported.F);
+}
+
+// Define each kind of processor resource and number available on the TSV110,
+// which has 8 pipelines, each with its own queue where micro-ops wait for
+// their operands and issue out-of-order to one of eight execution pipelines.
+let SchedModel = TSV110Model in {
+ def TSV110UnitALU : ProcResource<1>; // Int ALU
+ def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
+ def TSV110UnitMDU : ProcResource<1>; // Multi-Cycle
+ def TSV110UnitFSU1 : ProcResource<1>; // FP/ASIMD
+ def TSV110UnitFSU2 : ProcResource<1>; // FP/ASIMD
+ def TSV110UnitLdSt : ProcResource<2>; // Load/Store
+
+ def TSV110UnitF : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2]>;
+ def TSV110UnitALUAB : ProcResGroup<[TSV110UnitALU, TSV110UnitAB]>;
+ def TSV110UnitFLdSt : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2, TSV110UnitLdSt]>;
+}
+
+let SchedModel = TSV110Model in {
+
+//===--===//
+// Map the target-defined scheduler read/write resources and latency for
+// TSV110
+
+// Integer ALU
+def : WriteRes { let Latency = 1; }
+def : WriteRes { let Latency = 1; }
+def : WriteRes { let Latency = 2; }
+def : WriteRes { let Latency = 2; }
+def : WriteRes { let Latency = 1; }
+def : WriteRes { let Latency = 1; }
+
+// Integer Mul/MAC/Div
+def : WriteRes { let Latency
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
Elvina added a comment. @SjoerdMeijer thanks for the review! @bryanpkc does everything look fine? Can I commit it? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
SjoerdMeijer accepted this revision. SjoerdMeijer added a comment. This revision is now accepted and ready to land. I haven't checked the instruction descriptions in detail, but the overall structure looks good to me. Perhaps wait a day with committing in case @bryanpkc has more comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
Elvina marked 6 inline comments as done. Elvina added inline comments. Comment at: clang/test/Driver/aarch64-cpus.c:298 +// RUN: %clang -target aarch64 -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s +// RUN: %clang -target aarch64 -mlittle-endian -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s SjoerdMeijer wrote: > This is unrelated to the scheduling model. > Looks like good tests to me, so please go ahead and commit this separately, > no need for another review. Will do, thanks Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110Details.td:1 +//==- AArch64SchedTSV110Details.td - TSV110 Scheduling Defs -*- tablegen -*-==// +// SjoerdMeijer wrote: > Just a nit/question on this new file: is there a benefit of having this > separately? If there's none, just merge into AArch64SchedTSV110.td, as that > would be more consistent with other schedmodels? No specific needs to do this, so I'll merge all into one file. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
Elvina updated this revision to Diff 301821.
Elvina marked 2 inline comments as done.
Elvina added a comment.
Merged all into one AArch64SchedTSV110.td, removed aarch64-cpus.c test from
this patch
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D89972/new/
https://reviews.llvm.org/D89972
Files:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64SchedTSV110.td
llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -20,6 +20,7 @@
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=tsv110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -7,6 +7,7 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=tsv110 < %s | FileCheck %s
; Make sure that inst-combine fuses the multiply add in the addressing mode of
; the load.
Index: llvm/lib/Target/AArch64/AArch64SchedTSV110.td
===
--- /dev/null
+++ llvm/lib/Target/AArch64/AArch64SchedTSV110.td
@@ -0,0 +1,745 @@
+//==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the machine model for Huawei TSV110 to support
+// instruction scheduling and other instruction cost heuristics.
+//
+//===--===//
+
+// ===-===//
+// The following definitions describe the simpler per-operand machine model.
+// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
+
+// Huawei TSV110 scheduling machine model.
+def TSV110Model : SchedMachineModel {
+ let IssueWidth= 4; // 4 micro-ops dispatched per cycle.
+ let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
+ let LoopMicroOpBufferSize = 16;
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
+ let CompleteModel = 1;
+
+ list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+PAUnsupported.F);
+}
+
+// Define each kind of processor resource and number available on the TSV110,
+// which has 8 pipelines, each with its own queue where micro-ops wait for
+// their operands and issue out-of-order to one of eight execution pipelines.
+let SchedModel = TSV110Model in {
+ def TSV110UnitALU : ProcResource<1>; // Int ALU
+ def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
+ def TSV110UnitMDU : ProcResource<1>; // Multi-Cycle
+ def TSV110UnitFSU1 : ProcResource<1>; // FP/ASIMD
+ def TSV110UnitFSU2 : ProcResource<1>; // FP/ASIMD
+ def TSV110UnitLdSt : ProcResource<2>; // Load/Store
+
+ def TSV110UnitF : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2]>;
+ def TSV110UnitALUAB : ProcResGroup<[TSV110UnitALU, TSV110UnitAB]>;
+ def TSV110UnitFLdSt : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2, TSV110UnitLdSt]>;
+}
+
+let SchedModel = TSV110Model in {
+
+//===--===//
+// Map the target-defined scheduler read/write resources and latency for
+// TSV110
+
+// Integer ALU
+def : WriteRes { let Latency = 1; }
+def : WriteRes { let Latency = 1; }
+def : WriteRes { let Latency = 2; }
+def : WriteRes { let Latency = 2; }
+def : WriteRes { let Latency = 1; }
+def : WriteRes { let Latency = 1; }
+
+// Integer Mul/MAC/Div
+def : WriteRes { let Latency = 12;
+
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
bryanpkc added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:9
+//
+// This file defines the machine model for ARM Huawei TSV110 to support
+// instruction scheduling and other instruction cost heuristics.
I suggest deleting the word `ARM` here to avoid confusion.
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:28
+ list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F);
+}
Indent to align with the previous argument?
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:53
+
+//Integer ALU
+def : WriteRes { let Latency = 1; }
Nit: Leave a space after the `//` delimiter.
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:128
+
+// Detailed Refinedments
+//===--===//
Type: `Refinements`
Repository:
rG LLVM Github Monorepo
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[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
SjoerdMeijer added inline comments. Comment at: clang/test/Driver/aarch64-cpus.c:298 +// RUN: %clang -target aarch64 -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s +// RUN: %clang -target aarch64 -mlittle-endian -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s This is unrelated to the scheduling model. Looks like good tests to me, so please go ahead and commit this separately, no need for another review. Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110Details.td:1 +//==- AArch64SchedTSV110Details.td - TSV110 Scheduling Defs -*- tablegen -*-==// +// Just a nit/question on this new file: is there a benefit of having this separately? If there's none, just merge into AArch64SchedTSV110.td, as that would be more consistent with other schedmodels? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
Elvina added a comment. Gentle ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
Elvina added a comment. Failure on test "linux > HWAddressSanitizer-x86_64.TestCases::sizes.cpp" looks bogus. I found the same cases https://reviews.llvm.org/D89895 and https://reviews.llvm.org/D89964. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
Elvina created this revision.
Elvina added reviewers: bryanpkc, kristof.beyls, t.p.northover, SjoerdMeijer.
Elvina added projects: LLVM, clang.
Herald added subscribers: cfe-commits, jfb, hiraditya.
Elvina requested review of this revision.
This patch adds the scheduling and cost model for TSV110.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D89972
Files:
clang/test/Driver/aarch64-cpus.c
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64SchedTSV110.td
llvm/lib/Target/AArch64/AArch64SchedTSV110Details.td
llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -20,6 +20,7 @@
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=tsv110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -7,6 +7,7 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=tsv110 < %s | FileCheck %s
; Make sure that inst-combine fuses the multiply add in the addressing mode of
; the load.
Index: llvm/lib/Target/AArch64/AArch64SchedTSV110Details.td
===
--- /dev/null
+++ llvm/lib/Target/AArch64/AArch64SchedTSV110Details.td
@@ -0,0 +1,637 @@
+//==- AArch64SchedTSV110Details.td - TSV110 Scheduling Defs -*- tablegen -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the uop and latency details for the machine model for the
+// Huawei TSV110 subtarget.
+//
+//===--===//
+
+// Contains all of the TSV110 specific SchedWriteRes types. The approach
+// below is to define a generic SchedWriteRes for every combination of
+// latency and microOps. The naming conventions is to use a prefix, one field
+// for latency, and one or more microOp count/type designators.
+// Prefix: TSV110Wr
+// Latency: #cyc
+// MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
+//
+// e.g. TSV110Wr_6cyc_1ALU_6MDU_4LdSt means the total latency is 6 and there are
+// 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
+//
+
+//===--===//
+// Define Generic 1 micro-op types
+
+def TSV110Wr_1cyc_1AB: SchedWriteRes<[TSV110UnitAB]>{ let Latency = 1; }
+def TSV110Wr_1cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 1; }
+def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
+def TSV110Wr_1cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 1; }
+def TSV110Wr_1cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 1; }
+def TSV110Wr_1cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 1; }
+def TSV110Wr_1cyc_1LdSt : SchedWriteRes<[TSV110UnitLdSt]> { let Latency = 1; }
+
+def TSV110Wr_2cyc_1AB: SchedWriteRes<[TSV110UnitAB]>{ let Latency = 2; }
+def TSV110Wr_2cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 2; }
+def TSV110Wr_2cyc_1LdSt : SchedWriteRes<[TSV110UnitLdSt]> { let Latency = 2; }
+def TSV110Wr_2cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 2; }
+def TSV110Wr_2cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 2; }
+def TSV110Wr_2cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 2; }
+
+def TSV110Wr_3cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 3; }
+def TSV110Wr_3cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 3; }
+def TSV110Wr_3cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 3; }
+
+def
