[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-11 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 closed 
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-11 Thread Hubert Tong via cfe-commits 

hubert-reinterpretcast wrote:

The code formatting check failure seems to be a infrastructure problem: 
https://discourse.llvm.org/t/clang-format-github-action-cannot-find-merge-base/73894

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-11 Thread Stefan Pintilie via cfe-commits 

https://github.com/stefanp-ibm edited 
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-11 Thread Stefan Pintilie via cfe-commits 

https://github.com/stefanp-ibm approved this pull request.

Thank you for fixing this!
LGTM.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-11 Thread Stefan Pintilie via cfe-commits 


@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
-  else
-return TargetInfo::getGCCAddlRegNames();
+  return llvm::ArrayRef(GCCAddlRegNames);

stefanp-ibm wrote:

Okay fair enough. If GCC accepts there on ELFv1 then we can too. 

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-11 Thread Hubert Tong via cfe-commits 

https://github.com/hubert-reinterpretcast approved this pull request.

LGTM, but I am not sure if @stefanp-ibm continues to be concerned about 
enabling this for ABIs that have not been updated to specify a treatment of the 
VSX registers.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Chen Zheng via cfe-commits 


@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.

chenzheng1030 wrote:

Done.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 updated 
https://github.com/llvm/llvm-project/pull/68476

>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng 
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/3] [AIX] recognize vsr in inline asm for AIX

---
 clang/lib/Basic/Targets/PPC.cpp  | 3 ++-
 clang/lib/Basic/Targets/PPC.h| 3 ++-
 clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 4 
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e0abc069032e1ce..fa56d39fd2fdada 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,6 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 // Table of additional register names to use in user input.
 {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35},
@@ -828,7 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
+  if (ABI == "elfv2" || ABI == "aix")
 return llvm::ArrayRef(GCCAddlRegNames);
   else
 return TargetInfo::getGCCAddlRegNames();
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ef667b3d511f0e6..c2a18d77a60a510 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -385,6 +385,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public 
PPCTargetInfo {
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
   break;
 default:
   break;
@@ -418,11 +419,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public 
PPCTargetInfo {
 std::string DataLayout;
 
 if (Triple.isOSAIX()) {
-  // TODO: Set appropriate ABI for AIX platform.
   DataLayout = "E-m:a-Fi64-i64:64-n32:64";
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
   DataLayout = "e-m:e-Fn32-i64:64-n32:64";
   ABI = "elfv2";
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c 
b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..a8033f22073cc9f 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,10 @@
 
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
 // RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
 
 // This case is to test VSX register support in the clobbers list for inline 
asm.
 void testVSX (void) {

>From 0d44bd306dc330f3f6c920789f986ae30b970505 Mon Sep 17 00:00:00 2001
From: Chen Zheng 
Date: Sat, 7 Oct 2023 23:03:06 -0400
Subject: [PATCH 2/3] address comments

---
 clang/lib/Basic/Targets/PPC.cpp  | 7 ++-
 clang/lib/Basic/Targets/PPC.h| 3 +--
 clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 8 +---
 3 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa56d39fd2fdada..47cc8ee5db1b896 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
-// And this mapping applies to all OSes which runs on powerpc.
+// And this mapping applies to all OSes which run on powerpc.
 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 // Table of additional register names to use in user input.
 {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35},
@@ -829,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2" || ABI == "aix")
-return llvm::ArrayRef(GCCAddlRegNames);
-  else
-return TargetInfo::getGCCAddlRegNames();
+  return llvm::ArrayRef(GCCAddlRegNames);
 }
 
 static constexpr llvm::StringLiteral ValidCPUNames[] = {
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index

[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Hubert Tong via cfe-commits 


@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.

hubert-reinterpretcast wrote:

> I prefer to solve this in another patch with solution: for targets that have 
> no canonical name for physically overlapping registers, `ReturnCanonical` 
> should always be false.
> 
> What do you think?

I think the usage of `ReturnCanonical` is at least partially intended (and 
applies to the situation with vs0 -> f0). In particular, it is intended to 
diagnose (as GCC does):
```
void f(void) {
  register float f __asm__("fr1");
  __asm__ __volatile__ (
"fmul %0,%0,%0"
:
: "f"(f)
: "vs1"
  );
}
```

That diagnostic does not seem to operate for Clang (at least for PPC) even with 
a simpler case where the clobber is `fr1` though.

I think we can leave that for later. For now, with the current patch, I think a 
comment to say that these numbers are used for indexing into the `GCCRegNames` 
array would be correct. If you believe that is a problem, then an additional 
FIXME comment can be added.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Chen Zheng via cfe-commits 


@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.

chenzheng1030 wrote:

@hubert-reinterpretcast I think you are right. There is a legacy issue in the 
function `getNormalizedGCCRegisterName()`. Once `ReturnCanonical` is true for 
that function, current clang(without this patch) will use name f0 ~ f31 and v0 
~ v31 for vs0 ~ vs63 on ELFABIV2. And this patch extends this "issue" to AIX.

The `ReturnCanonical` was introduced in https://reviews.llvm.org/D15075 which 
was targeted for X86. Seems for X86, physically overlapping registers have 
canonical names, for example X86 ([eax|rax|al|ah] -> ax). But targets like PPC 
and SystemZ do not have such canonical register names, for example, PPC (vs0 -> 
f0), SystemZ(v0 -> f0) which are not right.

I prefer to solve this in another patch with solution: for targets that have no 
canonical name for physically overlapping registers, `ReturnCanonical` should 
always be false.

What do you think?

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 edited 
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Chen Zheng via cfe-commits 


@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.

chenzheng1030 wrote:

FP and VMX registers should have different DWARF number with VSX registers 
although on PPC they are physically overlapped.

Let me check the usage for the DWARF numbers...

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Chen Zheng via cfe-commits 


@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
-  else
-return TargetInfo::getGCCAddlRegNames();
+  return llvm::ArrayRef(GCCAddlRegNames);

chenzheng1030 wrote:

Accepting an non-exist(future defined) register in the asm clobber list should 
not cause any issue in the compiler side, I think. The register allocator can 
not allocate these future defined registers anyhow.

The more serious issue is that clang accepts vsx instructions in asm block even 
for targets that does not have VSX, see https://godbolt.org/z/rYnMbPPTE (gcc 
has same behavior.)

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Hubert Tong via cfe-commits 


@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
-  else
-return TargetInfo::getGCCAddlRegNames();
+  return llvm::ArrayRef(GCCAddlRegNames);

hubert-reinterpretcast wrote:

@stefanp-ibm, GCC does accept these register names for ELFv1: 
https://github.com/llvm/llvm-project/pull/68476#discussion_r1349529109

For the compiler, I think the main responsibility would be to understand that 
these registers may overlay non-volatile FP and VMX registers.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Hubert Tong via cfe-commits 


@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.

hubert-reinterpretcast wrote:

> To me, the DWARF number should be architecture specific, i.e., although the 
> ABIs are different, all these ABIs on same architecture should use same DWARF 
> register mapping, because the hardware registers are bound to architecture?

While that makes sense, I am not seeing elsewhere in the code comments that the 
DWARF numbers are being used. The code _does_ support (in 
`getNormalizedGCCRegisterName`) that these numbers are used to index into the 
`GCCRegNames` array.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-10 Thread Stefan Pintilie via cfe-commits 


@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
-  else
-return TargetInfo::getGCCAddlRegNames();
+  return llvm::ArrayRef(GCCAddlRegNames);

stefanp-ibm wrote:

This blanket addition of the vs registers for all ABIs makes me a little 
nervous. I'm not sure that all ABIs will (or do) support these registers. For 
example, we support ELFv1 but based on this: 
https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html#REG
I'm not sure it supports the vs registers.

Since we are doing this for AIX it may be safer just to explicitly mention 
XCOFF.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-09 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 edited 
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-09 Thread Chen Zheng via cfe-commits 


@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.

chenzheng1030 wrote:

This is what I get from DWARF spec:

Note that the register number represents a DWARF specific mapping of numbers 
onto the actual registers of a given architecture. The mapping should be chosen 
to gain optimal density and should be shared by all users of a given 
architecture. It is recommended that this mapping be defined by the ABI 
authoring committee for each architecture.

To me, the DWARF number should be architecture specific, i.e., although the 
ABIs are different, all these ABIs on same architecture should use same DWARF 
register mapping, because the hardware registers are bound to architecture?

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-09 Thread Hubert Tong via cfe-commits 


@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.

hubert-reinterpretcast wrote:

I am not sure it helps to appeal to the ELFABIv2 DWARF definition if we are no 
longer restraining this data to be used only under ELFABIv2. Instead, the usage 
here can be explained as the index numbers for the related FPRs and VRs in 
`GCCRegNames` above.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Chen Zheng via cfe-commits 


@@ -2,6 +2,10 @@
 
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
 // RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
 
 // This case is to test VSX register support in the clobbers list for inline 
asm.
 void testVSX (void) {

chenzheng1030 wrote:

Done, test case is updated to compileable by AIX system assembler.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Chen Zheng via cfe-commits 


@@ -807,6 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.

chenzheng1030 wrote:

Now always return `GCCAddlRegNames()` for all PPC ABIs including big-endian 
linux.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 updated 
https://github.com/llvm/llvm-project/pull/68476

>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng 
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/2] [AIX] recognize vsr in inline asm for AIX

---
 clang/lib/Basic/Targets/PPC.cpp  | 3 ++-
 clang/lib/Basic/Targets/PPC.h| 3 ++-
 clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 4 
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e0abc069032e1ce..fa56d39fd2fdada 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,6 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 // Table of additional register names to use in user input.
 {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35},
@@ -828,7 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
+  if (ABI == "elfv2" || ABI == "aix")
 return llvm::ArrayRef(GCCAddlRegNames);
   else
 return TargetInfo::getGCCAddlRegNames();
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ef667b3d511f0e6..c2a18d77a60a510 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -385,6 +385,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public 
PPCTargetInfo {
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
   break;
 default:
   break;
@@ -418,11 +419,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public 
PPCTargetInfo {
 std::string DataLayout;
 
 if (Triple.isOSAIX()) {
-  // TODO: Set appropriate ABI for AIX platform.
   DataLayout = "E-m:a-Fi64-i64:64-n32:64";
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
   DataLayout = "e-m:e-Fn32-i64:64-n32:64";
   ABI = "elfv2";
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c 
b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..a8033f22073cc9f 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,10 @@
 
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
 // RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
 
 // This case is to test VSX register support in the clobbers list for inline 
asm.
 void testVSX (void) {

>From 0d44bd306dc330f3f6c920789f986ae30b970505 Mon Sep 17 00:00:00 2001
From: Chen Zheng 
Date: Sat, 7 Oct 2023 23:03:06 -0400
Subject: [PATCH 2/2] address comments

---
 clang/lib/Basic/Targets/PPC.cpp  | 7 ++-
 clang/lib/Basic/Targets/PPC.h| 3 +--
 clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 8 +---
 3 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa56d39fd2fdada..47cc8ee5db1b896 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,7 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
-// And this mapping applies to all OSes which runs on powerpc.
+// And this mapping applies to all OSes which run on powerpc.
 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 // Table of additional register names to use in user input.
 {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35},
@@ -829,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2" || ABI == "aix")
-return llvm::ArrayRef(GCCAddlRegNames);
-  else
-return TargetInfo::getGCCAddlRegNames();
+  return llvm::ArrayRef(GCCAddlRegNames);
 }
 
 static constexpr llvm::StringLiteral ValidCPUNames[] = {
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index

[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 edited 
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Hubert Tong via cfe-commits 

https://github.com/hubert-reinterpretcast edited 
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Hubert Tong via cfe-commits 


@@ -2,6 +2,10 @@
 
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
 // RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
 
 // This case is to test VSX register support in the clobbers list for inline 
asm.
 void testVSX (void) {

hubert-reinterpretcast wrote:

The `%vs32` syntax is not accepted by the AIX system assembler. It seems to me 
that, as a front-end patch, this is not responsible for the recognition of the 
`%vs32` syntax in the assembly string, so perhaps (to have a more portable C 
test source) we should use plain `32` instead?

[aside: The IBM XL compilers accepted (without the percent sign and without 
usage checking; probably not in a documented manner) things like `r0`, etc. as 
alternatives to literal `0`, etc. in the assembly string.]

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Hubert Tong via cfe-commits 


@@ -807,6 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.

hubert-reinterpretcast wrote:

While likely true (e.g., GCC for big-endian Linux accepts these: 
https://godbolt.org/z/sGK7znYGx), this patch does not implement things that way.

For info, GCC will recognize these clobber names even with `-mcpu=power4`.

https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang


Changes

Extend `PPCTargetInfo::getGCCAddlRegNames()` to aix as well. The definition 
should be common between Linux PPC and AIX PPC.

I also use "abi" as the ABI name for AIX ABI. This aligns with LLVM 
PPCSubtarget:
```
  bool isAIXABI() const { return TargetTriple.isOSAIX(); }
  bool isSVR4ABI() const { return !isAIXABI(); }
  bool isELFv2ABI() const;
```

---
Full diff: https://github.com/llvm/llvm-project/pull/68476.diff


3 Files Affected:

- (modified) clang/lib/Basic/Targets/PPC.cpp (+2-1) 
- (modified) clang/lib/Basic/Targets/PPC.h (+2-1) 
- (modified) clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c (+4) 


``diff
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e0abc069032e1ce..fa56d39fd2fdada 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,6 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 // Table of additional register names to use in user input.
 {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35},
@@ -828,7 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
+  if (ABI == "elfv2" || ABI == "aix")
 return llvm::ArrayRef(GCCAddlRegNames);
   else
 return TargetInfo::getGCCAddlRegNames();
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ef667b3d511f0e6..c2a18d77a60a510 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -385,6 +385,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public 
PPCTargetInfo {
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
   break;
 default:
   break;
@@ -418,11 +419,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public 
PPCTargetInfo {
 std::string DataLayout;
 
 if (Triple.isOSAIX()) {
-  // TODO: Set appropriate ABI for AIX platform.
   DataLayout = "E-m:a-Fi64-i64:64-n32:64";
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
   DataLayout = "e-m:e-Fn32-i64:64-n32:64";
   ABI = "elfv2";
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c 
b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..a8033f22073cc9f 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,10 @@
 
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
 // RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
 
 // This case is to test VSX register support in the clobbers list for inline 
asm.
 void testVSX (void) {

``




https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)

2023-10-07 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 created 
https://github.com/llvm/llvm-project/pull/68476

Extend `PPCTargetInfo::getGCCAddlRegNames()` to aix as well. The definition 
should be common between Linux PPC and AIX PPC.

I also use "abi" as the ABI name for AIX ABI. This aligns with LLVM 
PPCSubtarget:
```
  bool isAIXABI() const { return TargetTriple.isOSAIX(); }
  bool isSVR4ABI() const { return !isAIXABI(); }
  bool isELFv2ABI() const;
```

>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng 
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH] [AIX] recognize vsr in inline asm for AIX

---
 clang/lib/Basic/Targets/PPC.cpp  | 3 ++-
 clang/lib/Basic/Targets/PPC.h| 3 ++-
 clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 4 
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e0abc069032e1ce..fa56d39fd2fdada 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,6 +807,7 @@ ArrayRef 
PPCTargetInfo::getGCCRegAliases() const {
 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
 // vs0 ~ vs31 is mapping to 32 - 63,
 // vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 // Table of additional register names to use in user input.
 {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35},
@@ -828,7 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
 };
 
 ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
-  if (ABI == "elfv2")
+  if (ABI == "elfv2" || ABI == "aix")
 return llvm::ArrayRef(GCCAddlRegNames);
   else
 return TargetInfo::getGCCAddlRegNames();
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ef667b3d511f0e6..c2a18d77a60a510 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -385,6 +385,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public 
PPCTargetInfo {
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
   break;
 default:
   break;
@@ -418,11 +419,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public 
PPCTargetInfo {
 std::string DataLayout;
 
 if (Triple.isOSAIX()) {
-  // TODO: Set appropriate ABI for AIX platform.
   DataLayout = "E-m:a-Fi64-i64:64-n32:64";
   LongDoubleWidth = 64;
   LongDoubleAlign = DoubleAlign = 32;
   LongDoubleFormat = ::APFloat::IEEEdouble();
+  ABI = "aix";
 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
   DataLayout = "e-m:e-Fn32-i64:64-n32:64";
   ABI = "elfv2";
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c 
b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..a8033f22073cc9f 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,10 @@
 
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
 // RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
 
 // This case is to test VSX register support in the clobbers list for inline 
asm.
 void testVSX (void) {

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