Re: [coreboot] coreboot community chat
Quick reminder: This is coming up tomorrow (about 18h from now) Looking forward to seeing you all Stefan * Stefan Reinauer [150507 06:05]: > Hi coreboot community! > > In order to have more face time and a more personal connection with each > other than it is possible on the coreboot IRC channel, I would like to > invite you to participate in a monthly video conference to discuss the > up and coming projects, ideas and issues that all of us are involved in. > > We suggest to have these meetings via Google Hangouts, as we have > figured out in the past that other alternatives like Mumble didn’t work > as well for us. > > So I would like to invite interested contributors of the community to > join us. The first video conference will be on Thursday, May 21th at > 9:15am Pacific Time (16:15 UTC). The meeting can be joined by clicking > on this link: http://goo.gl/SD6t3G. If, for some reason you can not > access Hangouts, we can try and call you (no promises). Please let me > know ahead of time if you need assistance! > > The agenda for the first meeting is available here: http://goo.gl/7E0zYz > > Looking forward to seeing y’all! > > Stefan > > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SPD CRC failed
On Wed, May 20, 2015 at 1:13 PM, Michael Gerlach wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > I forgot to mention that somehow the ram frequency is not detected > correctly... > > PLL busy...done > PLL didn't lock. Retrying at lower frequency > PLL busy...done > PLL didn't lock. Retrying at lower frequency > PLL busy...done > PLL didn't lock. Retrying at lower frequency > PLL busy...done > PLL didn't lock. Retrying at lower frequency > No lock frequency found > The SPD data should be read via SMBus long before PLL locking for the DRAM itself takes place. If you're unable to successfully read the SPDs, then it makes sense that later init would fail. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] Preparing a crowdfunding campaign for the ASUS KGPE-D16
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 17/05/15 15:11, Paul Menzel wrote: > Dear coreboot folks, > > > Timothy, congratulations again on making a coreboot port for the > ASUS KGPE-D16 and therefore completing your third coreboot port! > That’s really amazing! > > > Am Mittwoch, den 29.04.2015, 22:46 +0100 schrieb The Gluglug: >> You should crowd-fund the $35,000 figure, there are lots of >> people who will be interested in this. I personally will chip in, >> and I'd ask others to as well. > > I am thinking about organizing the crowdfunding campaign to raise > the money. > > If somebody else wants to do it, please speak up! > > As this is more or less a donation by the backers, the process > should be as open and transparent as possible. That’s why I am > sharing the following information publicly. > > 1. Giant Monkey Software Engineering [1], the German company I work > for, would be the organizing entity. As a company with five > employees and a GmbH it might have enough credibility so that > people would pledge/give their money to Giant Monkey compared to a > private person or company run by a single person. Giant Monkey also > has some PR/campaign knowledge, but most importantly knows a lot of > people in the marketing sector. > > 2. After receiving the money, Giant Monkey would contract Raptor > Engineering. > > 3. I’d like to have the domain campaign.coreboot.org redirect to > the campaign page at the crowdfunding platform or set up a simple > Web site there. > > 4. git-annex’ second funding was done by itself with PayPal. That > saves the 4 % fee most other crowdfunding platforms charge. > > Using a crowdfunding platform might be easier though, as they have > experience and also provide a big community of possible backers. > > Currently I’m thinking about Indiegogo, which Jolla also used to > fund the Jolla Tablet. I heard, Kickstarter is also great with a > big network. > > 5. I plan to raise 100.000 € (around $110.000) to upstream, that > includes *paid review* and running the campaign, the whole port. > (I’ll continue to use Euros.) More money would be used for stretch > goals. > > ?) 4.000 € Indiegogo fees ?) 35.000 € for Raptor Engineering for > upstreaming for basic port ?) 15.000 € for Raptor Engineering for > implementing support for S2R (S3) ?) 10.000 € for code review > (inclusively hardware) (just an estimate) ?) 2.000 € for Gluglug > to release images (I have not talked to Francis yet.) ?) 10.000 € > campaign goodies (cf. 7.) ?) 4.000 € taxes (probably a lot more, > depends if given money counts as donation) ?) 20.000 € Giant Monkey > for running the campaign (Web site, press, marketing, videos, mile > stone tasks (see below), …) > > (Stretch goal) ?) 15.000 € for Raptor Engineering for upstreaming > Family 15h support for the board > > 6. I’d start with a minimal Web site and campaign platform page and > see how big the momentum alone through the coreboot community is. > If we get 10.000 € in a week, I’d fully step in with a professional > campaign. Otherwise I’d stop the campaign. > > 7. As a thank you for backers, I think of a payload included in > the distributed coreboot based firmware image, reading a text file > from CBFS with the names of the backers and displaying it. (Or a > simple splash screen.) Of course just for those wanting it. Big > backers (25.000 €) get a board with one CPU and RAM and coreboot > preinstalled; medium backers (10.000 €) get some BLOB free laptop > for example (Rockchip Chromebook or some Lenovo board). flash ROM > chips are sent to backers donating 25 €. > > 8. Milestone tasks: At certain mile stones (probably each 10.000 > €), I’d promise some more tasks to improve coreboot or the port > (see the 5.000 € steps in the top). Possible are also SSL > certificates for coreboot infrastructure, promising to run a 32-bit > userspace build host, redesigning the Web site, implementing CBMEM > time stamp support in SeaBIOS and GRUB, supporting Google’s > verified boot, …. > > 9. Reasons for contributing > > ?) server, cluster companies; administrators Do hosting/server > companies besides coreinfo [5] with AMD based offers exist? That > means, is there a chance of getting big contributions? > > What about the Free Software Foundation (FSF), FSF Europe (FSFE), > Electronic Frontier Foundation (EFF)? What about governments? > > ?) free software enthusiasts I hope with the FSF, FSFE and EFF some > big organizations will be able to motivate a lot of people to > donate. ?) private “normal” people This is my main problem. > Alexandru Gagniuc uses(?)/used(?) the board as a workstation, but > the normal user will never use that expensive server board at home. > Therefore they will never hold it in their hands. In the end the > given money is a donation. Therefore, we need good arguments that > Jane User will participate. > > I have the bad feeling, that most of them won’t donate, as they do > not see the benefit as coreboot is h
Re: [coreboot] SPD CRC failed
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi! I added debug statements (http://pastebin.com/iSFstXmv) and realized that the calculated checksum is 0.. CLC_CRC : 0 SPD_CRC : ce66 Furthermore I had a look at src/device/dram/ddr3.c line 155 - The capacity is given with 4GB (as you see in the log) but the dram_print_spd_ddr3 output from dimm->size_mb is 8192MB O_o The first log was from a quite out-dated build - I reseted on 4679c41db292b80ce51c7d923e2f22258145522b.. - -> http://pastebin.com/Xxq0Lwyp Best regards, n3ph On 05/20/15 21:03, Timothy Pearson wrote: > On 05/20/2015 12:46 PM, Michael Gerlach wrote: >> -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 >> >> I guess this check is done by Lenovo BIOS in a different way? >> Because this board+ram has no problems booting with vendor >> BIOS... >> >> Unfortunately I do not have any other DDR3 modules to test. >> >> >> Best regards, >> >> n3ph > > It is possible the vendor BIOS ignores the checksum. Is there any > way to get a dump of the SPD contents while running Linux (e.g. via > decode-dimms)? > - -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQEcBAEBAgAGBQJVXOruAAoJEE1l5S41evqaRL4IAKCRiTtquLEQLtNhPsuMeKhx pC0Jk+p3TKJO7CelC8va/JY8P9TSwVLrgUglbbOMP5N/ufS4p4Vdeh06gzsQ6Rrl oO0XZKOy7wDlxUfgM16uxTvOCwtvqozcSReT1QQ4zMBAIujCL5wig5eMW+qdTeyI QjJSS2HmLXS3cZZDoE8qZGZ8ZEVBwt73q93Be5rxM6svagO7Et040dMSUDYMosd8 xi1iZZOgyiScq5375dSI/MX0bAGp2+lm1wbNZK9nULybttewDOSBcX0+mU1+jBnk TPXNGeNWHlFBMJesyXEJwUCB9fXLj/RMucuYITr6SMPTLoDX6K2yd59Qe95aErk= =wsZb -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SPD CRC failed
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I forgot to mention that somehow the ram frequency is not detected correctly... PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency No lock frequency found Here is the output from dmidecode -t 17: # dmidecode 2.12 # SMBIOS entry point at 0xdaa9e000 SMBIOS 2.7 present. Handle 0x0008, DMI type 17, 34 bytes Memory Device Array Handle: 0x0007 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 8192 MB Form Factor: SODIMM Set: None Locator: ChannelA-DIMM0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Kingston Serial Number: 302A9F79 Asset Tag: None Part Number: 9905428-095.D00LF Rank: Unknown Configured Clock Speed: 1600 MHz Handle 0x0009, DMI type 17, 34 bytes Memory Device Array Handle: 0x0007 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 8192 MB Form Factor: SODIMM Set: None Locator: ChannelB-DIMM0 Bank Locator: BANK 2 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Kingston Serial Number: 322A201D Asset Tag: None Part Number: 9905428-095.D00LF Rank: Unknown Configured Clock Speed: 1600 MHz best regards, n3ph On 05/20/15 21:03, Timothy Pearson wrote: > On 05/20/2015 12:46 PM, Michael Gerlach wrote: >> -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 >> >> I guess this check is done by Lenovo BIOS in a different way? >> Because this board+ram has no problems booting with vendor >> BIOS... >> >> Unfortunately I do not have any other DDR3 modules to test. >> >> >> Best regards, >> >> n3ph > > It is possible the vendor BIOS ignores the checksum. Is there any > way to get a dump of the SPD contents while running Linux (e.g. via > decode-dimms)? > - -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQEcBAEBAgAGBQJVXOsCAAoJEE1l5S41evqalq4H/068geAvMY2zZwbdqCOBUG35 9MqHkxWJ13/VDFh6bZ+Ys7neFUBgvTe4Wei/KElRVZqmNUjVDX513u0Wu7sH+hZY GeI3+gNSDrZ8WtMVwfuc9Q9kLly/bPg+bi6rmOtxciAgH6utnM/PdguryVuNv6+r +cu+lx4kV9JgCT+J7GH79DhRHrMwfcF9I7NcJ6naKHLWe7FvXwRh5gGY6X8f9szw LpQSU/dVJjrdw22ZoGkgWoxP7AMOaT0U4gGUOfNbza7FyoKRhdTMU/OQcIhAcwpC ukcVFPpvzxBHZqc8zLGsjodSyI+n5bV3s0Kg1Do41fBpSnLWWbIU3sSHhx9TxOY= =KKkr -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SPD CRC failed
On 05/20/2015 12:46 PM, Michael Gerlach wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS... Unfortunately I do not have any other DDR3 modules to test. Best regards, n3ph It is possible the vendor BIOS ignores the checksum. Is there any way to get a dump of the SPD contents while running Linux (e.g. via decode-dimms)? -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SPD CRC failed
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS... Unfortunately I do not have any other DDR3 modules to test. Best regards, n3ph On 05/20/15 19:20, Vadim Bendebury wrote: > SPD is some data saved on the memory module, available to the > processor to read to find out memory properies. These data are > protected by a check code (CRC) which allows the CPU to verify > that it read the data correctly. Apparently this check is failing > in your case. > > Some likely reasons could be a noisy i2c interface (used to read > SPD) or someone writing the SPD storage on memory module(s) and > corrupteding it. > > --vb > > > On Wed, May 20, 2015 at 8:51 AM, Michael Gerlach > wrote: Hi all, > > i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like > there are some issues regarding the size of the modules.. > > http://pastebin.com/mLcS6vhQ > > Best regards, > > > n3ph >> >> -- coreboot mailing list: coreboot@coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > - -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQEcBAEBAgAGBQJVXMh0AAoJEE1l5S41evqarKYIALphxsdF9WcQ4g+p561oG6TK VM0c3uRZF+TtISKZ+9h4zbBEISezcYWae0Fyvw6dm3xNzNn6u70aAsYvCXHFHgnu kk/hWxxSN8wIjWha4DZOmHxRxczMJF5cXsPIEWazIU1ftgnid37Ce2JEViDtGMX5 LGB+yKY5L32hkWzUo2g/Ob1A5TdX80ESsAWlxHaWbqRCn0j7BC1o7UT48DfaKAuv wi5mQnW4L+X8r+q9t1f0nv2mGHeGRlU8rXmJ0d+dExAwdPZz+EW4NPHY2brMBT3a 1xh+OVAKkaJXL4ZI1TyaaODRltHDRrZ63g3laVOJR4k6+sA2rI6Q+1DUznhFB6k= =Qthr -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SPD CRC failed
SPD is some data saved on the memory module, available to the processor to read to find out memory properies. These data are protected by a check code (CRC) which allows the CPU to verify that it read the data correctly. Apparently this check is failing in your case. Some likely reasons could be a noisy i2c interface (used to read SPD) or someone writing the SPD storage on memory module(s) and corrupteding it. --vb On Wed, May 20, 2015 at 8:51 AM, Michael Gerlach wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > Hi all, > > i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like > there are some issues regarding the size of the modules.. > > http://pastebin.com/mLcS6vhQ > > Best regards, > > > n3ph > -BEGIN PGP SIGNATURE- > Version: GnuPG v2 > > iQEcBAEBAgAGBQJVXK2LAAoJEE1l5S41evqaCa8IAMqXBkzXdd72Vsi4mJ6MT73e > V3SMLABBJZ/IdEtea1HixhaTYVgyhghMsNsw3rgPSugN0bPKCutL647xz8xORv2r > hHQWDO0VF4KScPtGH1cG6YgtZuVB+IJZusM2SqR5WRikGqAV3jn0q1EQbW2CFG4K > JzaqhVHUYta/iDi3utvT66CmlJuzr6A+PneB2NvrWc61inHzT8sLM/r55J6zyBH3 > 4IOw15wJTwPkogHrGeN5artKt7qeKgdUv8VrZZPWtO86qW8QroexQND5mlc+yqyq > IQBQ0uzm8FkBkI8WeYQvMCLnfd6iW57pGnxQysf+soDy8+1+/c7xAqkXp5nn3b8= > =QBlQ > -END PGP SIGNATURE- > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] SPD CRC failed
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi all, i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like there are some issues regarding the size of the modules.. http://pastebin.com/mLcS6vhQ Best regards, n3ph -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQEcBAEBAgAGBQJVXK2LAAoJEE1l5S41evqaCa8IAMqXBkzXdd72Vsi4mJ6MT73e V3SMLABBJZ/IdEtea1HixhaTYVgyhghMsNsw3rgPSugN0bPKCutL647xz8xORv2r hHQWDO0VF4KScPtGH1cG6YgtZuVB+IJZusM2SqR5WRikGqAV3jn0q1EQbW2CFG4K JzaqhVHUYta/iDi3utvT66CmlJuzr6A+PneB2NvrWc61inHzT8sLM/r55J6zyBH3 4IOw15wJTwPkogHrGeN5artKt7qeKgdUv8VrZZPWtO86qW8QroexQND5mlc+yqyq IQBQ0uzm8FkBkI8WeYQvMCLnfd6iW57pGnxQysf+soDy8+1+/c7xAqkXp5nn3b8= =QBlQ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
