[coreboot] unbricking an Acer CB5

[Holger Brunn]

Dear readers,

I played with compiling my own coreboot image for my Acer CB5 [1] and failed 
miserably - the bios is messed up and the device won't boot any more. Now I'm 
busy following some guides to undo the damage [2], [3] by flashing the 
original bios again, but given I'm quite clueless about hardware, I'd like to 
ask you for advice about how to proceed:

I ordered a Raspberry PI, some connector cables [4], and then I probably need 
a clip to connect the chip [5].

My question to you is how to locate the chip? The mainboard looks like that: 
http://opensource.holgerbrunn.net/debian-on-acer-cb5/images/DSC01629.JPG and 
the only chip that looks like those in the examples is U37 in the lower right. 
Is there any way to know beforehand if it's the correct one? And then when 
connecting the pins, can I look up somewhere what the correct assignment is or 
is this trial and error? I can't read what is printed on it, but if relevant, 
I'll get a magnifying glass to post the text.

Thank you a lot in advance, and be sure that I won't come back whining if 
anything goes wrong and I fry the chip following your advice - that's entirely 
my fault then.

I'll log the process on the above website if successful so that the next 
person messing this up won't have to bother you.

Regards,
Holger

Links:
[1] 
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices/acer-cb5-311-chromebook-13
[2] http://www.tnhh.net/2014/08/25/unbricking-chromebook-with-beaglebone.html
[3] https://johnlewis.ie/unbricking-a-samsung-series-5-550-chromebook
[4] 
https://www.conrad.nl/nl/raspberry-pi-verbindingskabel-rb-cb5-025-bont-banana-pi-pcduino-arduino-raspberry-pi-a-b-b-1290220.html?sc.ref=Homepage
[5] http://www.digikey.nl/product-detail/en/5250/501-1311-ND/745102


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Re: [coreboot] coreinfo "General Protection Fault Exception"

[Maxime de Roucy]

Le dimanche 06 septembre 2015 à 16:20 +0200, Maxime de Roucy a écrit :
> Hello,
> 
> On a pcengines apu1 when I tried to leave coreinfo (press ESC) I get 
> a "General Protection Fault Exception".

I forget to mention I build coreinfo on a x86_64 Archlinux with :

cd …/coreboot/payloads/coreinfo
make LIBPAYLOAD_DIR=../libpayload/install 
CC=…/coreboot/util/crossgcc/xgcc/bin/i386-elf-gcc

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Maxime de Roucy

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[coreboot] Is flashrom safe on the x220 with coreboot?

[James Heald]

Hi there!

Just curious, I was able to successfully (albeit maybe not very
intelligently) read the flash chip on my lappy twice, and it read
successfully. However, since the x220 is not "officially" supported by
flashrom I has to use laptop:force_i_want_a_brick.

I'm curious if anyone with the x220 has reflashed coreboot (multiple times
even?) on their x220 and not had any issues. I *thought* I read somewhere
that since the firmware is unlocked it was safe to do, though I could have
been reading something for another laptop.

Thanks!

Jim
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Re: [coreboot] pcengines apu1 nvram support

[Maxime de Roucy]

Le dimanche 06 septembre 2015 à 16:30 +0200, Maxime de Roucy a écrit :
> I made a patch for the pcengines apu1 board to support nvram
> (HAVE_OPTION_TABLE).
> I made/adapt this patch from the "Sage" source available at
> http://www.pcengines.ch/howto.php#CoreBoot

I change the patch a little by adding a cmos.default file.
-- 
Regards
Maxime de Roucydiff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index b1b19c9..7ea1821 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
 
diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default
new file mode 100644
index 000..8022b63
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.default
@@ -0,0 +1,16 @@
+boot_option=Fallback
+last_boot=Fallback
+ECC_memory=Disable
+baud_rate=115200
+hw_scrubber=Disable
+interleave_chip_selects=Disable
+max_mem_clock=DDR3-1066
+multi_core=Enable
+power_on_after_fail=Disable
+debug_level=Emerg
+boot_first=Network
+boot_second=Network
+boot_third=Network
+slow_cpu=off
+nmi=Disable
+iommu=Disable
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
new file mode 100755
index 000..2f8d26b
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -0,0 +1,79 @@
+entries
+
+0  384   r   0reserved_memory
+384  1   e   4boot_option
+385  1   e   4last_boot
+386  1   e   1ECC_memory
+388  4   r   0reboot_bits
+392  3   e   5baud_rate
+395  1   e   1hw_scrubber
+396  1   e   1interleave_chip_selects
+397  2   e   8max_mem_clock
+399  1   e   2multi_core
+400  1   e   1power_on_after_fail
+412  4   e   6debug_level
+416  4   e   7boot_first
+420  4   e   7boot_second
+424  4   e   7boot_third
+428  4   h   0boot_index
+432  8   h   0boot_countdown
+440  4   e   9slow_cpu
+444  1   e   1nmi
+445  1   e   1iommu
+728256   h   0user_data
+984 16   h   0check_sum
+# Reserve the extended AMD configuration registers
+100024   r   0amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 0 Emerg
+6 1 Alert
+6 2 Crit
+6 3 Err
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10Fallback_Floppy
+8 0 DDR3-1600
+8 1 DDR3-1333
+8 2 DDR3-1066
+8 3 DDR3-800
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+


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[coreboot] Support intel Bay-trail tablet pc board

[Adil producer]

Hi,
My name is Adil. I with my friend developing console for smart home system
based on Intel Z3735g tablet pc motherboard. We planning use coreboot for
booting write it on SPI flash.
Now we have two Chinese tablet pc motherboard we BIOS on Winbond 25Q64FWSIG.
But we don't found in supported hardware list Bay-trail chips. We need help
to prepare firmware for this boot. Can you help us?
If we successful boot on this motherboard - we send you all instructions
and Bay-trail chips can supported coreboot.

Thanks.
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[coreboot] coreinfo "General Protection Fault Exception"

[Maxime de Roucy]

Hello,

On a pcengines apu1 when I tried to leave coreinfo (press ESC) I get a
"General Protection Fault Exception".

I attached my .config file of coreinfo (it's the default configuration)
and the console output when coreinfo crash.
-- 
Regards
Maxime de Roucy#
# Automatically generated file; DO NOT EDIT.
# coreinfo Configuration
#

#
# General settings
#
CONFIG_SHOW_DATE_TIME=y
CONFIG_PAYLOAD_INFO_NAME="coreinfo"
CONFIG_PAYLOAD_INFO_LISTNAME="System Information"
CONFIG_PAYLOAD_INFO_DESC="Display information about the system"
CONFIG_PAYLOAD_INFO_VERSION="0.1"

#
# Modules
#
CONFIG_MODULE_COREBOOT=y
CONFIG_MODULE_MULTIBOOT=y
CONFIG_MODULE_CPUINFO=y
CONFIG_MODULE_PCI=y
CONFIG_MODULE_NVRAM=y
CONFIG_MODULE_BOOTLOG=y
CONFIG_MODULE_RAMDUMP=y
# CONFIG_MODULE_LAR is not set
CONFIG_MODULE_CBFS=y
General Protection Fault Exception
Error code: 0x20 - descriptor 0x4 in the GDT, internal to the CPU
EIP:0x000fd272
CS: 0x0010
EFLAGS: 0x00010087
EAX:0x0020
ECX:0x6fca
EDX:0x7e2f
EBX:0x9b78
ESP:0x6fb4
EBP:0xffe8e404
ESI:0x
EDI:0x00136760
DS: 0x0018
ES: 0x0018
SS: 0x0018
FS: 0x0018
GS: 0x0018
Dumping stack:
0x71a0:         
0x7180:         
0x7160:         
0x7140:         
0x7120:         
0x7100:         
0x70e0:         
0x70c0:         
0x70a0:         
0x7080:         
0x7060:         
0x7040:         
0x7020:         
0x7000:         
0x6fe0:   e981 0200f000     
0x6fc0:  ffe8e3e8       
0x6fa0: 0010 0020 000fd272 0010 00010087 6fb4 6fb4 000f5eba 



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[coreboot] pcengines apu1 nvram support

[Maxime de Roucy]

Hello,

I made a patch for the pcengines apu1 board to support nvram
(HAVE_OPTION_TABLE).
I made/adapt this patch from the "Sage" source available at
http://www.pcengines.ch/howto.php#CoreBoot
-- 
Regards
Maxime de Roucydiff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index b1b19c9..35f315f 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
 
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
new file mode 100755
index 000..2f8d26b
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -0,0 +1,79 @@
+entries
+
+0  384   r   0reserved_memory
+384  1   e   4boot_option
+385  1   e   4last_boot
+386  1   e   1ECC_memory
+388  4   r   0reboot_bits
+392  3   e   5baud_rate
+395  1   e   1hw_scrubber
+396  1   e   1interleave_chip_selects
+397  2   e   8max_mem_clock
+399  1   e   2multi_core
+400  1   e   1power_on_after_fail
+412  4   e   6debug_level
+416  4   e   7boot_first
+420  4   e   7boot_second
+424  4   e   7boot_third
+428  4   h   0boot_index
+432  8   h   0boot_countdown
+440  4   e   9slow_cpu
+444  1   e   1nmi
+445  1   e   1iommu
+728256   h   0user_data
+984 16   h   0check_sum
+# Reserve the extended AMD configuration registers
+100024   r   0amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 0 Emerg
+6 1 Alert
+6 2 Crit
+6 3 Err
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10Fallback_Floppy
+8 0 DDR3-1600
+8 1 DDR3-1333
+8 2 DDR3-1066
+8 3 DDR3-800
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+


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[coreboot] STACK_SIZE pcengines apu1

[Maxime de Roucy]

Hello,

I am building a coreboot rom for my pcengines apu1.
A bug is logged during the boot process :
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=pcengines/apu1/4.0-9873-g7b9762f/2015-06-04T15:16:28Z/coreboot_console.txt;hb=HEAD#l1281

In order to solve it I applied this changed :

diff --git a/src/Kconfig b/src/Kconfig
index 9c01687..c8b8ad2 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -427,7 +427,7 @@ config HEAP_SIZE
 config STACK_SIZE
hex
default 0x0 if (ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_MIPS || 
ARCH_RAMSTAGE_RISCV)
-   default 0x1000
+   default 0x2000
 
 config MAX_CPUS
int

I don't see the bug line anymore, instead I see :

CPU0: stack: 00148000 - 0014a000, lowest used address 00148d34, stack used: 
4812 bytes

I now the patch is not good since it change the default stack size for
all the boards. I didn't found the right place the change the stack
size only for pcengines apu1 board.
But maybe those informations can help developers to improve coreboot.
-- 
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Maxime de Roucy

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[coreboot] QEMU Q35 about Linux booting problem

[Yu-Cheng Liu]

Dear all:
I can boot in Linux with default machine use :
qemu-system-x86_64 -bios [ Path to coreboot with FILO ] -hda [ Path to
Linux image ] -nographic

when I use Q35 machine :
qemu-system-x86_64 *-M q35* -bios [ Path to coreboot with FILO ] -hda [
Path to Linux image ] -nographic
the FILO would tell us that "IDE channel 0 not found",and not boot in Linux

how can I fix this problem ?

Thank you ~
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[coreboot] New on blogs.coreboot.org: 2015-08-28 Librem 13: Weekly BIOS Update

[WordPress]

A new post titled "2015-08-28 Librem 13: Weekly BIOS Update" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/09/02/2015-08-28-librem-13-weekly-bios-update/

Author: larry.mob...@puri.sm
This post gives some details on the Librem 15 rev2 prototype. One challenge with developing BIOS is finding parts that can be reused; coreboot makes heavy reuse of certain pieces of code.
Very Similar
Starting with the chips on the back of the mainboard, the 15 prototype uses the same ene KB3930QF-A1 as the Librem 13, and it is configured to read from an external Macronix MX25L512 SPI flash for firmware. The 15 has this SPI chip on the front side of the board between the DIMMs and the USB3 ports.
The 15 prototype uses a Realtek ALC269 codec via the AC’97. The Librem 13 should have a very similar codec.
On the front (the side visible just by removing the back laptop case), the 15 prototype uses an MX25L6406E SPI flash for the BIOS. The Librem 13 prototype uses a GD25Q64B, but other than the Intel Firmware Descriptor fields for JEDEC ID etc, these chips are interchangeable.
Both CPUs are Broadwell-U. They use the same FSP. They both have the LPC bus exposed on pads.
These similarities help us by reducing the amount of variation between the board subdirs in coreboot and can use the same development rig.
Acceptance Test Matrix
We’ve put together the following tests to validate coreboot builds:

Cold boot: memory controller works.
Cold boot: all installed DRAM is online.
Cold boot: graphics controller works.
Cold boot: SATA controller succeeds.
Cold boot: EC controller responds ok to init code.
Cold boot: LCD backlight turns on.
Cold boot: linux boots ok in text mode.
Cold boot: linux boots ok in framebuffer (boot splash) mode.
Cold boot: X initializes the LCD at full native resolution.
Cold boot: X enables hardware acceleration.
Boot time: Cold boot to grub succeeds in less than a set timeout.
Boot time: Reboot from linux back to linux succeeds in less than a set timeout.
Boot time: Power down succeeds in less than a set timeout.
SeaBIOS test: keyboard works.
Grub test: keyboard works.
Grub test: text mode and framebuffer graphics work.
Cold boot to USB linux succeeds. (We plan to use SeaBIOS for boot device selection, barring major bugs.)
Reboot to USB linux succeeds.
EC test: fan spins.
EC test: holding power for >5 seconds forces a power down.
ACPI test: lid switch works.
ACPI test: power button event received ok.
ACPI test: AC power on/off event received ok.
ACPI+EC+battery test: battery percentage works.
Media keys on keyboard work in linux.
Device tests: internal mic, internal speakers, webcam, webcam mic, wifi, bluetooth, hard drive, SSD, SD card, each USB port, headphone jack.
prime95 (one instance bound to each hyperthread) for a fixed time to test CPU thermal management.
glxgears for a fixed time to test GPU thermal management.
During prime95 test, CPU digital thermal sensor should give reasonable results.
Linux suspend ok.
LCD backlight adjustable in linux.
Linux kernel boot messages should not contain too many errors.

The effort to write Free Software implementations for all binary blobs will continue in parallel.
Secondary items would include further tweaks to PCI IRQ routing, additional ACPI tables, and optimizing battery life/power use.


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[coreboot] [help]build cbfstool fail with cygwin64

[Kurt Qiao]

does anyone try cygwin64 to build coreboot in windows7 64bit?
i got fail when build cbfstool with cygwin64.
my steps as below:

1. cygwin64 install utility "patch", "flex", 'wget' etc.

2. git pull latest coreboot from github
build crossgcc
./buildgcc -j 4

3. build iasl
download src from link [1]
make
cp acpica-unix-20150818/generate/unix/bin/iasl /usr/local/bin

4. make menuconfig
choose "emulation/qemu-q35" in my case

5.make
then fail as below

: In function 'yy_init_buffer':
:1395:9: error: implicit declaration of function 'fileno'
[-Werror=implicit-function-declaration]
cc1: all warnings being treated as errors
util/cbfstool/Makefile.inc:59: recipe for target
'build/util/cbfstool/fmd_scanner.o' failed
make: *** [build/util/cbfstool/fmd_scanner.o] Error 1
---

i follow link [2] to modify cbfstool makefile, add _D_GNU_SOURCE for
TOOLCPPFLAGS, CPPFLAGS
and fail as below log.
---
Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 432 Optimizations
HOSTCC cbfstool/fmaptool.o
HOSTCC cbfstool/cbfs_sections.o
HOSTCC cbfstool/fmap_from_fmd.o
HOSTCC cbfstool/fmd.o
HOSTCC cbfstool/fmd_parser.o
HOSTCC cbfstool/fmd_scanner.o
HOSTCC cbfstool/fmap.o
HOSTCC cbfstool/kv_pair.o
HOSTCC cbfstool/valstr.o
HOSTCC cbfstool/fmaptool (link)
build/util/cbfstool/fmd.o:fmd.c:(.text+0xa23): undefined reference to
`yylex_destroy'
build/util/cbfstool/fmd.o:fmd.c:(.text+0xa23): relocation truncated to
fit: R_X86_64_PC32 against undefined symbol `yylex_destroy'
build/util/cbfstool/fmd.o:fmd.c:(.rdata$.refptr.yyin[.refptr.yyin]+0x0):
undefined reference to `yyin'
build/util/cbfstool/fmd_parser.o:fmd_parser.c:(.text+0x386): undefined
reference to `yylex'
build/util/cbfstool/fmd_parser.o:fmd_parser.c:(.text+0x386):
relocation truncated to fit: R_X86_64_PC32 against undefined symbol
`yylex'
collect2: error: ld returned 1 exit status
util/cbfstool/Makefile.inc:83: recipe for target
'build/util/cbfstool/fmaptool' failed
make: *** [build/util/cbfstool/fmaptool] Error 1
---

[1]:https://acpica.org/sites/acpica/files/acpica-unix-20150818.tar.gz
[2]:http://review.coreboot.org/#/c/10027/1

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Re: [coreboot] unbricking an Acer CB5

[John Lewis]

On 2015-09-06 17:52, Holger Brunn wrote:

Dear readers,

I played with compiling my own coreboot image for my Acer CB5 [1] and 
failed
miserably - the bios is messed up and the device won't boot any more. 
Now I'm

busy following some guides to undo the damage [2], [3] by flashing the
original bios again, but given I'm quite clueless about hardware, I'd 
like to

ask you for advice about how to proceed:

I ordered a Raspberry PI, some connector cables [4], and then I 
probably need

a clip to connect the chip [5].

My question to you is how to locate the chip? The mainboard looks like 
that:
http://opensource.holgerbrunn.net/debian-on-acer-cb5/images/DSC01629.JPG 
and
the only chip that looks like those in the examples is U37 in the lower 
right.
Is there any way to know beforehand if it's the correct one? And then 
when
connecting the pins, can I look up somewhere what the correct 
assignment is or
is this trial and error? I can't read what is printed on it, but if 
relevant,

I'll get a magnifying glass to post the text.


Yes, u37 looks like it. But, bear in mind many Chromebooks have the SPI 
on the other side of the board. If the chip is the wrong size (early 
Chromebooks had a separate EC on a 512k SPI) Flashrom will crap out and 
complain when you try to flash an 8MB binary to it. Pin assignment is 
available in various articles on the web, this is one I found by 
searching - 
https://github.com/bibanon/Coreboot-ThinkPads/wiki/Hardware-Flashing-with-Raspberry-Pi. 
I have used a magnifying app on my smart-phone before, but it's 
unnecessary.


HTH,

John.



Thank you a lot in advance, and be sure that I won't come back whining 
if
anything goes wrong and I fry the chip following your advice - that's 
entirely

my fault then.

I'll log the process on the above website if successful so that the 
next

person messing this up won't have to bother you.

Regards,
Holger

Links:
[1]
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices/acer-cb5-311-chromebook-13
[2] 
http://www.tnhh.net/2014/08/25/unbricking-chromebook-with-beaglebone.html

[3] https://johnlewis.ie/unbricking-a-samsung-series-5-550-chromebook
[4]
https://www.conrad.nl/nl/raspberry-pi-verbindingskabel-rb-cb5-025-bont-banana-pi-pcduino-arduino-raspberry-pi-a-b-b-1290220.html?sc.ref=Homepage
[5] http://www.digikey.nl/product-detail/en/5250/501-1311-ND/745102


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Re: [coreboot] coreinfo "General Protection Fault Exception"

[Marc Jones]

It looks like coreinfo is the only payload, so there is nothing to exit
back to. What were you expecting to happen?

You can try using seabios with multiple payloads or work with bayou as a
multiple payload loader.

Marc

On Thu, Sep 10, 2015 at 12:54 AM Maxime de Roucy 
wrote:

> Hello,
>
> On a pcengines apu1 when I tried to leave coreinfo (press ESC) I get a
> "General Protection Fault Exception".
>
> I attached my .config file of coreinfo (it's the default configuration)
> and the console output when coreinfo crash.
> --
> Regards
> Maxime de Roucy--
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> http://www.coreboot.org/mailman/listinfo/coreboot
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Re: [coreboot] STACK_SIZE pcengines apu1

[Aaron Durbin]

On Sun, Sep 6, 2015 at 9:10 AM, Maxime de Roucy
 wrote:
> Hello,
>
> I am building a coreboot rom for my pcengines apu1.
> A bug is logged during the boot process :
> http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=pcengines/apu1/4.0-9873-g7b9762f/2015-06-04T15:16:28Z/coreboot_console.txt;hb=HEAD#l1281
>
> In order to solve it I applied this changed :
>
> diff --git a/src/Kconfig b/src/Kconfig
> index 9c01687..c8b8ad2 100644
> --- a/src/Kconfig
> +++ b/src/Kconfig
> @@ -427,7 +427,7 @@ config HEAP_SIZE
>  config STACK_SIZE
> hex
> default 0x0 if (ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_MIPS || 
> ARCH_RAMSTAGE_RISCV)
> -   default 0x1000
> +   default 0x2000
>
>  config MAX_CPUS
> int
>
> I don't see the bug line anymore, instead I see :
>
> CPU0: stack: 00148000 - 0014a000, lowest used address 00148d34, stack 
> used: 4812 bytes
>
> I now the patch is not good since it change the default stack size for
> all the boards. I didn't found the right place the change the stack
> size only for pcengines apu1 board.
> But maybe those informations can help developers to improve coreboot.

That's quite the stack usage.  It'd be interesting to know what's
using all that stack. Could you apply this patch and run w/ it? It'd
help narrow down at what point in the boot where the stack gets used
up. Also, that you used 4812 bytes just means you overwrote the other
CPU's stack at some point when STACK_SIZE == 4KiB.


diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index b3c0c35..8a241b2 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -378,6 +378,8 @@ static void bs_walk_state_machine(void)
bs_report_time(state);

state->complete = 1;
+
+   checkstack(_estack, 0);
}
 }


> --
> Regards
> Maxime de Roucy
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] STACK_SIZE pcengines apu1

[Julius Werner]

I'd bet it's just a single large allocation somewhere. You can try adding

 CFLAGS_ramstage += -Wstack-usage=1024

somewhere in coreboot/Makefile.inc and then clean+rebuild your code while
passing '-k' to make. You'll get a bunch of compiler warnings, and one of
them is likely to be the culprit.
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Re: [coreboot] STACK_SIZE pcengines apu1

[Maxime de Roucy]

Le jeudi 10 septembre 2015 à 09:02 -0500, Aaron Durbin a écrit :
> That's quite the stack usage.  It'd be interesting to know what's
> using all that stack. Could you apply this patch and run w/ it? It'd
> help narrow down at what point in the boot where the stack gets used
> up.

You will find the spew log of the modified coreboot you asked.
(it's a reboot, not a boot… I don't know if that's change something).
-- 
Regards
MaximeCBFS @ 0 size 1ff9c0
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 140 size 774


coreboot-4.1-302-gbad0cc0-dirty Sun Sep  6 17:23:04 UTC 2015 ramstage starting...
BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
CPU0: stack: 00148000 - 0014a000, lowest used address 00149ce4, stack used: 796 bytes
SB800 - Smbus.c - alink_ab_indx - Start.
SB800 - Smbus.c - alink_ab_indx - End.
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 7163 exit 0
CPU0: stack: 00148000 - 0014a000, lowest used address 00149ce4, stack used: 796 bytes
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: : enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 1
PCI: 00:06.0: enabled 1
PCI: 00:07.0: enabled 1
PCI: 00:08.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:14.1: enabled 0
PCI: 00:14.2: enabled 0
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.10: enabled 0
PNP: 002e.11: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.f: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.607: enabled 0
PNP: 002e.e: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 0
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 1
PCI: 00:16.2: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: : enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 0
  PCI: 00:04.0: enabled 1
  PCI: 00:05.0: enabled 1
  PCI: 00:06.0: enabled 1
  PCI: 00:07.0: enabled 1
  PCI: 00:08.0: enabled 1
  PCI: 00:11.0: enabled 1
  PCI: 00:12.0: enabled 1
  PCI: 00:12.2: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:13.2: enabled 1
  PCI: 00:14.0: enabled 1
  PCI: 00:14.1: enabled 0
  PCI: 00:14.2: enabled 0
  PCI: 00:14.3: enabled 1
   PNP: 002e.0: enabled 0
   PNP: 002e.2: enabled 1
   PNP: 002e.3: enabled 1
   PNP: 002e.10: enabled 0
   PNP: 002e.11: enabled 0
   PNP: 002e.8: enabled 0
   PNP: 002e.f: enabled 0
   PNP: 002e.7: enabled 0
   PNP: 002e.107: enabled 0
   PNP: 002e.607: enabled 0
   PNP: 002e.e: enabled 0
  PCI: 00:14.4: enabled 1
  PCI: 00:14.5: enabled 0
  PCI: 00:15.0: enabled 1
  PCI: 00:15.1: enabled 0
  PCI: 00:15.2: enabled 0
  PCI: 00:15.3: enabled 0
  PCI: 00:16.0: enabled 1
  PCI: 00:16.2: enabled 1
  PCI: 00:18.0: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
  PCI: 00:18.5: enabled 1
  PCI: 00:18.6: enabled 1
  PCI: 00:18.7: enabled 1
Mainboard APU1 Enable.
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xe000, msr.hi = 0x
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f00, msr.hi = 0x0001
CPU_CLUSTER: 0 enabled
DOMAIN:  enabled
CPU_CLUSTER: 0 scanning...
  AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
DOMAIN:  scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1022/1510] ops
PCI: 00:00.0 [1022/1510] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/1512] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:05.0 subordinate bus PCI Express
PCI: 00:05.0 [1022/1513] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:06.0 subordinate bus PCI Express
PCI: 00:06.0 [1022/1514] enabled
PCI: Static device PCI: 00:07.0 not found, disabling it.
PCI: Static device PCI: 00:08.0 not found, disabling it.
PCI: 00:11.0 [1002/4390] enabled
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
PCI: 00:13.0 [1002/4397] ops
PCI: 

Re: [coreboot] Hotel rooms: coreboot conference 2015

[Carl-Daniel Hailfinger]

My sincere apologies, the email address seems to be out of order.

Please use wissenschaftszent...@wzbonn.de for booking a
bed+breakfast room at the conference venue.

Regards,
Carl-Daniel

On 10.09.2015 22:14, Carl-Daniel Hailfinger wrote:
> The venue still has 7 very affordable single/double rooms available!
>
> Email i...@wzbonn.de and tell them you're attending the coreboot
> conference. Those rooms are reserved for conference participants.
>
> Regards,
> Carl-Daniel
>
>
> On 05.09.2015 03:12, coreboot conference wrote:
>> Dear vendors, developers, users and interested parties,
>>
>> On behalf of the Federal Office for Information Security (BSI) Germany I 
>> would
>> like to invite you to the coreboot conference and developer meeting on 
>> October 9-11 2015 in Bonn, Germany.
>>
>> This conference and developer meeting is geared towards manufacturers of 
>> hardware (processors, chipsets, mainboards and servers/ laptops/ tablets/ 
>> desktops/ appliances) as well as developers of firmware with an interest in 
>> coreboot and the possibilities it offers as well as (potential) coreboot 
>> users. Both professionals and hobbyists are invited.
>>
>> Please see the full text of the invitation at 
>> http://coreboot.org/coreboot_conference_Bonn_2015
>>
>> Sincerely,
>> Carl-Daniel Hailfinger
>


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Re: [coreboot] STACK_SIZE pcengines apu1

[Aaron Durbin]

On Thu, Sep 10, 2015 at 4:34 PM, Maxime de Roucy
 wrote:
> Le jeudi 10 septembre 2015 à 09:02 -0500, Aaron Durbin a écrit :
>> That's quite the stack usage.  It'd be interesting to know what's
>> using all that stack. Could you apply this patch and run w/ it? It'd
>> help narrow down at what point in the boot where the stack gets used
>> up.
>
> You will find the spew log of the modified coreboot you asked.
> (it's a reboot, not a boot… I don't know if that's change something).

BS: BS_DEV_INIT times (us): entry 0 run 358353 exit 0
CPU0: stack: 00148000 - 0014a000, lowest used address 00149a2c, stack
used: 1492 bytes
CBMEM:
IMD: root @ d000 254 entries.
IMD: root @ dfffec00 62 entries.
Moving GDT to dfffea00...ok
Finalize devices...
Devices finalized
agesawrapper_amdinitlate() returned AGESA_SUCCESS
agesawrapper_amdS3Save() returned AGESA_SUCCESS
SF: Detected MX25L1605D with sector size 0x1000, total 0x20
SF: Successfully erased 4096 bytes @ 0x1000
SF: Detected MX25L1605D with sector size 0x1000, total 0x20
SF: Successfully erased 4096 bytes @ 0x
BS: BS_POST_DEVICE times (us): entry 9377 run 3502 exit 113447
CPU0: stack: 00148000 - 0014a000, lowest used address 00148d34, stack
used: 4812 bytes

So I'd get either agesawrapper_amdinitlate() or
agesawrapper_amdS3Save(). In either case it's in AGESA.

> --
> Regards
> Maxime

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[coreboot] Hotel rooms: coreboot conference 2015

[Carl-Daniel Hailfinger]

The venue still has 7 very affordable single/double rooms available!

Email i...@wzbonn.de and tell them you're attending the coreboot
conference. Those rooms are reserved for conference participants.

Regards,
Carl-Daniel


On 05.09.2015 03:12, coreboot conference wrote:
> Dear vendors, developers, users and interested parties,
>
> On behalf of the Federal Office for Information Security (BSI) Germany I would
> like to invite you to the coreboot conference and developer meeting on 
> October 9-11 2015 in Bonn, Germany.
>
> This conference and developer meeting is geared towards manufacturers of 
> hardware (processors, chipsets, mainboards and servers/ laptops/ tablets/ 
> desktops/ appliances) as well as developers of firmware with an interest in 
> coreboot and the possibilities it offers as well as (potential) coreboot 
> users. Both professionals and hobbyists are invited.
>
> Please see the full text of the invitation at 
> http://coreboot.org/coreboot_conference_Bonn_2015
>
> Sincerely,
> Carl-Daniel Hailfinger


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Re: [coreboot] coreinfo "General Protection Fault Exception"

[Maxime de Roucy]

Le jeudi 10 septembre 2015 à 15:35 +, Marc Jones a écrit :
> It looks like coreinfo is the only payload, so there is nothing to
> exit back to. What were you expecting to happen? 
> 
> You can try using seabios with multiple payloads or work with bayou
> as a multiple payload loader. 

No, coreinfo isn't the only payload. SeaBIOS is the main payload, I
also have memtest and ipxe (once I also have nvramcui).

I didn't expect coreinfo to launch to the next payload when it stop.
I expect it to reboot the computer as nvramcui do.

max@max-laptop % ./cbfstool coreboot.rom print
coreboot.rom: 2048 kB, bootblocksize 1576, romsize 2097152, offset 0x0
alignment: 64 bytes, architecture: x86

Name   Offset Type Size
…
genroms/ipxe.rom   0x6a880raw  56832
img/coreinfo   0x786c0payload  65500
img/memtest0x88700payload  147240
…

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Maxime

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