Re: [coreboot] Inteal Leafhill : Linux SATA driver fails when used with coreboot+grub

[Andrey Petrov]

On 03/05/2017 10:58 AM, Gailu Singh wrote:

Hi Again,

I tried to find out the details for following error

ata1: SATA link down (SStatus 4 SControl 300)

As per status register description

SStatus 4 : Phy in offline mode as a result of the interface being
disabled or running in a BIST loopback mode

Is there any chance that coreboot/grub/Linux is putting SATA in to BIST
loopback mode?

I am trying to understand who is responsible for SATA Linux status 4 and
possible candidates are
a) coreboot
b) grub
c) Linux


You already mentioned coreboot+tianocore worked fine under Linux. I 
think it is safe to assume the problem is not originating from the 
kernel. Why don't you check what tianocore does about SATA? I suspect 
tianocore may be injecting some ACPI tables for SATA controller which 
kernel picks up. Perhaps you can dump, decompile and compare asl from 
coreboot+tianocore and coreboot+grub and see what is different?


Andrey

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Re: [coreboot] AGESA massive rewrite expected

[Kyösti Mälkki]

On Mon, Mar 6, 2017 at 1:03 AM, taii...@gmx.com  wrote:

> Does this mean that the IOMMU stubs will be functional?
>

I am not sure what you mean. APCI IVRS is not modified.

Kyösti
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[coreboot] AGESA massive rewrite expected

[Kyösti Mälkki]

Hi

Again, it would be good time to update your board-status if you happen to
use some Family 15 Trinity or 16 Kabini board. Older Family 14 most welcome
also. Specially the fairly recent ports of elmex/pcm205400 and msi/ms7721
are without any report, and it should not take more than 15 minutes to have
one sent.

Currently pending work:

src/mainboard/* anything AMD_AGESA
 131 files changed, 672 insertions(+), 2511 deletions(-)

src/cpu/amd/agesa/*
src/southbridge/amd/agesa/*
src/northbridge/amd/agesa/*
 53 files changed, 1429 insertions(+), 807 deletions(-)

Yes, stuff will get pushed away from mainboard directories towards common
directories. Should get us closer to EARLY_CBMEM_INIT and working
timestamps and CBMEM console from romstage.

It probably will not make it in time for coreboot 4.6 unless I meet
exceptionally eager people to run some tests.

Kyösti
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Re: [coreboot] Inteal Leafhill : Linux SATA driver fails when used with coreboot+grub

[Gailu Singh]

Hi Again,

I tried to find out the details for following error

ata1: SATA link down (SStatus 4 SControl 300)

As per status register description

SStatus 4 : Phy in offline mode as a result of the interface being disabled
or running in a BIST loopback mode

Is there any chance that coreboot/grub/Linux is putting SATA in to BIST
loopback mode?

I am trying to understand who is responsible for SATA Linux status 4 and
possible candidates are
a) coreboot
b) grub
c) Linux

Looking forward to your expert advice


Thanks

On Fri, Mar 3, 2017 at 9:29 PM, Gailu Singh  wrote:

> Hi Experts,
>
> I am trying to boot Linux 4.1 with coreboot and grub but SATA drive fails
> with error  "ata1: SATA link down (SStatus 4 SControl 300)". It is
> interesting that GRUB2 can use the SATA drive without issue and able to
> load kernel from SATA disk.
>
> If I use same SATA Drive with Coreboot+UEFI payload then Linux driver just
> works fine and I am able to boot linux.
>
> Any Idea What might be going wrong with Linux Driver. Does it expect
> something from BIOS/Coreboot that is not fulfilled
>
> Linux boot logs:
> -
> Initializing cgroup subsys cpuset
> Initializing cgroup subsys cpu
> Initializing cgroup subsys cpuacct
> Linux version 4.1.21-WR8.0.0.11_standard (vgahlaut@ubuntu) (gcc version
> 5.2.0 (Wind River Linux 5.2.0-8.0-intel-apollolake-i-64) ) #1 SMP PREEMPT
> Mon Feb 6 18:38:46 PST 2017
> Command line: BOOT_IMAGE=(ahci0,msdos1)/boot/bzImage root=/dev/sda1
> rootdelay=10 console=ttyS2,115200
> KERNEL supported cpus:
>   Intel GenuineIntel
>   AMD AuthenticAMD
>   Centaur CentaurHauls
> e820: BIOS-provided physical RAM map:
> BIOS-e820: [mem 0x-0x0fff] type 16
> BIOS-e820: [mem 0x1000-0x0009] usable
> BIOS-e820: [mem 0x000a-0x000f] reserved
> BIOS-e820: [mem 0x0010-0x0fff] usable
> BIOS-e820: [mem 0x1000-0x12150fff] reserved
> BIOS-e820: [mem 0x12151000-0x7a64] usable
> BIOS-e820: [mem 0x7a65-0x7aff] type 16
> BIOS-e820: [mem 0x7b00-0x7fff] reserved
> BIOS-e820: [mem 0xd000-0x] reserved
> BIOS-e820: [mem 0x0001-0x00017fff] usable
> NX (Execute Disable) protection: active
> SMBIOS 2.7 present.
> e820: last_pfn = 0x18 max_arch_pfn = 0x4
> PAT configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- UC
> e820: last_pfn = 0x7a650 max_arch_pfn = 0x4
> Scanning 1 areas for low memory corruption
> Using GB pages for direct mapping
> init_memory_mapping: [mem 0x-0x000f]
> init_memory_mapping: [mem 0x17fe0-0x17fff]
> init_memory_mapping: [mem 0x16000-0x17fdf]
> init_memory_mapping: [mem 0x0010-0x0fff]
> init_memory_mapping: [mem 0x12151000-0x7a64]
> init_memory_mapping: [mem 0x1-0x15fff]
> ACPI: Early table checksum verification disabled
> ACPI: RSDP 0x000F 24 (v02 CORE  )
> ACPI: XSDT 0x7A6690E0 5C (v01 CORE   COREBOOT  CORE
> )
> ACPI: FACP 0x7A66BA60 00010C (v05 CORE   COREBOOT  CORE
> 0001)
> ACPI BIOS Warning (bug): 32/64X length mismatch in FADT/Pm1aEventBlock:
> 32/16 (20150410/tbfadt-623)
> ACPI BIOS Warning (bug): Invalid length for FADT/Pm1aEventBlock: 16, using
> default 32 (20150410/tbfadt-704)
> ACPI: DSDT 0x7A669280 0027D8 (v05 COREv4 COREBOOT 20110725 INTL
> 20160831)
> ACPI: FACS 0x7A669240 40
> ACPI: FACS 0x7A669240 40
> ACPI: SSDT 0x7A66BB70 000774 (v02 CORE   COREBOOT 002A CORE
> 002A)
> ACPI: MCFG 0x7A66C2F0 3C (v01 CORE   COREBOOT  CORE
> )
> ACPI: TCPA 0x7A66C330 32 (v02 CORE   COREBOOT  CORE
> )
> ACPI: TPM2 0x7A66C370 34 (v04 CORE   COREBOOT  CORE
> )
> ACPI: APIC 0x7A66C3B0 6C (v01 CORE   COREBOOT  CORE
> )
> ACPI: HPET 0x7A66C420 38 (v01 CORE   COREBOOT  CORE
> )
> Zone ranges:
>   DMA  [mem 0x1000-0x00ff]
>   DMA32[mem 0x0100-0x]
>   Normal   [mem 0x0001-0x00017fff]
> Movable zone start for each node
> Early memory node ranges
>   node   0: [mem 0x1000-0x0009]
>   node   0: [mem 0x0010-0x0fff]
>   node   0: [mem 0x12151000-0x7a64]
>   node   0: [mem 0x0001-0x00017fff]
> Initmem setup node 0 [mem 0x1000-0x00017fff]
> ACPI: PM-Timer IO Port: 0x408
> IOAPIC[0]: apic_id 2, version 32, address 0xfec0, GSI 0-119
> ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
> ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
> Using ACPI (MADT) for SMP configuration information
> ACPI: HPET id: 0x8086a701 base: 0xfed0
> smpboot: 

[coreboot] ASUS KGPE-D16 Automated Test Failure [master]

[Raptor Engineering Automated Coreboot Test Stand]

The ASUS KGPE-D16 fails verification for branch master as of commit 
03353de80b2c0604e778d81e9010af787a183ab3

The following tests failed:
BOOT_FAILURE

Commits since last successful test:
03353de buildgcc: Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM

See attached log for details

This message was automatically generated from Raptor Engineering's ASUS 
KGPE-D16 test stand
Want to test on your own equipment?  Check out 
https://www.raptorengineering.com/content/REACTS/intro.html

Raptor Engineering also offers coreboot consulting services!  Please visit 
https://www.raptorengineering.com for more information

Please contact Timothy Pearson at Raptor Engineering 
 regarding any issues stemming from this 
notification


1488739274-3-automaster.log.bz2
Description: application/bzip2
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Re: [coreboot] New on blogs.coreboot.org: Results of the coreboot "Mailing List vs Blog" poll

[Zoran Stojsavljevic]

Hello Mailing List,

I am all just about forum. Since I think forum is more clear, and better
organized (in my view/opinion). I do not like mailing lists. I hate them.
But...

I admit complete defeat!

"If you can not defeat/beat them, you join them!" ;-)

Zoran

On Sun, Mar 5, 2017 at 12:18 AM, WordPress 
wrote:

> A new post titled "Results of the coreboot "Mailing List vs Blog" poll"
> has been published on the coreboot blog. Find the full post at
> http://blogs.coreboot.org/blog/2017/03/04/results-of-
> the-coreboot-mailing-list-vs-blog-poll/
>
> A little while back, there were a few requests to switch from the mailing
> list format to a web-based forum for our official communication channel.
> The coreboot leadership wanted to see what the actual preferences of the
> coreboot community was, so I posted a poll.  The poll was publicized in IRC
> and on the mailing list itself, so should have been communicated to the
> people who would be most directly affected by any change.
> Poll results
>
> *Here are the overall results from all responses:*
> [image: Hate Mailing List:1, Prefer Forum: 6, Don't care: 2, Prefer
> Mailing list: 21, Hate Forum: 26]
> 
> All_responses
>
> We had a total of 60 valid responses, and I think the overall results
> pretty clearly indicate that the coreboot project should NOT move away from
> the mailing list.
>
> One suggestion was to split the communication into the mailing list for
> Developers, and a forum for non-developers. To see what the various groups
> thought, I made a few more charts:
>
> *Developer preferences:*
> [image: Prefer Forum: 1, Prefer Mailing list: 16, Hate Forum: 15, Other: 3]
> Developer
> Responses
>
> So not unexpectedly, the coreboot developers even more overwhelmingly
> prefer the mailing list to the general results
>
> *Non-developer preferences:*
> [image: Hate Mailing list: 1, Prefer Forum: 5, Don't care: 2, Prefer
> Mailing list: 5, Hate Forum: 11, Other: 1]
> Non-developer
> Responses
>
> So even within the non-developer group, there was a definite preference
> for the mailing list format.
>
> Finally, I broke the Non-developer group down into the group that said
> they were coreboot users, as opposed to those that mainly read the mailing
> list.
>
> *coreboot users (non-developers):*
>
>
> [image: Hate Mailing list: 1, Prefer Forum: 4, Prefer Mailing list: 4,
> Hate Forum: 5]
> coreboot
> Users (Non-Developers)
>
> That group had the highest percentage of people who preferred the forum,
> but it was still well under 40%.
> Suggestions
>
> We also asked people what we should do to improve the mailing list.
> Here’s a summary of the suggestions:
>
>- Show people how to set up their (or a different) email client to
>make reading the mailing list easier.
>- Have people be more polite.
>- Add a FAQ showing previously asked question and answers.
>- A netiquette should be established like on the Linux kernel mailing
>list.
>- Several suggestions to improve the coreboot mailing list archive at
>https://www.coreboot.org/pipermail/coreboot/
>
>   - Fix the archive so that long threads aren’t spread into different
>   sections by months.
>   - Add a search function to the archive
>   - Create monthly archives that can be downloaded (This exists.)
>   - Update from Pipermail to a more modern archiver like Hyperkitty –
>   https://pypi.python.org/pypi/HyperKitty
>   
>
> Since it doesn’t look like we’re going to switch to a forum, I’m not going
> to list the suggestions that people had for that.
> Follow-up
>
> Over the upcoming weeks, we’ll look at our options, and discuss our
> options and plans in the bi-weekly coreboot community meetings.
>
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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[cb]

There's a lot of useful info here relating to X230 ECs, which may help.
Mostly applicable to the X220 too.


https://github.com/hamishcoleman/thinkpad-ec





On Sun, 5 Mar 2017, at 14:31, qma ster wrote:

> It should be possible to reflash EC internal firmware through a
> keyboard port, - or maybe through some other debug port that may or
> may not be soldered by default... For example, here is a guide that
> describes how to reflash EC KB9012 internal firmware on Lenovo G505S -
> "AMD based laptop that is supported by coreboot project" ,
> http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate .
> Thanks to this method it is possible to flash a completely clean EC
> KB9012 firmware image, which: 1) does not contain any "secret configs"
> (could be stored in the free place after the firmware) 2) does not
> contain any serial numbers or other specific laptop information ...
> For any EC it is guaranteed that it IS possible to reflash a firmware
> through In-System Programming (direct flashing) - otherwise, 1) how
> the manufacturers flash EC for the first time? ;) 2) if some laptop's
> EC is burned, how do repair shops flash a firmware to a new
> replacement EC?
> Sadly, for this direct flashing method you may need to buy a
> proprietary programmer (closed source hardware/software) , because a
> flashrom does not support every EC in existence
> 

> 2017-03-05 13:20 GMT+03:00 Arthur Heymans :

>> "taii...@gmx.com"  writes:
>>
>>  > Well I managed to download the latest BIOS from the lenovo site,
>>  > which includes an ME update now the issue is that I can't seem to
>>  > figure out how to extract it from the .FL1 and .FL2 files.
>>  >
>> Those might have a length too long to fit a flash so you need to trim
>>  those down before using ifdtool on those (If they contain and ifd of
>>  course)

>>  so depending on size of rom

>>  dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM

>> 

>>  and then ifdtool -x vendor_bios.rom

>>
>>  > I would also like to know as to how I can re-flash the EC firmware
>>  > if that could potentially cause problems, I of course do not know
>>  > if it has DMA.
>>  >
>>
>> Only existing tool to flash EC is using vendor tool.
>>  EC are only accessed trough port mapped IO (or on newer ones
>>  also via
>>  memory mapped IO). EC itself does not have DMA afaik.

>> 
>>  --
>>  Arthur Heymans

>> 

>> --

>>  coreboot mailing list: coreboot@coreboot.org

>> https://www.coreboot.org/mailman/listinfo/coreboot

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> coreboot mailing list: coreboot@coreboot.org

> https://www.coreboot.org/mailman/listinfo/coreboot


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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[qma ster]

It should be possible to reflash EC internal firmware through a keyboard
port, - or maybe through some other debug port that may or may not be
soldered by default... For example, here is a guide that describes how to
reflash EC KB9012 internal firmware on Lenovo G505S - "AMD based laptop
that is supported by coreboot project" ,
http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate .
Thanks to this method it is possible to flash a completely clean EC KB9012
firmware image, which: 1) does not contain any "secret configs" (could be
stored in the free place after the firmware) 2) does not contain any serial
numbers or other specific laptop information ... For any EC it is
guaranteed that it IS possible to reflash a firmware through In-System
Programming (direct flashing) - otherwise, 1) how the manufacturers flash
EC for the first time? ;) 2) if some laptop's EC is burned, how do repair
shops flash a firmware to a new replacement EC?
Sadly, for this direct flashing method you may need to buy a proprietary
programmer (closed source hardware/software) , because a flashrom does not
support every EC in existence

2017-03-05 13:20 GMT+03:00 Arthur Heymans :

> "taii...@gmx.com"  writes:
>
> > Well I managed to download the latest BIOS from the lenovo site, which
> > includes an ME update now the issue is that I can't seem to figure out
> > how to extract it from the .FL1 and .FL2 files.
> >
> Those might have a length too long to fit a flash so you need to trim
> those down before using ifdtool on those (If they contain and ifd of
> course)
> so depending on size of rom
> dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM
>
> and then ifdtool -x vendor_bios.rom
>
> > I would also like to know as to how I can re-flash the EC firmware if
> > that could potentially cause problems, I of course do not know if it
> > has DMA.
> >
>
> Only existing tool to flash EC is using vendor tool.
> EC are only accessed trough port mapped IO (or on newer ones also via
> memory mapped IO). EC itself does not have DMA afaik.
>
> --
> Arthur Heymans
>
> --
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> https://www.coreboot.org/mailman/listinfo/coreboot
>
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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[Arthur Heymans]

"taii...@gmx.com"  writes:

> Well I managed to download the latest BIOS from the lenovo site, which
> includes an ME update now the issue is that I can't seem to figure out
> how to extract it from the .FL1 and .FL2 files.
>
Those might have a length too long to fit a flash so you need to trim
those down before using ifdtool on those (If they contain and ifd of
course)
so depending on size of rom
dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM

and then ifdtool -x vendor_bios.rom

> I would also like to know as to how I can re-flash the EC firmware if
> that could potentially cause problems, I of course do not know if it
> has DMA.
>

Only existing tool to flash EC is using vendor tool.
EC are only accessed trough port mapped IO (or on newer ones also via
memory mapped IO). EC itself does not have DMA afaik.

-- 
Arthur Heymans

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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[taii...@gmx.com]

Well I managed to download the latest BIOS from the lenovo site, which 
includes an ME update now the issue is that I can't seem to figure out 
how to extract it from the .FL1 and .FL2 files.


I would also like to know as to how I can re-flash the EC firmware if 
that could potentially cause problems, I of course do not know if it has 
DMA.



If I was a foreign intel service I would definitely be selling thinkpads 
on ebay, considering that sysadmins and programmers are the only ones 
who buy them.

On 02/20/2017 05:16 PM, taii...@gmx.com wrote:
I want generic ones, not the sketchy extracted ones that came with my 
fleabay laptop.


The lenovo website doesn't work on my computer BTW





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