Re: [coreboot] [SMSC SCH3114] Super I/O issues

[Alexander Couzens]

Hi Kkonstantin,

just by any chance, do you tried to use baytrail and _not_ fsp_baytrail?

best,
lynxis
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Re: [coreboot] [SMSC SCH3114] Super I/O issues

[Alexander Couzens]

Hi Konstantin,

the IRQ are usually freely configurable via the LDN.
Using the lower bits of 0x70h is quite common to select the IRQ.

The SuperIO is connected via LPC, which supports all legacy IRQs by
Serial-IRQ.
Further, depending on the Chipset, it must allow to receive the IRQs
over the SerIRQ line of the LPC.

Best Regards,
lynxis
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[coreboot] how users can control additional features?

[Alexander Couzens]

Hi,

I would like to merge https://review.coreboot.org/c/coreboot/+/12888
But how the user can control this feature (and all other "special
features")?

Should coreboot add an acpi function and the OS offer a UI
(e.g. /sys/class/foo/feature)?
Add a nvram option? (and set a acpi variable based on nvram, so we
don't need SMM)

Any other idea?

Best,
lynxis
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[coreboot] Berlin Usergroup Meeting 30. August Thursday @AfRA

[Alexander Couzens]

tldr;
30.08.2018 18:30 (open end) AfRA

Hi,

the Berlin Usergroup Meeting in August will taken
place on 30.08.2017 in the rooms of the Department Of Redundancy
Department (AfRA).

Abteilung für Redundanz Abteilung
Margaretenstraße 30
10317 Berlin

https://afra-berlin.de/

best,
lynxis

Ps. If you want to flash your laptop, send me a notice in advance.
Certain things might need to prepared for your device.
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Re: [coreboot] Intel GMA: Backlight brightness driver

[Alexander Couzens]

Hi Patrick,

thanks for your work.
Are there any documentation or description what Mailbox 3 support is?
Where it come from?

Best,
lynxis


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Re: [coreboot] Reproducible builds

[Alexander Couzens]

Hi Tom,

only the coreboot region itself should be reproducible.
The BIOS flash contains multiple regions (or call them "partitions").
Only the bios region, which contains coreboot and the payloads is
reproducible. And so far I know, only SeaBIOS as payload is
reproducible.
GRUB might be reproducible, but I'vn't tracked the reamining issues
there. Those might have been fixed.

> I found the config used, 
> https://github.com/coreboot/coreboot/blob/master/configs/builder/config.lenovo_x230,
>  
> does not include payloads and that the IFD, ME and GBE binaries were 
> sourced from "./site-local/" but I cannot find these files in any
> public repo.  If these are not available, then the generated hashes
> cannot be confirmed outside of the reproducible-builds Jenkins
> environments.

Those 3 files needs to be extracted from the BIOS chip.
Here is an example, how the layout of a sandy/ivy machine look like:

0 MB
---
| IFD |
---
| GBE |
---
| ME  |
---
| BIOS|
---
12 MB

> 
> My question ultimately comes down to how much of Coreboot is 
> reproducible and can a complete binary with payloads be built 
> consistently given the same build enviroment?  The more specific 
> question is, if the downloading the Coreboot 4.8.1 release using this 
> config, 
> https://github.com/Thrilleratplay/coreboot-builder-scripts/blob/master/x230/config-4.8.1,
>  
> why would the SHA256 hashes never match and, at times, cbfstool 
> partition sizes vary?

That's a good question, it shouldn't! Sounds like a bug in our versions
script.

You can try out diffoscope to find more about the reproducible builds
issue. There is also a website around diffoscope, so you don't have to
install the toolsuite on your machine.

https://try.diffoscope.org/

Best,
lynxis


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Re: [coreboot] New Subscriber

[Alexander Couzens]

> > 3) About the EC
> > Is it possible to create a full EC, which I can flash on the
> > mainboard chip with the raspberry pi?, or does an open source EC
> > already exist for the T420 (I just found one for T400 on
> > libreboot). Is the EC store on another chip?  
> It is stored on another chip, AFAIK someone made a replacement for
> the *30 EC but not the *20 EC - which sucks because then you're stuck
> with the serial number on the T420.

Which projects do you mean? *20 *30?

best,
lynxis 


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Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

[Alexander Couzens]

Hi Stefan,

we have two versions in the tree
a) fsp baytrail
b) non-fsp baytrail but with mrc.bin as meminit

Do you tried to use coreboot (w/o FSP) + u-boot instead? Or is this out
of scope?

Best,
lynxis
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Re: [coreboot] Where is the serial number stored on the thinkpad ivy/sandy bridge laptops

[Alexander Couzens]

> I am curious as to how it survives the coreboot flash re-write, maybe 
> the EC?

e.g.
> Base Board Information
>   Manufacturer: LENOVO
>   Product Name: 4291QT1
>   Version: ThinkPad X220
>   Serial Number: XYZU1234...

comes from a small i2c eeprom (at24 based).
src/drivers/i2c/at24rf08c/lenovo_serials.c

best,
lynxis

ps: The at24 also contains your lenovo bios password.
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Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

[Alexander Couzens]

Hi Martin,

I would like to take a look on your brick. Do you come to the meeting?

Best,
lynxis

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Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

[Alexander Couzens]

> No. Using a pomona 5250 clip to program a wson-8 chip on board is
> possible, according to
> https://www.coreboot.org/Board:lenovo/t430s#Preparation .
> 
> I have used this method to program my t430s.
I never tried it. Thanks for the tip!


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Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

[Alexander Couzens]

On Mon, 18 Sep 2017 02:17:56 +
Persmule  wrote:

> Why solder is needed? X230 is in-system
>  programmable with even a ch341a. 

Some boards come with a WSON8 spi flash. Or is there another way to
do in-system-programmable without an SPI clip?


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Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

[Alexander Couzens]

Hi,

the x230 is quite good working,
... but recently some boards died (I know from 2 boards over the last
years). I'm still not sure why they died, but rumors that the EC
firmware ran into a bug when doing In-Circuit flashing.

I've an x230 myself and never managed to trigger that bug. I would
recommend you to update the EC to the newest firmware. The EC firmware
is updated together with the bios, so updating the vendor bios/uefi is
enough.

We can also desolder your spi chip, programm it and put it back. But
that's also a way I wouldn't recommend doing to often.

Best,
lynxis
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Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

[Alexander Couzens]

Next meeting is coming.

> tldr;
21.09.2017 18:30 (open end) AfRA (different location!)

Hi,
 
the Berlin coreboot Meeting in September will taken
place on 21.09.2017 in the rooms of the Department Of Redundancy
Department (AfRA).

Abteilung für Redundanz Abteilung
Margaretenstraße 30
10317 Berlin
 
https://afra-berlin.de/

best,
lynxis

Ps. If you want to flash your laptop, send me a notice in advance.
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Re: [coreboot] Lenovo X1 carbon 3460 Screen stays black

[Alexander Couzens]

Hi Nico,

here is a follow. I somehow missed that when reviewing your commit...
https://review.coreboot.org/#/c/20918/

@Jo here is my image. I've enabled usb debug for output, which consumes
a lot boot time. So better compile coreboot another time on your own.

https://own.fe80.eu/s/OzAMekv0TpRGsFj

Best,
lynxis

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[coreboot] Berlin Usergroup Meeting 10. August Thursday (different location)

[Alexander Couzens]

tldr;
10.08.2017 18:30 (open end) AfRA (different location!)

Hi,

the Berlin Usergroup Meeting in August will taken
place on 10.08.2017 in the rooms of the Department Of Redundancy
Department (AfRA).

Abteilung für Redundanz Abteilung
Margaretenstraße 30
10317 Berlin

https://afra-berlin.de/

best,
lynxis

Ps. If you want to flash your laptop, send me a notice in advance.
Certain things might need to prepared for your device.
-- 
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Re: [coreboot] question on SMM

[Alexander Couzens]

On Fri, 30 Jun 2017 04:25:06 +
ron minnich  wrote:

> there's something I am certain I don't understand about SMM on intel
> chipsets.
> 
> The question is pretty simple. Consider a system with a recent intel
> chipset and flash. Is there some special secret sauce that disables
> writing to flash unless in SMM and if so, what is it?

There is also a talk explaining it (without SMM_BWP).

https://media.ccc.de/v/31c3_-_6129_-_en_-_saal_2_-_201412282030_-_attacks_on_uefi_security_inspired_by_darth_venamis_s_misery_and_speed_racer_-_rafal_wojtczuk_-_corey_kallenberg


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Re: [coreboot] GPG public key for corboot release signatures

[Alexander Couzens]

Hi Laszlo,

you can find the keys on the public key servern.
I've attached the fingerprints, but gpg can also show you when trying to
verify it.

> Why are there two signatures in the GPG signature file (for release
> 4.6) and why do the signature dates differ from the release date
> (according to the website)?

More signatures are better ;). Choose your own trust anchor.
I've signed it after it was released.

Best,
lynxis

Alexander Couzens <lyn...@fe80.eu>
  Key fingerprint = 390D CF78 8BF9 AA50 4F8F  F1E2 C29E 9DA6 A0DF 8604

Martin Roth (coreboot developer) <mar...@coreboot.org>
  Key fingerprint = 574C E6F6 855C FDEB 7D36  8E9D 1979 6C2B 3E4F 7DF7

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Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

[Alexander Couzens]

On Thu, 13 Apr 2017 20:37:58 +0200
Marek Behun <ka...@blackhole.sk> wrote:

> > but even without removing the pin 47, the card could work in the
> > wwan slot of the x201. do you tried this?  
> 
> According to this table
> http://www.thinkwiki.org/wiki/Problem_with_unauthorized_MiniPCI_network_card
> this method does not work on X201.

it doesn't work with vendor bios, but you're using coreboot, so it's
working. I've used 2 wifi cards in my x201 for years ;).

best,
lynxis

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Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

[Alexander Couzens]

On Thu, 13 Apr 2017 19:53:17 +0200
Marek Behun  wrote:

> Alexander,
> on the X230 I am putting the card into the slot for the WiFi card. I
> took out another 802.11ac WiFi card and put in this one (COMPLEX
> WLE900VX-7A). So if I remove port 47 and it will work on X201, it must
> also work on X230.

if the datasheets doesn't lie ;), correct.

but even without removing the pin 47, the card could work in the wwan
slot of the x201. do you tried this?


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Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

[Alexander Couzens]

Hi Marek,

I guess it's pin 47 which is the problem. All other pins look ok for
the x201 (even the MCI_ pins). So you could try to cut the line on the
card or remove the copper of this pin.

In your x201, the card should work in the WWAN slot well, except the
MCI_pins are connector to the sim slock, but no idea if this is a
problem ;).

The other solution would be, try to put the (x201) CL_DATA_WLAN/CL_DATA1
(me link) in tri state on the chipset side, but no idea if this is even
possible on the chipset.

Best,
lynxis

ps. x230 doesnt have a pcie capable wwan port
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Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

[Alexander Couzens]

On Thu, 13 Apr 2017 16:26:16 +0200
Marek Behun <ka...@blackhole.sk> wrote:

> I've just realized that on the compexshop webpage
> http://www.compexshop.com/product_info.php/cPath/104_105/products_id/452
> there is written
> 
>   Attention : Atheros 11ac radio can't be used in PC or laptop, as
> BIOS do not detects it, as Atheros do not release such driver. Pls
> read reviews for more details about supported PC boards

Strange. haven't heared about that. But if it's neither on lspci nor on
lsusb, I'm really surprise, how the non-pc's should use this card?!

It might be a special "resevered"-minipcie-pin which must be put on
3.3V.
Or the card doesn't like the additional I2C, which is used by the
ME to connect to the Wifi card.

Can you write a mail to compex about it?
IMHO you should see the card on lspci anyhow, even if it's missing
some magic init procedures.

Best,
lynxis
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Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

[Alexander Couzens]

On Thu, 13 Apr 2017 15:58:14 +0200
Marek Behun <ka...@blackhole.sk> wrote:

> Hello,
> 
> so I have tried to insert the COMPEX WLE900VX-7A wifi module
> (http://www.compexshop.com/product_info.php/cPath/104_105/products_id/452
> ) into the wifi slot of ThinkPad X230 and X201 (since on X230 the
> wifi slot is for half-sized module only, I had to file out the bump
> that is on one side istead of the hole for the screw).
> 
> For some reason this module does not show on lspci on either of this
> laptops (with coreboot installed). On Lenovo 3000 N200, it does show
> up.

I'm using an atheros card as well on x201 and x220. It should work. 

a) you're using WWAN slot and not WLAN (on some models wwan slot is a
full mini-pcie, but on most it's just usb)

b) the slot is disabled in nvram - try to use nvramtool. If such a slot
is disabled, the slot is hidden on pcie level, not sure if the power is
cut as well.

Best,
lynxis
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[coreboot] 33c3 congress organisation

[Alexander Couzens]

hi,

the chaos communication congress is knocking at the door.
I started a pad to track the hardware which is there for hacking.

https://pads.ccc.de/coreboot-33c3

best,
lynxis

ps. there is also a wiki link
https://events.ccc.de/congress/2016/wiki/Assembly:Coreboot
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Re: [coreboot] [RFC] Explicitly use C11 (was: Setting C99 by default)

[Alexander Couzens]

I like the idea of using C11.

best,
lynxis
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Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

[Alexander Couzens]

Hi Charlotte,

here are some description of the EC in your board. Don't know how much
you already know.

The Thinkpad has 2 EC controller.

1x Thinker
1x H8S (W530 has a SMSC chip).

The ectool dump only shows a buffer, which both side(host+ec) can use to
communicate.

The ectool usually talks to the H8S and not to the Thinker. There is a
way to community to the Thinker using different I/O address.

-
|Chipset|
-
   |
   | LPC
   |
---
| H8S |
---
   |
   | SPI
   |
-
|Thinker|
-

best,
lynxis
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Re: [coreboot] hackathon in Berlin next weekend 12-14.

[Alexander Couzens]

On Tue, 09 Aug 2016 11:15:34 +0200
Paul Menzel <paulepan...@users.sourceforge.net> wrote:

> Dear Alexander,
> 
> 
> Thank you for announcing the event on the list.
> 
> 
> Am Montag, den 08.08.2016, 18:00 +0200 schrieb Alexander Couzens:
> > some people are visiting Berlin for a hackathon next weekend (12-14)
> > The hackathon will taken place at the Finowstr. 2a.  
> 
> Do you already have an agenda? What do you want hack on?
no idea. 
there a lots of projects ;).

* LPC sniffer
* auto flasher (raspi + test clip + auto detect the board via flash
  content)
* Memory init haswell
* fix x201
[..]
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[coreboot] hackathon in Berlin next weekend 12-14.

[Alexander Couzens]

hi,

some people are visiting Berlin for a hackathon next weekend (12-14)
The hackathon will taken place at the Finowstr. 2a.
It's between the subway station U Samariter, U Frankfurter Str.

Best,
lynxis
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Re: [coreboot] How can extract descriptor.bin from bios image?

[Alexander Couzens]

Hi, 
use
 ifdtool -x 

best,
lynxis
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Re: [coreboot] account for lava hardware testing

[Alexander Couzens]

On Thu, 9 Jun 2016 20:32:59 +0200
Alexander Couzens <lyn...@fe80.eu> wrote:

> hi,
> 
> I would like to integrate gerrit into my jenkins to build coreboot and
> do hardware tests with lava.
> The jenkins can built a coreboot image and deploy + test the image via
> lava on a device (currently only x60).
> 
> It's based on two jenkins job
> 
> 1. compile coreboot
>  |
> 2. run lava job and wait for it's completion
> 
> But I would like also allow gerrit users to add a Lava user which
> triggers a job on jenkins and get an result in the end.
> 
> https://jenkins.fe80.eu/
> 
> jenkins config in .yml with jenkins job builder:
> https://code.fe80.eu/lynxis/coreboot-jenkins-jobs
> 
> coreboot.config and lava job.yml used by jenkins jobs:
> https://code.fe80.eu/lynxis/coreboot-configs
> 
> best,
> lynxis
> 
> ps. it's github auth if somebody want access, just ask.

forgot to mention, I would like to have a testing account with access
to the "event stream".

best,
lynxis

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[coreboot] account for lava hardware testing

[Alexander Couzens]

hi,

I would like to integrate gerrit into my jenkins to build coreboot and
do hardware tests with lava.
The jenkins can built a coreboot image and deploy + test the image via
lava on a device (currently only x60).

It's based on two jenkins job

1. compile coreboot
 |
2. run lava job and wait for it's completion

But I would like also allow gerrit users to add a Lava user which
triggers a job on jenkins and get an result in the end.

https://jenkins.fe80.eu/

jenkins config in .yml with jenkins job builder:
https://code.fe80.eu/lynxis/coreboot-jenkins-jobs

coreboot.config and lava job.yml used by jenkins jobs:
https://code.fe80.eu/lynxis/coreboot-configs

best,
lynxis

ps. it's github auth if somebody want access, just ask.
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Re: [coreboot] ThinkPad x220 - Status

[Alexander Couzens]

hey,

nice you made it!

> *3) Coreboot rocks but... Current Open issues:*
> -
> I decided to use coreboot-4.4 release instead of git-master.
> As payload I'm using SeaBIOS (booting Archlinux with Syslinux as
> bootloader).
That's ok.

> Before, with dmidecode -t 17 the speed was 1333Mhz and now it is just
> 667Mhz...
we might written the wrong value into dmidata. (dmidecode reads a
description written by the firmware, has nothing to do with the real
values).

> *3.2) TP-SMAPI: *
> --
tp smapi depends on lot of SMM/SMI code. So tp-smapi kernel module
asked the Lenovo BIOS to tell the EC to do something. coreboot don't
want to support SMM/SMI APIs, because they are quite dangerous.
But there is another way to get those features back.
We know how to enable it, but we haven't yet create a way to control
this by the user.

One thing could be a userspace tool executed as root or we add another 
CMOS configuration for it. Any idea?

> *3.3) Config files:*
> --
> coreboot - http://pastebin.com/9ymtxLBW
It looks you're using the native graphics init instead of the binary
blob VGABIOS. The last time I tried it, I had a lot of problems. [3]

Thanks for your feedback. Feel free to create tickets or updating the
x220 wiki page.

Best,
lynxis

[3] https://ticket.coreboot.org/issues/37
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Re: [coreboot] openbios in config?

[Alexander Couzens]

On Sat, 14 May 2016 20:26:08 -0700
David Griffith <d...@661.org> wrote:

> Is there any interest in having the Coreboot build process downliad
> and build OpenBIOS in the same fashion as SeaBIOS is now?

hi david,

I like it. It would be nice if you can upload a patch to gerrit [1]
doing it.

best,
lynxis

[1] https://review.coreboot.org
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[coreboot] sign fsfe radio lock down statement

[Alexander Couzens]

hi,

https://fsfe.org/activities/radiodirective/statement

IMHO: this lockdown is also one thing against coreboot, because the
hardware has to be locked downed.

Can we sign it?

Best,
lynxis
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Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

[Alexander Couzens]

On Mon, 2 May 2016 01:06:10 +0200
Daniel Kulesz <daniel.i...@googlemail.com> wrote:

> Okay. I was just aware of the generic "processor.max_cstate=2"
> parameter. I tried with both parameters using the vendor BIOS and
> here are the results:

Can you do a test run with closed devices? This would ensure, you're
not measurring a brightness difference.

best,
lynxis

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Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

[Alexander Couzens]

Hey,

I guess the vendor bios activate pci clock power save and similiar
options. Some are supported by coreboot, but not activated by default.
I can only guess, but the native vga init might also miss some power
management features.

best,
lynxis


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Re: [coreboot] Issue Tracker down?

[Alexander Couzens]

On Mon, 25 Apr 2016 19:24:18 +0200
Daniel Kulesz via coreboot <coreboot@coreboot.org> wrote:

> I just wanted to report bug regarding memory initialization on the
> F2A85-M, but it looks like the issue tracker is down:
sorry about that. My hoster just re-scheduled a downtime.
It's online again.

best,
lynxis
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Re: [coreboot] coreboot 4.4 release coming soon

[Alexander Couzens]

Lenovo:
- t400 - tested by CaptainCoward - boot
- x201 - broken - doesn't boot
- x220 - works

@Martin:
Can you create a rc1 tag for this? Everybody would against test the same
revision.



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Re: [coreboot] On Intel Boot Guard

[Alexander Couzens]

hi gary,

as far I know, the x240 is not "protected" from yourself by Intel Boot
Guard.

> From what I've seen the x240 isn't supported on Coreboot yet right?
right. nobody got one in range.

thanks for the dump, but don't think i've time to look at it before
next week, sorry.

best,
lynxis
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Re: [coreboot] Cleaning up old commits in gerrit

[Alexander Couzens]

> We're looking at cleaning up gerrit, so we're planning on abandoning
> some older commits.  To keep from overwhelming people, we're going to
> do it in stages.  Right now we're looking at abandoning all commits
> that haven't been updated in 18 Months. This is around 90 commits.
nice you're doing this.

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Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[Alexander Couzens]

On Wed, 09 Mar 2016 22:30:44 +
ron minnich <rminn...@gmail.com> wrote:

> That's great to hear. So it sounds like rom o matic would be handy.
> 
> That said, w.r.t. features. I'm not big on features. coreboot is a
> chance to brick your laptop. That means
> rom o matic should never ever ever give you a bad coreboot image.

> What would be cool would be to have a program they can run that
> creates a string, and the either you paste
> that string into a form or it connects and pastes it in (but what
> about DDOS?) and you get back a URL for an image
> that is known to work. Could the coreboot board status repo be used to
> determine this?
> 
> I think the messy part is that just because you have, say, an "x220",
> doesn't mean coreboot works on it, because PCs
> are never the same, even given the same number. So you need a very
> long signature that can confirm the coreboot
> running on everyone else's "x220" will work on yours.
> 
> Do we have any record as to how uniform, e.g., the x220 experience has
> been? I know the chromebook uniformity is pretty good.
They are uniform, beside the case of the spi. Most x220 have a spi in a
SOIC8, but some have a WSON or mlp8 case.

I had problems with my x220 because I desolered the wson chip and
soldered a SOIC8 which wasn't quite supported by coreboot. I say the
"normal" coreboot user wouldn't do that ;). They only use a clip.

Best,
lynxis
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[coreboot] tpm api merge

[Alexander Couzens]

Hi,

I'm looking at a huge tpm merge commit. +625, -748

So the question how can we merge this? As long we don't have further
testing, it's hard to decide. We won't catch all bugs. May be
chromeos have a tpm testing?

And also reorganize the commit into smaller ones are very hard and I
think it's not the effort worthy. Because merging two apis into one
is a big thing.

The only other way I can imagine merge 
I don't know how easy it is, having 3 apis lying in the tree.
The 2 "old" apis and the new merged one. Extending the new api until
it's working.

Can we freeze the tpm apis for now? It would give zaolin more time to
fix the problems and give the reviewer also more time to look over?!

Best,
lynxis

https://review.coreboot.org/#/c/10542/
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Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[Alexander Couzens]

On Wed, 09 Mar 2016 20:57:23 +
ron minnich <rminn...@gmail.com> wrote:

> I suspect you know far more about writing such a tool than I ever
> will, but far less about coreboot than you need to know. Your first
> step should be to get it, build it, and boot it in qemu; bonus points
> for doing it on real

I know a lot people who don't know or have problems compiling
coreboot on their own or they don't want to spent hours to compiling the
toolchain + coreboot. For these people rom-o-matic is a nice thing.

German hacker culture likes coreboot a lot. Last coreboot user
group meeting a journalist showed up. Someone spent her a x60 and she
would like to have coreboot on it. But after disassembling the hardware
down to the board itself, it turns out, she already got coreboot. I
never looked at the x60 bios booting up :).

There are also the cryptoparty people, they also support coreboot.
zaolin is doing installation partys at his hackerspace, too. And may
others do the same.
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Re: [coreboot] Coreboot X230 step-by-step

[Alexander Couzens]

On Tue, 23 Feb 2016 08:33:16 -0800
Vadim Bendebury <vben...@chromium.org> wrote:

> I have not read the page in full detail, just curious: was it
> necessary to unsolder the chip, was it not possible to program it
> using flashrom from Linux command line instead?

It may be possible. the main problem is the lenovo bios update. It's
still unknown how it's updating the rom. But the lenovo protects the
bios region from writing. AFAIK there is a *scratch* region writeable
possible for bios updates.

best,
lynxis
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Re: [coreboot] ThinkPoint under coreboot

[Alexander Couzens]

what's thinkpoint?
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[coreboot] berlin coreboot user group meeting 17.02.2016 18:00

[Alexander Couzens]

hey,

the next coreboot user group meeting is on 17.02. at 1800 as usual at
club discordia / cccb.

everybody is welcome. I'll take some flasher with me, but it's still a
good idea to send me an email so everything is prepared for your
coreboot installation ;)

best,
lynxis
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[coreboot] baytrail + fsp_baytrail

[Alexander Couzens]

hi,

baytrail and fsp_baytrail shares a lot of code.
Any ideas how we can merge these?

best,
lynxis

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Re: [coreboot] [ANNOUNCE] SeaBIOS 1.9.0

[Alexander Couzens]

https://review.coreboot.org/#/c/12566/
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Re: [coreboot] ThinkPad X120e/X140e

[Alexander Couzens]

Hi lynx,

mue and I started working on the x121e (amd) which might be similiar to
the x120e.

mue has atm all the hardware, just ask around, maybe you can continue
the work together. Creating a wiki entry would be nice with lspci lsusb
attached. I've also found the schematics for the x121e intel
version. x121e is the name for two baords, one based on
amd and one on intel.

just ask in the irc for mue or me.


best,
lynxis

ps. nice nickname ;)

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Re: [coreboot] setting up a bug tracker

[Alexander Couzens]

Hi,

I've setted up a bug tracker. 

https://ticket.coreboot.org/

login/registration via openid, google.
New users need a confirmation by zaolin or me.
If there is anything missing, I'm happy to receive any feedback.

Best,
lynxis
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Re: [coreboot] Understanding BIOS I/O Adresses

[Alexander Couzens]

Hi panic,

0x80 is a debug io port. There are pci cards showing you one byte on a
lcd display.
coreboot is using 0x80 too for debug output. The interface is simple,
the firmware/bios will increment the value sent to that address while
it's booting. In the case your bios is hangs somewhere while booting,
you can read from the card it's last byte sent to that ioport 0x80.

No idea what for the others io codes are.

best,
lynxis
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Re: [coreboot] setting up a bug tracker

[Alexander Couzens]

Hi,

I've started to setup a redmine. 
The openid integration seems to need more improvements,
but it should work as soon ssl works (and a another patch applied).

@Stefan/Patrick Can you create a CName for ticket.coreboot.org -> 
coreboot.dtn10.de

Next question is, how we handle the ssl stuff. Should we try let's encrypt?

Best
lynxis

On Thu, 5 Nov 2015 09:15:41 -0800
"Alex G." <mr.nuke...@gmail.com> wrote:
> Let's try it.

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[coreboot] screwdriver 0.3.0 released

[Alexander Couzens]

hi,

I'm happy to announce the release of screwdriver 0.3.0.

screwdriver is a small distribution for bbb (beagleboneblack) based on OpenWrt 
supporting
spi flashing and usbdebug.

Take a look on the wiki page [1] for more infomation.

Best
lynxis

PS. help or feedback is welcome!

[1] http://www.coreboot.org/BBB_screwdriver
[2] https://github.com/lynxis/bbb_screwdriver_builder
[3] 
http://repo.fe80.eu/screwdriver/0.3.0/omap/generic/default/openwrt-0.3.0-omap-beagleboneblack-sdcard-vfat-am335x_evm.img
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Re: [coreboot] screwdriver 0.3.0 released

[Alexander Couzens]

On Tue, 20 Oct 2015 09:23:00 -0400
Gregg Levine <gregg.drw...@gmail.com> wrote:

> Hello!
> I'm impressed. In fact the wiki page is easy to understand. How well
> does the USB debug module perform? Also for setting up the board to do
> that, you should include a write up as well. Although I believe there
> was one earlier in the Wiki.

any thoughts how to do that? could you write a small draft on what you
exactly mean?

best,
lynxis

ps. a pull-request is also welcome ;)
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Re: [coreboot] Rangeley SoC FSP and Mohon Peak board support

[Alexander Couzens]

Hi David,

that's great!

Welcome to the coreboot.

Best,
Alex

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Re: [coreboot] Emergency: Talks needed for coreboot conference in Bonn

[Alexander Couzens]

Hi,

I would like to give a talk about my embedded controller programming.

And beside that, I would like to have a talk/workshop something, to
think about the future/roadmap/vision/roadmap name how you like it.
how coreboot should be in the next year.

Best,
lynxis

On Fri, 2 Oct 2015 00:20:41 +0200
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2...@gmx.net> wrote:
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Alexander Couzens

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[coreboot] Berlin User Group Meeting 21.Sep

[Alexander Couzens]

Hi folks,

I'm starting a User Group in Berlin. The first meeting will take
place on 21. Sep. in the CCCB.

For more information about the location take a look on
https://berlin.ccc.de/wiki/Club_Discordia

Best,
lynxis

PS: Yes it's Monday evening and it's open for everyone.
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Re: [coreboot] Berlin User Group Meeting 21.Sep

[Alexander Couzens]

Opps, I forgot to mention the time ;)
21.Sep 20:30


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Re: [coreboot] mute button on X200

[Alexander Couzens]

On Sat, 22 Aug 2015 14:48:22 +0200
Idwer Vollering vid...@gmail.com wrote:

 Boot into vendor BIOS/EFI thing, install and start acpi_listen, then
 press the mute button.
 http://linux.die.net/man/8/acpi_listen

and take a look on Interaction with the Embedded Controller
at https://wiki.ubuntu.com/Kernel/Reference/ACPITricksAndTips

you want to know which _QXX function is called. maybe that one is empty in the 
coreboot aml for h8s..
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Re: [coreboot] mute button on X200

[Alexander Couzens]

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Hash: SHA256


 Would it help if I include logs here? If so, which logs?
ectool will also show some timers, which are counting upwards in the dump.
Last time I've looked at the ECDT (x201) it doesn't contain any additional 
information. There are multiple ways to provide the information saved in the 
ECDT. Coreboot is using the DSDT for that.

Let's say you know which byte is changing in the EC ram, what would you do than?

Best,
lynxis

PS: http://www.coreboot.org/EC:lenovo/x201
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Re: [coreboot] mute button on X200

[Alexander Couzens]

 Thanks, I'll take a look. It doesn't seem like the mute button is
 controlled by ACPI, though.
 
 Perhaps I could use ectool (and other utils?) to see what happens when
 muting.

maybe, maybe not. 
acpi_listen only helps you, when something in the user space is missing. It'll
show you what acpi event is generated from acpi code. But when the acpi code is
missing, you don't see anything there.
Take a look on the ubutun wiki and do the kernel debug thing it's described 
there.

ectool might show you what's changed, but I would bet, the ec is generating an 
ACPI query event,
which must be handled by _Qxx function.

cheers,
lynxis
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Re: [coreboot] coreboot meeting @chaos communication camp

[Alexander Couzens]

I'm looking forward to meet you.
At the moment we only have a small /tmp table in the BER village,
in the big yellow tipi tent. On the table lies some thinkpads ;).

But this table isn't yet final.

Best,
lynxis


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[coreboot] coreboot meeting @chaos communication camp

[Alexander Couzens]

hi,

some people will visit the chaos communication camp this year.
I'll be around for coreboot hacking and give some people a introduction into 
coreboot. I've started a etherpad for (hardware) organisation.
Who brings what or can bring?!

https://pads.ccc.de/coreboot-camp-2015

Best,
lynxis
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Re: [coreboot] T400 screen issue / EDID handling

[Alexander Couzens]

On Sun, 05 Jul 2015 15:57:30 +0100
Francis Rowe i...@gluglug.org.uk wrote:

 Libreboot builds coreboot without the .git directory, so it's not
 possible to get the coreboot revision. You can find out what version
I don't understand why you're removing the .git directory.
But anyhow, you should patch the coreboot version script. The script should
take your specific version of your libreboot build script git repo.
Please prefix the version with libreboot, it makes all our live easier to 
know what version is running and from where the version comes from.
And btw. this makes your coreboot' build reproducible, which isn't it atm.

Best
lynxis
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[coreboot] rtc migrations / century byte used

[Alexander Couzens]

Hi,

I mentioned some problems while debugging windows on a x201.
Also linux throw a warning with the RTC, but it could recover
the correct time.
coreboot multiple use of one nvram byte on lots of boards.
On most board 0x32/b400 is used by some nvram settings as well as the OS 
interprets the time (century) from the same byte.
The century byte saves the century in bcd format. The default location is 0x32 
/ b400.

find src/mainboard/ -iname cmos.layout | xargs grep -h '^400'  | sort | uniq -c
112 400  1   e   1power_on_after_fail
 33 400  1   e   2hyper_threading
  1 400  8   h   0century
  9 400  8   h   0volume
  1 400 8 r   0stumpy_usb_reset_disable
  2 400 8   h   0volume
# 37 boards can be removed from this list, because they disabled the century 
byte in facp.

This leads to 3 topic:
 * how can we change cmos.layout in a way no or less settings gets lost? e.g. 
add a version field and a way to migrate these. or do we ignore the loss of 
data?
 * do we want to support the century byte?
 * how do we fix the multiusage, because it makes problems atm.

best
lynxis

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Re: [coreboot] On Intel Boot Guard

[Alexander Couzens]

Hi Iru,

we aren't still sure which boards use Intel Boot Guard and which doesn't use 
it. But we expect most board use it,
because it's recommended by intel - as we dont recommend it.
Also there isn't yet a test script for Intel Boot Guard.

Can you post a link to that forum post?
I would like to look into a x240 flash image. If you have such board it would 
be nice
if you can send me a copy of the flash image via private mail.

Cheers,
lynxis
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[coreboot] force https on review.coreboot.org

[Alexander Couzens]

Hi,

review isn't forcing https. Can we please do this? Otherwise stealing cookies 
is posibble.
Review supports https. There is atm an CACert based certificate and CaCert 
isn't included in the default root keychain.
Thus a normal user will shown a big fat warning, not to connect to 
review.coreboot.org,
because the certificate is unknown and untrusted.
I don't have a problem with that and I like CaCert. But if CaCert is the reason 
not enabling https-only,
than let us change to StartSSL or someother SSL authority.

Best lynxis

PS. Same issue on www.coreboot.org, but stealing review is much more worse than 
stealing wiki cookies.
PPS. Please write a +1 if you're supporting this opinion.
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[coreboot] device_t or struct device *|pci_devfn_t

[Alexander Couzens]

Hi,

there are some patches out in gerrit to use struct device * instead of device_t.
I dislike the typedef of device_t but I see the reason - this was done to use 
the same code in preram stages
as well in ramstage.

In which way to we want to run? Should we replace device_t with struct device * 
and pci_devfn_t?

Best
lynxis

Edward's commit replacing device_t with struct device *
http://review.coreboot.org/#/c/7138/
http://review.coreboot.org/#/c/7139/
http://review.coreboot.org/#/c/7166/
http://review.coreboot.org/#/c/7169/
http://review.coreboot.org/#/c/7277/

My commit replacing device_t with pci_devfn_t
http://review.coreboot.org/#/c/9250/

Add device_t to device ops acpi generators.
http://review.coreboot.org/#/c/9598/
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Re: [coreboot] Automated test system: Nominations wanted

[Alexander Couzens]

On Mon, 16 Mar 2015 01:20:17 -0500
Timothy Pearson tpear...@raptorengineeringinc.com wrote:

 Just wanted to mention that Raptor Engineering now has an automated test 
 stand for the ASUS KFSN4-DRE board, run nightly with automatic bricking 
 recovery.  It has two Opteron 2431 (AMD Family 10h, 6 core @ 2.4GHz)CPUs 
 and 6GB of DDR2-667 memory installed on Node 0.
 
 Each successful test result is recorded to the board-status repository, 
 and each failure is reported to this list.

Hi Timothy,

can you please write down (wiki?) how your system is setted up?
How do you do automatic bricking recovery?

Best,
lynxis
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Re: [coreboot] H8 EC question

[Alexander Couzens]

Hi Charles,

it would be nice if you could extend the wiki page 
http://www.coreboot.org/EC:lenovo/x201
I'ven't found anything yet, what's x201 specific.

A good source of EC behaviour is the OEM ACPI Tables (dsdt) and the thinkpad 
acpi lkernel module.

Best,
lynxis


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Re: [coreboot] H8 EC question

[Alexander Couzens]

That would be great!

If you need to query the EC by ectool - there's a patch waiting for review at
https://review.coreboot.org/#/c/8382/

Best,
lynxis


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Re: [coreboot] Coreboot reproducible builds

[Alexander Couzens]

Hi Emilian,

I chatted today with Holger from reproducible.debian.net and couldn't resist 
doing reproducible builds ;).
These patches need additonal work, but they are working when the git tree is 
clean.
You can test coreboot reproducible when building without payload. Or a more 
advanced way integrate my seabios git-tree
into coreboot's payload target.

coreboot needs 2 patches (one is very dirty ;) to build reproducible.
http://review.coreboot.org/#/c/8611/
http://review.coreboot.org/#/c/8612/

SeaBIOS requires one patch.
https://github.com/lynxis/seabios/commit/487ef74fc6cb1b1020fb25c9bb3f166602ca926c

Best,
lynxis


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Re: [coreboot] x201t + windows7

[Alexander Couzens]

Hi,

I got a checked build as well as a working `original` usbdebug device (thanks 
to peter and cristi).
My windows got nice after I disabled lowmem with `/lowmem`.
What does this means? I thought this might be a problem with the memory map? Or 
pci management?
Missing out a memory block to mark forbidden? VideoRAM? VBIOS? [...]

I've disabled a workaround for grub to free SeaBIOS from marking 0x0 - 0xfff as 
RAM.
But doesn't help.
I still get a bluescreen '... stop 0x7e'. The internet suggest a look on 
(video) drivers.

 However they're of limited use when trying to find issues in the 
 installer, since that (at least up to Win8) is non-checked even on 
 checked build media.
Ok, I forgotten this.  I'll take another try with my hdd win 7, maybe it gives 
me more information
with usb debug than the installer does.
Another thing on my list is disabling and hide useless pci device.  Starting 
with ethernet ;).

@Patrick: any further suggestions?

Thanks,
lynxis

[0.00] BIOS-e820: [mem 0x-0x0fff] reserved
[0.00] BIOS-e820: [mem 0x1000-0x0009fbff] usable
[0.00] BIOS-e820: [mem 0x0009fc00-0x0009] reserved
[0.00] BIOS-e820: [mem 0x000f-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0xbf6a7fff] usable
[0.00] BIOS-e820: [mem 0xbf6a8000-0xbfff] reserved
[0.00] BIOS-e820: [mem 0xc1c0-0xc3ff] reserved
[0.00] BIOS-e820: [mem 0xd000-0xefff] reserved
[0.00] BIOS-e820: [mem 0xfed0-0xfedf] reserved
[0.00] BIOS-e820: [mem 0x0001-0x0001fbff] usable
[0.00] BIOS-e820: [mem 0x0001fc00-0x0001] reserved
[0.00] BIOS-e820: [mem 0x0002-0x000237ff] usable


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[coreboot] jolla tabletswith or without intel boot guard?

[Alexander Couzens]

Hi,

FYI: I've created a ticket in jolla's ticket system. When I've received an 
answer I'll paste it here too.

Best,
lynxis
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Re: [coreboot] GSOC 2015 Preperations

[Alexander Couzens]

Hi Marc,

I would like to attend as a student this year.
I'm open for most of the ideas at the page.
Here are some of my ideas.

- porting new mainboards (hp micro n54L and x121e atm)
- porting new arm platforms
- refactoring amd code
- create an opensource firmware for some Thinkpad (H8S based)
- building a basic testing system (looking for a x60 or other supported_board)
- add usb debug support to SerialICE

Best,
lynxis

On Sat, 14 Feb 2015 00:05:28 +
Marc Jones marcj...@gmail.com wrote:

 Hi Everyone,
 
 It is time for coreboot to apply for GSOC 2015. We could use your help. We
 need student project ideas, mentors, and qualified students!
 
 Please update the wiki page with project ideas.
 http://www.coreboot.org/Project_Ideas
 
 Let me know if you would like to be a student mentor this summer. You need
 to signup with Google and then I can add you to the project.
 
 Start informing prospective GSOC students about coreboot. Please be helpful
 to new faces in IRC and direct them to me or Patrick if they have questions.
 
 Regards,
 Marc



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[coreboot] x201t + windows7

[Alexander Couzens]

Hi,

I tried today a windows 7 installation usb stick and a cd disc.
Both 32bit and 64bit.

Both Windows' stopping at disk.sys and the hdd led on.
32bit: sometimes windows boots, most time not.

Any ideas, what's wrong?

Best,
lynxis
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Re: [coreboot] GSoC 2015

[Alexander Couzens]

On Tue, 10 Feb 2015 01:16:26 +0100
Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote:

 Applications for organizations are open again. The deadline is very
 short this time: Only 10 days!
 
 http://www.google-melange.com/gsoc/homepage/google/gsoc2015

Who is doing the application for coreboot? Is something missing?
I would like to attend as student this year ;).

Best,
lynxis
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Re: [coreboot] Plans for upcoming Broadwell Thinkpads

[Alexander Couzens]

On Fri, 06 Feb 2015 11:16:48 -0600
Timothy Pearson tpear...@raptorengineeringinc.com wrote:

 On 02/06/2015 06:29 AM, Zaolin wrote:
  Hi,
 
  new thinkpad's can't be used anymore for coreboot. Especially the U and
  Y Intel CPU Series.
  They come with Intel Boot Guard and you are won't be able to boot
  anything which is unsigned and
  not approved by OEM. This means the OEM are fusing SHA256 public key
  hashes into the southbridge.
 
  For more details take a look at Intel Boot Guard architecture. It could
  be also confirmed by Secunet AG and Google.
 
  Regards Zaolin
 
 That's scary to say the least.  No more Thinkpads for us...
 

Is it used by Lenovo?
I think I can boot a USB-Linux on a new Thinkpad within a friendly Lenovo Store.
How can it tested? What registers must be read?

Best,
lynxis
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Re: [coreboot] Internal Ethernet controller on Mohon Peak CRB failed to get activated

[Alexander Couzens]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256

On Mon, 5 Jan 2015 13:49:05 +0100
Patrick Agrain patrick.agr...@alcatel-lucent.com wrote:

 Hello Fei,
 
 Thanks for your answer.
 Indeed, the INCLUDE_ME and ME_PATH are not configured, because I do not 
 really know what is the constitution of a descriptor.bin file.
 
 May anybody have any pointer which could explain me what it is ?

It's the intel management engine. It's does some power management and a lot 
other things. It's a cpu
and has access to *everything* like ram, chipset, ...

http://www.coreboot.org/Intel_Management_Engine

Best,
lynxis
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Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.

[Alexander Couzens]

Hi Andrew,

on my x201t I got the same problems. I bisect it to
cbmem console: Locate the preram console with a symbol instead of a section.
(commit 35382a6e, Change-Id: I3257b981e).

@Gabe: Do you tested the commit with SeaBios as payload?

@Andrew: You can also use a raspberry pi or a beaglebone black. They are a lot 
faster than
a buspirate (30min - 5min).

Best,
Alex

cfg:
http://lynxis.crew.c-base.org/coreboot.config.762d53d41_without_cbmem


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[coreboot] x201(t): function keys stopped working

[Alexander Couzens]

Hi everyone,

after some time the function keys stopped working on the x201t.
The FN-keys are emitted over SCI and ACPI EC Query functions.
It seems to be, the EC only raise SCI once until the first event is processed.
All events happened before the first event is queried will be queued.
I can get the FN-keys working again when I'm query the EC from userspace.
All remaining events in the queue will be processed now. I assume the bug comes 
with
suspend in rare cases.

Where can I put the EC query on wakeup?

Best,
Alex
-- 
Alexander Couzens

mail: lyn...@fe80.eu
jabber: lyn...@jabber.ccc.de
mobile: +4915123277221

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