[coreboot] Re: Change Romsize and CBFS size.
Hi Nico, Nico Huber wrote: > Hi Nitin, > > On 11.06.20 18:44, nitin.ramesh.singh(a)gmail.com wrote: > > Flash start -> 0xFC00 (with-in 4GB space > > @4227858432) > this is misleading. Setting it in the FMAP makes sense to make the > calculations work, but the flash is not mapped there. > > Because of other fixed resources below 0xff00, the architectural > limit of memory-mapped flash space is 16MiB. Some chipsets even limit > the mapping to 8MiB. Without making changes to coreboot code (e.g. > switch from memory mapped flash access to using the SPI controller), > all coreboot regions have to fall into the memory mapped space. > I am aware about the given fact... just wanted to describe the way fmap is being arranged. https://www.coreboot.org/Developer_Manual/Memory_map > > Can any one please let me know what are the other > > changes required to incorporate the Coreboot image as per the given layout? > Generally, such a big CBFS seems odd. I think changes are better made > outside of coreboot, e.g. the payload. What is your exact use case? > > Nico I am using the direct-grub payload (which incorporates cbfs with a limitation of maximum 16MB memory mapped flash space), plus I want to package few other binaries. Thanks, Nitin ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Change Romsize and CBFS size.
Hi Nitin, On 11.06.20 18:44, nitin.ramesh.si...@gmail.com wrote: > Flash start -> 0xFC00 (with-in 4GB space @4227858432) this is misleading. Setting it in the FMAP makes sense to make the calculations work, but the flash is not mapped there. Because of other fixed resources below 0xff00, the architectural limit of memory-mapped flash space is 16MiB. Some chipsets even limit the mapping to 8MiB. Without making changes to coreboot code (e.g. switch from memory mapped flash access to using the SPI controller), all coreboot regions have to fall into the memory mapped space. > Can any one please let me know what are the other changes required to > incorporate the Coreboot image as per the given layout? Generally, such a big CBFS seems odd. I think changes are better made outside of coreboot, e.g. the payload. What is your exact use case? Nico ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Change Romsize and CBFS size.
Hi,
Do you already have a 64MB BIOS chip? If not, you first need to check if
your CPU supports that size (that's pretty big, I'd be surprised). If it
does, are you planning to swap the chip?
Assuming the answer to the above is "yes", you'll also need to change the
Intel Firmware Descriptor to recognize a 64MB chip so you can flash it.
I did this to upgrade my 8MB chip to a 16MB chip and wrote up a guide /
experience report here:
https://rsend.wordpress.com/x210-coreboot/increasing-rom-chip-size-on-an-x210/
Good luck,
Rafael
On Thu, Jun 11, 2020 at 9:44 AM wrote:
> Hi,
>
> I am trying to build a Coreboot for a Flash Size as 64 MB, with 32MB
> reserved for a BIOS region.
>
> I have modified the descriptor for a bios region:
> 0200:03ff bios
>
> The fmap used for the given setting is as follows:
>
> FLASH@4227858432 0x400 {
> BIOS@33554432 0x200 {
> FMAP@0 0x200
>
> RW_MRC_CACHE@65536 0x1
> COREBOOT(CBFS)@131072 33423360
> }
> }
>
> Flash start -> 0xFC00 (with-in 4GB space @4227858432)
> Flash Size -> 0x400
> BIOS Start offset w.r.t Flash start -> 0x200 (@33554432)
> Bios region size -> 0x200
> CBFS Size -> 0x1FE
>
> Can any one please let me know what are the other changes required to
> incorporate the Coreboot image as per the given layout?
>
> Thanks,
> Nitin.
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