from:"Pankaj Bansal"

Re: [edk2-devel] [PATCH edk2-platforms 3/3] Silicon/NXP: Add Support for git commit info print

2020-08-07 Thread Pankaj Bansal

> > index 91b19f832f00..bc782e7e3873 100644
> > --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > @@ -12,6 +12,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >
> >  /**
> > @@ -89,10 +90,26 @@ ChassisInit (
> >VOID
> >)
> >  {
> > +  CHAR8 Buffer[100];
> > +  UINTN CharCount;
> > +
> >//
> >// Early init serial Port to get board information.
> >//
> >SerialPortInitialize ();
> >
> > +  CharCount = AsciiSPrint (
> > +Buffer, sizeof (Buffer),
> > +"UEFI firmware built at %a on %a. version:\n\r",
> > +__TIME__, __DATE__
> > +  );
> > +  SerialPortWrite ((UINT8 *) Buffer, CharCount);
> 
> Drop space before Buffer.

OK.

> 
> > +
> > +  CharCount = AsciiSPrint (
> > +Buffer, sizeof (Buffer), "%s\n\r",
> > +(CHAR16 *)PcdGetPtr (PcdFirmwareVersionString)
> > +  );
> > +  SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > +
> >SmmuInit ();
> >  }
> > diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
> b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
> > index 30f8f945b233..6d546f4754f9 100644
> > --- a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
> > +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
> > @@ -12,6 +12,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >
> >  /**
> > @@ -64,8 +65,24 @@ ChassisInit (
> >VOID
> >)
> >  {
> > +  CHAR8 Buffer[100];
> > +  UINTN CharCount;
> > +
> >//
> >// Early init serial Port to get board information.
> >//
> >SerialPortInitialize ();
> > +
> > +  CharCount = AsciiSPrint (
> > +Buffer, sizeof (Buffer),
> > +"UEFI firmware built at %a on %a. version:\n\r",
> > +__TIME__, __DATE__
> > +  );
> > +  SerialPortWrite ((UINT8 *) Buffer, CharCount);
> 
> Drop space before Buffer.

OK.

> 
> I will note here that you are adding identical content to two
> different ChassisLib implementations.
> 
> This is a strong indicator that the abstraction level is currently
> incorrect and should be revisited.
> 

I am preparing the patches to get the core/cluster info in NXP SOCs.
I will move the version print in that code.

> > +
> > +  CharCount = AsciiSPrint (
> > +Buffer, sizeof (Buffer), "%s\n\r",
> > +(CHAR16 *)PcdGetPtr (PcdFirmwareVersionString)
> > +  );
> > +  SerialPortWrite ((UINT8 *) Buffer, CharCount);
> >  }
> > diff --git a/Silicon/NXP/set_firmware_ver.sh
> b/Silicon/NXP/set_firmware_ver.sh
> 
> This script doesn't *set* anything (which is good, since I would have
> rejected that outright), so the name should reflect the actual function.

it *does* set the FIRMWARE_VER environment variable.
FIRMWARE_VER is just like WORKSPACE and PACKAGES_PATH.

> 
> > new file mode 100755
> > index ..ba2336ad23dc
> > --- /dev/null
> > +++ b/Silicon/NXP/set_firmware_ver.sh
> > @@ -0,0 +1,36 @@
> > +#!/bin/sh
> > +#
> > +# Copyright 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +# parse PACKAGES_PATH and set FIRMWARE_VER based on that
> 
> This too should reflect actual function.

see explanation above.

> 
> > +
> > +get_git_version()
> > +{
> > +  command -v git>/dev/null 2>&1
> > +  if [ $? -eq 0 ] && [ -n "$1" ]
> > +  then
> > +head_or_tag=`git -C $1 describe --tag --dirty --broken --always 
> > 2>/dev/null`
> > +printf $head_or_tag
> > +  fi
> > +}
> > +
> > +if [ -n "$FIRMWARE_VER" ]; then
> > +  echo "Warning FIRMWARE_VER=$FIRMWARE_VER is already set"
> > +  echo "Please retry after 'unset FIRMWARE_VER' command"
> > +fi
> 
> Just do
> FIRMWARE_VER=
> before the first code in the script.

OK.

> 
> > +
> > +directories=$(echo $PACKAGES_PATH | tr ":" "\n")
> 
> Could set IFS=: instead, it would have the same effect.

Good suggestion. will modify.

> 
> > +for dir in $directories; do
> > +  if [ -n "$FIRMWARE_VER" ]; then
> > +FIRMWARE_VER="$FIRMWARE_VER;$(basename $dir):$(get_git_version
> $dir)"
> > +  else
> > +FIRMWARE_VER=$(basename $dir):$(get_git_version $dir)
> > +  fi
> > +done
> > +
> > +echo "FIRMWARE_VER=$FIRMWARE_VER"
> > +export FIRMWARE_VER=$FIRMWARE_VER
> 
> What is this line supposed to achieve?

It would set the FIRMWARE_VER environment variable when "set_firmware_ver.sh" 
script is executed.
After that user can build platform firmware with -D FIRMWARE_VER=$ FIRMWARE_VER 
flag.
I have put this suggestion for users in "set_firmware_ver.sh" script.

> 
> /
> Leif
> 
> > +
> > +echo "build edk2 firmware with -D FIRMWARE_VER=\$FIRMWARE_VER"
> > --
> > 2.17.1
> >

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Re: [edk2-devel] [PATCH edk2-test 1/1] SctPkg: fix page alignment calculations

2020-07-23 Thread Pankaj Bansal

ping!!

> -Original Message-
> From: Pankaj Bansal (OSS) 
> Sent: Saturday, July 4, 2020 9:22 PM
> To: devel@edk2.groups.io; Eric Jin ; G Edhaya Chandran
> 
> Cc: Pankaj Bansal ; Paul Yang ;
> Samer El-Haj-Mahmoud ; Gaurav Jain
> 
> Subject: [PATCH edk2-test 1/1] SctPkg: fix page alignment calculations
> 
> From: Pankaj Bansal 
> 
> The BBTestAllocatePagesInterfaceTest tries to allocate pages for
> different memory types.
> While doing so, it tries to fix up the Start and PageNum for 64K
> Page size. There are multiple issues with this:
> 
> 1. 64K alignment is being done regardless of Processor type and Memory
>type. while this is correct for ARM64 Processor, it might not be so
>for other Processor types. Also 64K alignment for ARM64 Processor
>is needed for some Memory types not all.
> 2. The Start is being incremented by 64K, even if Start is already 64K
>aligned.
> 3. PageNum is being decreased by 16 pages indiscriminately, which might
>not be needed in all cases.
> 
> fix all these issues by correctly doing the alignment in all needed
> cases.
> 
> Cc: Paul Yang 
> Cc: Samer El-Haj-Mahmoud 
> Cc: Gaurav Jain 
> Signed-off-by: Pankaj Bansal 
> ---
>  .../MemoryAllocationServicesBBTestFunction.c  | 148 +-
>  1 file changed, 106 insertions(+), 42 deletions(-)
> 
> diff --git a/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
> oxTest/MemoryAllocationServicesBBTestFunction.c b/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
> oxTest/MemoryAllocationServicesBBTestFunction.c
> index d18fe1fc2b94..9ed9e6e0de74 100644
> --- a/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
> oxTest/MemoryAllocationServicesBBTestFunction.c
> +++ b/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
> oxTest/MemoryAllocationServicesBBTestFunction.c
> @@ -354,6 +354,7 @@ BBTestAllocatePagesInterfaceTest (
>EFI_TPL  OldTpl;
>EFI_MEMORY_DESCRIPTORDescriptor;
>UINTNPageNum;
> +  UINTNAlignment;
> 
>//
>// Get the Standard Library Interface
> @@ -700,14 +701,23 @@ BBTestAllocatePagesInterfaceTest (
>  PageNum = (UINTN)Descriptor.NumberOfPages;
>  Start   = Descriptor.PhysicalStart;
> 
> -//
> -// Some memory types need more alignment than 4K, so
> -//
> -if (PageNum <= 0x10) {
> +Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
> +
> +if  (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory   ||
> + AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS   ||
> + AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
> + AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
> +
> +  Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
> +}
> +
> +Start   = (Start + Alignment - 1) & ~(Alignment - 1);
> +PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
> +
> +PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
> +if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
>break;
>  }
> -Start   = (Start + 0x1) & 0x;
> -PageNum = PageNum - EFI_SIZE_TO_PAGES(0x1);
> 
>  Memory  = Start;
> 
> @@ -830,14 +840,23 @@ BBTestAllocatePagesInterfaceTest (
>  PageNum = (UINTN)Descriptor.NumberOfPages;
>  Start   = Descriptor.PhysicalStart;
> 
> -//
> -// Some memory types need more alignment than 4K, so
> -//
> -if (PageNum <= 0x10) {
> +Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
> +
> +if  (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory   ||
> + AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS   ||
> + AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
> + AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
> +
> +  Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
> +}
> +
> +Start   = (Start + Alignment - 1) & ~(Alignment - 1);
> +PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
> +
> +PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
> +if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
>break;
>  }
> -Start   = (Start + 0x1) & 0x;
> -PageNum = Pag

Re: [edk2-devel] [PATCH edk2-platforms 2/3] Silicon/NXP: Add support for reserving a chunk from RAM

2020-07-18 Thread Pankaj Bansal

Please don't merge this Patch.

This patch needs update. The ReservedRam needs to be reported to UEFI.
I will send v2 for this patch. other patches in this series can be reviewed.

Regards,
Pankaj Bansal

> -Original Message-
> From: Pankaj Bansal (OSS) 
> Sent: Wednesday, July 8, 2020 10:50 AM
> To: Leif Lindholm ; Meenakshi Aggarwal
> ; devel@edk2.groups.io; Ard Biesheuvel
> 
> Subject: [PATCH edk2-platforms 2/3] Silicon/NXP: Add support for reserving a
> chunk from RAM
> 
> From: Pankaj Bansal 
> 
> Some NXP SOCs have some specialized IP blocks (like MC), which
> require DDR memory to operate. This DDR memory should not be managed
> by OS or UEFI.
> 
> Moreover to ensure that these IP blocks always get memory, and maximum
> contiguous RAM is available for UEFI and OS to use, add the support for
> reserving a chunk from RAM before reporting available RAM to UEFI.
> 
> Signed-off-by: Pankaj Bansal 
> ---
>  Silicon/NXP/NxpQoriqLs.dec|  10 ++
>  Silicon/NXP/LX2160A/LX2160A.dsc.inc   |   4 +
>  Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf |   3 +
>  Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c   | 142
> +++-
>  4 files changed, 157 insertions(+), 2 deletions(-)
> 
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 188a9fe1f382..0e762066e547 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -41,3 +41,13 @@ [PcdsDynamic.common]
> 
> gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x06
> 00
>gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x0601
> 
> gNxpQoriqLsTokenSpaceGuid.PcdPciHideRootPort|FALSE|BOOLEAN|0x060
> 2
> +
> +  # Reserved RAM Base address alignment. This number ought to be Power of
> two
> +  # in case no alignment is needed, this number should be 1.
> +
> gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x1|UINT64|0x
> 0603
> +  # Size of the RAM to be reserved. This RAM region is neither reported to 
> UEFI
> +  # nor to OS
> +
> gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x0604
> +  # Reserved RAM Base address which is calculated based on
> PcdReservedMemSize
> +  # and PcdReservedMemAlignment
> +
> gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0|UINT64|0x0605
> diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> index 43e361464c8e..755ca169f213 100644
> --- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> @@ -29,6 +29,10 @@ [PcdsDynamicDefault.common]
>gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x620
>gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C
> 
> +[PcdsDynamicHii]
> +
> gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|L"ReservedMemAlig
> nment"|gEfiGlobalVariableGuid|0x0|0x2000|NV,BS
> +
> gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|L"ReservedMemSize"|gEfi
> GlobalVariableGuid|0x0|0x2000|NV,BS
> +
>  [PcdsFixedAtBuild.common]
>gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A
>gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x239
> diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> index a33f8cd3f743..ed23a86b43d9 100644
> --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> @@ -49,6 +49,9 @@ [FixedPcd]
>  [Pcd]
>gArmTokenSpaceGuid.PcdSystemMemoryBase
>gArmTokenSpaceGuid.PcdSystemMemorySize
> +  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
> +  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase
> +  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
> 
>  [Depex]
>TRUE
> diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> index 11d1f1260b35..b416323a4ced 100644
> --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> @@ -118,6 +118,127 @@ GetDramRegionsInfo (
>return EFI_BUFFER_TOO_SMALL;
>  }
> 
> +/**
> +  Calculate the base address of Reserved RAM.
> +  Reserved RAM is not reported to either UEFI or OS.
> +
> +  @param[in, out] DramRegions  Array of type DRAM_REGION_INFO. The size
> of this
> +   array must be one more (+ 1) than the maximum
> +   regions supported on platform. This is 
> because,
> +   if due to Reserved RAM alignment requirements 
> a
> +

[edk2-devel] [PATCH edk2-platforms 1/3] Silicon/NXP: Use runtime safe version of DebugLib

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

For DXE_RUNTIME_DRIVER runtime safe version of DebugLib should be
used. Otherwise, any DEBUG print in code can result in abort in OS.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/NxpQoriqLs.dsc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index ee639d552483..06ee012c227a 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -163,6 +163,7 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER]
   
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+  
DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
 
 [LibraryClasses.AARCH64]
   #
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 2/3] Silicon/NXP: Add support for reserving a chunk from RAM

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

Some NXP SOCs have some specialized IP blocks (like MC), which
require DDR memory to operate. This DDR memory should not be managed
by OS or UEFI.

Moreover to ensure that these IP blocks always get memory, and maximum
contiguous RAM is available for UEFI and OS to use, add the support for
reserving a chunk from RAM before reporting available RAM to UEFI.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/NxpQoriqLs.dec|  10 ++
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   |   4 +
 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf |   3 +
 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c   | 142 
+++-
 4 files changed, 157 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 188a9fe1f382..0e762066e547 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -41,3 +41,13 @@ [PcdsDynamic.common]
   gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x0600
   gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x0601
   gNxpQoriqLsTokenSpaceGuid.PcdPciHideRootPort|FALSE|BOOLEAN|0x0602
+
+  # Reserved RAM Base address alignment. This number ought to be Power of two
+  # in case no alignment is needed, this number should be 1.
+  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x1|UINT64|0x0603
+  # Size of the RAM to be reserved. This RAM region is neither reported to UEFI
+  # nor to OS
+  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x0604
+  # Reserved RAM Base address which is calculated based on PcdReservedMemSize
+  # and PcdReservedMemAlignment
+  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0|UINT64|0x0605
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc 
b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
index 43e361464c8e..755ca169f213 100644
--- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
+++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
@@ -29,6 +29,10 @@ [PcdsDynamicDefault.common]
   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x620
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C
 
+[PcdsDynamicHii]
+  
gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|L"ReservedMemAlignment"|gEfiGlobalVariableGuid|0x0|0x2000|NV,BS
+  
gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|L"ReservedMemSize"|gEfiGlobalVariableGuid|0x0|0x2000|NV,BS
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A
   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x239
diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf 
b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
index a33f8cd3f743..ed23a86b43d9 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
@@ -49,6 +49,9 @@ [FixedPcd]
 [Pcd]
   gArmTokenSpaceGuid.PcdSystemMemoryBase
   gArmTokenSpaceGuid.PcdSystemMemorySize
+  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
+  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase
+  gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
 
 [Depex]
   TRUE
diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c 
b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
index 11d1f1260b35..b416323a4ced 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
@@ -118,6 +118,127 @@ GetDramRegionsInfo (
   return EFI_BUFFER_TOO_SMALL;
 }
 
+/**
+  Calculate the base address of Reserved RAM.
+  Reserved RAM is not reported to either UEFI or OS.
+
+  @param[in, out] DramRegions  Array of type DRAM_REGION_INFO. The size of this
+   array must be one more (+ 1) than the maximum
+   regions supported on platform. This is because,
+   if due to Reserved RAM alignment requirements a
+   hole is created in any DRAM region, then the RAM
+   after hole gets reported to UEFI and then
+   subsequently to OS. which is why, the last entry
+   of this array will not be parsed while
+   calculating Reserved RAM base address. Caller
+   must ensure that last entry of this array is 
zero
+   initialized.
+  @param[in] NumRegionsSize of DramRegions array (including +1 for 
hole)
+  @param[in] ReservedMemSize   Size of RAM to be reserved.
+
+  @return  if successful Address of the Reserved RAM region, 0 otherwise.
+**/
+STATIC
+UINTN
+CalculateReservedMemBase (
+  IN DRAM_REGION_INFO *DramRegions,
+  IN UINT32   NumRegions,
+  IN UINTNReservedMemSize
+)
+{
+  UINTN ReservedMemAlignment;
+  EFI_PHYSICAL_ADDRESS  AlignmentMask;
+  UINTN RegionBaseAddress;
+  UINTN

[edk2-devel] [PATCH edk2-platforms 3/3] Silicon/NXP: Add Support for git commit info print

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

This patch adds the Support for printing the git commit information
in linux build environment.

Ideal place of retrieving this information should be python script in
BaseTools.

A Feature request for the same has been created:
https://bugzilla.tianocore.org/show_bug.cgi?id=2838

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/NxpQoriqLs.dsc.inc   |  3 ++
 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf   |  5 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf |  5 +++
 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 17 +
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c   | 17 +
 Silicon/NXP/set_firmware_ver.sh  | 36 

 6 files changed, 83 insertions(+)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 06ee012c227a..a0762a6ef61d 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -224,6 +224,9 @@ [PcdsDynamicHii.common.DEFAULT]
   
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
 
 [PcdsFixedAtBuild.common]
+  !ifdef $(FIRMWARE_VER)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+  !endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf 
b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
index f5dbd1349dc5..69f884af9e34 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -16,6 +16,7 @@ [Defines]
 
 [Packages]
   ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/NXP/Chassis2/Chassis2.dec
   Silicon/NXP/NxpQoriqLs.dec
@@ -24,6 +25,7 @@ [LibraryClasses]
   IoAccessLib
   IoLib
   PcdLib
+  PrintLib
   SerialPortLib
 
 [Sources.common]
@@ -31,3 +33,6 @@ [Sources.common]
 
 [FeaturePcd]
   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
index 75b68cc4ca2d..632acc52b20a 100644
--- a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -16,6 +16,7 @@ [Defines]
 
 [Packages]
   ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/NXP/Chassis3V2/Chassis3V2.dec
   Silicon/NXP/NxpQoriqLs.dec
@@ -24,6 +25,7 @@ [LibraryClasses]
   IoAccessLib
   IoLib
   PcdLib
+  PrintLib
   SerialPortLib
 
 [Sources.common]
@@ -31,3 +33,6 @@ [Sources.common]
 
 [FeaturePcd]
   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c 
b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
index 91b19f832f00..bc782e7e3873 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 /**
@@ -89,10 +90,26 @@ ChassisInit (
   VOID
   )
 {
+  CHAR8 Buffer[100];
+  UINTN CharCount;
+
   //
   // Early init serial Port to get board information.
   //
   SerialPortInitialize ();
 
+  CharCount = AsciiSPrint (
+Buffer, sizeof (Buffer),
+"UEFI firmware built at %a on %a. version:\n\r",
+__TIME__, __DATE__
+  );
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+  CharCount = AsciiSPrint (
+Buffer, sizeof (Buffer), "%s\n\r",
+(CHAR16 *)PcdGetPtr (PcdFirmwareVersionString)
+  );
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
   SmmuInit ();
 }
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
index 30f8f945b233..6d546f4754f9 100644
--- a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 /**
@@ -64,8 +65,24 @@ ChassisInit (
   VOID
   )
 {
+  CHAR8 Buffer[100];
+  UINTN CharCount;
+
   //
   // Early init serial Port to get board information.
   //
   SerialPortInitialize ();
+
+  CharCount = AsciiSPrint (
+Buffer, sizeof (Buffer),
+"UEFI firmware built at %a on %a. version:\n\r",
+__TIME__, __DATE__
+  );
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+

[edk2-devel] [PATCH edk2-platforms 0/3] Add Features to NXP Platforms

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

This patch series adds some useful features to NXP platforms.
- runtime safe version of DebugLib
- Add support for reserving a chunk from RAM
- Add Support for git commit info print

Pankaj Bansal (3):
  Silicon/NXP: Use runtime safe version of DebugLib
  Silicon/NXP: Add support for reserving a chunk from RAM
  Silicon/NXP: Add Support for git commit info print

 Silicon/NXP/NxpQoriqLs.dec|  10 ++
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   |   4 +
 Silicon/NXP/NxpQoriqLs.dsc.inc|   4 +
 .../Library/ChassisLib/ChassisLib.inf |   5 +
 .../Library/ChassisLib/ChassisLib.inf |   5 +
 .../MemoryInitPeiLib/MemoryInitPeiLib.inf |   3 +
 .../Chassis2/Library/ChassisLib/ChassisLib.c  |  17 +++
 .../Library/ChassisLib/ChassisLib.c   |  17 +++
 .../MemoryInitPeiLib/MemoryInitPeiLib.c   | 142 +-
 Silicon/NXP/set_firmware_ver.sh   |  36 +
 10 files changed, 241 insertions(+), 2 deletions(-)
 create mode 100755 Silicon/NXP/set_firmware_ver.sh

-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 5/5] Platform/NXP/LS1046aFrwyPkg: Add VarStore

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- Added Reviewed-by: Leif Lindholm 

V2:
- No change

 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf |  1 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc   | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 8da5b57cb49e..24af547729c7 100644
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -48,6 +48,7 @@ [FD.LS1046AFRWY_EFI]
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc 
b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
new file mode 100644
index ..727705feaea1
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1046aFrwyNv_EFI]
+BaseAddress   = 0x4050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LS1046AFRWY NVRAM Area
+# LS1046AFRWY NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # W

[edk2-devel] [PATCH edk2-platforms v3 4/5] Platform/NXP: Add LS1046AFRWY Platform

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.

Co-authored-by: Pramod Kumar 
Signed-off-by: Pankaj Bansal 
---

Notes:
V3:
- Squashed previous commit to this commit

V2:
- No change

 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec 
|  23 +++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc 
|  46 ++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
| 168 
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
|  42 +
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 147 +
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
|  75 +
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
|  45 ++
 7 files changed, 546 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
new file mode 100644
index ..a693d8262444
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
@@ -0,0 +1,23 @@
+#  LS1046aFrwyPkg.dec
+#  LS1046a board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LS1046aFrwyPkg
+  PACKAGE_GUID   = 3547d88c-62c2-4fb2-a11b-80245f80928f
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
new file mode 100644
index ..3f29dadd5d1d
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -0,0 +1,46 @@
+#  LS1046aFrwyPkg.dsc
+#
+#  LS1046AFRWY Board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LS1046aFrwyPkg
+  PLATFORM_GUID  = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
+  OUTPUT_DIRECTORY   = Build/LS1046aFrwyPkg
+  FLASH_DEFINITION   = 
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
new file mode 100644
index ..8da5b57cb49e
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -0,0 +1,168 @@
+#  LS1046aFrwyPkg.fdf
+#
+#  FLASH layout file for LS1046a board.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be use

[edk2-devel] [PATCH edk2-platforms v3 3/5] Silicon/NXP: Add LS1046A Soc package

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.

Co-authored-by: Vabhav Sharma 
Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- Removed Co-authored-by: Pankaj Bansal 
- Added Reviewed-by: Leif Lindholm 

V2:
- No change

 Silicon/NXP/LS1046A/LS1046A.dec   |  13 +++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  42 +++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +
 Silicon/NXP/LS1046A/Include/Soc.h |  63 +++
 Silicon/NXP/LS1046A/Include/SocSerDes.h   |  33 ++
 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c   | 119 
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 +
 7 files changed, 375 insertions(+)

diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index ..bf4863c6d89e
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001A
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc 
b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index ..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+#  LS1046A.dsc
+#  LS1046A Soc package.
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x0141
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0142
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index ..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = ddd5f950-8816-4d38-8f98-f42b07333f78
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1046A/LS1046A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h 
b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index ..84f433d5cb94
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,63 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LS1046A_DRAM0_SIZE   (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS   (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE   (SIZE_32GB - SIZE_2GB)  // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LS1046A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS   (BASE_1GB)
+#define LS1046A_QSPI0_SIZE   (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
26 27 28 29 30 31

[edk2-devel] [PATCH edk2-platforms v3 0/5] Add LS1046AFRWY Platform

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.

The LS1046A SOC is based on Layerscape Chassis2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

V2 can be referred here:
https://edk2.groups.io/g/devel/message/62064

Changes in V2 w.r.t V1:
- No functional changes
- Removed Co-authored-by: Pankaj Bansal 
  from "PATCH 3/6 Silicon/NXP: Add LS1046A Soc package" and
  "PATCH 5/6 Platform/NXP: Add LS1046AFRWY Platform"
- Squashed "PATCH 4/6 Platform/NXP/LS1046AFRWY: Add ArmPlatformLib"
  in "PATCH 5/6 Platform/NXP: Add LS1046AFRWY Platform"

Pankaj Bansal (5):
  Silicon/NXP: Add comments explaining RCW bits' parsing
  Silicon/NXP/LS1043A: Fix the RCW bits' parsing
  Silicon/NXP: Add LS1046A Soc package
  Platform/NXP: Add LS1046AFRWY Platform
  Platform/NXP/LS1046aFrwyPkg: Add VarStore

 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec |  23 +++
 Silicon/NXP/LS1046A/LS1046A.dec   |  13 ++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  42 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc |  46 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 169 ++
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +++
 Silicon/NXP/LS1043A/Include/Soc.h |  29 ++-
 Silicon/NXP/LS1046A/Include/Soc.h |  63 +++
 Silicon/NXP/LS1046A/Include/SocSerDes.h   |  33 
 Silicon/NXP/LX2160A/Include/Soc.h |  28 ++-
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 +++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  75 
 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c   | 119 
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 
 .../AArch64/ArmPlatformHelper.S   |  45 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc  |  91 ++
 17 files changed, 1068 insertions(+), 2 deletions(-)
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Include/Soc.h
 create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc

-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 2/5] Silicon/NXP/LS1043A: Fix the RCW bits' parsing

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.

However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.

Currently, we are parsing the RCW bits in LE bit format i.e. LSBit 0.
Therefore, Fix the RCW bits' parsing as per MSBit 0.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- Added Reviewed-by: Leif Lindholm 

V2:
- Changed commit header and description.
- Moved changes in comments to previous commit

 Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h 
b/Silicon/NXP/LS1043A/Include/Soc.h
index c694576ed18d..40619536c6fe 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -78,7 +78,7 @@ Bit(s) | Field Name  | Description  | 
Notes/comments
 
   which is why the RCW bits in RCWSR registers are parsed this way
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
 
 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 1/5] Silicon/NXP: Add comments explaining RCW bits' parsing

2020-07-07 Thread Pankaj Bansal

From: Pankaj Bansal 

RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.

Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- Added Reviewed-by: Leif Lindholm 

V2:
- new commit

 Silicon/NXP/LS1043A/Include/Soc.h | 27 +++
 Silicon/NXP/LX2160A/Include/Soc.h | 28 +++-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h 
b/Silicon/NXP/LS1043A/Include/Soc.h
index 21b0dafffe91..c694576ed18d 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -50,6 +50,33 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
26 27 28 29 30 31
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description  | Notes/comments
+--
+ 2-6   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the 
platform
+   | |  | clock:SYSCLK ratio.
+   | |  | 0_0011 3:1
+   | |  | 0_0100 4:1
+   | |  | 0_1101 13:1
+   | |  | 0_ 15:1
+   | |  | 1_ 16:1
+
+  which is why the RCW bits in RCWSR registers are parsed this way
 **/
 #define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
 
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h 
b/Silicon/NXP/LX2160A/Include/Soc.h
index d62b8adcdbe7..e8198addc966 100644
--- a/Silicon/NXP/LX2160A/Include/Soc.h
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -36,8 +36,34 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are same as bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description  | Notes/comments
+--
+ 6-2   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the 
platform
+   | |  | clock:SYSCLK ratio.
+   | |  | 0_0100 4:1
+   | |  | 0_0110 6:1
+   | |  | 0_1000 8:1
+   | |  | 0_1101 13:1
+   | |  | 0_ 15:1
+
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 6-2
 
 typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 1/6] Silicon/NXP: Add comments explaining RCW bits' parsing

2020-07-06 Thread Pankaj Bansal

From: Pankaj Bansal 

RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.

Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1043A/Include/Soc.h | 27 +++
 Silicon/NXP/LX2160A/Include/Soc.h | 28 +++-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h 
b/Silicon/NXP/LS1043A/Include/Soc.h
index 21b0dafffe91..c694576ed18d 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -50,6 +50,33 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
26 27 28 29 30 31
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description  | Notes/comments
+--
+ 2-6   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the 
platform
+   | |  | clock:SYSCLK ratio.
+   | |  | 0_0011 3:1
+   | |  | 0_0100 4:1
+   | |  | 0_1101 13:1
+   | |  | 0_ 15:1
+   | |  | 1_ 16:1
+
+  which is why the RCW bits in RCWSR registers are parsed this way
 **/
 #define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
 
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h 
b/Silicon/NXP/LX2160A/Include/Soc.h
index d62b8adcdbe7..e8198addc966 100644
--- a/Silicon/NXP/LX2160A/Include/Soc.h
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -36,8 +36,34 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are same as bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description  | Notes/comments
+--
+ 6-2   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the 
platform
+   | |  | clock:SYSCLK ratio.
+   | |  | 0_0100 4:1
+   | |  | 0_0110 6:1
+   | |  | 0_1000 8:1
+   | |  | 0_1101 13:1
+   | |  | 0_ 15:1
+
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 6-2
 
 typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 5/6] Platform/NXP: Add LS1046AFRWY Platform

2020-07-06 Thread Pankaj Bansal

From: Pankaj Bansal 

LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.

Co-authored-by: Pramod Kumar 
Co-authored-by: Pankaj Bansal 
Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec |  23 
+++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc |  46 
++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 168 

 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  |   4 +
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c|  53 
+-
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c |  49 
+-
 6 files changed, 341 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
new file mode 100644
index ..a693d8262444
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
@@ -0,0 +1,23 @@
+#  LS1046aFrwyPkg.dec
+#  LS1046a board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LS1046aFrwyPkg
+  PACKAGE_GUID   = 3547d88c-62c2-4fb2-a11b-80245f80928f
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
new file mode 100644
index ..3f29dadd5d1d
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -0,0 +1,46 @@
+#  LS1046aFrwyPkg.dsc
+#
+#  LS1046AFRWY Board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LS1046aFrwyPkg
+  PLATFORM_GUID  = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
+  OUTPUT_DIRECTORY   = Build/LS1046aFrwyPkg
+  FLASH_DEFINITION   = 
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
new file mode 100644
index ..8da5b57cb49e
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -0,0 +1,168 @@
+#  LS1046aFrwyPkg.fdf
+#
+#  FLASH layout file for LS1046a board.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+
+
+[FD.LS1046AFRWY_EFI]
+BaseAddress   = 0x8200|gArmTokenSpaceGuid.PcdFdBaseAddress  #The base 
address of the FLASH Device.
+Size  =

[edk2-devel] [PATCH edk2-platforms v2 4/6] Platform/NXP/LS1046AFRWY: Add ArmPlatformLib

2020-07-06 Thread Pankaj Bansal

From: Pankaj Bansal 

Add ArmPlatformLib for LS1046AFRWY platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
| 38 
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 96 
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
| 28 ++
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
| 45 +
 4 files changed, 207 insertions(+)

diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index ..de93681708e3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,38 @@
+# @file
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index ..f59e7aa556a3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,96 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+#include 
+
+ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or 
ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN MpId
+  )
+{
+  //TODO: Implement me
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable
+  )
+{
+  if (ArmIsMpCore()) {
+*CoreCount= sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+*ArmCoreTable = mLS1046aMpCoreInfoTable;
+return EFI_SUCCESS;
+  } else {
+return EFI_UNSUPPORTED;
+  }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR  gPlatformPpiTable[] = {
+  {
+EFI_PEI_PPI_DESCRIPTOR_PPI,
+,
+
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  if (ArmIsMpCore()) {
+*PpiListSize = sizeof(gPlatformPpiTable);
+*PpiList = gPlatformPpiTable;
+  } else {
+*PpiListSize = 0;
+*PpiList = NULL;
+  }
+}
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index ..24d949369b98
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,28 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the 
MMU on your platform.
+
+  @param[out]   VirtualMemoryMapArray of ARM_MEMORY_REGION_DESCRIPTOR 
describing a Physical-to-
+Virtual Memory mapping. This array must be 
ended by a zero-filled
+entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ASSERT(0);
+}
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S

[edk2-devel] [PATCH edk2-platforms v2 2/6] Silicon/NXP/LS1043A: Fix the RCW bits' parsing

2020-07-06 Thread Pankaj Bansal

From: Pankaj Bansal 

For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.

However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.

Currently, we are parsing the RCW bits in LE bit format i.e. LSBit 0.
Therefore, Fix the RCW bits' parsing as per MSBit 0.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h 
b/Silicon/NXP/LS1043A/Include/Soc.h
index c694576ed18d..40619536c6fe 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -78,7 +78,7 @@ Bit(s) | Field Name  | Description  | 
Notes/comments
 
   which is why the RCW bits in RCWSR registers are parsed this way
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
 
 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 3/6] Silicon/NXP: Add LS1046A Soc package

2020-07-06 Thread Pankaj Bansal

From: Pankaj Bansal 

LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.

Co-authored-by: Vabhav Sharma 
Co-authored-by: Pankaj Bansal 
Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1046A/LS1046A.dec   |  13 +++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  42 +++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +
 Silicon/NXP/LS1046A/Include/Soc.h |  63 +++
 Silicon/NXP/LS1046A/Include/SocSerDes.h   |  33 ++
 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c   | 119 
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 +
 7 files changed, 375 insertions(+)

diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index ..bf4863c6d89e
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001A
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc 
b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index ..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+#  LS1046A.dsc
+#  LS1046A Soc package.
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x0141
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0142
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index ..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = ddd5f950-8816-4d38-8f98-f42b07333f78
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1046A/LS1046A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h 
b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index ..84f433d5cb94
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,63 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LS1046A_DRAM0_SIZE   (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS   (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE   (SIZE_32GB - SIZE_2GB)  // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LS1046A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS   (BASE_1GB)
+#define LS1046A_QSPI0_SIZE   (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
26 27 28 29 30 31
+
+LE   | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 
8 7 6 5 4 3

[edk2-devel] [PATCH edk2-platforms v2 6/6] Platform/NXP/LS1046aFrwyPkg: Add VarStore

2020-07-06 Thread Pankaj Bansal

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf |  1 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc   | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 8da5b57cb49e..24af547729c7 100644
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -48,6 +48,7 @@ [FD.LS1046AFRWY_EFI]
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc 
b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
new file mode 100644
index ..727705feaea1
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1046aFrwyNv_EFI]
+BaseAddress   = 0x4050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LS1046AFRWY NVRAM Area
+# LS1046AFRWY NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(F

[edk2-devel] [PATCH edk2-platforms v2 0/6] Add LS1046AFRWY Platform

2020-07-06 Thread Pankaj Bansal

From: Pankaj Bansal 

The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.

The LS1046A SOC is based on Layerscape Chassis2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

V1 can be referred here:
https://edk2.groups.io/g/devel/message/60577

Changes in V2 w.r.t V1:
- No functional changes
- Explaination Added for PATCH 2/6 Silicon/NXP/LS1043A: Fix the RCW bits' 
parsing
- Refer PATCH 1/6 Silicon/NXP: Add comments explaining RCW bits' parsing
  for expalaination for PATCH 2/6 Silicon/NXP/LS1043A: Fix the RCW bits' parsing

Pankaj Bansal (6):
  Silicon/NXP: Add comments explaining RCW bits' parsing
  Silicon/NXP/LS1043A: Fix the RCW bits' parsing
  Silicon/NXP: Add LS1046A Soc package
  Platform/NXP/LS1046AFRWY: Add ArmPlatformLib
  Platform/NXP: Add LS1046AFRWY Platform
  Platform/NXP/LS1046aFrwyPkg: Add VarStore

 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec |  23 +++
 Silicon/NXP/LS1046A/LS1046A.dec   |  13 ++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  42 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc |  46 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 169 ++
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +++
 Silicon/NXP/LS1043A/Include/Soc.h |  29 ++-
 Silicon/NXP/LS1046A/Include/Soc.h |  63 +++
 Silicon/NXP/LS1046A/Include/SocSerDes.h   |  33 
 Silicon/NXP/LX2160A/Include/Soc.h |  28 ++-
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 +++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  75 
 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c   | 119 
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 
 .../AArch64/ArmPlatformHelper.S   |  45 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc  |  91 ++
 17 files changed, 1068 insertions(+), 2 deletions(-)
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Include/Soc.h
 create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc

-- 
2.17.1


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[edk2-devel] [PATCH edk2-test 1/1] SctPkg: fix page alignment calculations

2020-07-04 Thread Pankaj Bansal

From: Pankaj Bansal 

The BBTestAllocatePagesInterfaceTest tries to allocate pages for
different memory types.
While doing so, it tries to fix up the Start and PageNum for 64K
Page size. There are multiple issues with this:

1. 64K alignment is being done regardless of Processor type and Memory
   type. while this is correct for ARM64 Processor, it might not be so
   for other Processor types. Also 64K alignment for ARM64 Processor
   is needed for some Memory types not all.
2. The Start is being incremented by 64K, even if Start is already 64K
   aligned.
3. PageNum is being decreased by 16 pages indiscriminately, which might
   not be needed in all cases.

fix all these issues by correctly doing the alignment in all needed
cases.

Cc: Paul Yang 
Cc: Samer El-Haj-Mahmoud 
Cc: Gaurav Jain 
Signed-off-by: Pankaj Bansal 
---
 .../MemoryAllocationServicesBBTestFunction.c  | 148 +-
 1 file changed, 106 insertions(+), 42 deletions(-)

diff --git 
a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
 
b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
index d18fe1fc2b94..9ed9e6e0de74 100644
--- 
a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
+++ 
b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
@@ -354,6 +354,7 @@ BBTestAllocatePagesInterfaceTest (
   EFI_TPL  OldTpl;
   EFI_MEMORY_DESCRIPTORDescriptor;
   UINTNPageNum;
+  UINTNAlignment;
 
   //
   // Get the Standard Library Interface
@@ -700,14 +701,23 @@ BBTestAllocatePagesInterfaceTest (
 PageNum = (UINTN)Descriptor.NumberOfPages;
 Start   = Descriptor.PhysicalStart;
 
-//
-// Some memory types need more alignment than 4K, so
-//
-if (PageNum <= 0x10) {
+Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+if  (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory   ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS   ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+  Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+}
+
+Start   = (Start + Alignment - 1) & ~(Alignment - 1);
+PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
   break;
 }
-Start   = (Start + 0x1) & 0x;
-PageNum = PageNum - EFI_SIZE_TO_PAGES(0x1);
 
 Memory  = Start;
 
@@ -830,14 +840,23 @@ BBTestAllocatePagesInterfaceTest (
 PageNum = (UINTN)Descriptor.NumberOfPages;
 Start   = Descriptor.PhysicalStart;
 
-//
-// Some memory types need more alignment than 4K, so
-//
-if (PageNum <= 0x10) {
+Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+if  (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory   ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS   ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+  Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+}
+
+Start   = (Start + Alignment - 1) & ~(Alignment - 1);
+PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
   break;
 }
-Start   = (Start + 0x1) & 0x;
-PageNum = PageNum - EFI_SIZE_TO_PAGES(0x1);
 
 Memory  = Start;
 
@@ -953,14 +972,23 @@ BBTestAllocatePagesInterfaceTest (
 PageNum = (UINTN)Descriptor.NumberOfPages;
 Start   = Descriptor.PhysicalStart;
 
-//
-// Some memory types need more alignment than 4K, so
-//
-if (PageNum <= 0x10) {
+Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+if  (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory   ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS   ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+  Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+}
+
+Start   = (Start + Alignment - 1) & ~(Alignment - 1);
+PageNum -= EFI_SIZE

Re: [edk2-devel] [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

2020-06-18 Thread Pankaj Bansal

Hi Leif,

Sorry for late reply.
Actually I had asked the design team to check this point.
I am waiting for their reply.
I will add comments in code based on their reply and send new version.

Regards,
Pankaj Bansal

> -Original Message-
> From: Leif Lindholm 
> Sent: Friday, June 12, 2020 8:41 PM
> To: Pankaj Bansal (OSS) 
> Cc: Meenakshi Aggarwal ; Michael D Kinney
> ; devel@edk2.groups.io; Varun Sethi
> ; Samer El-Haj-Mahmoud  mahm...@arm.com>; Augustine Philips ; Ard
> Biesheuvel ; Arokia Samy
> ; kuldip dwivedi
> 
> Subject: Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform
> PLL calculation
> 
> Hi Pankaj,
> 
> Apologies for delay in responding, this message got lost from my inbox.
> On a sidenote, I think this has something to do with the email
> moderation. Could you possibly subscribe the @oss.nxp.com address to
> the list? You can set it not to deliver email, under
> https://edk2.groups.io/g/devel/editsub, but I can't whitelist
> addresses that are not subscribed.
> 
> On Mon, Jun 08, 2020 at 19:56:35 +, Pankaj Bansal (OSS) wrote:
> > > > > OK, now I'm confused.
> > > > > DCFG is read using the DcfgRead32 function, which is supposed to
> > > > > handle the endianness issue.
> > > > >
> > > > > Ls1043a builds with
> > > > >   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> > > > > which means GetMmioOperations() returns the byte-swapping versions.
> > > > >
> > > > > Please clarify.
> > > >
> > > > OK. so this might be little confusing, so bear with me.
> > > > The reset configuration word (RCW) is 512 bits (1024 bits in LS2088
> > > > / LS2160) long and contains all necessary configuration information
> > > > for the chip. RCW data is read from external memory (Nor flash or
> > > > SD/eMMC card or I2c eeprom) and written to the RCW status registers
> > > > (RCWSR) contained in the Device Configuration and Pin Control module
> > > > (DCSR), after which the device is configured as specified in the
> > > > RCW.
> > > >
> > > > The PreBoot Loader (PBL) fetches RCW data from the source memory
> > > > device and writes it to the RCW status registers.
> > > > Now the PBL fetches the data from flash in little endian format and
> > > > writes it to the DCSR registers in little endian format always.
> > > > This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).
> > >
> > > This PBL is a ROM executing before the EDK2 code?
> >
> > Yes
> >
> > >
> > > > Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we
> > > > read the RCWSR registers in big endian fashion.
> > > > This causes the bit position to be reversed.
> > >
> > > I'm still not following.
> > >
> > > We've set up this elaborate Rube Goldberg machine to be able to *not*
> > > have to carry separate header files for devices with individual
> > > components with registers that may be big- or little-endian depending
> > > on which SoC/version they are in.
> > >
> > > And now we have an implementation that states that its DcfgRead
> > > operations need to happan as big-endian. And the *only* time the Dcfg
> > > registers are accessed, we immediately need to change the header file
> > > to treat it as little-endian?
> >
> > The RCW Status registers are a special case and a subset of DCFG
> > address space. The whole DCFG address space is big endian itself,
> > and should be read as such.
> 
> So the RCW status registers are in effect just temporary storage for
> data, as opposed to having any effect on the hw? Whereas other parts
> of DCFG *do* affect (and reflect) hw, and are big-endian?
> 
> If so, ok, I understand. And I think your platform designers owe me
> (and you, if so inclined) a beer.
> 
> > if it makes more sense, then I can swap the RCW status registers
> > after being read from DCFG space.
> > And I can put the explanation I wrote above in the code where I swap
> > RCW SR registers ?
> 
> Yes, I think manually swapping the words make more sense. This is a
> *weird* thing - it helps to call it out explicitly rather than try to
> make it look normal.
> 
> Please do that, and drop the .h change, and I'm happy with that.
> 
> > > What is the situation where Dcfg accesses *need* to be big-endian?
> >
> > Apart from RCWSR registers the DCFG space contains following
> > registers as well, which we need to access in boot firmware:
> >
> > - SVR (SOC Version Register)
> > - to retrieve Core and Cluster Information (which I plan to send shortly)
> > - To set the ICID of DMA connected devices like USB, SATA, SD/EMMC
> > - to retrieve the clock frequency of serial flash controller (qspi/flexspi)
> 
> Understood - thanks!
> 
> /
> Leif

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Re: [edk2-devel] [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

2020-06-08 Thread Pankaj Bansal




> -Original Message-
> From: Leif Lindholm 
> Sent: Monday, June 8, 2020 7:52 PM
> To: Pankaj Bansal (OSS) 
> Cc: Meenakshi Aggarwal ; Michael D Kinney
> ; devel@edk2.groups.io; Varun Sethi
> ; Samer El-Haj-Mahmoud  mahm...@arm.com>; Augustine Philips ; Ard
> Biesheuvel ; Arokia Samy
> ; kuldip dwivedi
> 
> Subject: Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform
> PLL calculation
> 
> On Fri, Jun 05, 2020 at 17:18:54 +, Pankaj Bansal (OSS) wrote:
> > > On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> > > > From: Pankaj Bansal 
> > > >
> > > > for LS1043A SOC the DCFG registers are read in big endian format.
> > > > However current Platofmr PLL calculation is being done assuing the
> > >
> > >   Platform?  assuming
> >
> > yes. typo mistake.
> >
> > >
> > > > little endian format.
> > > >
> > > > Fix the Platform PLL calculation
> > >
> > > OK, now I'm confused.
> > > DCFG is read using the DcfgRead32 function, which is supposed to
> > > handle the endianness issue.
> > >
> > > Ls1043a builds with
> > >   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> > > which means GetMmioOperations() returns the byte-swapping versions.
> > >
> > > Please clarify.
> >
> > OK. so this might be little confusing, so bear with me.
> > The reset configuration word (RCW) is 512 bits (1024 bits in LS2088
> > / LS2160) long and contains all necessary configuration information
> > for the chip. RCW data is read from external memory (Nor flash or
> > SD/eMMC card or I2c eeprom) and written to the RCW status registers
> > (RCWSR) contained in the Device Configuration and Pin Control module
> > (DCSR), after which the device is configured as specified in the
> > RCW.
> >
> > The PreBoot Loader (PBL) fetches RCW data from the source memory
> > device and writes it to the RCW status registers.
> > Now the PBL fetches the data from flash in little endian format and
> > writes it to the DCSR registers in little endian format always.
> > This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).
> 
> This PBL is a ROM executing before the EDK2 code?

Yes

> 
> > Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we
> > read the RCWSR registers in big endian fashion.
> > This causes the bit position to be reversed.
> 
> I'm still not following.
> 
> We've set up this elaborate Rube Goldberg machine to be able to *not*
> have to carry separate header files for devices with individual
> components with registers that may be big- or little-endian depending
> on which SoC/version they are in.
> 
> And now we have an implementation that states that its DcfgRead
> operations need to happan as big-endian. And the *only* time the Dcfg
> registers are accessed, we immediately need to change the header file
> to treat it as little-endian?

The RCW Status registers are a special case and a subset of DCFG address space.
The whole DCFG address space is big endian itself, and should be read as such.

if it makes more sense, then I can swap the RCW status registers after being 
read from DCFG space.
And I can put the explanation I wrote above in the code where I swap RCW SR 
registers ?

> 
> What is the situation where Dcfg accesses *need* to be big-endian?

Apart from RCWSR registers the DCFG space contains following registers as well, 
which we need to access in boot firmware:

- SVR (SOC Version Register)
- to retrieve Core and Cluster Information (which I plan to send shortly)
- To set the ICID of DMA connected devices like USB, SATA, SD/EMMC
- to retrieve the clock frequency of serial flash controller (qspi/flexspi)

> 
> Regards,
> 
> Leif
> 
> > In SOCs where DCSR space is little endian (LS2088 / LX2160), we read
> > the RCWSR registers in little endian fashion.
> > That is why the bit position is correct.
> >
> > >
> > > /
> > > Leif
> > >
> > > > Signed-off-by: Pankaj Bansal 
> > > > ---
> > > >  Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> > > b/Silicon/NXP/LS1043A/Include/Soc.h
> > > > index 97a77d3f5da6..afcd9da34cda 100644
> > > > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > > > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > > > @@ -48,7 +48,7 @@
> > > >  /**
> > > >Reset Control Word (RCW) Bits
> > > >  **/
> > > > -#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
> > > > +#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
> > > >
> > > >  typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG
> > > LS1043A_DEVICE_CONFIG;
> > > >
> > > > --
> > > > 2.17.1
> > > >

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Re: [edk2-devel] [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

2020-06-05 Thread Pankaj Bansal

> On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal 
> >
> > for LS1043A SOC the DCFG registers are read in big endian format.
> > However current Platofmr PLL calculation is being done assuing the
> 
>   Platform?  assuming

yes. typo mistake.

> 
> > little endian format.
> >
> > Fix the Platform PLL calculation
> 
> OK, now I'm confused.
> DCFG is read using the DcfgRead32 function, which is supposed to
> handle the endianness issue.
> 
> Ls1043a builds with
>   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> which means GetMmioOperations() returns the byte-swapping versions.
> 
> Please clarify.

OK. so this might be little confusing, so bear with me.
The reset configuration word (RCW) is 512 bits (1024 bits in LS2088 / LS2160) 
long and contains all necessary configuration information for
the chip. RCW data is read from external memory (Nor flash or SD/eMMC card or 
I2c eeprom)  and written to the RCW status registers
(RCWSR) contained in the Device Configuration and Pin Control module (DCSR), 
after which the device is configured as specified in the RCW.

The PreBoot Loader (PBL) fetches RCW data from the source memory device and 
writes it to the RCW status registers.
Now the PBL fetches the data from flash in little endian format and writes it 
to the DCSR registers in little endian format always.
This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).

Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we read the RCWSR 
registers in big endian fashion.
This causes the bit position to be reversed.

In SOCs where DCSR space is little endian (LS2088 / LX2160), we read the RCWSR 
registers in little endian fashion.
That is why the bit position is correct.

> 
> /
> Leif
> 
> > Signed-off-by: Pankaj Bansal 
> > ---
> >  Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> b/Silicon/NXP/LS1043A/Include/Soc.h
> > index 97a77d3f5da6..afcd9da34cda 100644
> > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > @@ -48,7 +48,7 @@
> >  /**
> >Reset Control Word (RCW) Bits
> >  **/
> > -#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
> > +#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
> >
> >  typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG
> LS1043A_DEVICE_CONFIG;
> >
> > --
> > 2.17.1
> >

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Re: [edk2-devel] [PATCH edk2-InfSpecification] Drop statement on package ordering

2020-06-02 Thread Pankaj Bansal

> >>
> >> (since I've been copied)
> >>
> >> I have not been aware of the header name collision scenario (nor that
> >> the [Packages] ordering was supposed to work around such issues).
> >>
> >> I work strictly with edk2 proper, where a name collision like this can
> >> be detected, and so should be prevented. (Insert yet another argument
> >> why keeping platform code outside of edk2 is a bad idea.) In particular,
> >> a collision between MdePkg and MdeModulePkg would be super bad.
> >>
> >> Which now seems to turn out consistent with my general review point that
> >> the [Packages] section, like (almost) all other INF file sections,
> >> should be sorted lexicographically.
> >>
> >> How about replacing
> >>
> >> """
> >> Packages must be listed in the order that may be required for specifying
> >> include path statements for a compiler. For example, the
> MdePkg/MdePkg.dec_
> >> file must be listed before the `MdeModulePkg/MdeModulePkg.dec` file.
> >> """
> >>
> >> with
> >>
> >> """
> >> The order in which packages are listed may be relevant. Said order
> >> specifies in what order include path statements are generated for a
> >> compiler. Normally, header file name collisions are not expected between
> >> packages -- they are forbidden in edk2 proper --, but with a module INF
> >> consuming both edk2-native and out-of-edk2 packages, header file names
> >> may collide. For setting specific include path priorities, the packages
> >> may be listed in matching order in the INF file. Listing a package
> >> earlier will cause a compiler to consider include paths from that
> >> package earlier.
> >> """
> >
> > Nicely summed up! it is much clearer now for anyone like me who wants to
> port edk2 for his platform.
> > one more suggestion. should this be mentioned along with above explaination:
> > "whenever possible use lexicographically ascending order"
> 
> I'd love that, but it's really just a policy question that I prefer.
> 
> If we tried to elevate my preference to official edk2 spec level, it
> could run into opposition (like any other proposal -- so that would be
> just fine, per se!). I just wouldn't like to delay the more important
> clarification with a discussion around my preference.
> 
> So minimally, that would take a two-part patch series, and even so the
> second patch would likely have to be marked RFC. I think we can simply
> postpone the official speccing of the lexicographical sorting idea
> (indefinitely, even).

The point that I want to make is that these document should guide new
developers, as to how to contribute to edk2 code as well as explaining how
edk2 code has been organized.

To explain a practice historically followed in edk2 (but no longer followed),
is informercial to new developers. but it is of little help for them to 
contribute to edk2.

perhaps along the edk2 c guidelines, there should be a section in each 
specification
file, titled Guidelines ?

> 
> Thanks
> Laszlo


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Re: [edk2-devel] [PATCH edk2-InfSpecification] Drop statement on package ordering

2020-06-02 Thread Pankaj Bansal



> -Original Message-
> From: Laszlo Ersek 
> Sent: Tuesday, June 2, 2020 7:00 PM
> To: Leif Lindholm ; devel@edk2.groups.io;
> michael.d.kin...@intel.com
> Cc: Andrew Fish ; Pankaj Bansal (OSS)
> 
> Subject: Re: [edk2-devel] [PATCH edk2-InfSpecification] Drop statement on
> package ordering
> 
> On 06/01/20 00:43, Leif Lindholm wrote:
> > Hi Mike,
> >
> > Ok, I'm happy to hear that.
> >
> > I agree that the overriding behaviour is useful, and it would be good
> > to document it. The problem is that the current wording does not say
> > that (in a way that is useful to anyone who does not already know what
> > it means). And the MdePkg/MdeModulePkg example sounds positively
> > horrific when interpreted in this light.
> >
> > Clearly, my proposed modification is not the right thing to do here.
> >
> > The problem with the document implying that the order should reflect
> > some sort of hierarchy *apart from when explicitly overriding* is that
> > this is asking a human to do the thing that humans are bad at and
> > computers are good at. It can't scale where humans are reviewing ports
> > that they understand less well than the people contributing them.
> >
> > I think we should find a wording that explains the behaviour instead
> > of explaining some potential derivative of the behaviour, as well as
> > providing a realistic example instead of the MdePkg/MdeModulePkg
> > statament.
> >
> > My suggestion is to keep it simple: say something like "where there is
> > a need to override an include file provided by one package with one
> > provided by another package, know that the compiler invocation will
> > list the include directories in the same order as the .dec files are
> > listed in the .inf".
> 
> (since I've been copied)
> 
> I have not been aware of the header name collision scenario (nor that
> the [Packages] ordering was supposed to work around such issues).
> 
> I work strictly with edk2 proper, where a name collision like this can
> be detected, and so should be prevented. (Insert yet another argument
> why keeping platform code outside of edk2 is a bad idea.) In particular,
> a collision between MdePkg and MdeModulePkg would be super bad.
> 
> Which now seems to turn out consistent with my general review point that
> the [Packages] section, like (almost) all other INF file sections,
> should be sorted lexicographically.
> 
> How about replacing
> 
> """
> Packages must be listed in the order that may be required for specifying
> include path statements for a compiler. For example, the MdePkg/MdePkg.dec_
> file must be listed before the `MdeModulePkg/MdeModulePkg.dec` file.
> """
> 
> with
> 
> """
> The order in which packages are listed may be relevant. Said order
> specifies in what order include path statements are generated for a
> compiler. Normally, header file name collisions are not expected between
> packages -- they are forbidden in edk2 proper --, but with a module INF
> consuming both edk2-native and out-of-edk2 packages, header file names
> may collide. For setting specific include path priorities, the packages
> may be listed in matching order in the INF file. Listing a package
> earlier will cause a compiler to consider include paths from that
> package earlier.
> """

Nicely summed up! it is much clearer now for anyone like me who wants to port 
edk2 for his platform.
one more suggestion. should this be mentioned along with above explaination:
"whenever possible use lexicographically ascending order"

> 
> Thanks
> Laszlo


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[edk2-devel] [PATCH edk2-platforms 4/5] Platform/NXP: Add LS1046AFRWY Platform

2020-06-02 Thread Pankaj Bansal

From: Pankaj Bansal 

LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.

Co-authored-by: Pramod Kumar 
Co-authored-by: Pankaj Bansal 
Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec |  23 
+++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc |  46 
++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 168 

 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  |   4 +
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c|  53 
+-
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c |  50 
+-
 6 files changed, 342 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
new file mode 100644
index ..a693d8262444
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
@@ -0,0 +1,23 @@
+#  LS1046aFrwyPkg.dec
+#  LS1046a board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LS1046aFrwyPkg
+  PACKAGE_GUID   = 3547d88c-62c2-4fb2-a11b-80245f80928f
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
new file mode 100644
index ..2e7d7da6db3a
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -0,0 +1,46 @@
+#  LS1046aFrwyPkg.dsc
+#
+#  LS1046AFRWY Board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LS1046aFrwyPkg
+  PLATFORM_GUID  = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
+  OUTPUT_DIRECTORY   = Build/LS1046aFrwyPkg
+  FLASH_DEFINITION   = 
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+ ##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
new file mode 100644
index ..8da5b57cb49e
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -0,0 +1,168 @@
+#  LS1046aFrwyPkg.fdf
+#
+#  FLASH layout file for LS1046a board.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+
+
+[FD.LS1046AFRWY_EFI]
+BaseAddress   = 0x8200|gArmTokenSpaceGuid.PcdFdBaseAddress  #The base 
address of the FLASH Device.
+Size  =

[edk2-devel] [PATCH edk2-platforms 3/5] Platform/NXP/LS1046AFRWY: Add ArmPlatformLib

2020-06-02 Thread Pankaj Bansal

From: Pankaj Bansal 

Add ArmPlatformLib for LS1046AFRWY platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
| 38 
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 96 
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
| 28 ++
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
| 45 +
 4 files changed, 207 insertions(+)

diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index ..e6b6fb4d7e88
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,38 @@
+#/* @file
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index ..f59e7aa556a3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,96 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+#include 
+
+ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or 
ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN MpId
+  )
+{
+  //TODO: Implement me
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable
+  )
+{
+  if (ArmIsMpCore()) {
+*CoreCount= sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+*ArmCoreTable = mLS1046aMpCoreInfoTable;
+return EFI_SUCCESS;
+  } else {
+return EFI_UNSUPPORTED;
+  }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR  gPlatformPpiTable[] = {
+  {
+EFI_PEI_PPI_DESCRIPTOR_PPI,
+,
+
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  if (ArmIsMpCore()) {
+*PpiListSize = sizeof(gPlatformPpiTable);
+*PpiList = gPlatformPpiTable;
+  } else {
+*PpiListSize = 0;
+*PpiList = NULL;
+  }
+}
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index ..24d949369b98
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,28 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the 
MMU on your platform.
+
+  @param[out]   VirtualMemoryMapArray of ARM_MEMORY_REGION_DESCRIPTOR 
describing a Physical-to-
+Virtual Memory mapping. This array must be 
ended by a zero-filled
+entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ASSERT(0);
+}
diff --git 
a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 
b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64

[edk2-devel] [PATCH edk2-platforms 2/5] Silicon/NXP: Add LS1046A Soc package

2020-06-02 Thread Pankaj Bansal

From: Pankaj Bansal 

LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.

Co-authored-by: Vabhav Sharma 
Co-authored-by: Pankaj Bansal 
Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1046A/LS1046A.dec   | 13 
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   | 42 +++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 27 +++
 Silicon/NXP/LS1046A/Include/Soc.h | 36 +
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   | 78 
 5 files changed, 196 insertions(+)

diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index ..deb473b549c2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001B
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc 
b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index ..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+#  LS1046A.dsc
+#  LS1046A Soc package.
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x0141
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0142
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index ..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = ddd5f950-8816-4d38-8f98-f42b07333f78
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1046A/LS1046A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h 
b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index ..6ff8db927865
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,36 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LS1046A_DRAM0_SIZE   (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS   (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE   (SIZE_32GB - SIZE_2GB) // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LS1046A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS   (BASE_1GB)
+#define LS1046A_QSPI0_SIZE   (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+
+#endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c 
b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
new file mode 100644
index ..3b15aee6ecae
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -0,0 +1,78 @@
+/** @Soc.c
+  SoC specific Library containg functions to initialize various SoC components
+
+  Copyright 2017-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Return the input clock frequency to an IP Module.
+  Thi

[edk2-devel] [PATCH edk2-platforms 5/5] Platform/NXP/LS1046aFrwyPkg: Add VarStore

2020-06-02 Thread Pankaj Bansal

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf |  1 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc   | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf 
b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 8da5b57cb49e..24af547729c7 100644
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -48,6 +48,7 @@ 
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc 
b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
new file mode 100644
index ..727705feaea1
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1046aFrwyNv_EFI]
+BaseAddress   = 0x4050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LS1046AFRWY NVRAM Area
+# LS1046AFRWY NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x0

[edk2-devel] [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

2020-06-02 Thread Pankaj Bansal

From: Pankaj Bansal 

for LS1043A SOC the DCFG registers are read in big endian format.
However current Platofmr PLL calculation is being done assuing the
little endian format.

Fix the Platform PLL calculation

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h 
b/Silicon/NXP/LS1043A/Include/Soc.h
index 97a77d3f5da6..afcd9da34cda 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -48,7 +48,7 @@
 /**
   Reset Control Word (RCW) Bits
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
 
 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 0/5] Add LS1046AFRWY Platform

2020-06-02 Thread Pankaj Bansal

From: Pankaj Bansal 

The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.

The LS1046A SOC is based on Layerscape Chassis2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

Pankaj Bansal (5):
  Silicon/NXP/LS1043A: Fix the Platform PLL calculation
  Silicon/NXP: Add LS1046A Soc package
  Platform/NXP/LS1046AFRWY: Add ArmPlatformLib
  Platform/NXP: Add LS1046AFRWY Platform
  Platform/NXP/LS1046aFrwyPkg: Add VarStore

 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec |  23 +++
 Silicon/NXP/LS1046A/LS1046A.dec   |  13 ++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  42 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc |  46 +
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 169 ++
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +++
 Silicon/NXP/LS1043A/Include/Soc.h |   2 +-
 Silicon/NXP/LS1046A/Include/Soc.h |  36 
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 +++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  76 
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 
 .../AArch64/ArmPlatformHelper.S   |  45 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc  |  91 ++
 14 files changed, 836 insertions(+), 1 deletion(-)
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Include/Soc.h
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
 create mode 100644 
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc

-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 09/10] Platform/NXP: Add LX2160ARDB Platform

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

Signed-off-by: Pankaj Bansal 
---

Notes:
V4:
- Alphabetically sorted Packages in
  Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf

V3:
- Alphabetically sorted LibraryClasses in
  Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf

V2:
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
  part containing gPlatformGetClockPpi is put before PL011UartClockLib
  implementation.

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  |  23 +++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  |  46 
++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf  | 168 

 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  |   3 +
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c|   4 +-
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c |  54 
++-
 6 files changed, 296 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
new file mode 100644
index ..03996b07fcb9
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
@@ -0,0 +1,23 @@
+#  LX2160aRdbPkg.dec
+#  LX2160a board package.
+#
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LX2160aRdbPkg
+  PACKAGE_GUID   = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
new file mode 100644
index ..9b3e0386c13e
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
@@ -0,0 +1,46 @@
+#  LX2160aRdbPkg.dsc
+#
+#  LX2160ARDB Board package.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LX2160aRdbPkg
+  PLATFORM_GUID  = be06d8bc-05eb-44d6-b39f-191e93617ebd
+  OUTPUT_DIRECTORY   = Build/LX2160aRdbPkg
+  FLASH_DEFINITION   = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LX2160A/LX2160A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+ ##
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
new file mode 100644
index ..13ad6e73cd48
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -0,0 +1,168 @@
+#  LX2160aRdbPkg.fdf
+#
+#  FLASH layout file for LX2160a board.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a s

[edk2-devel] [PATCH edk2-platforms v4 02/10] Platform/NXP: Use Monotonic counter from MdeModulePkg

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.

Therefore, use Monotonic counter module from MdeModulePkg

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc   | 2 +-
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 54236e19531c..12e2b89fac58 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -337,7 +337,7 @@
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
   EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
 
   # FDT installation
   MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 95bbb54cc420..dd31b45b4d78 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -100,7 +100,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF 
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
   INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 03/10] Silicon/NXP/PciHostBridgeLib: Fix compilation with MDEPKG_NDEBUG flag

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

when MDEPKG_NDEBUG flag is enabled, RELEASE build fails with this error:

error: mPciHostBridgeLibAcpiAddressSpaceTypeStr defined but not used
[-Werror=unused-variable]

Fix this error by protecting mPciHostBridgeLibAcpiAddressSpaceTypeStr
with MDEPKG_NDEBUG macro.

Suggested-by: Leif Lindholm 
Signed-off-by: Pankaj Bansal 
---

Notes:
V4:
- No change

V3:
- New commit

V2:
- No change

 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c 
b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 549f4fa133fb..e5309a4f4248 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -167,11 +167,13 @@ STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH 
mEfiPciRootBridgeDevicePath[] = {
   }
 };
 
+#ifndef MDEPKG_NDEBUG
 STATIC
 GLOBAL_REMOVE_IF_UNREFERENCED
 CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
   L"Mem", L"I/O", L"Bus"
 };
+#endif
 
 #define PCI_ALLOCATION_ATTRIBUTES   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | 
\
 EFI_PCI_HOST_BRIDGE_MEM64_DECODE
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 04/10] Silicon/NXP: Use edk2 recommended compilation flags

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.

Therefore, enable these flags for NXP platforms as well

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 12e2b89fac58..ee639d552483 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -173,7 +173,12 @@
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
 
 [BuildOptions]
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+  #
+  # Disable deprecated APIs.
+  #
+  GCC:*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 06/10] Silicon/NXP: Implement PL011UartClockLib for NXP platforms

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

V2:
- No change

 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf | 24 

 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c   | 22 
++
 2 files changed, 46 insertions(+)

diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
new file mode 100644
index ..b771dba7697f
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
@@ -0,0 +1,24 @@
+#/* @file
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PL011UartClockLib
+  FILE_GUID  = af8fef24-afbb-472a-b8b7-13101a79703c
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PL011UartClockLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[Sources.common]
+  PL011UartClockLib.c
+
+[LibraryClasses]
+  ArmPlatformLib
diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
new file mode 100644
index ..3814685585eb
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
@@ -0,0 +1,22 @@
+/** @file
+*
+*  Copyright 2018, 2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+/**
+  Return clock in for PL011 Uart IP
+**/
+UINT32
+EFIAPI
+PL011UartClockGetFreq (
+  VOID
+  )
+{
+  return gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
+}
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 08/10] Silicon/NXP: Add LX2160A Soc package

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

V2:
- No change

 Silicon/NXP/LX2160A/LX2160A.dec   | 13 
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   | 50 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 27 +++
 Silicon/NXP/LX2160A/Include/Soc.h | 38 ++
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   | 80 
 5 files changed, 208 insertions(+)

diff --git a/Silicon/NXP/LX2160A/LX2160A.dec b/Silicon/NXP/LX2160A/LX2160A.dec
new file mode 100644
index ..50481c0f2ebd
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dec
@@ -0,0 +1,13 @@
+# LX2160A.dec
+#
+# Copyright 2018, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001A
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc 
b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
new file mode 100644
index ..af22b4dd973c
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
@@ -0,0 +1,50 @@
+#  LX2160A.dsc
+#  LX2160A Soc package.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
+
+  PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
+  
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  PL011UartClockLib|Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x600
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x620
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C
+
+[PcdsFixedAtBuild.common]
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x239
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|91
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+##
diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
new file mode 100644
index ..421072b88019
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/LX2160A/LX2160A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h 
b/Silicon/NXP/LX2160A/Include/Soc.h
new file mode 100644
index ..52674ee5f32c
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -0,0 +1,38 @@
+/** @file
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LX2160A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LX2160A_DRAM0_SIZE   (SIZE_2GB)
+#define LX2160A_DRAM1_PHYS_ADDRESS   (BASE_128GB + BASE_2GB)
+#define LX2160A_DRAM1_SIZE   (SIZE_128GB - SIZE_2GB) // 126 GB
+#define LX2160A_DRAM2_PHYS_ADDRESS   (BASE_256GB + BASE_128GB)
+#define LX2160A_DRAM2_SIZE   (SIZE_128GB)
+
+#define LX2160A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LX2160A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LX2160A_FSPI0_PHYS_ADDRESS   (BASE_512MB)
+#define LX2160A_FSPI0_SIZE   (SIZE_256MB)
+
+#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x)  (((x) & 0x7c)

[edk2-devel] [PATCH edk2-platforms v4 01/10] Silicon/NXP: Use Metronome implementation from MdeModulePkg

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

There are two implementations of Metronome protocol.

EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf

Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg over
EmbeddedPkg.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc   | 4 +---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 03759c7cee7c..54236e19531c 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -218,8 +218,6 @@
   
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
 
 [PcdsFixedAtBuild.common]
-  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1 # expressed in 100ns units, 
100,000 x 100 ns = 10,000,000 ns = 10 ms
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
@@ -348,7 +346,7 @@
   MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/Metronome/Metronome.inf
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 1c160e349eb9..95bbb54cc420 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -117,7 +117,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/Metronome/Metronome.inf
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
 
   #
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 07/10] Silicon/NXP: Add Chassis3V2 Package

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

V2:
- No change

 Silicon/NXP/Chassis3V2/Chassis3V2.dec| 22 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc| 10 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf | 33 +
 Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c   | 71 

 5 files changed, 162 insertions(+)

diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
new file mode 100644
index ..f7269e6bf6de
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
@@ -0,0 +1,22 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 1.27
+  PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
new file mode 100644
index ..b9f388a59f2a
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
@@ -0,0 +1,10 @@
+#  @file
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+  ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index ..75b68cc4ca2d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,33 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION= 1.27
+  BASE_NAME  = Chassis3V2Lib
+  FILE_GUID  = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ChassisLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  IoAccessLib
+  IoLib
+  PcdLib
+  SerialPortLib
+
+[Sources.common]
+  ChassisLib.c
+
+[FeaturePcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h 
b/Silicon/NXP/Chassis3V2/Include/Chassis.h
new file mode 100644
index ..0fd70132d897
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
@@ -0,0 +1,26 @@
+/** @file
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#include 
+
+#define  NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS  0x1E0
+
+/**
+  The Device Configuration Unit provides general purpose configuration and
+  status for the device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+  UINT8   Reserved0[0x100 - 0x0];
+  UINT32  RcwSr[32]; // Reset Control Word Status Register
+} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index ..30f8f945b233
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,71 @@
+/** @file
+  Chassis specific functions common to all SOCs based on a specific Chessis
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Read Dcfg register
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+  IN  UINTN Address
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->Read32 (Address);
+}
+
+/**
+  Write Dcfg register
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+  @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+  IN  UINTN Address,
+  IN  UINT32Value
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->W

[edk2-devel] [PATCH edk2-platforms v4 10/10] Platform/NXP/LX2160aRdbPkg: Add VarStore

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

V2:
- No change

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf |  1 +
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc  | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
index 13ad6e73cd48..55d998e96951 100644
--- a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -48,6 +48,7 @@ 
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc 
b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
new file mode 100644
index ..799eee87193f
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LX2160aRdbNv_EFI]
+BaseAddress   = 0x2050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LX2160ARDB NVRAM Area
+# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xF

[edk2-devel] [PATCH edk2-platforms v4 00/10] Add LX2160ARDB Platform

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

This Platform is based on Layerscape Chassis3V2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

v3 of this series can be referred here:
https://edk2.groups.io/g/devel/message/60428

Changes w.r.t v3:

05/10: Platform/NXP/LX2160ARDB: Add ArmPlatformLib

  - Alphabetically sorted Packages in
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf

09/10: Platform/NXP: Add LX2160ARDB Platform

  - Alphabetically sorted Packages in
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf

Pankaj Bansal (10):
  Silicon/NXP: Use Metronome implementation from MdeModulePkg
  Platform/NXP: Use Monotonic counter from MdeModulePkg
  Silicon/NXP/PciHostBridgeLib: Fix compilation with MDEPKG_NDEBUG flag
  Silicon/NXP: Use edk2 recommended compilation flags
  Platform/NXP/LX2160ARDB: Add ArmPlatformLib
  Silicon/NXP: Implement PL011UartClockLib for NXP platforms
  Silicon/NXP: Add Chassis3V2 Package
  Silicon/NXP: Add LX2160A Soc package
  Platform/NXP: Add LX2160ARDB Platform
  Platform/NXP/LX2160aRdbPkg: Add VarStore

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  |  23 +++
 Silicon/NXP/Chassis3V2/Chassis3V2.dec |  22 +++
 Silicon/NXP/LX2160A/LX2160A.dec   |  13 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc |  10 ++
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   |  50 ++
 Silicon/NXP/NxpQoriqLs.dsc.inc|  13 +-
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  |  46 ++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf  |   4 +-
 .../LX2160aRdbPkg.fdf}|  51 ++
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +
 .../Library/ChassisLib/ChassisLib.inf |  33 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf |  27 
 .../PL011UartClockLib/PL011UartClockLib.inf   |  24 +++
 Silicon/NXP/Chassis3V2/Include/Chassis.h  |  26 
 Silicon/NXP/LX2160A/Include/Soc.h |  38 +
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 ++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  80 ++
 .../Library/ChassisLib/ChassisLib.c   |  71 +
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   |  80 ++
 .../PL011UartClockLib/PL011UartClockLib.c |  22 +++
 .../PciHostBridgeLib/PciHostBridgeLib.c   |   2 +
 .../AArch64/ArmPlatformHelper.S   |  45 ++
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc   |  91 +++
 23 files changed, 917 insertions(+), 43 deletions(-)
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dsc.inc
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
 copy Platform/NXP/{LS1043aRdbPkg/LS1043aRdbPkg.fdf => 
LX2160aRdbPkg/LX2160aRdbPkg.fdf} (82%)
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
 create mode 100644 Silicon/NXP/LX2160A/Include/Soc.h
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc

-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 05/10] Platform/NXP/LX2160ARDB: Add ArmPlatformLib

2020-06-01 Thread Pankaj Bansal

From: Pankaj Bansal 

Add ArmPlatformLib for LX2160ARDB platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Apart from the the interfaces exposed by ArmPlatformLibNull, this
library also implements gPlatformGetClockPpi, which is specific to NXP
SOCs' based platforms.

Refer edk2-platforms/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h for
the details.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- Sorted [Packages] and [FixedPcd] alphabetically in
  Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf

V3:
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
  part containing gPlatformGetClockPpi is put before PL011UartClockLib
  implementation.

V2:
- No change

 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
|  39 ++
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 145 
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
|  28 
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
|  45 ++
 4 files changed, 257 insertions(+)

diff --git 
a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index ..53d8af58925a
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,39 @@
+#/* @file
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = d1361285-8a47-421c-9efd-6b262c9093fc
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index ..806cfd180bee
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,145 @@
+/** @file
+*
+*  Copyright 2018-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+#include 
+#include 
+
+ARM_CORE_INFO mLX2160aMpCoreInfoTable[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP 
clock
+ is to be retrieved.
+  @param[in]  ...Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, 
then
+ the second argument will be interpreted as controller
+ number.
+ if ClockType is NXP_CORE_CLOCK, then second argument
+ is interpreted as cluster number and third argument is
+ interpreted as core number (within the cluster)
+
+  @returnActual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+  IN  UINT32  ClockType,
+  ...
+  )
+{
+  UINT64  Clock;
+  VA_LIST Args;
+
+  Clock = 0;
+
+  VA_START (Args, ClockType);
+
+  switch (ClockType) {
+  case NXP_SYSTEM_CLOCK:
+Clock = 100 * 1000 * 1000; // 100 MHz
+break;
+  case NXP_I2C_CLOCK:
+  case NXP_UART_CLOCK:
+Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+break;
+  default:
+break;
+  }
+
+  VA_END (Args);
+
+  return Clock;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or 
ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN MpId
+  )
+{
+  //TODO: Implement me
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS

Re: [edk2-devel] [PATCH edk2-InfSpecification] Drop statement on package ordering

2020-06-01 Thread Pankaj Bansal

Hi Mike,

But doesn't this violate the edk2 c guidelines ?

https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/53_include_files#5-3-2-every-include-file-shall-have-a-unique-name

The case above explicitly forbids the edk2 port to have the same filename that 
is used by MdePkg / MdeModulePkg.

Which one to follow ??

Regards,
Pankaj Bansal 

> -Original Message-
> From: Kinney, Michael D 
> Sent: Monday, June 1, 2020 10:45 AM
> To: Pankaj Bansal (OSS) ; Leif Lindholm
> ; devel@edk2.groups.io; Kinney, Michael D
> 
> Cc: Andrew Fish ; Laszlo Ersek 
> Subject: RE: [edk2-devel] [PATCH edk2-InfSpecification] Drop statement on
> package ordering
> 
> Pankaj Bansal,
> 
> The override package should be listed before the standard package
> in the [Packages] section of an INF file.
> 
> The internal behavior of the build system is to generate makefiles
> that invoke compilers.  The list of -I include paths passed to
> compilers is generated from [Includes] sections of the package DEC
> files listed in an INF [Packages] section.  The order that the
> -I directives are listed is based is the same order that the
> packages are listed in the INF [Packages] section.
> 
> Mike
> 
> > -Original Message-
> > From: Pankaj Bansal (OSS) 
> > Sent: Sunday, May 31, 2020 8:39 PM
> > To: Leif Lindholm ;
> > devel@edk2.groups.io; Kinney, Michael D
> > 
> > Cc: Andrew Fish ; Laszlo Ersek
> > ; Pankaj Bansal (OSS)
> > 
> > Subject: RE: [edk2-devel] [PATCH edk2-InfSpecification]
> > Drop statement on package ordering
> >
> > Hi Mike,
> >
> > This means any port of edk2, should it so wish to
> > override the include file provided by edk2 packages
> > (MdePkg or MdeModulePkg),
> > must be listed after these dec files (MdePkg.dec or
> > MdeModulePkg.dec) in an inf file?
> >
> > Regards,
> > Pankaj Bansal
> >
> > > -Original Message-
> > > From: Leif Lindholm 
> > > Sent: Monday, June 1, 2020 4:14 AM
> > > To: devel@edk2.groups.io; michael.d.kin...@intel.com
> > > Cc: Andrew Fish ; Laszlo Ersek
> > ; Pankaj
> > > Bansal (OSS) 
> > > Subject: Re: [edk2-devel] [PATCH edk2-
> > InfSpecification] Drop statement on
> > > package ordering
> > >
> > > Hi Mike,
> > >
> > > Ok, I'm happy to hear that.
> > >
> > > I agree that the overriding behaviour is useful, and
> > it would be good
> > > to document it. The problem is that the current
> > wording does not say
> > > that (in a way that is useful to anyone who does not
> > already know what
> > > it means). And the MdePkg/MdeModulePkg example sounds
> > positively
> > > horrific when interpreted in this light.
> > >
> > > Clearly, my proposed modification is not the right
> > thing to do here.
> > >
> > > The problem with the document implying that the order
> > should reflect
> > > some sort of hierarchy *apart from when explicitly
> > overriding* is that
> > > this is asking a human to do the thing that humans
> > are bad at and
> > > computers are good at. It can't scale where humans
> > are reviewing ports
> > > that they understand less well than the people
> > contributing them.
> > >
> > > I think we should find a wording that explains the
> > behaviour instead
> > > of explaining some potential derivative of the
> > behaviour, as well as
> > > providing a realistic example instead of the
> > MdePkg/MdeModulePkg
> > > statament.
> > >
> > > My suggestion is to keep it simple: say something
> > like "where there is
> > > a need to override an include file provided by one
> > package with one
> > > provided by another package, know that the compiler
> > invocation will
> > > list the include directories in the same order as the
> > .dec files are
> > > listed in the .inf".
> > >
> > > Regards,
> > >
> > > Leif
> > >
> > > On Sun, May 31, 2020 at 22:19:24 +, Michael D
> > Kinney wrote:
> > > > Hi Leif,
> > > >
> > > > The reason for this statement is not for
> > performance.
> > > >
> > > > It is if the same include file exists in the same
> > path
> > > > in more than one package.  Defining this behavior
> > makes
> > > > the build system deterministic.
> > > >
> > > > There is use case where

Re: [edk2-devel] [PATCH edk2-InfSpecification] Drop statement on package ordering

2020-05-31 Thread Pankaj Bansal

Hi Mike,

This means any port of edk2, should it so wish to override the include file 
provided by edk2 packages (MdePkg or MdeModulePkg),
must be listed after these dec files (MdePkg.dec or MdeModulePkg.dec) in an inf 
file?

Regards,
Pankaj Bansal

> -Original Message-
> From: Leif Lindholm 
> Sent: Monday, June 1, 2020 4:14 AM
> To: devel@edk2.groups.io; michael.d.kin...@intel.com
> Cc: Andrew Fish ; Laszlo Ersek ; Pankaj
> Bansal (OSS) 
> Subject: Re: [edk2-devel] [PATCH edk2-InfSpecification] Drop statement on
> package ordering
> 
> Hi Mike,
> 
> Ok, I'm happy to hear that.
> 
> I agree that the overriding behaviour is useful, and it would be good
> to document it. The problem is that the current wording does not say
> that (in a way that is useful to anyone who does not already know what
> it means). And the MdePkg/MdeModulePkg example sounds positively
> horrific when interpreted in this light.
> 
> Clearly, my proposed modification is not the right thing to do here.
> 
> The problem with the document implying that the order should reflect
> some sort of hierarchy *apart from when explicitly overriding* is that
> this is asking a human to do the thing that humans are bad at and
> computers are good at. It can't scale where humans are reviewing ports
> that they understand less well than the people contributing them.
> 
> I think we should find a wording that explains the behaviour instead
> of explaining some potential derivative of the behaviour, as well as
> providing a realistic example instead of the MdePkg/MdeModulePkg
> statament.
> 
> My suggestion is to keep it simple: say something like "where there is
> a need to override an include file provided by one package with one
> provided by another package, know that the compiler invocation will
> list the include directories in the same order as the .dec files are
> listed in the .inf".
> 
> Regards,
> 
> Leif
> 
> On Sun, May 31, 2020 at 22:19:24 +, Michael D Kinney wrote:
> > Hi Leif,
> >
> > The reason for this statement is not for performance.
> >
> > It is if the same include file exists in the same path
> > in more than one package.  Defining this behavior makes
> > the build system deterministic.
> >
> > There is use case where a platform package can provide
> > an include override of a common package and the platform
> > modules list the platform package before the common
> > package in the [Packages] section.
> >
> > So deterministic build when there are include file
> > name collisions and overrides are 2 reasons to keep
> > the currently defined behavior.
> >
> > With this background, perhaps some clarification or
> > rewording of the spec is required?  Do you have suggestions?
> >
> > Thanks,
> >
> > Mike
> >
> >   This is not a common use case,
> > but one that does apply is a platform module that wants
> > to use an override of a standard include file in a platform
> > package.
> >
> > For the build system autogen stage, this statement
> >
> > Mike
> >
> > > -Original Message-
> > > From: Leif Lindholm 
> > > Sent: Friday, May 29, 2020 7:03 AM
> > > To: devel@edk2.groups.io
> > > Cc: Kinney, Michael D ;
> > > Andrew Fish ; Laszlo Ersek
> > > ; Pankaj Bansal
> > > 
> > > Subject: [PATCH edk2-InfSpecification] Drop statement
> > > on package ordering
> > >
> > > The description of [Packages] sections stated that
> > > "Packages must be listed in the order that may be
> > > required for specifying
> > >  include path statements for a compiler. For example,
> > > the
> > >  MdePkg/MdePkg.dec file must be listed before the
> > >  MdeModulePkg/MdeModulePkg.dec file."
> > >
> > > Drop it.
> > >
> > > Signed-off-by: Leif Lindholm 
> > > ---
> > >
> > > Surely this isn't something we take seriously?
> > > If there is a measurable performance impact to the
> > > order of -I option
> > > on the compiler command line, we should approach this
> > > programmatically.
> > >
> > >  3_edk_ii_inf_file_format/37_[packages]_sections.md | 7
> > > ++-
> > >  1 file changed, 2 insertions(+), 5 deletions(-)
> > >
> > > diff --git
> > > a/3_edk_ii_inf_file_format/37_[packages]_sections.md
> > > b/3_edk_ii_inf_file_format/37_[packages]_sections.md
> > > index 17a8d91..c09112b 100644
> > > ---
> > > a/3_edk_ii_inf_file_format/37_[packag

Re: [edk2-devel] [PATCH edk2-platforms v2 8/9] Platform/NXP: Add LX2160ARDB Platform

2020-05-30 Thread Pankaj Bansal

> On Fri, May 29, 2020 at 12:25:43 +0000, Pankaj Bansal (OSS) wrote:
> > > > I intentionally kept these in this order. because Soc depends on Chassis
> for any
> > > include files
> > > > Chassis depends on NxpQoriqLs.dec for any include files.
> > >
> > > OK, I see the logic behind that, but as it has no functional meaning I
> > > don't think it outweighs the benefit of alphabetical sorting.
> > >
> >
> > I referred to the inf specifications for this:
> > https://edk2-docs.gitbook.io/edk-ii-inf-
> specification/3_edk_ii_inf_file_format/37_-packages-_sections
> >
> > "Packages must be listed in the order that may be required for
> > specifying include path statements for a compiler.
> > For example, the MdePkg/MdePkg.dec file must be listed before the
> > MdeModulePkg/MdeModulePkg.dec file"
> 
> I see that. (And sigh.) Clearly, that needs to be fixed. I have cc:d
> you on the patch to do that.
> 
> I am sure that made sense when that text was originally written, which
> was presumably the previous millenium. But this is akin to "optimising"
> the order in which header files is included.
> 

hmm. I think it was written to maintain the dependency between include files.
But I guess if we follow edk2 c guideline we can avoid this problem.

https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/53_include_files#5-3-4-include-files-may-include-only-those-headers-that-it-directly-depends-upon


> > By design the Chassis package files can include generic NXP package
> > files. not the other way around.
> > same goes for SOC package files. SOC package files can include
> > Chassis Package file but not the other way around
> > and we can extend this further. any platform package files can
> > include SOC package files
> >
> > > I *do* tend to say "alphabetically, unless there is a better logical
> > > order", but by that I usually mean grouping related Pcd dependency
> > > declarations.
> >
> > as I mentioned above, there *is* a logical order to packages.
> 
> And as I said "I see the logic behind that".
> I'm saying readability trumps that logic.

Ok. it makes sense.

> 
> > >
> > > This is my only remaining niggle with this set - are you OK with me
> > > folding in
> > >
> > > ---
> a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > +++
> > >
> b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > @@ -18,9 +18,9 @@ [Packages]
> > >MdeModulePkg/MdeModulePkg.dec
> > >ArmPkg/ArmPkg.dec
> > >ArmPlatformPkg/ArmPlatformPkg.dec
> > > -  Silicon/NXP/NxpQoriqLs.dec
> > >Silicon/NXP/Chassis3V2/Chassis3V2.dec
> > >Silicon/NXP/LX2160A/LX2160A.dec
> > > +  Silicon/NXP/NxpQoriqLs.dec
> > >
> > > to v3 9/10 and pushing the set?

Ok. can you please sort all the dec files under [Packages] based on names 
before pushing ?
I think this file also needs alphabetical sorting:
https://github.com/tianocore/edk2/blob/master/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf#L16

> > >
> > > /
> > > Leif

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Re: [edk2-devel] [PATCH edk2-platforms v2 8/9] Platform/NXP: Add LX2160ARDB Platform

2020-05-29 Thread Pankaj Bansal

> On Fri, May 29, 2020 at 05:21:24 +0000, Pankaj Bansal (OSS) wrote:
> > > > ---
> > >
> a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > > +++
> > >
> b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > > @@ -19,9 +19,12 @@
> > > >ArmPkg/ArmPkg.dec
> > > >ArmPlatformPkg/ArmPlatformPkg.dec
> > > >Silicon/NXP/NxpQoriqLs.dec
> > > > +  Silicon/NXP/Chassis3V2/Chassis3V2.dec
> > > > +  Silicon/NXP/LX2160A/LX2160A.dec
> > >
> > > Please insert alphabetically sorted.
> >
> > I intentionally kept these in this order. because Soc depends on Chassis 
> > for any
> include files
> > Chassis depends on NxpQoriqLs.dec for any include files.
> 
> OK, I see the logic behind that, but as it has no functional meaning I
> don't think it outweighs the benefit of alphabetical sorting.
> 

I referred to the inf specifications for this:
https://edk2-docs.gitbook.io/edk-ii-inf-specification/3_edk_ii_inf_file_format/37_-packages-_sections

"Packages must be listed in the order that may be required for specifying 
include path statements for a compiler.
For example, the MdePkg/MdePkg.dec file must be listed before the 
MdeModulePkg/MdeModulePkg.dec file"

By design the Chassis package files can include generic NXP package files. not 
the other way around.
same goes for SOC package files. SOC package files can include Chassis Package 
file but not the other way around
and we can extend this further. any platform package files can include SOC 
package files

> I *do* tend to say "alphabetically, unless there is a better logical
> order", but by that I usually mean grouping related Pcd dependency
> declarations.

as I mentioned above, there *is* a logical order to packages.

> 
> This is my only remaining niggle with this set - are you OK with me
> folding in
> 
> --- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++
> b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -18,9 +18,9 @@ [Packages]
>MdeModulePkg/MdeModulePkg.dec
>ArmPkg/ArmPkg.dec
>ArmPlatformPkg/ArmPlatformPkg.dec
> -  Silicon/NXP/NxpQoriqLs.dec
>Silicon/NXP/Chassis3V2/Chassis3V2.dec
>Silicon/NXP/LX2160A/LX2160A.dec
> +  Silicon/NXP/NxpQoriqLs.dec
> 
> to v3 9/10 and pushing the set?
> 
> /
> Leif

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[edk2-devel] [PATCH edk2-platforms v3 03/10] Silicon/NXP/PciHostBridgeLib: Fix compilation with MDEPKG_NDEBUG flag

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

when MDEPKG_NDEBUG flag is enabled, RELEASE build fails with this error:

error: mPciHostBridgeLibAcpiAddressSpaceTypeStr defined but not used
[-Werror=unused-variable]

Fix this error by protecting mPciHostBridgeLibAcpiAddressSpaceTypeStr
with MDEPKG_NDEBUG macro.

Suggested-by: Leif Lindholm 
Signed-off-by: Pankaj Bansal 
---

Notes:
V3:
- New commit

 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c 
b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 549f4fa133fb..e5309a4f4248 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -167,11 +167,13 @@ STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH 
mEfiPciRootBridgeDevicePath[] = {
   }
 };
 
+#ifndef MDEPKG_NDEBUG
 STATIC
 GLOBAL_REMOVE_IF_UNREFERENCED
 CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
   L"Mem", L"I/O", L"Bus"
 };
+#endif
 
 #define PCI_ALLOCATION_ATTRIBUTES   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | 
\
 EFI_PCI_HOST_BRIDGE_MEM64_DECODE
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 05/10] Platform/NXP/LX2160ARDB: Add ArmPlatformLib

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

Add ArmPlatformLib for LX2160ARDB platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Apart from the the interfaces exposed by ArmPlatformLibNull, this
library also implements gPlatformGetClockPpi, which is specific to NXP
SOCs' based platforms.

Refer edk2-platforms/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h for
the details.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- New commit
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
  part containing gPlatformGetClockPpi is put before PL011UartClockLib
  implementation.

 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
|  39 ++
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 145 
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
|  28 
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
|  45 ++
 4 files changed, 257 insertions(+)

diff --git 
a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index ..743836e57141
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,39 @@
+#/* @file
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = d1361285-8a47-421c-9efd-6b262c9093fc
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index ..806cfd180bee
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,145 @@
+/** @file
+*
+*  Copyright 2018-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+#include 
+#include 
+
+ARM_CORE_INFO mLX2160aMpCoreInfoTable[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP 
clock
+ is to be retrieved.
+  @param[in]  ...Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, 
then
+ the second argument will be interpreted as controller
+ number.
+ if ClockType is NXP_CORE_CLOCK, then second argument
+ is interpreted as cluster number and third argument is
+ interpreted as core number (within the cluster)
+
+  @returnActual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+  IN  UINT32  ClockType,
+  ...
+  )
+{
+  UINT64  Clock;
+  VA_LIST Args;
+
+  Clock = 0;
+
+  VA_START (Args, ClockType);
+
+  switch (ClockType) {
+  case NXP_SYSTEM_CLOCK:
+Clock = 100 * 1000 * 1000; // 100 MHz
+break;
+  case NXP_I2C_CLOCK:
+  case NXP_UART_CLOCK:
+Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+break;
+  default:
+break;
+  }
+
+  VA_END (Args);
+
+  return Clock;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or 
ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN MpId
+  )
+{
+  //TODO: Implement me
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable

[edk2-devel] [PATCH edk2-platforms v3 08/10] Silicon/NXP: Add LX2160A Soc package

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- No change

 Silicon/NXP/LX2160A/LX2160A.dec   | 13 
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   | 50 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 27 +++
 Silicon/NXP/LX2160A/Include/Soc.h | 38 ++
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   | 80 
 5 files changed, 208 insertions(+)

diff --git a/Silicon/NXP/LX2160A/LX2160A.dec b/Silicon/NXP/LX2160A/LX2160A.dec
new file mode 100644
index ..50481c0f2ebd
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dec
@@ -0,0 +1,13 @@
+# LX2160A.dec
+#
+# Copyright 2018, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001A
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc 
b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
new file mode 100644
index ..af22b4dd973c
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
@@ -0,0 +1,50 @@
+#  LX2160A.dsc
+#  LX2160A Soc package.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
+
+  PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
+  
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  PL011UartClockLib|Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x600
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x620
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C
+
+[PcdsFixedAtBuild.common]
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x239
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|91
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+##
diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
new file mode 100644
index ..421072b88019
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/LX2160A/LX2160A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h 
b/Silicon/NXP/LX2160A/Include/Soc.h
new file mode 100644
index ..52674ee5f32c
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -0,0 +1,38 @@
+/** @file
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LX2160A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LX2160A_DRAM0_SIZE   (SIZE_2GB)
+#define LX2160A_DRAM1_PHYS_ADDRESS   (BASE_128GB + BASE_2GB)
+#define LX2160A_DRAM1_SIZE   (SIZE_128GB - SIZE_2GB) // 126 GB
+#define LX2160A_DRAM2_PHYS_ADDRESS   (BASE_256GB + BASE_128GB)
+#define LX2160A_DRAM2_SIZE   (SIZE_128GB)
+
+#define LX2160A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LX2160A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LX2160A_FSPI0_PHYS_ADDRESS   (BASE_512MB)
+#define LX2160A_FSPI0_SIZE   (SIZE_256MB)
+
+#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6

[edk2-devel] [PATCH edk2-platforms v3 04/10] Silicon/NXP: Use edk2 recommended compilation flags

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.

Therefore, enable these flags for NXP platforms as well

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 12e2b89fac58..ee639d552483 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -173,7 +173,12 @@
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
 
 [BuildOptions]
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+  #
+  # Disable deprecated APIs.
+  #
+  GCC:*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 02/10] Platform/NXP: Use Monotonic counter from MdeModulePkg

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.

Therefore, use Monotonic counter module from MdeModulePkg

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc   | 2 +-
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 54236e19531c..12e2b89fac58 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -337,7 +337,7 @@
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
   EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
 
   # FDT installation
   MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 95bbb54cc420..dd31b45b4d78 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -100,7 +100,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF 
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
   INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 09/10] Platform/NXP: Add LX2160ARDB Platform

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

Signed-off-by: Pankaj Bansal 
---

Notes:
V3:
- Alphabetically sorted LibraryClasses in
  Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf

V2:
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
  part containing gPlatformGetClockPpi is put before PL011UartClockLib
  implementation.

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  |  23 +++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  |  46 
++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf  | 168 

 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  |   3 +
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c|   4 +-
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c |  54 
++-
 6 files changed, 296 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
new file mode 100644
index ..03996b07fcb9
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
@@ -0,0 +1,23 @@
+#  LX2160aRdbPkg.dec
+#  LX2160a board package.
+#
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LX2160aRdbPkg
+  PACKAGE_GUID   = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
new file mode 100644
index ..9b3e0386c13e
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
@@ -0,0 +1,46 @@
+#  LX2160aRdbPkg.dsc
+#
+#  LX2160ARDB Board package.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LX2160aRdbPkg
+  PLATFORM_GUID  = be06d8bc-05eb-44d6-b39f-191e93617ebd
+  OUTPUT_DIRECTORY   = Build/LX2160aRdbPkg
+  FLASH_DEFINITION   = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LX2160A/LX2160A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+ ##
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
new file mode 100644
index ..19d2ca9bbe58
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -0,0 +1,168 @@
+#  LX2160aRdbPkg.fdf
+#
+#  FLASH layout file for LX2160a board.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be use

[edk2-devel] [PATCH edk2-platforms v3 01/10] Silicon/NXP: Use Metronome implementation from MdeModulePkg

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

There are two implementations of Metronome protocol.

EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf

Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg over
EmbeddedPkg.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc   | 4 +---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 03759c7cee7c..54236e19531c 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -218,8 +218,6 @@
   
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
 
 [PcdsFixedAtBuild.common]
-  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1 # expressed in 100ns units, 
100,000 x 100 ns = 10,000,000 ns = 10 ms
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
@@ -348,7 +346,7 @@
   MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/Metronome/Metronome.inf
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 1c160e349eb9..95bbb54cc420 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -117,7 +117,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/Metronome/Metronome.inf
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
 
   #
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 06/10] Silicon/NXP: Implement PL011UartClockLib for NXP platforms

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- No change

 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf | 24 

 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c   | 22 
++
 2 files changed, 46 insertions(+)

diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
new file mode 100644
index ..b771dba7697f
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
@@ -0,0 +1,24 @@
+#/* @file
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PL011UartClockLib
+  FILE_GUID  = af8fef24-afbb-472a-b8b7-13101a79703c
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PL011UartClockLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[Sources.common]
+  PL011UartClockLib.c
+
+[LibraryClasses]
+  ArmPlatformLib
diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
new file mode 100644
index ..3814685585eb
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
@@ -0,0 +1,22 @@
+/** @file
+*
+*  Copyright 2018, 2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+/**
+  Return clock in for PL011 Uart IP
+**/
+UINT32
+EFIAPI
+PL011UartClockGetFreq (
+  VOID
+  )
+{
+  return gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
+}
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v3 07/10] Silicon/NXP: Add Chassis3V2 Package

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- No change

 Silicon/NXP/Chassis3V2/Chassis3V2.dec| 22 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc| 10 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf | 33 +
 Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c   | 71 

 5 files changed, 162 insertions(+)

diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
new file mode 100644
index ..f7269e6bf6de
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
@@ -0,0 +1,22 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 1.27
+  PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
new file mode 100644
index ..b9f388a59f2a
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
@@ -0,0 +1,10 @@
+#  @file
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+  ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index ..75b68cc4ca2d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,33 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION= 1.27
+  BASE_NAME  = Chassis3V2Lib
+  FILE_GUID  = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ChassisLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  IoAccessLib
+  IoLib
+  PcdLib
+  SerialPortLib
+
+[Sources.common]
+  ChassisLib.c
+
+[FeaturePcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h 
b/Silicon/NXP/Chassis3V2/Include/Chassis.h
new file mode 100644
index ..0fd70132d897
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
@@ -0,0 +1,26 @@
+/** @file
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#include 
+
+#define  NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS  0x1E0
+
+/**
+  The Device Configuration Unit provides general purpose configuration and
+  status for the device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+  UINT8   Reserved0[0x100 - 0x0];
+  UINT32  RcwSr[32]; // Reset Control Word Status Register
+} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index ..30f8f945b233
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,71 @@
+/** @file
+  Chassis specific functions common to all SOCs based on a specific Chessis
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Read Dcfg register
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+  IN  UINTN Address
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->Read32 (Address);
+}
+
+/**
+  Write Dcfg register
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+  @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+  IN  UINTN Address,
+  IN  UINT32Value
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->Write32 (Address,

[edk2-devel] [PATCH edk2-platforms v3 10/10] Platform/NXP/LX2160aRdbPkg: Add VarStore

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V3:
- No change

V2:
- No change

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf |  1 +
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc  | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
index 19d2ca9bbe58..eec1c0774a86 100644
--- a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -48,6 +48,7 @@ 
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc 
b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
new file mode 100644
index ..799eee87193f
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LX2160aRdbNv_EFI]
+BaseAddress   = 0x2050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LX2160ARDB NVRAM Area
+# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xF

[edk2-devel] [PATCH edk2-platforms v3 00/10] Add LX2160ARDB Platform

2020-05-28 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

This Platform is based on Layerscape Chassis3V2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

v2 of this series can be referred here:
https://edk2.groups.io/g/devel/message/60320

Changes w.r.t v2:

03/10: Silicon/NXP/PciHostBridgeLib: Fix compilation with MDEPKG_NDEBUG flag

  - new commit

09/10: Platform/NXP: Add LX2160ARDB Platform

  - Alphabetically sorted LibraryClasses in
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf

Pankaj Bansal (10):
  Silicon/NXP: Use Metronome implementation from MdeModulePkg
  Platform/NXP: Use Monotonic counter from MdeModulePkg
  Silicon/NXP/PciHostBridgeLib: Fix compilation with MDEPKG_NDEBUG flag
  Silicon/NXP: Use edk2 recommended compilation flags
  Platform/NXP/LX2160ARDB: Add ArmPlatformLib
  Silicon/NXP: Implement PL011UartClockLib for NXP platforms
  Silicon/NXP: Add Chassis3V2 Package
  Silicon/NXP: Add LX2160A Soc package
  Platform/NXP: Add LX2160ARDB Platform
  Platform/NXP/LX2160aRdbPkg: Add VarStore

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  |  23 +++
 Silicon/NXP/Chassis3V2/Chassis3V2.dec |  22 +++
 Silicon/NXP/LX2160A/LX2160A.dec   |  13 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc |  10 ++
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   |  50 ++
 Silicon/NXP/NxpQoriqLs.dsc.inc|  13 +-
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  |  46 ++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf  |   4 +-
 .../LX2160aRdbPkg.fdf}|  51 ++
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +
 .../Library/ChassisLib/ChassisLib.inf |  33 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf |  27 
 .../PL011UartClockLib/PL011UartClockLib.inf   |  24 +++
 Silicon/NXP/Chassis3V2/Include/Chassis.h  |  26 
 Silicon/NXP/LX2160A/Include/Soc.h |  38 +
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 ++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  80 ++
 .../Library/ChassisLib/ChassisLib.c   |  71 +
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   |  80 ++
 .../PL011UartClockLib/PL011UartClockLib.c |  22 +++
 .../PciHostBridgeLib/PciHostBridgeLib.c   |   2 +
 .../AArch64/ArmPlatformHelper.S   |  45 ++
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc   |  91 +++
 23 files changed, 917 insertions(+), 43 deletions(-)
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dsc.inc
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
 copy Platform/NXP/{LS1043aRdbPkg/LS1043aRdbPkg.fdf => 
LX2160aRdbPkg/LX2160aRdbPkg.fdf} (82%)
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
 create mode 100644 Silicon/NXP/LX2160A/Include/Soc.h
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc

-- 
2.17.1


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Re: [edk2-devel] [PATCH edk2-platforms v2 8/9] Platform/NXP: Add LX2160ARDB Platform

2020-05-28 Thread Pankaj Bansal

> > ---
> a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > +++
> b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > @@ -19,9 +19,12 @@
> >ArmPkg/ArmPkg.dec
> >ArmPlatformPkg/ArmPlatformPkg.dec
> >Silicon/NXP/NxpQoriqLs.dec
> > +  Silicon/NXP/Chassis3V2/Chassis3V2.dec
> > +  Silicon/NXP/LX2160A/LX2160A.dec
> 
> Please insert alphabetically sorted.

I intentionally kept these in this order. because Soc depends on Chassis for 
any include files
Chassis depends on NxpQoriqLs.dec for any include files.

> 
> >
> >  [LibraryClasses]
> >ArmLib
> > +  SocLib
> >DebugLib
> 
> Please insert alphabetically sorted.

This I can take care

> 
> No further comments on this set for v2.
> For the patches I have not commented on:
> Reviewed-by: Leif Lindholm 
> 
> /
> Leif
> 
> >

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[edk2-devel] [PATCH edk2-platforms v2 2/9] Platform/NXP: Use Monotonic counter from MdeModulePkg

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.

Therefore, use Monotonic counter module from MdeModulePkg

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc   | 2 +-
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 54236e19531c..12e2b89fac58 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -337,7 +337,7 @@
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
   EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
 
   # FDT installation
   MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index fede51ced10e..49d8885477c7 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -98,7 +98,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF 
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
   INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 7/9] Silicon/NXP: Add LX2160A Soc package

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- No change

 Silicon/NXP/LX2160A/LX2160A.dec   | 13 
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   | 50 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 27 +++
 Silicon/NXP/LX2160A/Include/Soc.h | 38 ++
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   | 80 
 5 files changed, 208 insertions(+)

diff --git a/Silicon/NXP/LX2160A/LX2160A.dec b/Silicon/NXP/LX2160A/LX2160A.dec
new file mode 100644
index ..50481c0f2ebd
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dec
@@ -0,0 +1,13 @@
+# LX2160A.dec
+#
+# Copyright 2018, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001A
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc 
b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
new file mode 100644
index ..af22b4dd973c
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
@@ -0,0 +1,50 @@
+#  LX2160A.dsc
+#  LX2160A Soc package.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
+
+  PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
+  
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  PL011UartClockLib|Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x600
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x620
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C
+
+[PcdsFixedAtBuild.common]
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x239
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|91
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+##
diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
new file mode 100644
index ..421072b88019
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/LX2160A/LX2160A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h 
b/Silicon/NXP/LX2160A/Include/Soc.h
new file mode 100644
index ..52674ee5f32c
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -0,0 +1,38 @@
+/** @file
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LX2160A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LX2160A_DRAM0_SIZE   (SIZE_2GB)
+#define LX2160A_DRAM1_PHYS_ADDRESS   (BASE_128GB + BASE_2GB)
+#define LX2160A_DRAM1_SIZE   (SIZE_128GB - SIZE_2GB) // 126 GB
+#define LX2160A_DRAM2_PHYS_ADDRESS   (BASE_256GB + BASE_128GB)
+#define LX2160A_DRAM2_SIZE   (SIZE_128GB)
+
+#define LX2160A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LX2160A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LX2160A_FSPI0_PHYS_ADDRESS   (BASE_512MB)
+#define LX2160A_FSPI0_SIZE   (SIZE_256MB)
+
+#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS3V2_DEV

[edk2-devel] [PATCH edk2-platforms v2 5/9] Silicon/NXP: Implement PL011UartClockLib for NXP platforms

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- No change

 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf | 24 

 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c   | 22 
++
 2 files changed, 46 insertions(+)

diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
new file mode 100644
index ..b771dba7697f
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
@@ -0,0 +1,24 @@
+#/* @file
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PL011UartClockLib
+  FILE_GUID  = af8fef24-afbb-472a-b8b7-13101a79703c
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PL011UartClockLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[Sources.common]
+  PL011UartClockLib.c
+
+[LibraryClasses]
+  ArmPlatformLib
diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
new file mode 100644
index ..3814685585eb
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
@@ -0,0 +1,22 @@
+/** @file
+*
+*  Copyright 2018, 2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+/**
+  Return clock in for PL011 Uart IP
+**/
+UINT32
+EFIAPI
+PL011UartClockGetFreq (
+  VOID
+  )
+{
+  return gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
+}
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 9/9] Platform/NXP/LX2160aRdbPkg: Add VarStore

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- No change

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf |  1 +
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc  | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
index 19d2ca9bbe58..eec1c0774a86 100644
--- a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -48,6 +48,7 @@ 
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc 
b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
new file mode 100644
index ..799eee87193f
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LX2160aRdbNv_EFI]
+BaseAddress   = 0x2050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LX2160ARDB NVRAM Area
+# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0xFF, 0x03, 0x0

[edk2-devel] [PATCH edk2-platforms v2 6/9] Silicon/NXP: Add Chassis3V2 Package

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- No change

 Silicon/NXP/Chassis3V2/Chassis3V2.dec| 22 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc| 10 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf | 33 +
 Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c   | 71 

 5 files changed, 162 insertions(+)

diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
new file mode 100644
index ..f7269e6bf6de
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
@@ -0,0 +1,22 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 1.27
+  PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
new file mode 100644
index ..b9f388a59f2a
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
@@ -0,0 +1,10 @@
+#  @file
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+  ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index ..75b68cc4ca2d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,33 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION= 1.27
+  BASE_NAME  = Chassis3V2Lib
+  FILE_GUID  = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ChassisLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  IoAccessLib
+  IoLib
+  PcdLib
+  SerialPortLib
+
+[Sources.common]
+  ChassisLib.c
+
+[FeaturePcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h 
b/Silicon/NXP/Chassis3V2/Include/Chassis.h
new file mode 100644
index ..0fd70132d897
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
@@ -0,0 +1,26 @@
+/** @file
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#include 
+
+#define  NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS  0x1E0
+
+/**
+  The Device Configuration Unit provides general purpose configuration and
+  status for the device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+  UINT8   Reserved0[0x100 - 0x0];
+  UINT32  RcwSr[32]; // Reset Control Word Status Register
+} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index ..30f8f945b233
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,71 @@
+/** @file
+  Chassis specific functions common to all SOCs based on a specific Chessis
+
+  Copyright 2018-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Read Dcfg register
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+  IN  UINTN Address
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->Read32 (Address);
+}
+
+/**
+  Write Dcfg register
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+  @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+  IN  UINTN Address,
+  IN  UINT32Value
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->Write32 (Address, Value);
+}
+
+/**
+  Function to initialize Chassis Sp

[edk2-devel] [PATCH edk2-platforms v2 8/9] Platform/NXP: Add LX2160ARDB Platform

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
  part containing gPlatformGetClockPpi is put before PL011UartClockLib
  implementation.

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  |  23 +++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  |  46 
++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf  | 168 

 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  |   3 +
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c|   4 +-
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c |  54 
++-
 6 files changed, 296 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
new file mode 100644
index ..03996b07fcb9
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
@@ -0,0 +1,23 @@
+#  LX2160aRdbPkg.dec
+#  LX2160a board package.
+#
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LX2160aRdbPkg
+  PACKAGE_GUID   = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
new file mode 100644
index ..9b3e0386c13e
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
@@ -0,0 +1,46 @@
+#  LX2160aRdbPkg.dsc
+#
+#  LX2160ARDB Board package.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LX2160aRdbPkg
+  PLATFORM_GUID  = be06d8bc-05eb-44d6-b39f-191e93617ebd
+  OUTPUT_DIRECTORY   = Build/LX2160aRdbPkg
+  FLASH_DEFINITION   = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LX2160A/LX2160A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+ ##
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
new file mode 100644
index ..19d2ca9bbe58
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -0,0 +1,168 @@
+#  LX2160aRdbPkg.fdf
+#
+#  FLASH layout file for LX2160a board.
+#
+#  Copyright 2018-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+
+
+[FD.LX2160ARDB_EFI]
+BaseAddress   = 0x8200|gArmTo

[edk2-devel] [PATCH edk2-platforms v2 3/9] Silicon/NXP: Use edk2 recommended compilation flags

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.

Therefore, enable these flags for NXP platforms as well

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 12e2b89fac58..ee639d552483 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -173,7 +173,12 @@
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
 
 [BuildOptions]
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+  #
+  # Disable deprecated APIs.
+  #
+  GCC:*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 4/9] Platform/NXP/LX2160ARDB: Add ArmPlatformLib

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

Add ArmPlatformLib for LX2160ARDB platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Apart from the the interfaces exposed by ArmPlatformLibNull, this
library also implements gPlatformGetClockPpi, which is specific to NXP
SOCs' based platforms.

Refer edk2-platforms/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h for
the details.

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- New commit
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
  part containing gPlatformGetClockPpi is put before PL011UartClockLib
  implementation.

 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
|  39 ++
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 145 
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
|  28 
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
|  45 ++
 4 files changed, 257 insertions(+)

diff --git 
a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index ..743836e57141
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,39 @@
+#/* @file
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = d1361285-8a47-421c-9efd-6b262c9093fc
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index ..806cfd180bee
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,145 @@
+/** @file
+*
+*  Copyright 2018-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+#include 
+#include 
+
+ARM_CORE_INFO mLX2160aMpCoreInfoTable[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP 
clock
+ is to be retrieved.
+  @param[in]  ...Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, 
then
+ the second argument will be interpreted as controller
+ number.
+ if ClockType is NXP_CORE_CLOCK, then second argument
+ is interpreted as cluster number and third argument is
+ interpreted as core number (within the cluster)
+
+  @returnActual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+  IN  UINT32  ClockType,
+  ...
+  )
+{
+  UINT64  Clock;
+  VA_LIST Args;
+
+  Clock = 0;
+
+  VA_START (Args, ClockType);
+
+  switch (ClockType) {
+  case NXP_SYSTEM_CLOCK:
+Clock = 100 * 1000 * 1000; // 100 MHz
+break;
+  case NXP_I2C_CLOCK:
+  case NXP_UART_CLOCK:
+Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+break;
+  default:
+break;
+  }
+
+  VA_END (Args);
+
+  return Clock;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or 
ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN MpId
+  )
+{
+  //TODO: Implement me
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable
+  )
+{
+  if (ArmIsMpCore()) {
+*CoreCount= sizeof

[edk2-devel] [PATCH edk2-platforms v2 0/9] Add LX2160ARDB Platform

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

This Platform is based on Layerscape Chassis3V2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

v1 of this series can be referred here:
https://edk2.groups.io/g/devel/message/59923

Pankaj Bansal (9):
  Silicon/NXP: Use Metronome implementation from MdeModulePkg
  Platform/NXP: Use Monotonic counter from MdeModulePkg
  Silicon/NXP: Use edk2 recommended compilation flags
  Platform/NXP/LX2160ARDB: Add ArmPlatformLib
  Silicon/NXP: Implement PL011UartClockLib for NXP platforms
  Silicon/NXP: Add Chassis3V2 Package
  Silicon/NXP: Add LX2160A Soc package
  Platform/NXP: Add LX2160ARDB Platform
  Platform/NXP/LX2160aRdbPkg: Add VarStore

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  |  23 +++
 Silicon/NXP/Chassis3V2/Chassis3V2.dec |  22 +++
 Silicon/NXP/LX2160A/LX2160A.dec   |  13 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc |  10 ++
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   |  50 ++
 Silicon/NXP/NxpQoriqLs.dsc.inc|  13 +-
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  |  46 ++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf  |   4 +-
 .../LX2160aRdbPkg.fdf}|  33 ++--
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +
 .../Library/ChassisLib/ChassisLib.inf |  33 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf |  27 
 .../PL011UartClockLib/PL011UartClockLib.inf   |  24 +++
 Silicon/NXP/Chassis3V2/Include/Chassis.h  |  26 
 Silicon/NXP/LX2160A/Include/Soc.h |  38 +
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 ++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  80 ++
 .../Library/ChassisLib/ChassisLib.c   |  71 +
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   |  80 ++
 .../PL011UartClockLib/PL011UartClockLib.c |  22 +++
 .../AArch64/ArmPlatformHelper.S   |  45 ++
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc   |  91 +++
 22 files changed, 913 insertions(+), 27 deletions(-)
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dsc.inc
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
 copy Platform/NXP/{LS1043aRdbPkg/LS1043aRdbPkg.fdf => 
LX2160aRdbPkg/LX2160aRdbPkg.fdf} (88%)
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
 create mode 100644 Silicon/NXP/LX2160A/Include/Soc.h
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc

-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v2 1/9] Silicon/NXP: Use Metronome implementation from MdeModulePkg

2020-05-27 Thread Pankaj Bansal

From: Pankaj Bansal 

There are two implementations of Metronome protocol.

EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf

Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg over
EmbeddedPkg.

Signed-off-by: Pankaj Bansal 
---

Notes:
V2:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc   | 4 +---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 03759c7cee7c..54236e19531c 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -218,8 +218,6 @@
   
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
 
 [PcdsFixedAtBuild.common]
-  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1 # expressed in 100ns units, 
100,000 x 100 ns = 10,000,000 ns = 10 ms
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
@@ -348,7 +346,7 @@
   MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/Metronome/Metronome.inf
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 931d0bb14f9b..fede51ced10e 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -115,7 +115,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/Metronome/Metronome.inf
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
 
   #
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 5/8] Silicon/NXP: Add Chassis3V2 Package

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/Chassis3V2/Chassis3V2.dec| 22 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc| 10 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf | 33 +
 Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 +++
 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c   | 71 

 5 files changed, 162 insertions(+)

diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
new file mode 100644
index ..d3674cd6dff9
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
@@ -0,0 +1,22 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 1.27
+  PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc 
b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
new file mode 100644
index ..dabe2ae23054
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
@@ -0,0 +1,10 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+  ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index ..75b68cc4ca2d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,33 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION= 1.27
+  BASE_NAME  = Chassis3V2Lib
+  FILE_GUID  = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ChassisLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  IoAccessLib
+  IoLib
+  PcdLib
+  SerialPortLib
+
+[Sources.common]
+  ChassisLib.c
+
+[FeaturePcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h 
b/Silicon/NXP/Chassis3V2/Include/Chassis.h
new file mode 100644
index ..1f8a3fb129df
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
@@ -0,0 +1,26 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#include 
+
+#define  NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS  0x1E0
+
+/**
+  The Device Configuration Unit provides general purpose configuration and
+  status for the device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+  UINT8   Reserved0[0x100 - 0x0];
+  UINT32  RcwSr[32]; // Reset Control Word Status Register
+} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c 
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index ..2d1157d05174
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,71 @@
+/** @file
+  Chassis specific functions common to all SOCs based on a specific Chessis
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Read Dcfg register
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+  IN  UINTN Address
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->Read32 (Address);
+}
+
+/**
+  Write Dcfg register
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+  @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+  IN  UINTN Address,
+  IN  UINT32Value
+  )
+{
+  MMIO_OPERATIONS *DcfgOps;
+
+  DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+  return DcfgOps->Write32 (Address, Value);
+}
+
+/**
+  Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+

[edk2-devel] [PATCH edk2-platforms 7/8] Platform/NXP: Add LX2160ARDB Platform

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  
|  23 +++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  
|  46 ++
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf  
| 168 
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
|  41 +
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
| 150 +
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c 
|  85 ++
 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
|  45 ++
 7 files changed, 558 insertions(+)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
new file mode 100644
index ..192eabc5b3f2
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
@@ -0,0 +1,23 @@
+#  LX2160aRdbPkg.dec
+#  LX2160a board package.
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME   = LX2160aRdbPkg
+  PACKAGE_GUID   = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
new file mode 100644
index ..c292f3b8bff4
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
@@ -0,0 +1,46 @@
+#  LX2160aRdbPkg.dsc
+#
+#  LX2160ARDB Board package.
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LX2160aRdbPkg
+  PLATFORM_GUID  = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+  OUTPUT_DIRECTORY   = Build/LX2160aRdbPkg
+  FLASH_DEFINITION   = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LX2160A/LX2160A.dsc.inc
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+ ##
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
new file mode 100644
index ..6bd5d86ab2bd
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -0,0 +1,168 @@
+#  LX2160aRdbPkg.fdf
+#
+#  FLASH layout file for LX2160a board.
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+
+
+[FD.LX2160ARDB_EFI]
+BaseAddress   = 0x8200|gArmTokenSpaceGuid.PcdFdBaseAddress  #The

[edk2-devel] [PATCH edk2-platforms 3/8] Silicon/NXP: Use edk2 recommended compilation flags

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.

Therefore, enable these flags for NXP platforms as well

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/NxpQoriqLs.dsc.inc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 12e2b89fac58..ee639d552483 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -173,7 +173,12 @@
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
 
 [BuildOptions]
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+  #
+  # Disable deprecated APIs.
+  #
+  GCC:*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 2/8] Platform/NXP: Use Monotonic counter from MdeModulePkg

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.

Therefore, use Monotonic counter module from MdeModulePkg

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/NxpQoriqLs.dsc.inc   | 2 +-
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 54236e19531c..12e2b89fac58 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -337,7 +337,7 @@
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
   EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
 
   # FDT installation
   MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index fede51ced10e..49d8885477c7 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -98,7 +98,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF 
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
   INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 6/8] Silicon/NXP: Add LX2160A Soc package

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/LX2160A/LX2160A.dec   | 13 
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   | 50 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 27 +++
 Silicon/NXP/LX2160A/Include/Soc.h | 38 ++
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   | 80 
 5 files changed, 208 insertions(+)

diff --git a/Silicon/NXP/LX2160A/LX2160A.dec b/Silicon/NXP/LX2160A/LX2160A.dec
new file mode 100644
index ..b39a44692361
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dec
@@ -0,0 +1,13 @@
+# LX2160A.dec
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001001A
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc 
b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
new file mode 100644
index ..65c1b6e567b3
--- /dev/null
+++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
@@ -0,0 +1,50 @@
+#  LX2160A.dsc
+#  LX2160A Soc package.
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
+
+  PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
+  
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  PL011UartClockLib|Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsDynamicDefault.common]
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x600
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x620
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C
+
+[PcdsFixedAtBuild.common]
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x239
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|91
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+[Components.common]
+  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+##
diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf 
b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
new file mode 100644
index ..70e14bbabe64
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = SocLib
+  FILE_GUID  = e868c5ca-9729-43ae-bff4-438c67de8c68
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis3V2/Chassis3V2.dec
+  Silicon/NXP/LX2160A/LX2160A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h 
b/Silicon/NXP/LX2160A/Include/Soc.h
new file mode 100644
index ..626e3a0cee07
--- /dev/null
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -0,0 +1,38 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include 
+
+/**
+  Soc Memory Map
+**/
+#define LX2160A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LX2160A_DRAM0_SIZE   (SIZE_2GB)
+#define LX2160A_DRAM1_PHYS_ADDRESS   (BASE_128GB + BASE_2GB)
+#define LX2160A_DRAM1_SIZE   (SIZE_128GB - SIZE_2GB) // 126 GB
+#define LX2160A_DRAM2_PHYS_ADDRESS   (BASE_256GB + BASE_128GB)
+#define LX2160A_DRAM2_SIZE   (SIZE_128GB)
+
+#define LX2160A_CCSR_PHYS_ADDRESS(BASE_16MB)
+#define LX2160A_CCSR_SIZE(SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LX2160A_FSPI0_PHYS_ADDRESS   (BASE_512MB)
+#define LX2160A_FSPI0_SIZE   (SIZE_256MB)
+
+#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
+
+#endif // SOC_H__
diff --git a/S

[edk2-devel] [PATCH edk2-platforms 1/8] Silicon/NXP: Use Metronome implementation from MdeModulePkg

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

There are two implementations of Metronome protocol.

EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf

Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg over
EmbeddedPkg.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/NxpQoriqLs.dsc.inc   | 4 +---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 03759c7cee7c..54236e19531c 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -218,8 +218,6 @@
   
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
 
 [PcdsFixedAtBuild.common]
-  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1 # expressed in 100ns units, 
100,000 x 100 ns = 10,000,000 ns = 10 ms
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
@@ -348,7 +346,7 @@
   MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/Metronome/Metronome.inf
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 931d0bb14f9b..fede51ced10e 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -115,7 +115,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/Metronome/Metronome.inf
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
 
   #
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 4/8] Silicon/NXP: Implement PL011UartClockLib for NXP platforms

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.

Signed-off-by: Pankaj Bansal 
---
 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf | 24 

 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c   | 22 
++
 2 files changed, 46 insertions(+)

diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
new file mode 100644
index ..b771dba7697f
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
@@ -0,0 +1,24 @@
+#/* @file
+#  Copyright 2018, 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PL011UartClockLib
+  FILE_GUID  = af8fef24-afbb-472a-b8b7-13101a79703c
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PL011UartClockLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[Sources.common]
+  PL011UartClockLib.c
+
+[LibraryClasses]
+  ArmPlatformLib
diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c 
b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
new file mode 100644
index ..3814685585eb
--- /dev/null
+++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
@@ -0,0 +1,22 @@
+/** @file
+*
+*  Copyright 2018, 2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+
+/**
+  Return clock in for PL011 Uart IP
+**/
+UINT32
+EFIAPI
+PL011UartClockGetFreq (
+  VOID
+  )
+{
+  return gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
+}
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 0/8] Add LX2160ARDB Platform

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

This Platform is based on Layerscape Chassis3V2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

Pankaj Bansal (8):
  Silicon/NXP: Use Metronome implementation from MdeModulePkg
  Platform/NXP: Use Monotonic counter from MdeModulePkg
  Silicon/NXP: Use edk2 recommended compilation flags
  Silicon/NXP: Implement PL011UartClockLib for NXP platforms
  Silicon/NXP: Add Chassis3V2 Package
  Silicon/NXP: Add LX2160A Soc package
  Platform/NXP: Add LX2160ARDB Platform
  Platform/NXP/LX2160aRdbPkg: Add VarStore

 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec  |  23 +++
 Silicon/NXP/Chassis3V2/Chassis3V2.dec |  22 +++
 Silicon/NXP/LX2160A/LX2160A.dec   |  13 ++
 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc |  10 ++
 Silicon/NXP/LX2160A/LX2160A.dsc.inc   |  50 ++
 Silicon/NXP/NxpQoriqLs.dsc.inc|  13 +-
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc  |  46 ++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf  |   4 +-
 .../LX2160aRdbPkg.fdf}|  33 ++--
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  41 +
 .../Library/ChassisLib/ChassisLib.inf |  33 
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf |  27 
 .../PL011UartClockLib/PL011UartClockLib.inf   |  24 +++
 Silicon/NXP/Chassis3V2/Include/Chassis.h  |  26 +++
 Silicon/NXP/LX2160A/Include/Soc.h |  38 +
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 150 ++
 .../ArmPlatformLib/ArmPlatformLibMem.c|  85 ++
 .../Library/ChassisLib/ChassisLib.c   |  71 +
 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c   |  80 ++
 .../PL011UartClockLib/PL011UartClockLib.c |  22 +++
 .../AArch64/ArmPlatformHelper.S   |  45 ++
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc   |  91 +++
 22 files changed, 920 insertions(+), 27 deletions(-)
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dec
 create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
 create mode 100644 Silicon/NXP/LX2160A/LX2160A.dsc.inc
 create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
 copy Platform/NXP/{LS1043aRdbPkg/LS1043aRdbPkg.fdf => 
LX2160aRdbPkg/LX2160aRdbPkg.fdf} (88%)
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
 create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
 create mode 100644 Silicon/NXP/LX2160A/Include/Soc.h
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
 create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c
 create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
 create mode 100644 
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc

-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms 8/8] Platform/NXP/LX2160aRdbPkg: Add VarStore

2020-05-19 Thread Pankaj Bansal

From: Pankaj Bansal 

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal 
---
 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf |  1 +
 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc  | 91 
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf 
b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
index 6bd5d86ab2bd..6f40fa9e566f 100644
--- a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -48,6 +48,7 @@ 
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc 
b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
new file mode 100644
index ..76c30580d773
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LX2160aRdbNv_EFI]
+BaseAddress   = 0x2050  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LX2160ARDB NVRAM Area
+# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x400
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = 
gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 
0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32#WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(F

[edk2-devel] [PATCH edk2-platforms v5 00/24] Add PEI phase to LS1043ARDB Platform

2020-05-13 Thread Pankaj Bansal

From: Pankaj Bansal 

This patch series adds PEI phase to NXP LS1043ARDB Platform.
V4 series can be referred here:
https://edk2.groups.io/g/devel/message/58367

I have taken care of the review comments received on V4.
I am only sending the patch in V5 that needed rework.
rest of the patches can be taken from V4

Pankaj Bansal (13):
  Silicon/NXP: Move RAM retrieval from SocLib
  Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs
  Silicon/NXP: Use Clock retrieval PPI in modules
  Silicon: NXP: Remove direct calls to SwapMmio* APIs
  Silicon/NXP: Add Chassis2 Package
  Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg
  Silicon/NXP/LS1043A: Move SocLib to Soc Package
  NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit
  NXP: LS1043aRdbPkg: Use ArmPlatformHelper.S from ArmPlatformPkg
  Platform/NXP: Use FV rules from ArmVirtPkg
  Platform/NXP/LS1043aRdbPkg: Add VarStore
  Silicon/NXP: move MemoryInitPeiLib as per PEIM structures
  Platform/NXP/LS1043aRdbPkg: Add PEI Phase

 Silicon/NXP/Chassis2/Chassis2.dec |  22 ++
 Silicon/NXP/NxpQoriqLs.dec|  15 +-
 Silicon/NXP/Chassis2/Chassis2.dsc.inc |  10 +
 Silicon/NXP/LS1043A/LS1043A.dsc.inc   |  11 +-
 Silicon/NXP/NxpQoriqLs.dsc.inc|  67 +++--
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc  |  11 -
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf  |  21 +-
 .../Drivers/PlatformDxe/PlatformDxe.inf   |   1 +
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |   2 +
 .../Library/ChassisLib/ChassisLib.inf |  33 +++
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf |   2 +-
 .../Library/SocLib/SocLib.inf}|  20 +-
 .../NXP/Library/DUartPortLib/DUartPortLib.inf |   5 +-
 .../MemoryInitPeiLib.inf  |  10 +-
 Silicon/NXP/Chassis2/Include/Chassis.h|  36 +++
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h   |   6 -
 Silicon/NXP/Include/Chassis2/NxpSoc.h |  53 
 Silicon/NXP/Include/DramInfo.h|  38 ---
 Silicon/NXP/Include/Library/ChassisLib.h  |  51 
 Silicon/NXP/Include/Library/IoAccessLib.h | 236 +--
 Silicon/NXP/Include/Library/SocLib.h  |  52 
 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h |  52 
 Silicon/NXP/LS1043A/Include/Soc.h |  11 +
 Silicon/NXP/Library/DUartPortLib/DUart.h  |   8 +-
 .../MemoryInitPeiLib/MemoryInitPeiLib.h   |  40 +++
 Silicon/NXP/Library/SocLib/NxpChassis.h   |  22 --
 .../Library/ArmPlatformLib/ArmPlatformLib.c   |  59 +++-
 .../Chassis2/Library/ChassisLib/ChassisLib.c  |  98 +++
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c   |   3 +-
 Silicon/NXP/LS1043A/Library/SocLib/SocLib.c   |  77 +
 .../NXP/Library/DUartPortLib/DUartPortLib.c   |   7 +-
 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c |  17 +-
 .../Library/MemoryInitPei/MemoryInitPeiLib.c  | 140 -
 .../MemoryInitPeiLib/MemoryInitPeiLib.c   | 276 ++
 Silicon/NXP/Library/SocLib/Chassis.c  | 143 -
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c |  69 -
 Platform/NXP/FVRules.fdf.inc  |  59 ++--
 .../AArch64/ArmPlatformHelper.S   |  60 ++--
 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc   |  91 ++
 39 files changed, 1087 insertions(+), 847 deletions(-)
 create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
 create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
 create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
 rename Silicon/NXP/{Library/SocLib/LS1043aSocLib.inf => 
LS1043A/Library/SocLib/SocLib.inf} (56%)
 rename Silicon/NXP/Library/{MemoryInitPei => 
MemoryInitPeiLib}/MemoryInitPeiLib.inf (74%)
 create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
 delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
 delete mode 100644 Silicon/NXP/Include/DramInfo.h
 create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
 create mode 100644 Silicon/NXP/Include/Library/SocLib.h
 create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
 create mode 100644 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
 delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
 create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
 create mode 100644 Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
 delete mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
 create mode 100644 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
 delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
 delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
 create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc

-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v5 12/24] Silicon/NXP: Move RAM retrieval from SocLib

2020-05-13 Thread Pankaj Bansal

From: Pankaj Bansal 

RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to common MemoryInit Pei Lib.

Signed-off-by: Pankaj Bansal 
---

Notes:
V5:
- Add SMC_DRAM_TOTAL_DRAM_ARG1 to denote the x1 argument to pass to
  SMC call to retrieve the total DRAM size
- cast away the return from GetDramRegionsInfo using 
(VOID)GetDramRegionsInfo
- remove unused variable Status from MemoryPeim.

V4:
- fixed line adds white space error in MemoryInitPeiLib.h
- Added SMC_OK and SMC_UOK Macros to denote the return values from
  SMC calls
- Added explanation for SMC_DRAM_BANK_INFO and DRAM_REGION_INFO in
  MemoryInitPeiLib.h
- Modified GetDramSize to check for return value of SMC call against
  SMC_OK. Also added comments when returning 0 from this function
- Modified GetDramRegionsInfo for loop and return values as per Leif's
  suggestion. Also added DEBUG_ERROR in case of return BUFFER_TOO_SMALL.
- Added SMC_OK in GetDramRegionsInfo
- Check for GetDramRegionsInfo return value in MemoryPeim
- regios -> regions

V3:
- sort headers alphabetically
- Moved DRAM region retrieval and Total DRAM size retrieval to separate
  functions
- Fixed MemoryPeim function description
- Modified check on FoundSystemMem = TRUE to check the RAM region against
  MemoryPeim function input arguments UefiMemoryBase and UefiMemorySize
- (!DramRegions[Index].Size) => (DramRegions[Index].Size == 0)
- (FoundSystemMem) => (FoundSystemMem == TRUE)
- Added explanation for starting for loop from the last DRAM region

 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf |   7 +-
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf   |   1 -
 Silicon/NXP/Include/DramInfo.h |  38 
 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h   |  40 
 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c   | 203 

 Silicon/NXP/Library/SocLib/Chassis.c   |  67 ---
 6 files changed, 211 insertions(+), 145 deletions(-)

diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf 
b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
index a5bd39415def..ad2371115b17 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -18,7 +18,6 @@
 [Sources]
   MemoryInitPeiLib.c
 
-
 [Packages]
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
@@ -30,6 +29,7 @@
 [LibraryClasses]
   ArmMmuLib
   ArmPlatformLib
+  ArmSmcLib
   DebugLib
   HobLib
   PcdLib
@@ -40,6 +40,11 @@
 [FeaturePcd]
   gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
 
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+  gArmTokenSpaceGuid.PcdFdSize
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
 [Pcd]
   gArmTokenSpaceGuid.PcdSystemMemoryBase
   gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf 
b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index b7c7fc78cc8f..99d89498e0e2 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -20,7 +20,6 @@
   Silicon/NXP/NxpQoriqLs.dec
 
 [LibraryClasses]
-  ArmSmcLib
   BaseLib
   DebugLib
   IoAccessLib
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
deleted file mode 100644
index a934aaeff1f5..
--- a/Silicon/NXP/Include/DramInfo.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @file
-*  Header defining the structure for Dram Information
-*
-*  Copyright 2019 NXP
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DRAM_INFO_H_
-#define DRAM_INFO_H_
-
-#include 
-
-#define SMC_DRAM_BANK_INFO  (0xC200FF12)
-
-typedef struct {
-  UINTNBaseAddress;
-  UINTNSize;
-} DRAM_REGION_INFO;
-
-typedef struct {
-  UINT32NumOfDrams;
-  UINT32Reserved;
-  DRAM_REGION_INFO  DramRegion[3];
-} DRAM_INFO;
-
-EFI_STATUS
-GetDramBankInfo (
-  IN OUT DRAM_INFO *DramInfo
-  );
-
-VOID
-UpdateDpaaDram (
-  IN OUT DRAM_INFO *DramInfo
-  );
-
-#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h 
b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
new file mode 100644
index ..520277d45c95
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
@@ -0,0 +1,40 @@
+/** @file
+*
+*  Copyright 2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef MEMORY_INIT_PEI_LIB_H_
+#define MEMORY_INIT_PEI_LIB_H_
+
+#include 
+
+// Specifies the Maximum regions onto which DDR memory can be mapped in
+// a Platform
+#define MAX_DRAM_REGIONS3
+
+// Unique SMC call to retrieve the total DDR RAM size installed in system
+// and the SOC  memory map regions to which DDR RAM is mapped
+// This SMC call works in this way:
+// x1 = -1 : return x0: SMC_OK, x1: tota

Re: [edk2-devel] [PATCH edk2-platforms v4 12/24] Silicon/NXP: Move RAM retrieval from SocLib

2020-05-07 Thread Pankaj Bansal

> 
> On Thu, May 07, 2020 at 07:28:30 +, Pankaj Bansal (OSS) wrote:
> > Hi Leif,
> >
> > > > +  ARM_SMC_ARGS  ArmSmcArgs;
> > > >
> > > > -Routine Description:
> > > > +  ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> > > > +  ArmSmcArgs.Arg1 = -1;
> > >
> > > Should this be SMC_UNK?
> >
> > No. SMC_OK / SMC_UNK is returned values.
> > While x0, x1 are arguments.
> > I have explained this in the MemoryInitPeiLib.h
> 
> OK, then that -1 needs a separate #define.

OK. That I will take care.

> 
> > // This SMC call works in this way:
> > // x1 = -1 : return x0: SMC_OK, x1: total DDR Ram size
> > // x1 >= number of DRAM regions to which DDR RAM is mapped : return x0:
> SMC_UNK
> > // 0 <= x1 < number of DRAM regions to which DDR RAM is mapped : return
> > //   x0: SMC_OK, x1: Base address of DRAM region,
> > //   x2: Size of DRAM region
> >
> > >
> > > >
> > > > +  ArmCallSmc ();
> > > >
> > > > +  if (ArmSmcArgs.Arg0 == SMC_OK) {
> > > > +return ArmSmcArgs.Arg1;
> > > > +  }
> > > >
> >
> > 
> >
> > > > -  {
> > > > -Found = TRUE;
> > > > -break;
> > > > -  }
> > > > -  NextHob.Raw = GET_NEXT_HOB (NextHob);
> > > > +  Status = GetDramRegionsInfo (DramRegions, ARRAY_SIZE
> (DramRegions));
> > > > +  ASSERT_EFI_ERROR (Status);
> > >
> > > Slightly concerned here because we end up with a variable Status that
> > > is only *used* in DEBUG builds. That could lead to toolchain warnings.
> >
> > I don't think this would cause build warnings in RELEASE builds. I have 
> > tested it.
> > Also the Status is frequently being handled in this way in other places in 
> > edk2:
> >
> >
> https://github.com/tianocore/edk2/blob/master/ArmPlatformPkg/PlatformPei/
> PlatformPeim.c#L90
> 
> The example you point to sets Status, overwrites it (once or twice
> depending on conditionals), then returns it.
> This patch in its current form sets Status, accesses it only in DEBUG
> builds and does not return it.

Ok. Then I can return status at the end of this function (MemoryPeim).
I still can't bring myself to just ignore the critical error status from a 
function.

> 
> > > And I was completely serious last time around, I am OK with the return
> > > value being cast away explicitly. What I meant with that is:
> > >   (VOID)GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions));
> >
> > I agreed with your suggestion to return EFI_BUFFER_TOO_SMALL from
> GetDramRegionsInfo,
> > But If we discard the return value it means we are OK with some RAM not
> being reported to UEFI firmware
> > and subsequently to OS. Isn't this a critical error ?
> 
> ASSERTs are only triggered in DEBUG builds, and send the processor
> into WFI.
> 
> If it is a critical error (is it critical if you have found some RAM,
> but been unable to fully reconcile all of the RAM in the system?), it
> should do more than that.
> 
> I am all for properly handling that situation, but this patch has
> never done that. Feel free to rework before submitting v5, or leave it
> until (if) adding ACPI support and report the condition properly
> through BERT.

I have referred reference platform lib 
https://github.com/tianocore/edk2/blob/master/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoPeiLibConstructor.c#L83
As per this lib, I have added ASSERTS in all the scenarios, which are critical.
I thought ASSERT means we will halt the program execution regardless of DEBUG 
or RELEASE build.
Can you point me to a reference platform which handles these errors using ACPI 
BERT methods ?
I see that in DebugLib.h : 

  Note that a reserved macro named MDEPKG_NDEBUG is introduced for the intention
  of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is
  defined, then debug and assert related macros wrapped by it are the NULL 
implementations.

We have NOT defined MDEPKG_NDEBUG in our platforms for RELEASE or DEBUG builds.
Up until we have not implemented the ACPI BERT methods, can we keep it this way 
to avoid masking the errors?

> 
> /
> Leif

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Re: [edk2-devel] [PATCH edk2-platforms v4 12/24] Silicon/NXP: Move RAM retrieval from SocLib

2020-05-07 Thread Pankaj Bansal

Hi Leif,

> > +  ARM_SMC_ARGS  ArmSmcArgs;
> >
> > -Routine Description:
> > +  ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> > +  ArmSmcArgs.Arg1 = -1;
> 
> Should this be SMC_UNK?

No. SMC_OK / SMC_UNK is returned values.
While x0, x1 are arguments.
I have explained this in the MemoryInitPeiLib.h

// This SMC call works in this way:
// x1 = -1 : return x0: SMC_OK, x1: total DDR Ram size
// x1 >= number of DRAM regions to which DDR RAM is mapped : return x0: SMC_UNK
// 0 <= x1 < number of DRAM regions to which DDR RAM is mapped : return
//   x0: SMC_OK, x1: Base address of DRAM region,
//   x2: Size of DRAM region

> 
> >
> > +  ArmCallSmc ();
> >
> > +  if (ArmSmcArgs.Arg0 == SMC_OK) {
> > +return ArmSmcArgs.Arg1;
> > +  }
> >



> > -  {
> > -Found = TRUE;
> > -break;
> > -  }
> > -  NextHob.Raw = GET_NEXT_HOB (NextHob);
> > +  Status = GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions));
> > +  ASSERT_EFI_ERROR (Status);
> 
> Slightly concerned here because we end up with a variable Status that
> is only *used* in DEBUG builds. That could lead to toolchain warnings.

I don't think this would cause build warnings in RELEASE builds. I have tested 
it.
Also the Status is frequently being handled in this way in other places in edk2:

https://github.com/tianocore/edk2/blob/master/ArmPlatformPkg/PlatformPei/PlatformPeim.c#L90

> 
> And I was completely serious last time around, I am OK with the return
> value being cast away explicitly. What I meant with that is:
>   (VOID)GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions));
> 

I agreed with your suggestion to return EFI_BUFFER_TOO_SMALL from 
GetDramRegionsInfo,
But If we discard the return value it means we are OK with some RAM not being 
reported to UEFI firmware
and subsequently to OS. Isn't this a critical error ?

> /
> Leif
> 
> > +
> > +  FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> > +  FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> > +
> > +  // Declare memory regions to system

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[edk2-devel] [PATCH edk2-platforms v4 11/24] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

Keep the names and location of files as mentioned in ArmPlatformPkg.
This helps in porting the common changes (if any in future) easily.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc   
   | 2 +-
 Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => 
ArmPlatformLib}/ArmPlatformLib.inf | 4 ++--
 Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => 
ArmPlatformLib}/ArmPlatformLib.c   | 2 +-
 Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => 
ArmPlatformLib/ArmPlatformLibMem.c}| 0
 Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsHelper.S => 
ArmPlatformLib/AArch64/ArmPlatformHelper.S} | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 1975f2c4c52c..e5383aaf0cc5 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -26,7 +26,7 @@
 !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
 
 [LibraryClasses.common]
-  
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+  
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
   RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
 
 [PcdsFixedAtBuild.common]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
similarity index 89%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7563a1c43630..7a43ad86d183 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -27,8 +27,8 @@
   SocLib
 
 [Sources.common]
-  NxpQoriqLsHelper.S| GCC
-  NxpQoriqLsMem.c
+  AArch64/ArmPlatformHelper.S| GCC
+  ArmPlatformLibMem.c
   ArmPlatformLib.c
 
 [Ppis]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
similarity index 93%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index eac7d4aa4e47..718c71bf02eb 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -6,7 +6,7 @@
 *
 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
 *  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-*  Copyright 2017 NXP
+*  Copyright 2017, 2020 NXP
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
similarity index 100%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
similarity index 88%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
rename to 
Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
index 84ee8c9f9700..dfbf73675a2d 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
+++ 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -1,7 +1,7 @@
 #  @file
 #
 #  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-#  Copyright 2017 NXP
+#  Copyright 2017, 2020 NXP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 08/24] Silicon/NXP: remove not needed components

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

The structures elements and functions that are not necessary for booting
for now are being deleted.
Once the directory structure has been changed (i.e. we have clear
distinction between chassis code and header files and SOC code and header
files), we will put back the code and
structure components back at their appropriate respective place.

Also right now all the elements are being defined in structures, which are
not being used right now. So to simplify the code restructuring, I have
removed those for now. When we need to use those elements, we can define
those one by one.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- remove CpuMaskNext from this patch and put in previous patch

 Silicon/NXP/NxpQoriqLs.dec   |  27 --
 Silicon/NXP/LS1043A/LS1043A.dsc.inc  |   6 -
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc |   4 -
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf |   7 +-
 Silicon/NXP/Include/Chassis2/LsSerDes.h  |  62 
 Silicon/NXP/Include/Chassis2/NxpSoc.h| 314 +---
 Silicon/NXP/LS1043A/Include/SocSerDes.h  |  51 
 Silicon/NXP/Library/SocLib/NxpChassis.h  |  90 --
 Silicon/NXP/Library/SocLib/Chassis.c | 208 -
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c|  79 -
 Silicon/NXP/Library/SocLib/SerDes.c  | 268 -
 11 files changed, 3 insertions(+), 1113 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 1aff519bfaf4..bc604e586283 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -32,10 +32,7 @@
   # Pcds for base address and size
   #
   gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x0100
-  gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x0101
-  gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x0102
   gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x0103
-  gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x0104
   gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x0105
   gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x0106
   gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x0107
@@ -61,10 +58,6 @@
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x011B
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x011C
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x011D
-  gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x011E
-  gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x011F
-  gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x0120
-  gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x0121
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x0122
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x0123
 
@@ -75,36 +68,16 @@
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x0191
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x0192
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x0193
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x0194
-  gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x0195
-  gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x0196
-
-  #
-  # NV Pcd
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x0210
-  gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x0211
 
   #
   # Platform PCDs
   #
   gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x0250
-  gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x0251
-
-  #
-  # Clock PCDs
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x02A0
-  gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x02A1
 
   #
   # Pcds to support Big Endian IPs
   #
-  gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x310
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x311
-  gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x0312
-  gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x0313
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x0314
 
 [PcdsFeatureFlag]
   gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x0315
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc 
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index d2d4133428c3..f6ada08dad9d 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -31,12 +31,10 @@
   #
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0100
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F00
-  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x6000
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x2000
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x062000
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E000

[edk2-devel] [PATCH edk2-platforms v4 16/24] Silicon/NXP: Add Chassis2 Package

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

A Chassis is a base framework used for building SoCs.
We can think of Chassis/Soc/Platform(a.k.a Board) in Object model terms.
Chassis is base. Soc is based on some Chassis.
Platform is based on some Soc.

SOCs that are designed around same chassis, reuse most of the components.

Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong
to Chassis2.

Signed-off-by: Pankaj Bansal 
---

Notes:
V4:
- Fixed line adds whitespace error
- Added Uefi.h in Chassis.h
- Fixed Typo Borad -> Board in commit description
- Fixed license in ChassisLib.inf
- Added lines between Copyright and license in ChassisLib.c

V3:
- in patch description Oops -> Object model
- Sorted includes alphabetically
- removed direct calls to SwapMmio** APIs and used GetMmioOperations**

 Silicon/NXP/Chassis2/Chassis2.dec  | 22 +
 Silicon/NXP/NxpQoriqLs.dec |  4 +
 Silicon/NXP/Chassis2/Chassis2.dsc.inc  | 10 ++
 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 33 +++
 Silicon/NXP/Chassis2/Include/Chassis.h | 36 +++
 Silicon/NXP/Include/Library/ChassisLib.h   | 51 ++
 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c   | 98 

 7 files changed, 254 insertions(+)

diff --git a/Silicon/NXP/Chassis2/Chassis2.dec 
b/Silicon/NXP/Chassis2/Chassis2.dec
new file mode 100644
index ..d3674cd6dff9
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dec
@@ -0,0 +1,22 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 1.27
+  PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index e61592b4fe61..b327e52da139 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -14,6 +14,9 @@
   Include
 
 [LibraryClasses]
+  ##  @libraryclass  Provides Chassis specific functions to other modules
+  ChassisLib|Include/Library/ChassisLib.h
+
   ##  @libraryclass  Provides services to read/write to I2c devices
   I2cLib|Include/Library/I2cLib.h
 
@@ -29,3 +32,4 @@
 
 [PcdsFeatureFlag]
   gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x0315
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x0316
diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc 
b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
new file mode 100644
index ..db8e5a92eacb
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
@@ -0,0 +1,10 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+  ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf 
b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index ..f5dbd1349dc5
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,33 @@
+#  @file
+#
+#  Copyright 2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION= 1.27
+  BASE_NAME  = Chassis2Lib
+  FILE_GUID  = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ChassisLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  IoAccessLib
+  IoLib
+  PcdLib
+  SerialPortLib
+
+[Sources.common]
+  ChassisLib.c
+
+[FeaturePcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h 
b/Silicon/NXP/Chassis2/Include/Chassis.h
new file mode 100644
index ..14e21ef9daf4
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -0,0 +1,36 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#include 
+
+#define  NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS  0x1EE
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x0900
+#define SMMU_REG_SCR0  (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR  (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+
+#define SCR0_USFCFG_MASK   0x0400
+#define SCR0_CLIENTPD_MASK 0x0001
+#

[edk2-devel] [PATCH edk2-platforms v4 18/24] Silicon/NXP/LS1043A: Move SocLib to Soc Package

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

The SocLib contains code specific to an Soc. it should be part of
SOC package.
Therefore, move the SocLib to Soc Package.
Since we are moving the files to Soc Package, no need to mention the
Soc name in file names. Their location is enough to indicate for which
Soc the files are.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

 Silicon/NXP/LS1043A/LS1043A.dsc.inc
 | 2 +-
 Silicon/NXP/{Library/SocLib/LS1043aSocLib.inf => 
LS1043A/Library/SocLib/SocLib.inf} | 2 +-
 Silicon/NXP/{Library/SocLib/Chassis2/Soc.c => LS1043A/Library/SocLib/SocLib.c} 
 | 0
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc 
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index ea0854f967a3..67f5ba68dcd5 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -10,7 +10,7 @@
 !include Silicon/NXP/Chassis2/Chassis2.dsc.inc
 
 [LibraryClasses.common]
-  SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+  SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
   SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
 
 

diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf 
b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
similarity index 92%
rename from Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
index 1d042bbfc4e4..3d0f988e1c67 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
@@ -24,4 +24,4 @@
   DebugLib
 
 [Sources.common]
-  Chassis2/Soc.c
+  SocLib.c
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c 
b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
similarity index 100%
rename from Silicon/NXP/Library/SocLib/Chassis2/Soc.c
rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 07/24] Silicon/NXP: remove print information from Soc lib

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

The Soc info being printed can be removed from SOC lib.
We are in the process of implementing PEI Phase.
After PEI phase implementation this info would be printed in
common PEIM based on the information retrieved from PPIs.
e.g. gArmMpCoreInfoPpiGuid can be used to print cluster and
core info.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- cluser -> cluster

V3:
- remove CpuMaskNext from this patch and put in previous patch

 Silicon/NXP/Library/SocLib/NxpChassis.h   |  26 +---
 Silicon/NXP/Library/SocLib/Chassis.c  | 144 
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c |  16 +--
 3 files changed, 2 insertions(+), 184 deletions(-)

diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h 
b/Silicon/NXP/Library/SocLib/NxpChassis.h
index 99f6439d8f35..a11acf71563e 100644
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -1,7 +1,7 @@
 /** @file
 *  Header defining the Base addresses, sizes, flags etc for chassis 1
 *
-*  Copyright 2017-2019 NXP
+*  Copyright 2017-2020 NXP
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -54,14 +54,6 @@ typedef struct {
   UINTN SdhcClk;
 } SOC_CLOCK_INFO;
 
-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
-  VOID
-  );
-
 /*
  * Initialize Clock structure
  */
@@ -79,22 +71,6 @@ SmmuInit (
   VOID
   );
 
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
-  VOID
-  );
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
-  VOID
-  );
-
 UINT32
 InitiatorType (
   IN UINT32 Cluster,
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c 
b/Silicon/NXP/Library/SocLib/Chassis.c
index b8a8118c5e24..adca7b8dd413 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -204,79 +204,6 @@ QoriqCoreToType (
   return EFI_NOT_FOUND;  /* cannot identify the cluster */
 }
 
-STATIC
-UINTN
-CpuMaskNext (
-  IN  UINTN  Cpu,
-  IN  UINTN  Mask
-  )
-{
-  for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
-
-  return Cpu;
-}
-
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
-  VOID
-  )
-{
-  SYS_INFO SysInfo;
-  UINTNCoreIndex;
-  UINTNCore;
-  UINT32   Type;
-  UINT32   NumCpus;
-  UINT32   Mask;
-  CHAR8*CoreName;
-
-  GetSysInfo ();
-  DEBUG ((DEBUG_INIT, "Clock Configuration:"));
-
-  NumCpus = CpuNumCores ();
-  Mask = CpuMask ();
-
-  for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
-   CoreIndex < NumCpus;
-   CoreIndex++, Core = CpuMaskNext(Core, Mask))
-  {
-if (!(CoreIndex % 3)) {
-  DEBUG ((DEBUG_INIT, "\n  "));
-}
-
-Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
-switch (Type) {
-  case TY_ITYP_VERSION_A7:
-CoreName = "A7";
-break;
-  case TY_ITYP_VERSION_A53:
-CoreName = "A53";
-break;
-  case TY_ITYP_VERSION_A57:
-CoreName = "A57";
-break;
-  case TY_ITYP_VERSION_A72:
-CoreName = "A72";
-break;
-  default:
-CoreName = " Unknown Core ";
-}
-DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz  ",
-  Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
-  }
-
-  DEBUG ((DEBUG_INIT, "\n  Bus:  %-4d MHz  ", SysInfo.FreqSystemBus / 
MHZ));
-  DEBUG ((DEBUG_INIT, "DDR:  %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
-
-  if (SysInfo.FreqFman[0] != 0) {
-DEBUG ((DEBUG_INIT, "\n  FMAN: %-4d MHz  ",  SysInfo.FreqFman[0] / 
MHZ));
-  }
-
-  DEBUG ((DEBUG_INIT, "\n"));
-}
-
 /*
  * Return system bus frequency
  */
@@ -307,77 +234,6 @@ GetSdxcFrequency (
   return SocSysInfo.FreqSdhc;
 }
 
-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
-  VOID
-  )
-{
-  CHAR8Buf[20];
-  CCSR_GUR *GurBase;
-  UINTNCount;
-  //
-  // Svr : System Version Register
-  //
-  UINTNSvr;
-  UINTNVer;
-
-  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
-  Svr = GurRead ((UINTN)>Svr);
-  Ver = SVR_SOC_VER (Svr);
-
-  for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
-if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
-  AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
-
-  if (IS_E_PROCESSOR (Svr)) {
-AsciiStrCatS (Buf, sizeof (Buf), "E");
-  }
-  break;
-}
-  }
-
-  DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
-  Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
-
-  return;
-}
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
-  VOID
-  )
-{
-  CCSR_GUR *Base;
-  UINTNCount;
-
-  Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
-  /*
-   * Display the RCW, so that no one gets confused as to what RCW
-   * we're actually using for this boot.
-   */
-
-  DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
-  for (Count = 0; Count < ARRAY_SIZE (Base->R

[edk2-devel] [PATCH edk2-platforms v4 19/24] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

SocInit can be defined in SocLib.h
No need to make it extern in ArmPlatformLib

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- Moved commit three commits before in series

 Silicon/NXP/Include/Library/SocLib.h   | 8 
 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 2 --
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/Include/Library/SocLib.h 
b/Silicon/NXP/Include/Library/SocLib.h
index fc4d786c710b..7b25107e4746 100644
--- a/Silicon/NXP/Include/Library/SocLib.h
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -41,4 +41,12 @@ SocGetClock (
   IN  VA_LIST   Args
   );
 
+/**
+  Function to initialize SoC specific constructs
+ **/
+VOID
+SocInit (
+  VOID
+  );
+
 #endif // SOC_LIB_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 7f5872a78cfc..a554d1377484 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -16,8 +16,6 @@
 #include 
 #include 
 
-extern VOID SocInit (VOID);
-
 /**
   Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 06/24] NXP/LS1043aRdb: Move Soc specific components to soc files

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

Soc specific components ought to be part of Soc files and not
platform files. move the same to SOC files

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

 Platform/NXP/NxpQoriqLs.dsc.inc  | 2 ++
 Silicon/NXP/LS1043A/LS1043A.dsc.inc  | 7 ++-
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 7 +--
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 25c0a41e5d4a..8fbd6288cfae 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -95,6 +95,8 @@
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
 
   I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
+  
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+  IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
 
 [LibraryClasses.common.SEC]
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc 
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index dbd680b0ad28..d2d4133428c3 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -1,12 +1,16 @@
 #  LS1043A.dsc
 #  LS1043A Soc package.
 #
-#  Copyright 2017-2019 NXP
+#  Copyright 2017-2020 NXP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #
 
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
 

 #
 # Pcd Section - list of all EDK II PCD Entries defined by this Platform
@@ -20,6 +24,7 @@
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
 
 [PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
 
   #
   # CCSR Address Space and other attached Memories
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index c8105593533f..802cccdce63b 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -2,7 +2,7 @@
 #
 #  LS1043ARDB Board package.
 #
-#  Copyright 2017-2019 NXP
+#  Copyright 2017-2020 NXP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -26,11 +26,7 @@
 !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
 
 [LibraryClasses.common]
-  SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
   
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
-  
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
-  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
-  IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
   RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
 
 [PcdsFixedAtBuild.common]
@@ -46,7 +42,6 @@
   #
   # Board Specific Pcds
   #
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
   gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
   gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
 
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 21/24] Platform/NXP: Use FV rules from ArmVirtPkg

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

FVRules.fdf.inc is being replaced by the ArmVirtPkg/ArmVirtRules.fdf.inc
at commit hash 746c5b6238f1ee55deb4b3ec32a6d732e27eeeaa

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- Modify commit description

 Platform/NXP/FVRules.fdf.inc | 59 +---
 1 file changed, 38 insertions(+), 21 deletions(-)

diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
index c9fba65dae85..63de26abe056 100644
--- a/Platform/NXP/FVRules.fdf.inc
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -1,8 +1,7 @@
-#  FvRules.fdf.inc
 #
-#  Rules for creating FD.
-#
-#  Copyright 2017-2019 NXP
+#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+#  Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
+#  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -16,40 +15,49 @@
 #
 

 
+
+
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#DXE_DEPEXDXE_DEPEX   Optional 
$(INF_OUTPUT)/$(MODULE_NAME).depex
+#COMPRESS PI_STD {
+#  GUIDED {
+#PE32 PE32$(INF_OUTPUT)/$(MODULE_NAME).efi
+#UI   STRING="$(MODULE_NAME)" Optional
+#VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#  }
+#}
+#  }
+#
+
+
 [Rule.Common.SEC]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-TE  TEAlign = 32$(INF_OUTPUT)/$(MODULE_NAME).efi
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+TE  TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
   }
 
 [Rule.Common.PEI_CORE]
-  FILE PEI_CORE = $(NAMED_GUID) {
-TE TE   $(INF_OUTPUT)/$(MODULE_NAME).efi
+  FILE PEI_CORE = $(NAMED_GUID) FIXED {
+TE TE Align = Auto  $(INF_OUTPUT)/$(MODULE_NAME).efi
 UI STRING ="$(MODULE_NAME)" Optional
   }
 
 [Rule.Common.PEIM]
-  FILE PEIM = $(NAMED_GUID) {
+  FILE PEIM = $(NAMED_GUID) FIXED {
  PEI_DEPEX PEI_DEPEX Optional   $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32  PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE   TE Align = Auto   $(INF_OUTPUT)/$(MODULE_NAME).efi
  UI   STRING="$(MODULE_NAME)" Optional
   }
 
-[Rule.Common.PEIM.TIANOCOMPRESSED]
-  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
-PEI_DEPEX PEI_DEPEX Optional$(INF_OUTPUT)/$(MODULE_NAME).depex
-GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
-  PE32  PE32$(INF_OUTPUT)/$(MODULE_NAME).efi
-  UISTRING="$(MODULE_NAME)" Optional
-}
-  }
-
 [Rule.Common.DXE_CORE]
   FILE DXE_CORE = $(NAMED_GUID) {
 PE32 PE32   $(INF_OUTPUT)/$(MODULE_NAME).efi
 UI   STRING="$(MODULE_NAME)" Optional
   }
 
-
 [Rule.Common.UEFI_DRIVER]
   FILE DRIVER = $(NAMED_GUID) {
 DXE_DEPEXDXE_DEPEX  Optional 
$(INF_OUTPUT)/$(MODULE_NAME).depex
@@ -62,6 +70,8 @@
 DXE_DEPEXDXE_DEPEX  Optional 
$(INF_OUTPUT)/$(MODULE_NAME).depex
 PE32 PE32   $(INF_OUTPUT)/$(MODULE_NAME).efi
 UI   STRING="$(MODULE_NAME)" Optional
+RAW  ACPI  Optional   |.acpi
+RAW  ASL   Optional   |.aml
   }
 
 [Rule.Common.DXE_RUNTIME_DRIVER]
@@ -73,7 +83,7 @@
 
 [Rule.Common.UEFI_APPLICATION]
   FILE APPLICATION = $(NAMED_GUID) {
-UI STRING ="$(MODULE_NAME)" Optional
+UI STRING ="$(MODULE_NAME)" Optional
 PE32   PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
   }
 
@@ -91,3 +101,10 @@
 UISTRING="$(MODULE_NAME)" Optional
 VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
   }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+RAW   ACPI|.acpi
+RAW   ASL |.aml
+UISTRING="$(MODULE_NAME)" Optional
+  }
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 10/24] Silicon/NXP: Move dsc file

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

As per convention being followed in edk2-platforms, keep the dec
file and dsc file together.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

 {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
similarity index 100%
rename from Platform/NXP/NxpQoriqLs.dsc.inc
rename to Silicon/NXP/NxpQoriqLs.dsc.inc
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 385b6e067e26..1975f2c4c52c 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -22,7 +22,7 @@
   OUTPUT_DIRECTORY   = Build/LS1043aRdbPkg
   FLASH_DEFINITION   = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
 
-!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
 !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
 
 [LibraryClasses.common]
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 15/24] Silicon: NXP: Remove direct calls to SwapMmio* APIs

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

The SwapMmio** APIs are supposed to be called indirectly via
GetMmioOperations** APIs.
Therefore, remove the SwapMmio** APIs from IoAccessLib.h and make
these APIs STATIC to IoAccessLib.c, so that no accidental call can
be made to these.

Signed-off-by: Pankaj Bansal 
---

Notes:
V4:
- Use GetMmioOperations in place of GetMmioOperations32
- Use MMIO_OPERATIONS in place of MMIO_OPERATIONS_32

V3:
- New commit

 Silicon/NXP/Include/Library/IoAccessLib.h | 236 +---
 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c |  17 +-
 Silicon/NXP/Library/SocLib/Chassis.c  |  10 +-
 3 files changed, 22 insertions(+), 241 deletions(-)

diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h 
b/Silicon/NXP/Include/Library/IoAccessLib.h
index 0f5b19dcf149..3dbb35d2ce5a 100644
--- a/Silicon/NXP/Include/Library/IoAccessLib.h
+++ b/Silicon/NXP/Include/Library/IoAccessLib.h
@@ -1,6 +1,6 @@
 /** @file
  *
- *  Copyright 2017-2019 NXP
+ *  Copyright 2017-2020 NXP
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  *
@@ -47,238 +47,4 @@ GetMmioOperations  (
   IN  BOOLEAN  Swap
   );
 
-/**
-  MmioRead16 for Big-Endian modules.
-
-  @param  Address The MMIO register to read.
-
-  @return The value read.
-
-**/
-UINT16
-EFIAPI
-SwapMmioRead16 (
-  IN  UINTN Address
-  );
-
-/**
-  MmioRead32 for Big-Endian modules.
-
-  @param  Address The MMIO register to read.
-
-  @return The value read.
-
-**/
-UINT32
-EFIAPI
-SwapMmioRead32 (
-  IN  UINTN Address
-  );
-
-/**
-  MmioRead64 for Big-Endian modules.
-
-  @param  Address The MMIO register to read.
-
-  @return The value read.
-
-**/
-UINT64
-EFIAPI
-SwapMmioRead64 (
-  IN  UINTN Address
-  );
-
-/**
-  MmioWrite16 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  Value   The value to write to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-SwapMmioWrite16 (
-  IN  UINTN Address,
-  IN  UINT16Value
-  );
-
-/**
-  MmioWrite32 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  Value   The value to write to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-SwapMmioWrite32 (
-  IN  UINTN Address,
-  IN  UINT32Value
-  );
-
-/**
-  MmioWrite64 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  Value   The value to write to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-SwapMmioWrite64 (
-  IN  UINTN Address,
-  IN  UINT64Value
-  );
-
-/**
-  MmioAndThenOr16 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  AndData The value to AND with the read value from the MMIO register.
-  @param  OrData  The value to OR with the result of the AND operation.
-
-  @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-SwapMmioAndThenOr16 (
-  IN  UINTN Address,
-  IN  UINT16AndData,
-  IN  UINT16OrData
-  );
-
-/**
-  MmioAndThenOr32 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  AndData The value to AND with the read value from the MMIO register.
-  @param  OrData  The value to OR with the result of the AND operation.
-
-  @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-SwapMmioAndThenOr32 (
-  IN  UINTN Address,
-  IN  UINT32AndData,
-  IN  UINT32OrData
-  );
-
-/**
-  MmioAndThenOr64 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  AndData The value to AND with the read value from the MMIO register.
-  @param  OrData  The value to OR with the result of the AND operation.
-
-  @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-SwapMmioAndThenOr64 (
-  IN  UINTN Address,
-  IN  UINT64AndData,
-  IN  UINT64OrData
-  );
-
-/**
-  MmioOr16 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  OrData  The value to OR with the read value from the MMIO register.
-
-  @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-SwapMmioOr16 (
-  IN  UINTN Address,
-  IN  UINT16OrData
-  );
-
-/**
-  MmioOr32 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  OrData  The value to OR with the read value from the MMIO register.
-
-  @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-SwapMmioOr32 (
-  IN  UINTN Address,
-  IN  UINT32OrData
-  );
-
-/**
-  MmioOr64 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  OrData  The value to OR with the read value from the MMIO register.
-
-  @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-SwapMmioOr64 (
-  IN  UINTN Address,
-  IN  UINT64OrData
-  );
-
-/**
-  MmioAnd16 for Big-Endian modules.
-
-  @param  Address The MMIO register to write.
-  @param  AndData The value to AND with the read value from the MMIO register.
-
-  @return The value written back to the MMIO register

[edk2-devel] [PATCH edk2-platforms v4 09/24] Silicon/NXP: Remove unnecessary PCDs

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

The memory map of an SOC is fixed in hardware. it doesn't change with
platform that uses SOC. So, there is no need to keep PCDs for these values
and we can use macros for these in SOC header file.

Any Platform using the SOC, can make use of the SOC header file.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

 Silicon/NXP/NxpQoriqLs.dec| 47 

 Silicon/NXP/LS1043A/LS1043A.dsc.inc   | 26 ---
 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf| 10 +--
 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 21 +-
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf  |  1 -
 Silicon/NXP/Include/Chassis2/NxpSoc.h |  2 +
 Silicon/NXP/LS1043A/Include/Soc.h | 44 
+++
 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c  | 15 ++--
 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c| 79 
+---
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c |  2 +-
 10 files changed, 97 insertions(+), 150 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index bc604e586283..841d403f6f10 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,53 +22,6 @@
   gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 
0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
 
 [PcdsFixedAtBuild.common]
-  #
-  # Pcds for I2C Controller
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x0001
-  gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x0002
-
-  #
-  # Pcds for base address and size
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x0100
-  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x0103
-  gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x0105
-  gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x0106
-  gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x0107
-  gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x0108
-  gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x0109
-  gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x010A
-  gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x010B
-  gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x010C
-  gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x010D
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x010E
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x010F
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x0110
-  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x0111
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x0112
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x0113
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x0114
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x0115
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x0116
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x0117
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x118
-  gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x119
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x011A
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x011B
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x011C
-  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x011D
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x0122
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x0123
-
-  #
-  # IFC PCDs
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x0190
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x0191
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x0192
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x0193
-
   #
   # Platform PCDs
   #
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc 
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index f6ada08dad9d..7690e4caa593 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -26,32 +26,6 @@
 [PcdsFixedAtBuild.common]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
 
-  #
-  # CCSR Address Space and other attached Memories
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0100
-  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F00
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x6000
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x2000
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x062000
-  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E000
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x05
-  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x008000

[edk2-devel] [PATCH edk2-platforms v4 24/24] Platform/NXP/LS1043aRdbPkg: Add PEI Phase

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

Add PEI phase to LS1043aRdb. This is needed because we need to have
dynamic PCDs support to be able to reserve memory before reporting
memory to UEFI firmware.
Using PEI phase we are now also dynamically setting the
PcdSystemMemoryBase and PcdSystemMemorySize depending upon the DRAM
regions detected.
This in turn would depend on the DDR DIMMs installed on board.

Signed-off-by: Pankaj Bansal 
---

Notes:
V4:
- Use ArmPkg version of PeiServicesTablePointerLib instead of MdePkg.
  This allows us to run PEI phase from memory mapped flash devices

V3:
- Update commit description

 Silicon/NXP/NxpQoriqLs.dsc.inc| 63 
+-
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc  |  9 ---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf  | 18 --
 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf |  3 +-
 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c   | 67 
+++-
 5 files changed, 99 insertions(+), 61 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 3c8b11d9e04c..03759c7cee7c 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -93,46 +93,53 @@
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
 
   I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
   
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
   IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
 
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
   MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
 
 [LibraryClasses.common.SEC]
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-  
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
-  
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
-  
LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
-  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
-  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
-  
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
-  
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  
DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  
PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
   PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
-  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+  
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
 
-  # 1/123 faster than Stm or Vstm version
-  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-
-  # Uncomment to turn on GDB stub in SEC.
-  #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+  
PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
 
 [LibraryClasses.common.PEIM]
   PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
   PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
   PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
-  
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  
PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
   
ReportStatusCodeLib

[edk2-devel] [PATCH edk2-platforms v4 12/24] Silicon/NXP: Move RAM retrieval from SocLib

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to common MemoryInit Pei Lib.

Signed-off-by: Pankaj Bansal 
---

Notes:
V4:
- fixed line adds white space error in MemoryInitPeiLib.h
- Added SMC_OK and SMC_UOK Macros to denote the return values from
  SMC calls
- Added explanation for SMC_DRAM_BANK_INFO and DRAM_REGION_INFO in
  MemoryInitPeiLib.h
- Modified GetDramSize to check for return value of SMC call against
  SMC_OK. Also added comments when returning 0 from this function
- Modified GetDramRegionsInfo for loop and return values as per Leif's
  suggestion. Also added DEBUG_ERROR in case of return BUFFER_TOO_SMALL.
- Added SMC_OK in GetDramRegionsInfo
- Check for GetDramRegionsInfo return value in MemoryPeim
- regios -> regions

V3:
- sort headers alphabetically
- Moved DRAM region retrieval and Total DRAM size retrieval to separate
  functions
- Fixed MemoryPeim function description
- Modified check on FoundSystemMem = TRUE to check the RAM region against
  MemoryPeim function input arguments UefiMemoryBase and UefiMemorySize
- (!DramRegions[Index].Size) => (DramRegions[Index].Size == 0)
- (FoundSystemMem) => (FoundSystemMem == TRUE)
- Added explanation for starting for loop from the last DRAM region

 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf |   7 +-
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf   |   1 -
 Silicon/NXP/Include/DramInfo.h |  38 
 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h   |  38 
 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c   | 205 

 Silicon/NXP/Library/SocLib/Chassis.c   |  67 ---
 6 files changed, 211 insertions(+), 145 deletions(-)

diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf 
b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
index a5bd39415def..ad2371115b17 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -18,7 +18,6 @@
 [Sources]
   MemoryInitPeiLib.c
 
-
 [Packages]
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
@@ -30,6 +29,7 @@
 [LibraryClasses]
   ArmMmuLib
   ArmPlatformLib
+  ArmSmcLib
   DebugLib
   HobLib
   PcdLib
@@ -40,6 +40,11 @@
 [FeaturePcd]
   gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
 
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+  gArmTokenSpaceGuid.PcdFdSize
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
 [Pcd]
   gArmTokenSpaceGuid.PcdSystemMemoryBase
   gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf 
b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index b7c7fc78cc8f..99d89498e0e2 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -20,7 +20,6 @@
   Silicon/NXP/NxpQoriqLs.dec
 
 [LibraryClasses]
-  ArmSmcLib
   BaseLib
   DebugLib
   IoAccessLib
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
deleted file mode 100644
index a934aaeff1f5..
--- a/Silicon/NXP/Include/DramInfo.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @file
-*  Header defining the structure for Dram Information
-*
-*  Copyright 2019 NXP
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DRAM_INFO_H_
-#define DRAM_INFO_H_
-
-#include 
-
-#define SMC_DRAM_BANK_INFO  (0xC200FF12)
-
-typedef struct {
-  UINTNBaseAddress;
-  UINTNSize;
-} DRAM_REGION_INFO;
-
-typedef struct {
-  UINT32NumOfDrams;
-  UINT32Reserved;
-  DRAM_REGION_INFO  DramRegion[3];
-} DRAM_INFO;
-
-EFI_STATUS
-GetDramBankInfo (
-  IN OUT DRAM_INFO *DramInfo
-  );
-
-VOID
-UpdateDpaaDram (
-  IN OUT DRAM_INFO *DramInfo
-  );
-
-#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h 
b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
new file mode 100644
index ..7a41f4d226f1
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
@@ -0,0 +1,38 @@
+/** @file
+*
+*  Copyright 2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef MEMORY_INIT_PEI_LIB_H_
+#define MEMORY_INIT_PEI_LIB_H_
+
+#include 
+
+// Specifies the Maximum regions onto which DDR memory can be mapped in
+// a Platform
+#define MAX_DRAM_REGIONS3
+
+// Unique SMC call to retrieve the total DDR RAM size installed in system
+// and the SOC  memory map regions to which DDR RAM is mapped
+// This SMC call works in this way:
+// x1 = -1 : return x0: SMC_OK, x1: total DDR Ram size
+// x1 >= number of DRAM regions to which DDR RAM is mapped : return x0: SMC_UNK
+// 0 <= x1 < number of DRAM regions to which DDR RAM is mapped : return
+//   x0: SMC_OK, x1: Base address of DRAM region,
+//   x2: Size of DR

[edk2-devel] [PATCH edk2-platforms v4 13/24] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

The SOC takes primary clocking input from the external signal (a clock
generator on board). The input (frequency) is multiplied using multiple
phase locked loops (PLL) to create a variety of frequencies which can
then be passed to a variety of internal logic, including cores and
peripheral IP modules.

Therefore, move the clock retrieval APIs to Platform Lib.
The Input clock is retrieved from board components in Platform Lib, and
passed on to SOC Lib APIs to get the correct clock for an IP (after PLL
multiplication).

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- fixed line adds whitespace error in NxpPlatformGetClock.h

V3:
- sorted NXP_IP_CLOCK enum alphabetically

 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf   |  1 +
 Silicon/NXP/Include/Library/SocLib.h   | 44 
+
 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h  | 52 

 Silicon/NXP/LS1043A/Include/Soc.h  | 11 +
 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 51 
+++
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c  | 52 

 6 files changed, 211 insertions(+)

diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf 
b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 99d89498e0e2..3d38a7e58b91 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -17,6 +17,7 @@
   ArmPkg/ArmPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
+  Silicon/NXP/LS1043A/LS1043A.dec
   Silicon/NXP/NxpQoriqLs.dec
 
 [LibraryClasses]
diff --git a/Silicon/NXP/Include/Library/SocLib.h 
b/Silicon/NXP/Include/Library/SocLib.h
new file mode 100644
index ..fc4d786c710b
--- /dev/null
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -0,0 +1,44 @@
+/** @file
+
+  Copyright 2020 NXP
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SOC_LIB_H__
+#define SOC_LIB_H__
+
+#include 
+#include 
+
+/**
+  Return the input clock frequency to an IP Module.
+  This function reads the RCW bits and calculates the  PLL multiplier/divider
+  values to be applied to various IP modules.
+  If a module is disabled or doesn't exist on platform, then return zero.
+
+  @param[in]  BaseClock  Base clock to which PLL multiplier/divider values is
+ to be applied.
+  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP 
clock
+ is to be retrieved.
+  @param[in]  Args   Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, 
then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+  @returnActual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+  IN  UINT64BaseClock,
+  IN  NXP_IP_CLOCK  ClockType,
+  IN  VA_LIST   Args
+  );
+
+#endif // SOC_LIB_H__
diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h 
b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
new file mode 100644
index ..8431148acb9f
--- /dev/null
+++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
@@ -0,0 +1,52 @@
+/** @file
+*
+*  Copyright 2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_PLATFORM_PPI_H__
+#define NXP_PLATFORM_PPI_H__
+
+#include 
+
+typedef enum _NXP_IP_CLOCK {
+  NXP_CORE_CLOCK,
+  NXP_I2C_CLOCK,
+  NXP_SYSTEM_CLOCK,
+  NXP_UART_CLOCK
+} NXP_IP_CLOCK;
+
+/**
+  Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP 
clock
+ is to be retrieved.
+  @param[in]  ...Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, 
then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+  @returnActual

[edk2-devel] [PATCH edk2-platforms v4 23/24] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

MemoryInitPeiLib would be linked to MemoryInitPeim, when we implement
PEI phase. therefore, move the library to directory of same name.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- No change

 Silicon/NXP/NxpQoriqLs.dsc.inc   | 
4 ++--
 Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf | 0
 Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h   | 0
 Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c   | 0
 4 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 8fbd6288cfae..3c8b11d9e04c 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -98,6 +98,8 @@
   
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
   IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
 
+  MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+
 [LibraryClasses.common.SEC]
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
@@ -109,7 +111,6 @@
   
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
   PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
   PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
-  MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
 
   # 1/123 faster than Stm or Vstm version
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -139,7 +140,6 @@
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
   
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
-  MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
 
 [LibraryClasses.common.UEFI_APPLICATION]
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf 
b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h 
b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c 
b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
-- 
2.17.1


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[edk2-devel] [PATCH edk2-platforms v4 17/24] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

Now the we have added Chassis Package, move the chassis specific common
code for all SOCs belonging to same chassis to ChassisLib.

Use ChassisLib APIs in SocLib.

Signed-off-by: Pankaj Bansal 
---

Notes:
V4:
- No change

V3:
- No change

 Silicon/NXP/NxpQoriqLs.dec   |  6 --
 Silicon/NXP/LS1043A/LS1043A.dsc.inc  |  9 ++-
 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf   |  1 +
 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf |  1 +
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 15 +
 Silicon/NXP/Include/Chassis2/NxpSoc.h| 44 
--
 Silicon/NXP/LS1043A/Include/Soc.h|  6 +-
 Silicon/NXP/Library/SocLib/NxpChassis.h  | 22 
---
 Silicon/NXP/Library/SocLib/Chassis.c | 61 

 Silicon/NXP/Library/SocLib/Chassis2/Soc.c| 19 
+-
 10 files changed, 14 insertions(+), 170 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index b327e52da139..0722f59ef4f6 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -24,12 +24,6 @@
   gNxpQoriqLsTokenSpaceGuid  = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 
0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
   gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 
0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
 
-[PcdsFixedAtBuild.common]
-  #
-  # Pcds to support Big Endian IPs
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x311
-
 [PcdsFeatureFlag]
   gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x0315
   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x0316
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc 
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 7690e4caa593..ea0854f967a3 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -7,6 +7,8 @@
 #
 #
 
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
 [LibraryClasses.common]
   SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
   SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -26,9 +28,6 @@
 [PcdsFixedAtBuild.common]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
 
-  #
-  # Big Endian IPs
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
-
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
 ##
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf 
b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 038d48949a39..e522db81e5c0 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -24,6 +24,7 @@
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
   Silicon/NXP/LS1043A/LS1043A.dec
   Silicon/NXP/NxpQoriqLs.dec
 
diff --git 
a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7a43ad86d183..07ca6b34445f 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -19,6 +19,7 @@
   ArmPlatformPkg/ArmPlatformPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
   Silicon/NXP/LS1043A/LS1043A.dec
   Silicon/NXP/NxpQoriqLs.dec
 
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf 
b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index bb15e0a3d710..1d042bbfc4e4 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -14,25 +14,14 @@
   LIBRARY_CLASS  = SocLib
 
 [Packages]
-  ArmPkg/ArmPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
   Silicon/NXP/LS1043A/LS1043A.dec
   Silicon/NXP/NxpQoriqLs.dec
 
 [LibraryClasses]
-  BaseLib
+  ChassisLib
   DebugLib
-  IoAccessLib
-  SerialPortLib
 
 [Sources.common]
-  Chassis.c
   Chassis2/Soc.c
-
-[BuildOptions]
-  GCC:*_*_*_CC_FLAGS = -DCHASSIS2
-
-[FixedPcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h 
b/Silicon/NXP/Include/Chassis2/NxpSoc.h
deleted file mode 100644
index 3f00a2614131..
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/** Soc.h
-*  Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-*  Copyright 2017-2020 NXP
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_SOC_H_
-#define NXP_SOC_H_
-
-#define CLK_FREQ

[edk2-devel] [PATCH edk2-platforms v4 14/24] Silicon/NXP: Use Clock retrieval PPI in modules

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- No change

V3:
- Added clock retrieval APIs to DUartPortLib

 Silicon/NXP/NxpQoriqLs.dec|  5 
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc  |  2 --
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf |  2 +-
 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf |  5 ++--
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf  |  1 -
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h   |  6 
 Silicon/NXP/Include/Chassis2/NxpSoc.h |  9 --
 Silicon/NXP/Library/DUartPortLib/DUart.h  |  8 +
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c   |  3 +-
 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c   |  7 ++---
 Silicon/NXP/Library/SocLib/Chassis.c  | 15 --
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 31 
 12 files changed, 9 insertions(+), 85 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 841d403f6f10..e61592b4fe61 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,11 +22,6 @@
   gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 
0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
 
 [PcdsFixedAtBuild.common]
-  #
-  # Platform PCDs
-  #
-  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x0250
-
   #
   # Pcds to support Big Endian IPs
   #
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index e5383aaf0cc5..d486c9b36fab 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -39,8 +39,6 @@
   gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE0
   gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x0200
 
-  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
-
   #
   # RTC Pcds
   #
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf 
b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 867376044656..3bf7a8124fc6 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -25,13 +25,13 @@
 
 [LibraryClasses]
   ArmLib
+  ArmPlatformLib
   BaseMemoryLib
   DevicePathLib
   I2cLib
   IoLib
   MemoryAllocationLib
   PcdLib
-  SocLib
   TimerLib
   UefiBootServicesTableLib
   UefiDriverEntryPoint
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf 
b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
index 7a2fa619b027..b8a77ae05243 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -3,7 +3,7 @@
 #  Component description file for DUartPortLib module
 #
 #  Copyright (c) 2013, Freescale Ltd. All rights reserved.
-#  Copyright 2017 NXP
+#  Copyright 2017, 2020 NXP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -20,8 +20,8 @@
   DUartPortLib.c
 
 [LibraryClasses]
+  ArmPlatformLib
   PcdLib
-  SocLib
 
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
@@ -31,4 +31,3 @@
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf 
b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 3d38a7e58b91..bb15e0a3d710 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -36,4 +36,3 @@
 [FixedPcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
-  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h 
b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 88316f313380..7c4a306c16a0 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -37,12 +37,6 @@ typedef struct {
   NON_DISCOVERABLE_DEVICE *Dev;
 } NXP_I2C_MASTER;
 
-extern
-UINT64
-GetBusFrequency (
-  VOID
-  );
-
 EFI_STATUS
 NxpI2cInit (
   IN EFI_HANDLE  DriverBindingHandle,
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h 
b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 6812beafe447..3f00a2614131 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -27,10 +27,6 @@
 #define SACR_PAGESIZE_MASK 0x0001
 #define IDR1_PAGESIZE_MASK 0x8000
 
-typedef struct {
-  UINTN FreqSystemBus;
-} SYS_INFO;
-
 /* Device Configuration and Pin Control */
 typedef struct {
   UINT8Res0[0x100-0x00];
@@ -39,11 +35,6 @@ typedef struct {
 #define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK  0x1f
 } CCSR_GUR;
 
-VOID
-GetSysInfo (
-  OUT SYS_INFO *
-  );
-
 UINT32
 EFIAPI
 GurRead (
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h 
b/Silicon/NXP/Library/DUartPortLib/DUart.h
index c71e2ce55d1d..aca7cd8d3f01 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUart.h
+++ b/Silicon/NXP

[edk2-devel] [PATCH edk2-platforms v4 20/24] NXP: LS1043aRdbPkg: Use ArmPlatformHelper.S from ArmPlatformPkg

2020-04-29 Thread Pankaj Bansal

From: Pankaj Bansal 

ArmPlatformHelper.S is being replaced by the ArmPlatformPkg version at
commit hash f4dfad05dda2c7b29e8105605621f2b413f0af2b.

Signed-off-by: Pankaj Bansal 
Reviewed-by: Leif Lindholm 
---

Notes:
V4:
- fixed line adds whitespace error

V3:
- Modify commit description

 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  
|  1 +
 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
|  8 ---
 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
| 60 
 3 files changed, 38 insertions(+), 31 deletions(-)

diff --git 
a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 07ca6b34445f..cae0c7d1afc6 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -37,3 +37,4 @@
 
 [FixedPcd]
   gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index a554d1377484..dc81e7ba3101 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -137,11 +137,3 @@ ArmPlatformGetPlatformPpiList (
   *PpiList = gPlatformPpiTable;
 }
 
-
-UINTN
-ArmPlatformGetCorePosition (
-  IN UINTN MpId
-  )
-{
-  return 1;
-}
diff --git 
a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
index dfbf73675a2d..b7c6dbdc2e61 100644
--- 
a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
+++ 
b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -1,31 +1,45 @@
-#  @file
-#
-#  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-#  Copyright 2017, 2020 NXP
-#
-#  SPDX-License-Identifier: BSD-2-Clause-Patent
-#
+//
+//  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
 
 #include 
-#include 
-
-.text
-.align 2
-
-GCC_ASM_IMPORT(ArmReadMpidr)
-
-ASM_FUNC(ArmPlatformIsPrimaryCore)
-  tst x0, #3
-  cset x0, eq
-  ret
+#include 
 
 ASM_FUNC(ArmPlatformPeiBootAction)
-EL1_OR_EL2(x0)
-1:
-2:
   ret
 
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #6
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
 ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
-  MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
-  ldrh   w0, [x0]
+  MOV32  (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+  cmp   w0, w1
+  mov   x0, #1
+  mov   x1, #0
+  csel  x0, x0, x1, eq
   ret
-- 
2.17.1


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