Re: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
Reviewed-by: Eric Dong And pushed: SHA-1: f4c898f2b2db2819c519cdce05403d4ba0234979 Thanks, Eric > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of John > E Lofgren > Sent: Wednesday, September 18, 2019 11:43 PM > To: devel@edk2.groups.io > Subject: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split > lock > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 > V3 changes: > change to mov instruction (non locking instuction) instead > of xchg to simplify design. > > V2 changes: > Add xchg 16 bit instructions to handle sgdt and sidt base > 63:48 bits and 47:32 bits. > Add comment to explain why xchg 64bit isnt being used > > Split lock happens when a locking instruction is used on mis-aligned data > that crosses two cachelines. If close source platform enables Alignment Check > Exception(#AC), They can hit a double fault due to split lock being in > CpuExceptionHandlerLib. > > sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. > The data is mis-aligned, can cross two cacheline, and a xchg > instruction(locking instuction) is being utilize. > > Signed-off-by: John E Lofgren > --- > UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > | 14 -- > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > index 4db1a09f28..19198f2731 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > @@ -184,17 +184,19 @@ HasErrorCode: > pushrax > pushrax > sidt[rsp] > -xchgrax, [rsp + 2] > -xchgrax, [rsp] > -xchgrax, [rsp + 8] > +mov bx, word [rsp] > +mov rax, qword [rsp + 2] > +mov qword [rsp], rax > +mov word [rsp + 8], bx > > xor rax, rax > pushrax > pushrax > sgdt[rsp] > -xchgrax, [rsp + 2] > -xchgrax, [rsp] > -xchgrax, [rsp + 8] > +mov bx, word [rsp] > +mov rax, qword [rsp + 2] > +mov qword [rsp], rax > +mov word [rsp + 8], bx > > ;; UINT64 Ldtr, Tr; > xor rax, rax > -- > 2.16.2.windows.1 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47708): https://edk2.groups.io/g/devel/message/47708 Mute This Topic: https://groups.io/mt/34181976/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
On 09/18/19 17:43, John E Lofgren wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 > V3 changes: > change to mov instruction (non locking instuction) instead > of xchg to simplify design. This patch should have been posted as "v4" actually -- it differs from what you originally posted as v3. Therefore it cannot be considered v3. The changelog in the patch would say, v4: The v3 posting didn't do what it promised to do, so do it now for real. v3: Anyway, not a deal breaker. More comments below. > V2 changes: > Add xchg 16 bit instructions to handle sgdt and sidt base > 63:48 bits and 47:32 bits. > Add comment to explain why xchg 64bit isnt being used > > Split lock happens when a locking instruction is used on mis-aligned data > that crosses two cachelines. If close source platform enables Alignment Check > Exception(#AC), They can hit a double fault due to split lock being in > CpuExceptionHandlerLib. > > sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. > The data is mis-aligned, can cross two cacheline, and a xchg > instruction(locking instuction) is being utilize. > > Signed-off-by: John E Lofgren > --- > UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 14 > -- > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > index 4db1a09f28..19198f2731 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > @@ -184,17 +184,19 @@ HasErrorCode: > pushrax > pushrax > sidt[rsp] > -xchgrax, [rsp + 2] > -xchgrax, [rsp] > -xchgrax, [rsp + 8] > +mov bx, word [rsp] > +mov rax, qword [rsp + 2] > +mov qword [rsp], rax > +mov word [rsp + 8], bx > > xor rax, rax > pushrax > pushrax > sgdt[rsp] > -xchgrax, [rsp + 2] > -xchgrax, [rsp] > -xchgrax, [rsp + 8] > +mov bx, word [rsp] > +mov rax, qword [rsp + 2] > +mov qword [rsp], rax > +mov word [rsp + 8], bx > > ;; UINT64 Ldtr, Tr; > xor rax, rax > I think it would be nice to learn why XCHG was used in the first place. Then again, whatever it was preferred for, it could not have been locking, as the three XCHG instructions are not atomic as a whole (i.e. they are not locked all together). Another reason for XCHG could be that they wanted to use just one register -- but I totally don't see the point of not using BX too. So: Reviewed-by: Laszlo Ersek Thanks, Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47495): https://edk2.groups.io/g/devel/message/47495 Mute This Topic: https://groups.io/mt/34181976/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 V3 changes: change to mov instruction (non locking instuction) instead of xchg to simplify design. V2 changes: Add xchg 16 bit instructions to handle sgdt and sidt base 63:48 bits and 47:32 bits. Add comment to explain why xchg 64bit isnt being used Split lock happens when a locking instruction is used on mis-aligned data that crosses two cachelines. If close source platform enables Alignment Check Exception(#AC), They can hit a double fault due to split lock being in CpuExceptionHandlerLib. sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. The data is mis-aligned, can cross two cacheline, and a xchg instruction(locking instuction) is being utilize. Signed-off-by: John E Lofgren --- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 4db1a09f28..19198f2731 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -184,17 +184,19 @@ HasErrorCode: pushrax pushrax sidt[rsp] -xchgrax, [rsp + 2] -xchgrax, [rsp] -xchgrax, [rsp + 8] +mov bx, word [rsp] +mov rax, qword [rsp + 2] +mov qword [rsp], rax +mov word [rsp + 8], bx xor rax, rax pushrax pushrax sgdt[rsp] -xchgrax, [rsp + 2] -xchgrax, [rsp] -xchgrax, [rsp + 8] +mov bx, word [rsp] +mov rax, qword [rsp + 2] +mov qword [rsp], rax +mov word [rsp + 8], bx ;; UINT64 Ldtr, Tr; xor rax, rax -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47484): https://edk2.groups.io/g/devel/message/47484 Mute This Topic: https://groups.io/mt/34181976/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
Sorry. I forgot amend it to the commit. Ill fix it. Sorry Again, John >-Original Message- >From: Laszlo Ersek [mailto:ler...@redhat.com] >Sent: Wednesday, September 18, 2019 1:52 AM >To: devel@edk2.groups.io; Lofgren, John E >Subject: Re: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix >split lock > >On 09/18/19 00:49, John E Lofgren wrote: >> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 >> V3 changes: >> change to mov instruction (non locking instuction) instead of xchg to >> simplify design. > >I think something's wrong -- the v3 update described above isn't actually >implemented in the patch (it continues using XCHG, rather than MOV). > >Thanks >Laszlo > >> >> V2 changes: >> Add xchg 16 bit instructions to handle sgdt and sidt base >> 63:48 bits and 47:32 bits. >> Add comment to explain why xchg 64bit isnt being used >> >> Split lock happens when a locking instruction is used on mis-aligned >> data that crosses two cachelines. If close source platform enables >> Alignment Check Exception(#AC), They can hit a double fault due to >> split lock being in CpuExceptionHandlerLib. >> >> sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. >> The data is mis-aligned, can cross two cacheline, and a xchg >> instruction(locking instuction) is being utilize. >> >> Signed-off-by: John E Lofgren >> --- >> >> >UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas >m >> | 20 ++-- >> 1 file changed, 14 insertions(+), 6 deletions(-) >> >> diff --git >> >a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na >> sm >> >b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na >> sm >> index 4db1a09f28..7b7642b290 100644 >> --- >> >a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na >> sm >> +++ >b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAs >> +++ m.nasm >> @@ -180,21 +180,29 @@ HasErrorCode: >> pushqword [rbp + 24] >> >> ;; UINT64 Gdtr[2], Idtr[2]; >> +; sidt and sgdt saves 10 bytes to memory, 8 bytes = base and 2 bytes = >limit. >> +; To avoid #AC split lock when separating base and limit into their >> +; own separate 64 bit memory, we can’t use 64 bit xchg since base >> [63:48] >bits >> +; may cross the cache line. >> xor rax, rax >> pushrax >> pushrax >> sidt[rsp] >> -xchgrax, [rsp + 2] >> -xchgrax, [rsp] >> -xchgrax, [rsp + 8] >> +xchgeax, [rsp + 2] >> +xchgeax, [rsp] >> +xchgeax, [rsp + 8] >> +xchg ax, [rsp + 6] >> +xchg ax, [rsp + 4] >> >> xor rax, rax >> pushrax >> pushrax >> sgdt[rsp] >> -xchgrax, [rsp + 2] >> -xchgrax, [rsp] >> -xchgrax, [rsp + 8] >> +xchgeax, [rsp + 2] >> +xchgeax, [rsp] >> +xchgeax, [rsp + 8] >> +xchg ax, [rsp + 6] >> +xchg ax, [rsp + 4] >> >> ;; UINT64 Ldtr, Tr; >> xor rax, rax >> -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47483): https://edk2.groups.io/g/devel/message/47483 Mute This Topic: https://groups.io/mt/34181976/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
On 09/18/19 00:49, John E Lofgren wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 > V3 changes: > change to mov instruction (non locking instuction) instead > of xchg to simplify design. I think something's wrong -- the v3 update described above isn't actually implemented in the patch (it continues using XCHG, rather than MOV). Thanks Laszlo > > V2 changes: > Add xchg 16 bit instructions to handle sgdt and sidt base > 63:48 bits and 47:32 bits. > Add comment to explain why xchg 64bit isnt being used > > Split lock happens when a locking instruction is used on mis-aligned data > that crosses two cachelines. If close source platform enables Alignment Check > Exception(#AC), They can hit a double fault due to split lock being in > CpuExceptionHandlerLib. > > sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. > The data is mis-aligned, can cross two cacheline, and a xchg > instruction(locking instuction) is being utilize. > > Signed-off-by: John E Lofgren > --- > UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 20 > ++-- > 1 file changed, 14 insertions(+), 6 deletions(-) > > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > index 4db1a09f28..7b7642b290 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm > @@ -180,21 +180,29 @@ HasErrorCode: > pushqword [rbp + 24] > > ;; UINT64 Gdtr[2], Idtr[2]; > +; sidt and sgdt saves 10 bytes to memory, 8 bytes = base and 2 bytes = > limit. > +; To avoid #AC split lock when separating base and limit into their > +; own separate 64 bit memory, we can’t use 64 bit xchg since base > [63:48] bits > +; may cross the cache line. > xor rax, rax > pushrax > pushrax > sidt[rsp] > -xchgrax, [rsp + 2] > -xchgrax, [rsp] > -xchgrax, [rsp + 8] > +xchgeax, [rsp + 2] > +xchgeax, [rsp] > +xchgeax, [rsp + 8] > +xchg ax, [rsp + 6] > +xchg ax, [rsp + 4] > > xor rax, rax > pushrax > pushrax > sgdt[rsp] > -xchgrax, [rsp + 2] > -xchgrax, [rsp] > -xchgrax, [rsp + 8] > +xchgeax, [rsp + 2] > +xchgeax, [rsp] > +xchgeax, [rsp + 8] > +xchg ax, [rsp + 6] > +xchg ax, [rsp + 4] > > ;; UINT64 Ldtr, Tr; > xor rax, rax > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47472): https://edk2.groups.io/g/devel/message/47472 Mute This Topic: https://groups.io/mt/34181976/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 V3 changes: change to mov instruction (non locking instuction) instead of xchg to simplify design. V2 changes: Add xchg 16 bit instructions to handle sgdt and sidt base 63:48 bits and 47:32 bits. Add comment to explain why xchg 64bit isnt being used Split lock happens when a locking instruction is used on mis-aligned data that crosses two cachelines. If close source platform enables Alignment Check Exception(#AC), They can hit a double fault due to split lock being in CpuExceptionHandlerLib. sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. The data is mis-aligned, can cross two cacheline, and a xchg instruction(locking instuction) is being utilize. Signed-off-by: John E Lofgren --- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 4db1a09f28..7b7642b290 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -180,21 +180,29 @@ HasErrorCode: pushqword [rbp + 24] ;; UINT64 Gdtr[2], Idtr[2]; +; sidt and sgdt saves 10 bytes to memory, 8 bytes = base and 2 bytes = limit. +; To avoid #AC split lock when separating base and limit into their +; own separate 64 bit memory, we can’t use 64 bit xchg since base [63:48] bits +; may cross the cache line. xor rax, rax pushrax pushrax sidt[rsp] -xchgrax, [rsp + 2] -xchgrax, [rsp] -xchgrax, [rsp + 8] +xchgeax, [rsp + 2] +xchgeax, [rsp] +xchgeax, [rsp + 8] +xchg ax, [rsp + 6] +xchg ax, [rsp + 4] xor rax, rax pushrax pushrax sgdt[rsp] -xchgrax, [rsp + 2] -xchgrax, [rsp] -xchgrax, [rsp + 8] +xchgeax, [rsp + 2] +xchgeax, [rsp] +xchgeax, [rsp + 8] +xchg ax, [rsp + 6] +xchg ax, [rsp + 4] ;; UINT64 Ldtr, Tr; xor rax, rax -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47438): https://edk2.groups.io/g/devel/message/47438 Mute This Topic: https://groups.io/mt/34181976/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
