Re: [edk2-devel] [edk2-platforms][PATCH] Change edk2-platforms/master to BSD+Patent License
Agree on deleting extra license files. Thanks! Reviewed-by: Chasel Chiu > -Original Message- > From: Kubacki, Michael A > Sent: Thursday, May 16, 2019 12:45 AM > To: Kinney, Michael D ; Leif Lindholm > ; Chiu, Chasel > Cc: devel@edk2.groups.io; Ard Biesheuvel (ard.biesheu...@linaro.org) > ; Gillispie, Thad ; Bu, > Daocheng ; Oram, Isaac W > ; Piwko, Maciej ; Lu, Shifei > A ; Zhou, Bowen ; Sinha, Ankit > ; Chaganty, Rangasai V > > Subject: RE: [edk2-platforms][PATCH] Change edk2-platforms/master to > BSD+Patent License > > After the license files are deleted. > > Reviewed-by: Michael Kubacki > > > -Original Message- > > From: Kinney, Michael D > > Sent: Wednesday, May 15, 2019 9:33 AM > > To: Leif Lindholm ; Chiu, Chasel > > ; Kinney, Michael D > > > > Cc: devel@edk2.groups.io; Ard Biesheuvel (ard.biesheu...@linaro.org) > > ; Kubacki, Michael A > > ; Gillispie, Thad > > ; Bu, Daocheng ; > > Oram, Isaac W ; Piwko, Maciej > > ; Lu, Shifei A ; Zhou, > > Bowen ; Sinha, Ankit ; > > Chaganty, Rangasai V > > Subject: RE: [edk2-platforms][PATCH] Change edk2-platforms/master to > > BSD+Patent License > > > > Leif, > > > > Yes. Deleting the extra license files is correct if the content Uses > > the > > BSD+Patent license in the License.txt in the root. > > > > I will fix this in V2. > > > > Mike > > > > > -Original Message- > > > From: Leif Lindholm [mailto:leif.lindh...@linaro.org] > > > Sent: Wednesday, May 15, 2019 4:17 AM > > > To: Chiu, Chasel > > > Cc: devel@edk2.groups.io; Kinney, Michael D > > > ; Ard Biesheuvel > > > (ard.biesheu...@linaro.org) > > > ; Kubacki, Michael A > > > ; Gillispie, Thad > > > ; Bu, Daocheng ; > > > Oram, Isaac W ; Piwko, Maciej > > > ; Lu, Shifei A ; > > > Zhou, Bowen ; Sinha, Ankit > > > ; Chaganty, Rangasai V > > > > > > Subject: Re: [edk2-platforms][PATCH] Change edk2- platforms/master > > > to > > > BSD+Patent License > > > > > > On Wed, May 15, 2019 at 07:11:52AM +, Chiu, Chasel > > > wrote: > > > > > > > > Hi Mike, > > > > > > > > Seems we missed below files, would you please check? > > > > .\Platform\Intel\KabylakeOpenBoardPkg\License.txt > > > > .\Silicon\Intel\KabylakeSiliconPkg\License.txt > > > > > > > > With above 2 files updated, > > > > > > Would not deleting them be more appropriate? > > > > > > Best Regards, > > > > > > Leif > > > > > > > Reviewed-by: Chasel Chiu > > > > .\Platform\Intel\KabylakeOpenBoardPkg > > > > .\Silicon\Intel\KabylakeSiliconPkg > > > > > > > > Thanks! > > > > Chasel > > > > > > > > > > > > > -Original Message- > > > > > From: devel@edk2.groups.io > > > [mailto:devel@edk2.groups.io] On Behalf Of > > > > > Michael D Kinney > > > > > Sent: Wednesday, May 15, 2019 9:31 AM > > > > > To: devel@edk2.groups.io > > > > > Cc: leif.lindh...@linaro.org; Ard Biesheuvel > > > (ard.biesheu...@linaro.org) > > > > > ; Kubacki, Michael A > > > > > ; Gillispie, Thad > > > ; Bu, > > > > > Daocheng ; Oram, Isaac W > > > > > ; Piwko, Maciej > > > ; Chiu, > > > > > Chasel ; Lu, Shifei A > > > ; Zhou, > > > > > Bowen ; Sinha, Ankit > > > ; > > > > > Chaganty, Rangasai V > > > > > > > > Subject: [edk2-devel] [edk2-platforms][PATCH] > > > Change edk2-platforms/master > > > > > to BSD+Patent License > > > > > > > > > > Hello, > > > > > > > > > > BZ: > > > https://bugzilla.tianocore.org/show_bug.cgi?id=1373 > > > > > > > > > > This change is based on the following emails: > > > > > https://lists.01.org/pipermail/edk2-devel/2019- > > > February/036260.html > > > > > https://lists.01.org/pipermail/edk2-devel/2018- > > > October/030385.html > > > > > > > > > > RFCs with detailed process for the license change: > > > > > V3: https://lists.01.org/pipermail/edk2- > > > devel/2019-March/038116.html > > > > > V2: https://lists
Re: [edk2-devel] [[edk2-platforms][PATCH V2] 02/30] edk2-platforms: Change License.txt from 2-Clause BSD to BSD+Patent
Reviewed-by: Chasel Chiu > -Original Message- > From: Kinney, Michael D > Sent: Thursday, May 16, 2019 7:10 AM > To: devel@edk2.groups.io > Cc: Leif Lindholm ; Ard Biesheuvel > ; Gillispie, Thad ; Bu, > Daocheng ; Oram, Isaac W > ; Piwko, Maciej ; Chiu, > Chasel ; Kubacki, Michael A > ; Lu, Shifei A ; Zhou, > Bowen ; Sinha, Ankit ; > Chaganty, Rangasai V > Subject: [[edk2-platforms][PATCH V2] 02/30] edk2-platforms: Change > License.txt from 2-Clause BSD to BSD+Patent > > Change License.txt in the root of the edk2-platforms repository from the > 2-Clause BSD License to the BSD+Patent License. > > The text difference between these licenses in the patch is larger than > expected > due to different choices for the position of the line breaks. The text from > the > BSD 2-Clause license and its disclaimer are the same. New clauses from the > BSD+Patent license have been added. > > The License.txt files in other directories that contain the 2-Clause BSD > License are > deleted. The single License.txt in the root of the edk2-platforms repository > with > the BSD+Patent License contents is the preferred license for the > edk2-platforms > repository. > > https://bugzilla.tianocore.org/show_bug.cgi?id=1373 > > This change is based on the following emails: > > https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html > https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html > > RFCs with detailed process for the license change: > > V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html > V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html > V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html > > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Thad Gillispie > Cc: Daocheng Bu > Cc: Isaac W Oram > Cc: Maciej Piwko > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Shifei A Lu > Cc: Xiaohu Zhou > Cc: Ankit Sinha > Cc: Sai Chaganty > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Michael D Kinney > --- > License.txt | 70 +-- > Platform/AMD/License.txt | 25 --- > Platform/Intel/AdvancedFeaturePkg/License.txt | 25 --- > Platform/Intel/ClevoOpenBoardPkg/License.txt | 25 --- > .../Intel/KabylakeOpenBoardPkg/License.txt| 25 --- > Platform/Intel/MinPlatformPkg/License.txt | 25 --- > Platform/LeMaker/License.txt | 25 --- > Platform/SoftIron/License.txt | 25 --- > Silicon/AMD/Styx/License.txt | 25 --- > Silicon/Intel/KabylakeSiliconPkg/License.txt | 25 --- > 10 files changed, 48 insertions(+), 247 deletions(-) delete mode 100644 > Platform/AMD/License.txt delete mode 100644 > Platform/Intel/AdvancedFeaturePkg/License.txt > delete mode 100644 Platform/Intel/ClevoOpenBoardPkg/License.txt > delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/License.txt > delete mode 100644 Platform/Intel/MinPlatformPkg/License.txt > delete mode 100644 Platform/LeMaker/License.txt delete mode 100644 > Platform/SoftIron/License.txt delete mode 100644 > Silicon/AMD/Styx/License.txt delete mode 100644 > Silicon/Intel/KabylakeSiliconPkg/License.txt > > diff --git a/License.txt b/License.txt > index dea6f02f0f..ee840505cb 100644 > --- a/License.txt > +++ b/License.txt > @@ -1,25 +1,51 @@ > -Copyright (c) 2012-2017, Linaro Ltd. All rights reserved. > +Copyright (c) 2019, TianoCore and contributors. All rights reserved. > + > +SPDX-License-Identifier: BSD-2-Clause-Patent > > Redistribution and use in source and binary forms, with or without > -modification, are permitted provided that the following conditions -are met: > - > -* Redistributions of source code must retain the above copyright > - notice, this list of conditions and the following disclaimer. > -* Redistributions in binary form must reproduce the above copyright > - notice, this list of conditions and the following disclaimer in > - the documentation and/or other materials provided with the > - distribution. > - > -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND > CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, > INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF > MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE > DISCLAIMED. IN NO EVENT SHALL THE -COPYRIGHT HOLDER OR CONTRIBUTORS > BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR > CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, > PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR > PROFITS; O
Re: [edk2-devel] [[edk2-platforms][PATCH V2] 10/30] Platform/Intel/KabylakeOpenBoardPkg: Replace BSD License with BSD+Patent License
Reviewed-by: Chasel Chiu > -Original Message- > From: Kinney, Michael D > Sent: Thursday, May 16, 2019 7:10 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael A > > Subject: [[edk2-platforms][PATCH V2] 10/30] > Platform/Intel/KabylakeOpenBoardPkg: Replace BSD License with BSD+Patent > License > > https://bugzilla.tianocore.org/show_bug.cgi?id=1373 > > Replace BSD 2-Clause License with BSD+Patent License. This change is > based on the following emails: > > https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html > https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html > > RFCs with detailed process for the license change: > > V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html > V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html > V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html > > Cc: Chasel Chiu > Cc: Michael Kubacki > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Michael D Kinney > --- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c | 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 8 +--- > .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf| 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL | 8 +--- > .../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl | 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL | 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl | 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl | 8 +--- > .../Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL| 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl | 8 +--- > .../Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL| 8 +--- > .../Acpi/BoardAcpiDxe/Dsdt/PciTree.asl| 8 +--- > .../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 8 +--- > .../Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl | 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl | 8 +--- > .../KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c | 8 +--- > .../KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c | 8 +--- > .../KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h | 8 +--- > .../Features/PciHotPlug/PciHotPlug.inf| 8 +--- > .../Features/Tbt/AcpiTables/Rtd3SptPcieTbt.asl| 8 +--- > .../KabylakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl | 8 +--- > .../Features/Tbt/Include/Acpi/TbtNvs.asl | 8 +--- > .../Features/Tbt/Include/Acpi/TbtNvsAreaDef.h | 8 +--- > .../Features/Tbt/Include/Library/DxeTbtPolicyLib.h| 8 +--- > .../Features/Tbt/Include/Library/PeiTbtPolicyLib.h| 8 +--- > .../Features/Tbt/Include/Library/TbtCommonLib.h | 8 +--- > .../Features/Tbt/Include/Ppi/PeiTbtPolicy.h | 8 +--- > .../Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h | 8 +--- > .../Tbt/Include/Private/Library/PeiTbtCommonInitLib.h | 8 +--- > .../Features/Tbt/Include/Protocol/DxeTbtPolicy.h | 8 +--- > .../Features/Tbt/Include/Protocol/TbtNvsArea.h| 8 +--- > .../Features/Tbt/Include/TbtBoardInfo.h | 8 +--- > .../Features/Tbt/Include/TbtPolicyCommonDefinition.h | 8 +--- > .../Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c | 8 +--- > .../Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf | 8 +--- > .../Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h | 8 +--- > .../Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c | 8 +--- > .../Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf| 8 +--- > .../Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c | 8 +--- > .../Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf | 8 +--- > .../Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h | 8 +--- > .../Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c | 8 +--- > .../Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf | 8 +--- > .../Features/Tbt/TbtInit/Dxe/TbtDxe.c | 8 +--- > .../Features/Tbt/TbtInit/Dxe/TbtDxe.inf | 8 +--- > .../Features/Tbt/TbtInit/Pei/PeiTbtInit.c | 8 +--- > .../Features/Tbt/TbtInit/Pei/PeiTbtInit.inf | 8 +--- > .../Features/Tbt/TbtInit/Smm/TbtSmiHandler.c | 8 +--- > .../Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
Re: [edk2-devel][Patch] IntelFspPkg: Remove them
Hi Nate, Last time we talked, IntelFspPkg can be removed but IntelFspWrapperPkg might be still needed, would you please check if this is still true? With Nate's confirmation, Reviewed-by: Chasel Chiu Thanks! Chasel > -Original Message- > From: Ni, Ray > Sent: Thursday, May 16, 2019 4:38 PM > To: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Cc: devel@edk2.groups.io > Subject: [edk2-devel][Patch] IntelFspPkg: Remove them > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1819 > > Since there are V2 FSP packages (IntelFsp2Pkg, IntelFsp2WrapperPkg), this > patch > removes IntelFspPkg, IntelFspWrapperPkg to remove obsolete code in edk2 > repo. > > Signed-off-by: Ray Ni > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > -- > NOTE: This patch is to completely remove IntelFspPkg and IntelFspWrapperPkg > folder in edk2 repo. > I don't want to flood people's inbox with a big patch just removing every > line of > code in this two packages. > > The patch that modifies Maintainers.txt will be sent out later after > IntelFspPkg > and IntelFspWrapperPkg are removed. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40861): https://edk2.groups.io/g/devel/message/40861 Mute This Topic: https://groups.io/mt/31638674/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] Platform/Intel: Add fspapi build parameter
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1824
Going forward FSP Dispatch mode will be default in
KabylakeOpenBoardPkg and requires fspapi build parameter
to switch back to FSP API mode.
When --fspapi given to build python script it will set
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection to
1, otherwise the PCD will be the default value defined
by each *BoardPkg.
Test: verified the PCD PcdFspModeSelection can be
overridden by new build parameter.
Cc: Agyeman Prince
Cc: Nate DeSimone
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Platform/Intel/build_bios.py | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index 9effefc0c7..9f8d78f6e8 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -359,6 +359,11 @@ def build(config):
command.append("-D")
command.append("MAX_SOCKET=" + config["MAX_SOCKET"])
+if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+#Override PCD to enable API mode FSP wrapper.
+command.append("--pcd")
+command.append("gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection=1")
+
shell = True
if os.name == "posix":
shell = False
@@ -840,6 +845,9 @@ def get_cmd_config_arguments(arguments):
if arguments.fsp is True:
result["FSP_WRAPPER_BUILD"] = "TRUE"
+if arguments.fspapi is True:
+result["API_MODE_FSP_WRAPPER_BUILD"] = "TRUE"
+
return result
@@ -910,9 +918,12 @@ def get_cmd_arguments(build_config):
parser.add_argument("--performance", help="performance build enabled",
action='store_true', dest="performance")
-parser.add_argument("--fsp", help="fsp build enabled",
+parser.add_argument("--fsp", help="fsp wrapper build enabled",
action='store_true', dest="fsp")
+parser.add_argument("--fspapi", help="API mode fsp wrapper build enabled",
+action='store_true', dest="fspapi")
+
return parser.parse_args()
--
2.13.3.windows.1
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[edk2-devel] [PATCH] IntelFsp2Pkg/SplitFspBin.py: Revert FSP 1.x support.
This reverts commit:
591b8cb7f3d026d2fa4483c59f3d5fb14be181bf.
Will submit again after freeze done.
Cc: Liming Gao
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Tools/SplitFspBin.py | 21
-
IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md | 47
++-
2 files changed, 30 insertions(+), 38 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index 15c8bebee2..2458231d09 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -1,6 +1,6 @@
## @ FspTool.py
#
-# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,12 +14,12 @@ import argparse
from ctypes import *
"""
-This utility supports some operations for Intel FSP 1.x/2.x image.
+This utility supports some operations for Intel FSP 2.0 image.
It supports:
-- Display FSP 1.x/2.x information header
-- Split FSP 2.x image into individual FSP-T/M/S/O component
-- Rebase FSP 1.x/2.x components to a different base address
-- Generate FSP 1.x/2.x mapping C header file
+- Display FSP 2.0 information header
+- Split FSP 2.0 image into individual FSP-T/M/S/O component
+- Rebase FSP 2.0 components to a different base address
+- Generate FSP mapping C header file
"""
CopyRightHeaderFile = """/*
@@ -500,6 +500,8 @@ class FirmwareDevice:
fih = None
for fsp in self.FspList:
+if fsp.Fih.HeaderRevision < 3:
+raise Exception("ERROR: FSP 1.x is not supported by this tool
!")
if not fih:
fih = fsp.Fih
else:
@@ -711,8 +713,6 @@ def SplitFspBin (fspfile, outdir, nametemplate):
fd.ParseFsp ()
for fsp in fd.FspList:
-if fsp.Fih.HeaderRevision < 3:
-raise Exception("ERROR: FSP 1.x is not supported by the split
command !")
ftype = fsp.Type
if not nametemplate:
nametemplate = fspfile
@@ -742,11 +742,6 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
OutputDir, OutputFile):
found = False
for fsp in fd.FspList:
-# Is this FSP 1.x single binary?
-if fsp.Fih.HeaderRevision < 3:
-found = True
-ftype = 'X'
-break
ftype = fsp.Type.lower()
if ftype == fspcomp:
found = True
diff --git a/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
b/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
index 06d87bbb2e..064e0ac845 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
@@ -1,71 +1,68 @@
-# SplitFspBin.py is a python script to support some operations on Intel FSP
1.x/2.x image.
+# SplitFspBin.py is a python script to support some operations on Intel FSP
2.0 image.
It supports:
-- Split Intel FSP 2.x image into individual FSP-T/M/S/O component
+- Split Intel FSP 2.0 image into individual FSP-T/M/S/O component
-- Rebase Intel FSP 1.x/2.x components to different base addresses
+- Rebase Intel FSP 2.0 components to different base addresses
-- Generate Intel FSP 1.x/2.x C header file
+- Generate Intel FSP 2.0 C header file
-- Display Intel FSP 1.x/2.x information header for each FSP component
+- Display Intel FSP 2.0 information header for each FSP component
-## Split Intel FSP 2.x image
+## Split Intel FSP 2.0 image
-FSP 1.x image is not supported by split command.
-To split individual FSP component in Intel FSP 2.x image, the following
+To split individual FSP component in Intel FSP 2.0 image, the following
command can be used:
**python SplitFspBin.py split [-h] -f FSPBINARY [-o OUTPUTDIR] [-n
NAMETEMPLATE]**
-For example:
+For example:
`python SplitFspBin.py split -f FSP.bin`
It will create FSP_T.bin, FSP_M.bin and FSP_S.bin in current directory.
-## Rebase Intel FSP 1.x/2.x components
+## Rebase Intel FSP 2.0 components
-To rebase one or multiple FSP components in Intel FSP 1.x/2.x image, the
following
+To rebase one or multiple FSP components in Intel FSP 2.0 image, the following
command can be used:
**python SplitFspBin.py rebase [-h] -f FSPBINARY -c {t,m,s,o} [{t,m,s,o}
...] -b FSPBASE [FSPBASE ...] [-o OUTPUTDIR] [-n OUTPUTFILE]**
-For example:
+For example:
- `python SplitFspBin.py rebase -f FSP.bin -c t -b 0xFFF0 -n FSP_new.bin`
+ `python SplitFspBin.py rebase -f FSP.bin –c t –b 0xFFF0 –n FSP_new.bin`
It will rebase FSP-T component inside FSP.bin to new base 0xFFF0 and
save the
- rebased Intel FSP 2.x image into file FSP_new.bin.
- For FSP 1.x image there is only one component in binary so above command
also
- works for FSP 1.x image.
+ rebased Intel FSP 2.0
[edk2-devel] [PATCH] Revert "IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary." Will submit again after freeze done. This reverts commit 591b8cb7f3d026d2fa4483c59f3d5fb14be181bf.
Cc: Liming Gao
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Tools/SplitFspBin.py | 21
-
IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md | 47
++-
2 files changed, 30 insertions(+), 38 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index 15c8bebee2..2458231d09 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -1,6 +1,6 @@
## @ FspTool.py
#
-# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,12 +14,12 @@ import argparse
from ctypes import *
"""
-This utility supports some operations for Intel FSP 1.x/2.x image.
+This utility supports some operations for Intel FSP 2.0 image.
It supports:
-- Display FSP 1.x/2.x information header
-- Split FSP 2.x image into individual FSP-T/M/S/O component
-- Rebase FSP 1.x/2.x components to a different base address
-- Generate FSP 1.x/2.x mapping C header file
+- Display FSP 2.0 information header
+- Split FSP 2.0 image into individual FSP-T/M/S/O component
+- Rebase FSP 2.0 components to a different base address
+- Generate FSP mapping C header file
"""
CopyRightHeaderFile = """/*
@@ -500,6 +500,8 @@ class FirmwareDevice:
fih = None
for fsp in self.FspList:
+if fsp.Fih.HeaderRevision < 3:
+raise Exception("ERROR: FSP 1.x is not supported by this tool
!")
if not fih:
fih = fsp.Fih
else:
@@ -711,8 +713,6 @@ def SplitFspBin (fspfile, outdir, nametemplate):
fd.ParseFsp ()
for fsp in fd.FspList:
-if fsp.Fih.HeaderRevision < 3:
-raise Exception("ERROR: FSP 1.x is not supported by the split
command !")
ftype = fsp.Type
if not nametemplate:
nametemplate = fspfile
@@ -742,11 +742,6 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
OutputDir, OutputFile):
found = False
for fsp in fd.FspList:
-# Is this FSP 1.x single binary?
-if fsp.Fih.HeaderRevision < 3:
-found = True
-ftype = 'X'
-break
ftype = fsp.Type.lower()
if ftype == fspcomp:
found = True
diff --git a/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
b/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
index 06d87bbb2e..064e0ac845 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
@@ -1,71 +1,68 @@
-# SplitFspBin.py is a python script to support some operations on Intel FSP
1.x/2.x image.
+# SplitFspBin.py is a python script to support some operations on Intel FSP
2.0 image.
It supports:
-- Split Intel FSP 2.x image into individual FSP-T/M/S/O component
+- Split Intel FSP 2.0 image into individual FSP-T/M/S/O component
-- Rebase Intel FSP 1.x/2.x components to different base addresses
+- Rebase Intel FSP 2.0 components to different base addresses
-- Generate Intel FSP 1.x/2.x C header file
+- Generate Intel FSP 2.0 C header file
-- Display Intel FSP 1.x/2.x information header for each FSP component
+- Display Intel FSP 2.0 information header for each FSP component
-## Split Intel FSP 2.x image
+## Split Intel FSP 2.0 image
-FSP 1.x image is not supported by split command.
-To split individual FSP component in Intel FSP 2.x image, the following
+To split individual FSP component in Intel FSP 2.0 image, the following
command can be used:
**python SplitFspBin.py split [-h] -f FSPBINARY [-o OUTPUTDIR] [-n
NAMETEMPLATE]**
-For example:
+For example:
`python SplitFspBin.py split -f FSP.bin`
It will create FSP_T.bin, FSP_M.bin and FSP_S.bin in current directory.
-## Rebase Intel FSP 1.x/2.x components
+## Rebase Intel FSP 2.0 components
-To rebase one or multiple FSP components in Intel FSP 1.x/2.x image, the
following
+To rebase one or multiple FSP components in Intel FSP 2.0 image, the following
command can be used:
**python SplitFspBin.py rebase [-h] -f FSPBINARY -c {t,m,s,o} [{t,m,s,o}
...] -b FSPBASE [FSPBASE ...] [-o OUTPUTDIR] [-n OUTPUTFILE]**
-For example:
+For example:
- `python SplitFspBin.py rebase -f FSP.bin -c t -b 0xFFF0 -n FSP_new.bin`
+ `python SplitFspBin.py rebase -f FSP.bin –c t –b 0xFFF0 –n FSP_new.bin`
It will rebase FSP-T component inside FSP.bin to new base 0xFFF0 and
save the
- rebased Intel FSP 2.x image into file FSP_new.bin.
- For FSP 1.x image there is only one component in binary so above command
also
- works for FSP 1.x image.
+ rebased Intel FSP 2.0 image into file FSP_new.bin.
- `python SplitFspBin.py rebase -f FSP.bin -c t m -b 0xFFF0
Re: [edk2-devel] [PATCH 2/4] Platform/Intel:Add build parameter to support Binary Cache
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Fan, ZhijuX
> Sent: Friday, May 31, 2019 9:38 AM
> To: devel@edk2.groups.io
> Cc: Gao, Liming ; Feng, Bob C ;
> Shi, Steven ; Lu, Shifei A ;
> Zhou,
> Bowen ; Oram, Isaac W ;
> Chiu, Chasel ; Kubacki, Michael A
> ; Desimone, Nathaniel L
>
> Subject: [PATCH 2/4] Platform/Intel:Add build parameter to support Binary
> Cache
>
> BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1784
> BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1785
>
> Need extend the options in the Intel/build_bios.py file to support Binary
> Cache.
>
> --hash:
>Enable hash-based caching during build process.
> --binary-destination:
>Generate a cache of binary files in the specified directory.
> --binary-source:
>Consume a cache of binary files from the specified directory.
>
> Cc: Liming Gao
> Cc: Bob Feng
> Cc: Steven Shi
> Cc: Shifei A Lu
> Cc: Xiaohu Zhou
> Cc: Isaac W Oram
> Cc: Chasel Chiu
> Cc: Michael Kubacki
> Cc: Nate DeSimone
> Signed-off-by: Zhiju.Fan
> ---
> Platform/Intel/build_bios.py | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index
> 9f8d78f6e8..628b127417 100644
> --- a/Platform/Intel/build_bios.py
> +++ b/Platform/Intel/build_bios.py
> @@ -333,6 +333,7 @@ def build(config):
> print(" SILENT_MODE= ", config.get("SILENT_MODE"))
> print(" REBUILD_MODE = ", config.get("REBUILD_MODE"))
> print(" BUILD_ROM_ONLY = ", config.get("BUILD_ROM_ONLY"))
> +print(" BINARY_CACHE_CMD_LINE = ", config.get("HASH"),
> + config.get("BINARY_CACHE_CMD_LINE"))
> print("==")
>
> command = ["build", "-n", config["NUMBER_OF_PROCESSORS"]] @@
> -343,6 +344,10 @@ def build(config):
> if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "":
> command.append(config["EXT_BUILD_FLAGS"])
>
> +if config.get('BINARY_CACHE_CMD_LINE'):
> +command.append(config['HASH'])
> +command.append(config['BINARY_CACHE_CMD_LINE'])
> +
> if config.get("SILENT_MODE", "FALSE") == "TRUE":
> command.append("--silent")
> command.append("--quiet")
> @@ -848,6 +853,17 @@ def get_cmd_config_arguments(arguments):
> if arguments.fspapi is True:
> result["API_MODE_FSP_WRAPPER_BUILD"] = "TRUE"
>
> +if not arguments.UseHashCache:
> +result['BINARY_CACHE_CMD_LINE'] = ''
> +elif arguments.BinCacheDest:
> +result['HASH'] = '--hash'
> +result['BINARY_CACHE_CMD_LINE'] = '--binary-destination=%s' %
> arguments.BinCacheDest
> +elif arguments.BinCacheSource:
> +result['HASH'] = '--hash'
> +result['BINARY_CACHE_CMD_LINE'] = '--binary-source=%s' %
> arguments.BinCacheSource
> +else:
> +result['BINARY_CACHE_CMD_LINE'] = ''
> +
> return result
>
>
> @@ -924,6 +940,17 @@ def get_cmd_arguments(build_config):
> parser.add_argument("--fspapi", help="API mode fsp wrapper build
> enabled",
> action='store_true', dest="fspapi")
>
> +parser.add_argument("--hash", action="store_true",
> dest="UseHashCache", default=False,
> +help="Enable hash-based caching during build
> + process.")
> +
> +parser.add_argument("--binary-destination", help="Generate a cache of
> binary \
> +files in the specified directory.",
> +action='store', dest="BinCacheDest")
> +
> +parser.add_argument("--binary-source", help="Consume a cache of binary
> files \
> +from the specified directory.",
> +action='store', dest="BinCacheSource")
> +
> return parser.parse_args()
>
>
> --
> 2.14.1.windows.1
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Re: [edk2-devel] [PATCH 1/4] Intel/Readme.md:Add instructions about Binary Cache in Readme.md
Reviewed-by: Chasel Chiu > -Original Message- > From: Fan, ZhijuX > Sent: Friday, May 31, 2019 9:37 AM > To: devel@edk2.groups.io > Cc: Gao, Liming ; Feng, Bob C ; > Shi, Steven ; Lu, Shifei A ; > Zhou, > Bowen ; Oram, Isaac W ; > Chiu, Chasel ; Kubacki, Michael A > ; Desimone, Nathaniel L > > Subject: [PATCH 1/4] Intel/Readme.md:Add instructions about Binary Cache in > Readme.md > > BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1784 > BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1785 > > Add detailed instructions about Binary Cache in Readme.md, Extend options to > support Binary Cache in the Kabylake build bld.bat file, Purley build bld.bat > file, > build_bios.py > > Cc: Liming Gao > Cc: Bob Feng > Cc: Steven Shi > Cc: Shifei A Lu > Cc: Xiaohu Zhou > Cc: Isaac W Oram > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Nate DeSimone > Signed-off-by: Zhiju.Fan > --- > Platform/Intel/Readme.md | 11 +-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index > 443fb409b3..41ae99e8e6 100644 > --- a/Platform/Intel/Readme.md > +++ b/Platform/Intel/Readme.md > @@ -133,6 +133,9 @@ return back to the minimum platform caller. >| --silent | silent build enabled| >| --performance | performance build enabled | >| --fsp | fsp build enabled | > + | --hash| Enable hash-based caching | > + | --binary-destination | create cache in specified directory | > + | --binary-source | Consume cache from directory| >| | > > * For more information on build options @@ -191,14 +194,18 @@ For > KabylakeOpenBoardPkg 2. Type "cd > edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3". > 3. Type "GitEdk2MinKabylake.bat" to setup GIT environment. > 4. Type "prep" and make prebuild finish for debug build, "prep r" for release > build. > -5. Type "bld" to build Kaby Lake reference platform UEFI firmware image. > +5. Type "bld" to build Kaby Lake reference platform UEFI firmware image, "bld > cache-produce" Generate a cache of binary > + files in the specified directory, "bld cache-consume" Consume a cache of > binary files from the specified directory, > + BINARY_CACHE_PATH is empty, used "BinCache" as default path. > > For PurleyOpenBoardPkg > 1. Open command window, go to the workspace directory, e.g. c:\Purley. > 2. Type "cd > edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardMtOlympus". > 3. Type "GitEdk2MinMtOlympus.bat" to setup GIT environment. > 4. Type "bld" to build Purley Mt Olympus board UEFI firmware image, "bld > release" for release build, "bld clean" to > - remove intermediate files. > + remove intermediate files. "bld cache-produce" Generate a cache of binary > files in the specified directory, > + "bld cache-consume" Consume a cache of binary files from the specified > directory, BINARY_CACHE_PATH is empty, > + used "BinCache" as default path. > > The validated version of iasl compiler that can build MinPurley is 20180629. > Older version may generate ACPI build errors. > -- > 2.14.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41703): https://edk2.groups.io/g/devel/message/41703 Mute This Topic: https://groups.io/mt/31875851/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: FSP 2.1 SEC handling.
From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1865 To support FSP Dispatch mode, PlatformSecLib should consume FSP_TEMP_RAM_EXIT_PPI to disable temporary memory, and also report PeiCoreFvLocation PPI to SecMain so PeiCore form FSP-M can be launched. Test: API mode no impact and can still booted. Cc: Nate DeSimone Cc: Michael A Kubacki Cc: Sai Chaganty Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c | 186 ++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c | 47 +++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c | 89 + Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c | 78 ++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c | 36 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c | 73 + Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 ++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm | 130 ++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm | 361 + Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm | 72 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 97 + Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 2 +- 13 files changed, 1252 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c new file mode 100644 index 00..d73fc77f69 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c @@ -0,0 +1,186 @@ +/** @file + Provide FSP wrapper platform sec related function. + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/** + This interface conveys state information out of the Security (SEC) phase into PEI. + + @param[in] PeiServices Pointer to the PEI Services Table. + @param[in,out] StructureSize Pointer to the variable describing size of the input buffer. + @param[out]PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ); + +/** + This interface conveys performance information out of the Security (SEC) phase into PEI. + + This
[edk2-devel] [PATCH 0/2] Kabylake*Pkg: FSP 2.1 SEC handling.
To support Dispatch mode PlatformSecLib needs: 1. Report PeiCoreFvLocationPPI to SecMain so PeiCore from FSP-M can be loaded. 2. Consume FspTempRamExitPpi produced by FSP to disable temporary memory. 0001-KabylakeSiliconPkg: Add FspTempRamExitPpi 0002-KabylakeOpenBoardPkg: Report PeiCoreFvLocation and consume FspTempRamExitPpi Cc: Nate DeSimone Cc: Michael A Kubacki Cc: Sai Chaganty Signed-off-by: Chasel Chiu Chasel, Chiu (2): KabylakeSiliconPkg: FSP 2.1 SEC handling. KabylakeOpenBoardPkg: FSP 2.1 SEC handling. .../FspWrapperPlatformSecLib.c| 186 + .../PlatformInit.c| 47 +++ .../SecGetPerformance.c | 89 + .../SecPlatformInformation.c | 78 .../SecRamInitData.c | 36 ++ .../SecTempRamDone.c | 73 .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 ++ .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h| 42 ++ .../Ia32/PeiCoreEntry.nasm| 130 +++ .../Ia32/SecEntry.nasm| 361 ++ .../Ia32/Stack.nasm | 72 .../SecFspWrapperPlatformSecLib.inf | 97 + .../KabylakeRvp3/OpenBoardPkg.dsc | 2 +- .../KabylakeRvp3/OpenBoardPkg.fdf | 2 +- .../Include/Ppi/TempRamExitPpi.h | 50 +++ Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec| 2 + 16 files changed, 1305 insertions(+), 2 deletions(-) create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h -- 2.19.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41732): https://edk2.groups.io/g/devel/message/41732 Mute This Topic: https://groups.io/mt/31879181/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC handling.
From: "Chasel, Chiu"
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1865
To support FSP Dispatch mode, PlatformSecLib should
consume FSP_TEMP_RAM_EXIT_PPI to disable temporary
memory. This patch added the definition of this
FSP_TEMP_RAM_EXIT_PPI.
Test: API mode no impact and can still booted.
Cc: Nate DeSimone
Cc: Michael A Kubacki
Cc: Sai Chaganty
Signed-off-by: Chasel Chiu
---
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h | 50
++
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec| 2 ++
2 files changed, 52 insertions(+)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h
b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h
new file mode 100644
index 00..9e728a5d4d
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h
@@ -0,0 +1,50 @@
+/** @file
+ This file defines the Silicon Temp Ram Exit PPI which implements the
+ required programming steps for disabling temporary memory.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
+#define _FSP_TEMP_RAM_EXIT_PPI_H_
+
+///
+/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
+///
+#define FSP_TEMP_RAM_EXIT_GUID \
+ { \
+0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0,
0x52 } \
+ }
+
+//
+// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
+//
+typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
+
+/**
+ Silicon function for disabling temporary memory.
+ @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters
structure.
+ This structure is normally defined in the
Integration
+ Guide. If it is not defined in the
Integration Guide,
+ pass NULL.
+ @retval EFI_SUCCESS- Execution was completed successfully.
+ @retval Status - Error status reported by sub-functions if
implemented.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_EXIT) (
+ IN VOID*TempRamExitParamPtr
+ );
+
+///
+/// This PPI provides function to disable temporary memory.
+///
+struct _FSP_TEMP_RAM_EXIT_PPI {
+ FSP_TEMP_RAM_EXIT TempRamExit;
+};
+
+extern EFI_GUID gFspTempRamExitPpiGuid;
+
+#endif // _FSP_TEMP_RAM_EXIT_PPI_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
index a613079dd4..874cbee7a7 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
@@ -347,6 +347,8 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd,
0x447b, { 0x90, 0x64, 0x
##
gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84,
0x8c, 0x5e, 0x86, 0x70}}
gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1,
0x89, 0xd0, 0xab, 0x8d}}
+gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22,
0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
+
##
## SystemAgent
##
--
2.19.1.windows.1
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[edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP.
From: "Chasel, Chiu"
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1864
FSP Dispatch mode can consume DynamicEx PCD from
boot loader so it must include those PCD in PCD database
for FSP to consume.
PeiPostMemSiliconPolicyInitLib.inf (this is for FSP
Dispatch mode) has all PCDs included to ensure they can
be built into PCD database.
Also cleaned up unused PciExpress related
PCD from INFs.
Cc: Michael A Kubacki
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Chasel Chiu
---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
| 8 ++--
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
| 7 +--
Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
| 6 +-
Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
| 5 +++--
Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
| 3 +--
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
| 8 ++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf
| 7 +--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf
| 3 +--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf
| 3 +--
9 files changed, 25 insertions(+), 25 deletions(-)
diff --git
a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
index 51a06528e0..d99ee8e644 100644
---
a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
+++
b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
@@ -1,7 +1,7 @@
/** @file
This file contains routines that get PCI Express Address
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -27,5 +27,9 @@ MmPciBase (
{
ASSERT ((Bus <= 0xFF) && (Device <= 0x1F) && (Function <= 0x7));
- return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20) +
(UINTN) (Device << 15) + (UINTN) (Function << 12));
+#ifdef FSP_FLAG
+ return ((UINTN) PcdGet64 (PcdSiPciExpressBaseAddress) + (UINTN) (Bus << 20)
+ (UINTN) (Device << 15) + (UINTN) (Function << 12));
+#else
+ return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20)
+ (UINTN) (Device << 15) + (UINTN) (Function << 12));
+#endif
}
diff --git
a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
index 21d441a577..d2e813fea3 100644
---
a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
+++
b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
@@ -1,7 +1,7 @@
## @file
# Component description file for CPU Platform Lib
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -34,11 +34,6 @@ MdePkg/MdePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
KabylakeSiliconPkg/SiPkg.dec
-
-[Pcd]
-gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-
-
[Sources]
CpuPlatformLibrary.h
CpuPlatformLibrary.c
diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
index 5b114ae99e..aa481d0307 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
+++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
@@ -47,7 +47,11 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000
-gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x1000
+gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x1000
+#
+# This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress can
be FixedAtBuild
+#
+gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
[Defines]
PLATFORM_NAME = KabylakeSiliconPkg
diff --git
a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
index 8ae40a0c9e..02495953a7 100644
---
a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
+++
b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
@@ -1,7 +1,7 @@
## @file
# Component
[edk2-devel] [PATCH 0/2] Support DynamicExPCD from FSP
FSP Dispatch mode can consume DynamicEx PCDs from boot loader side so boot loader must build those PCDs into PcdDatabase. 0001-KabylakeSiliconPkg: Support DynamicExPCD from FSP. 0002-KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. Cc: Michael A Kubacki Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Chasel Chiu Chasel, Chiu (2): KabylakeSiliconPkg: Support DynamicExPCD from FSP. KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. .../PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c | 8 -- .../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 3 +-- .../KabylakeRvp3/OpenBoardPkg.dsc | 17 - .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 25 ++- .../PeiDxeSmmCpuPlatformLib.inf | 7 +- .../KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 6 - .../PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf | 5 ++-- .../Library/SiliconInitLib/SiliconInitLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec| 8 -- .../PeiDxeSmmSaPlatformLib.inf| 7 +- .../Library/PeiSaPolicyLib/PeiSaPolicyLib.inf | 3 +-- .../SystemAgent/SaInit/Dxe/SaInitDxe.inf | 3 +-- 12 files changed, 61 insertions(+), 34 deletions(-) -- 2.19.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41729): https://edk2.groups.io/g/devel/message/41729 Mute This Topic: https://groups.io/mt/31879156/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: Support DynamicExPCD from FSP.
From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1864 Cleaned up unused PciExpress related PCD from INF and remove unnecessary DEFINE from DSC. Defines some PCDs as different types per API mode or Dispatch mode, also enlarge PeiMemory for Dispatch mode as both FSP and boot loader shares the same PeiMemory. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 3 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 17 - Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc| 25 +++-- 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf index 9218c8fe67..8bc2f8729f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the ThunderBolt Smm module. # -# Copyright (c) 2018, Intel Corporation. All rights reserved. +# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ [Pcd] gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..8dbdf25787 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,6 @@ DEFINE PLATFORM_PACKAGE= MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE= AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg DEFINE BOARD = KabylakeRvp3 DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD) @@ -40,6 +39,22 @@ DEFINE PLATFORM_FSP_BIN_PACKAGE= AmberLakeFspBinPkg !endif +[PcdsDynamicExDefault.common.DEFAULT] +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == TRUE +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0 + # + # Include FSP DynamicEx PCD settings in Dispatch mode + # + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc + + # + # Override some FSP consumed PCD default value to match platform requirement. + # + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength +!endif +!endif + # # Defines Section - statements that will be processed to create a Makefile. diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index 63d0c4c2e6..fbd43a6947 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -48,7 +48,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000 gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF8 gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x0004 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF0 @@ -147,6 +147,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x80 gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE0 + ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild + # (They will be DynamicEx in FSP Dispatch mode) + # ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss
[edk2-devel] [PATCH v2] IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308
Support rebasing FSP 1.x binary.
FSP 1.x has single component in binary so not supported
by split command and rebase can be done with the same
command for rebasing FSP-T component in FSP 2.x image.
Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary
can be rebased successfully.
Cc: Maurice Ma
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Tools/SplitFspBin.py | 21
+
IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md | 47
+--
2 files changed, 38 insertions(+), 30 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index 2458231d09..15c8bebee2 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -1,6 +1,6 @@
## @ FspTool.py
#
-# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,12 +14,12 @@ import argparse
from ctypes import *
"""
-This utility supports some operations for Intel FSP 2.0 image.
+This utility supports some operations for Intel FSP 1.x/2.x image.
It supports:
-- Display FSP 2.0 information header
-- Split FSP 2.0 image into individual FSP-T/M/S/O component
-- Rebase FSP 2.0 components to a different base address
-- Generate FSP mapping C header file
+- Display FSP 1.x/2.x information header
+- Split FSP 2.x image into individual FSP-T/M/S/O component
+- Rebase FSP 1.x/2.x components to a different base address
+- Generate FSP 1.x/2.x mapping C header file
"""
CopyRightHeaderFile = """/*
@@ -500,8 +500,6 @@ class FirmwareDevice:
fih = None
for fsp in self.FspList:
-if fsp.Fih.HeaderRevision < 3:
-raise Exception("ERROR: FSP 1.x is not supported by this tool
!")
if not fih:
fih = fsp.Fih
else:
@@ -713,6 +711,8 @@ def SplitFspBin (fspfile, outdir, nametemplate):
fd.ParseFsp ()
for fsp in fd.FspList:
+if fsp.Fih.HeaderRevision < 3:
+raise Exception("ERROR: FSP 1.x is not supported by the split
command !")
ftype = fsp.Type
if not nametemplate:
nametemplate = fspfile
@@ -742,6 +742,11 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
OutputDir, OutputFile):
found = False
for fsp in fd.FspList:
+# Is this FSP 1.x single binary?
+if fsp.Fih.HeaderRevision < 3:
+found = True
+ftype = 'X'
+break
ftype = fsp.Type.lower()
if ftype == fspcomp:
found = True
diff --git a/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
b/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
index 064e0ac845..06d87bbb2e 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
@@ -1,68 +1,71 @@
-# SplitFspBin.py is a python script to support some operations on Intel FSP
2.0 image.
+# SplitFspBin.py is a python script to support some operations on Intel FSP
1.x/2.x image.
It supports:
-- Split Intel FSP 2.0 image into individual FSP-T/M/S/O component
+- Split Intel FSP 2.x image into individual FSP-T/M/S/O component
-- Rebase Intel FSP 2.0 components to different base addresses
+- Rebase Intel FSP 1.x/2.x components to different base addresses
-- Generate Intel FSP 2.0 C header file
+- Generate Intel FSP 1.x/2.x C header file
-- Display Intel FSP 2.0 information header for each FSP component
+- Display Intel FSP 1.x/2.x information header for each FSP component
-## Split Intel FSP 2.0 image
+## Split Intel FSP 2.x image
-To split individual FSP component in Intel FSP 2.0 image, the following
+FSP 1.x image is not supported by split command.
+To split individual FSP component in Intel FSP 2.x image, the following
command can be used:
**python SplitFspBin.py split [-h] -f FSPBINARY [-o OUTPUTDIR] [-n
NAMETEMPLATE]**
-For example:
+For example:
`python SplitFspBin.py split -f FSP.bin`
It will create FSP_T.bin, FSP_M.bin and FSP_S.bin in current directory.
-## Rebase Intel FSP 2.0 components
+## Rebase Intel FSP 1.x/2.x components
-To rebase one or multiple FSP components in Intel FSP 2.0 image, the following
+To rebase one or multiple FSP components in Intel FSP 1.x/2.x image, the
following
command can be used:
**python SplitFspBin.py rebase [-h] -f FSPBINARY -c {t,m,s,o} [{t,m,s,o}
...] -b FSPBASE [FSPBASE ...] [-o OUTPUTDIR] [-n OUTPUTFILE]**
-For example:
+For example:
- `python SplitFspBin.py rebase -f FSP.bin –c t –b 0xFFF0 –n FSP_new.bin`
+ `python SplitFspBin.py rebase -f FSP.bin -c t -b 0xFFF0 -n
Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspSplitBin.py: Support rebasing 1.x binary.
Yes. I will update the document.
Thanks!
Chasel
> -Original Message-
> From: Zeng, Star
> Sent: Wednesday, May 29, 2019 11:20 PM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: Ma, Maurice ; Desimone, Nathaniel L
> ; Zeng, Star
> Subject: RE: [PATCH] IntelFsp2Pkg/FspSplitBin.py: Support rebasing 1.x binary.
>
> Shouldn't the SplitFspBinUserManual.md also be updated?
>
>
> Thanks,
> Star
>
> > -Original Message-
> > From: Chiu, Chasel
> > Sent: Wednesday, May 29, 2019 10:33 PM
> > To: devel@edk2.groups.io
> > Cc: Ma, Maurice ; Desimone, Nathaniel L
> > ; Zeng, Star
> > Subject: [PATCH] IntelFsp2Pkg/FspSplitBin.py: Support rebasing 1.x binary.
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308
> >
> > Support rebasing FSP 1.X binary.
> >
> > Test: both FSP 2.X (Kabylake) and FSP 1.X (BroadwellDE) binary
> > can be rebased successfully.
> >
> > Cc: Maurice Ma
> > Cc: Nate DeSimone
> > Cc: Star Zeng
> > Signed-off-by: Chasel Chiu
> > ---
> > IntelFsp2Pkg/Tools/SplitFspBin.py | 21 +
> > 1 file changed, 13 insertions(+), 8 deletions(-)
> >
> > diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
> > b/IntelFsp2Pkg/Tools/SplitFspBin.py
> > index 2458231d09..15c8bebee2 100644
> > --- a/IntelFsp2Pkg/Tools/SplitFspBin.py
> > +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
> > @@ -1,6 +1,6 @@
> > ## @ FspTool.py
> > #
> > -# Copyright (c) 2015 - 2018, Intel Corporation. All rights
> > reserved.
> > +# Copyright (c) 2015 - 2019, Intel Corporation. All rights
> > +reserved.
> > # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -14,12
> > +14,12 @@ import argparse
> > from ctypes import *
> >
> > """
> > -This utility supports some operations for Intel FSP 2.0 image.
> > +This utility supports some operations for Intel FSP 1.x/2.x image.
> > It supports:
> > -- Display FSP 2.0 information header
> > -- Split FSP 2.0 image into individual FSP-T/M/S/O component
> > -- Rebase FSP 2.0 components to a different base address
> > -- Generate FSP mapping C header file
> > +- Display FSP 1.x/2.x information header
> > +- Split FSP 2.x image into individual FSP-T/M/S/O component
> > +- Rebase FSP 1.x/2.x components to a different base address
> > +- Generate FSP 1.x/2.x mapping C header file
> > """
> >
> > CopyRightHeaderFile = """/*
> > @@ -500,8 +500,6 @@ class FirmwareDevice:
> >
> > fih = None
> > for fsp in self.FspList:
> > -if fsp.Fih.HeaderRevision < 3:
> > -raise Exception("ERROR: FSP 1.x is not supported by this
> > tool !")
> > if not fih:
> > fih = fsp.Fih
> > else:
> > @@ -713,6 +711,8 @@ def SplitFspBin (fspfile, outdir, nametemplate):
> > fd.ParseFsp ()
> >
> > for fsp in fd.FspList:
> > +if fsp.Fih.HeaderRevision < 3:
> > +raise Exception("ERROR: FSP 1.x is not supported by the
> > + split command !")
> > ftype = fsp.Type
> > if not nametemplate:
> > nametemplate = fspfile
> > @@ -742,6 +742,11 @@ def RebaseFspBin (FspBinary, FspComponent,
> > FspBase, OutputDir, OutputFile):
> >
> > found = False
> > for fsp in fd.FspList:
> > +# Is this FSP 1.x single binary?
> > +if fsp.Fih.HeaderRevision < 3:
> > +found = True
> > +ftype = 'X'
> > +break
> > ftype = fsp.Type.lower()
> > if ftype == fspcomp:
> > found = True
> > --
> > 2.13.3.windows.1
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[edk2-devel] [PATCH] IntelFsp2Pkg/FspSplitBin.py: Support rebasing 1.x binary.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308
Support rebasing FSP 1.X binary.
Test: both FSP 2.X (Kabylake) and FSP 1.X (BroadwellDE) binary
can be rebased successfully.
Cc: Maurice Ma
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Tools/SplitFspBin.py | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index 2458231d09..15c8bebee2 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -1,6 +1,6 @@
## @ FspTool.py
#
-# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,12 +14,12 @@ import argparse
from ctypes import *
"""
-This utility supports some operations for Intel FSP 2.0 image.
+This utility supports some operations for Intel FSP 1.x/2.x image.
It supports:
-- Display FSP 2.0 information header
-- Split FSP 2.0 image into individual FSP-T/M/S/O component
-- Rebase FSP 2.0 components to a different base address
-- Generate FSP mapping C header file
+- Display FSP 1.x/2.x information header
+- Split FSP 2.x image into individual FSP-T/M/S/O component
+- Rebase FSP 1.x/2.x components to a different base address
+- Generate FSP 1.x/2.x mapping C header file
"""
CopyRightHeaderFile = """/*
@@ -500,8 +500,6 @@ class FirmwareDevice:
fih = None
for fsp in self.FspList:
-if fsp.Fih.HeaderRevision < 3:
-raise Exception("ERROR: FSP 1.x is not supported by this tool
!")
if not fih:
fih = fsp.Fih
else:
@@ -713,6 +711,8 @@ def SplitFspBin (fspfile, outdir, nametemplate):
fd.ParseFsp ()
for fsp in fd.FspList:
+if fsp.Fih.HeaderRevision < 3:
+raise Exception("ERROR: FSP 1.x is not supported by the split
command !")
ftype = fsp.Type
if not nametemplate:
nametemplate = fspfile
@@ -742,6 +742,11 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
OutputDir, OutputFile):
found = False
for fsp in fd.FspList:
+# Is this FSP 1.x single binary?
+if fsp.Fih.HeaderRevision < 3:
+found = True
+ftype = 'X'
+break
ftype = fsp.Type.lower()
if ftype == fspcomp:
found = True
--
2.13.3.windows.1
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[edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI.
From: "Chasel, Chiu"
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870
Basing on FSP modes the Fsp*WrapperPeim may not have
dependency on PolicyPpi, instead it should report
FSP-M or FPS-S FV to dispatcher so FSP can produce
DefaultPolicyInit PPIs.
A PEI policy update library was created to update
policy PPI basing on board configuration.
Test: Boot with FSP API mode successfully.
Cc: Michael A Kubacki
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Chasel Chiu
---
Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
| 564
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
| 50
++
Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
| 86
++
3 files changed, 700 insertions(+)
diff --git
a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
new file mode 100644
index 00..5cc7c03c61
--- /dev/null
+++
b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -0,0 +1,564 @@
+/** @file
+ Provides silicon policy update library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Get the next microcode patch pointer.
+
+ @param[in, out] MicrocodeData - Input is a pointer to the last microcode
patch address found,
+ and output points to the next patch address
found.
+
+ @retval EFI_SUCCESS - Patch found.
+ @retval EFI_NOT_FOUND - Patch not found.
+**/
+EFI_STATUS
+EFIAPI
+RetrieveMicrocode (
+ IN OUT CPU_MICROCODE_HEADER **MicrocodeData
+ )
+{
+ UINTNMicrocodeStart;
+ UINTNMicrocodeEnd;
+ UINTNTotalSize;
+
+ if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32
(PcdFlashMicrocodeFvSize) == 0)) {
+return EFI_NOT_FOUND;
+ }
+
+ ///
+ /// Microcode binary in SEC
+ ///
+ MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
+ ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32
(PcdFlashMicrocodeFvBase))->HeaderLength +
+ sizeof (EFI_FFS_FILE_HEADER);
+
+ MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN)
FixedPcdGet32 (PcdFlashMicrocodeFvSize);
+
+ if (*MicrocodeData == NULL) {
+*MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;
+ } else {
+if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) {
+ DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n"));
+ return EFI_NOT_FOUND;
+}
+
+TotalSize = (UINTN) ((*MicrocodeData)->TotalSize);
+if (TotalSize == 0) {
+ TotalSize = 2048;
+}
+
+*MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData +
TotalSize);
+if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) ||
(*MicrocodeData)->TotalSize == (UINT32) -1) {
+ DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n"));
+ return EFI_NOT_FOUND;
+}
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Get the microcode patch pointer.
+
+ @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if
not found.
+**/
+EFI_PHYSICAL_ADDRESS
+PlatformCpuLocateMicrocodePatch (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CPU_MICROCODE_HEADER *MicrocodeData;
+ EFI_CPUID_REGISTER Cpuid;
+ UINT32 UcodeRevision;
+ UINTNMicrocodeBufferSize;
+ VOID *MicrocodeBuffer = NULL;
+
+ AsmCpuid (
+CPUID_VERSION_INFO,
+,
+,
+,
+
+);
+
+ UcodeRevision = GetCpuUcodeRevision ();
+ MicrocodeData = NULL;
+ while (TRUE) {
+///
+/// Find the next patch address
+///
+Status = RetrieveMicrocode ();
+DEBUG
[edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI.
From: "Chasel, Chiu"
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870
FSP in dispatch mode will produce DefaultPolicyInit
PPI for boot loader to consume and install policy
with default settings built-in by FSP.
Boot loader then may patch policy with per-board
settings and then install PolicyReady PPI to start
silicon initialization (policy consumer code)
Since different version FSP has different version
policy structure, the policy revision check code has
been extended to support newer revision policy and
the policy structure boot loader consuming has been
aligned with the same structure inside FSP.
(FSP will maintain policy structure backward
compatibility)
Also removed microcode location searching code from
silicon scope because silicon code should not access
hard-coded flash region unconditionally.
This should be done by platform/boot loader side.
Cc: Michael A Kubacki
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Chasel Chiu
---
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
| 133
+++--
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
| 53
-
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
| 50
++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c
| 32
+---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c
| 39
+++
Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
| 6 +++---
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
| 4 ++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c
| 14 +++---
Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
| 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
| 4 +---
Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
| 32
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h
| 36
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
| 36
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
| 8 +---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h
| 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf
| 75
+++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf
=> PeiPreMemSiliconPolicyInitLib.inf} | 11 ---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
| 5 +++--
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf
| 1 +
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
| 4
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h
| 16 ++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf
| 3 ++-
22 files changed, 384 insertions(+), 186 deletions(-)
diff --git
a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
index cb7f379e0f..eb83cd4918 100644
---
[edk2-devel] [PATCH 0/2] Kabylake*Pkg: Support DefaultPolicyInit PPI.
FSP in dispatch mode will produce DefaultPolicyInit
PPI for boot loader to consume and install policy
with default settings built-in by FSP.
Boot loader then may patch policy with per-board
settings and then install PolicyReady PPI to start
silicon initialization (policy consumer code)
0001-KabylakeSiliconPkg: Add PPI definition and library
0002-KabylakeOpenBoardPkg: Link and add library instances
Cc: Michael A Kubacki
Cc: Sai Chaganty
Cc: Nate DeSimone
Signed-off-by: Chasel Chiu
Chasel, Chiu (2):
KabylakeSiliconPkg: Support DefaultPolicyInit PPI.
KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI.
Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
| 564
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
| 133
+++--
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
| 53
-
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
| 50
++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c
| 32
+---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c
| 39
+++
Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
| 6 +++---
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
| 4 ++--
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c
| 14 +++---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
| 50
++
Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
| 86
++
Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
| 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
| 4 +---
Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
| 32
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h
| 36
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
| 36
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
| 8 +---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h
| 4 +++-
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf
| 75
+++
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSiliconPolicyInitLib.inf
=> PeiPreMemSiliconPolicyInitLib.inf} | 11 ---
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
| 5 +++--
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf
|
[edk2-devel] [PATCH 0/2] Support DXE drivers in FSP 2.1.
In dispatch mode FSP-S contains DXE drivers to be dispatched by boot loader dispatcher. 0001-Intel/MinPlatformPkg: Report FSP-S to DXE dispatcher 0002-KabylakeOpenBoardPkg: Skip FspWrapperNotifyDxe Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu Chasel, Chiu (2): Intel/MinPlatformPkg: Support DXE drivers in FSP 2.1. KabylakeOpenBoardPkg: Support DXE drivers in FSP 2.1. Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c | 19 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 6 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 9 +++-- Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf | 5 - 4 files changed, 32 insertions(+), 7 deletions(-) -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41844): https://edk2.groups.io/g/devel/message/41844 Mute This Topic: https://groups.io/mt/31917293/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 1/2] Platform/Intel: Switch to FSP Dispatch mode.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1874
Build configuration is updated to support different
*FspBinPkg between FSP wrapper API and Dispatch modes.
Default will be Dispatch mode and to build FSP wrapper
for API mode:
"py -2 build_bios.py --platform KabylakeRvp3 --fspapi"
Cc: Michael Kubacki
Cc: Nate DeSimone
Cc: Liming Gao
Signed-off-by: Chasel Chiu
---
Platform/Intel/build_bios.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index 9f8d78f6e8..09eceddeff 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -125,6 +125,16 @@ def pre_build(build_config, build_type="DEBUG",
silent=False, toolchain=None):
config["BASE_TOOLS_PATH"] = config["EDK_TOOLS_PATH"]
config["EDK_TOOLS_BIN"] = os.path.join(config["WORKSPACE"],
config["EDK_TOOLS_BIN"])
+
+#
+# Board may have different FSP binary between API and Dispatch modes.
+# In API mode if FSP_BIN_PKG_FOR_API_MODE is assigned, it should
+# override FSP_BIN_PKG.
+#
+if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+if config.get("FSP_BIN_PKG_FOR_API_MODE") is not None:
+config['FSP_BIN_PKG'] = config['FSP_BIN_PKG_FOR_API_MODE']
+
config["PLATFORM_FSP_BIN_PACKAGE"] = \
os.path.join(config['WORKSPACE_FSP_BIN'], config['FSP_BIN_PKG'])
config['PROJECT_DSC'] = os.path.join(config["WORKSPACE_PLATFORM"],
--
2.13.3.windows.1
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[edk2-devel] [PATCH 0/2] Switch to FSP Dispatch mode.
KabylakeOpenBoardPkg is switched to build Dispatch mode as default. For building API mode: "py -2 build_bios.py --platform KabylakeRvp3 --fspapi" 0001-Platform/Intel: Separate FspBinPkg support. 0002-KabylakeOpenBoardPkg: Switch to dispatch mode. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu Chasel Chiu (2): Platform/Intel: Switch to FSP Dispatch mode. KabylakeOpenBoardPkg: Switch to FSP Dispatch mode. Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg| 5 +++-- Platform/Intel/build_bios.py | 10 ++ 3 files changed, 14 insertions(+), 3 deletions(-) -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41850): https://edk2.groups.io/g/devel/message/41850 Mute This Topic: https://groups.io/mt/31918435/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: Switch to FSP Dispatch mode.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1874 Now KabylakeOpenBoardPkg is building in FSP Dispatch mode as default. Test: Both FSP API and Dispatch mode can boot to Windows. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg| 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index 63d0c4c2e6..81244d7216 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -32,7 +32,7 @@ # 0: FSP Wrapper is running in Dispatch mode. # 1: FSP Wrapper is running in API mode. # - gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg index 64e02f7f48..bf89ea399c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg @@ -27,8 +27,9 @@ TARGET = DEBUG TARGET_SHORT = D PERFORMANCE_BUILD = FALSE FSP_WRAPPER_BUILD = TRUE -FSP_BIN_PKG = KabylakeFspBinPkg -FSP_PKG_NAME = KabylakeFspPkg +FSP_BIN_PKG = AmberLakeFspBinPkg +FSP_BIN_PKG_FOR_API_MODE = KabylakeFspBinPkg +FSP_PKG_NAME = AmberLakeFspPkg FSP_BINARY_BUILD = FALSE FSP_TEST_RELEASE = FALSE SECURE_BOOT_ENABLE = FALSE -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41852): https://edk2.groups.io/g/devel/message/41852 Mute This Topic: https://groups.io/mt/31918438/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC handling.
Yes. I will add TempRamExitPpi.h to IntelFsp2Pkg in separate review later.
Bugzilla filed: https://bugzilla.tianocore.org/show_bug.cgi?id=1883
Thanks!
Chasel
> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Thursday, June 6, 2019 3:53 AM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: Kubacki, Michael A ; Chaganty, Rangasai V
>
> Subject: RE: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC
> handling.
>
> Hi Chasel,
>
> FSP_TEMP_RAM_EXIT_PPI is defined by the FSP 2.1 specification. The definition
> for it should not go in KabyLakeSiliconPkg, it should be placed in
> IntelFsp2Pkg/Include/Ppi.
>
> Thanks,
> Nate
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chiu,
> Chasel
> Sent: Friday, May 31, 2019 4:43 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Kubacki, Michael A
> ; Chaganty, Rangasai V
>
> Subject: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC handling.
>
> From: "Chasel, Chiu"
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1865
>
> To support FSP Dispatch mode, PlatformSecLib should consume
> FSP_TEMP_RAM_EXIT_PPI to disable temporary memory. This patch added the
> definition of this FSP_TEMP_RAM_EXIT_PPI.
>
> Test: API mode no impact and can still booted.
>
> Cc: Nate DeSimone
> Cc: Michael A Kubacki
> Cc: Sai Chaganty
> Signed-off-by: Chasel Chiu
> ---
> Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h | 50
> ++
> Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec| 2 ++
> 2 files changed, 52 insertions(+)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h
> b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h
> new file mode 100644
> index 00..9e728a5d4d
> --- /dev/null
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h
> @@ -0,0 +1,50 @@
> +/** @file
> + This file defines the Silicon Temp Ram Exit PPI which implements the
> + required programming steps for disabling temporary memory.
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
> +#define _FSP_TEMP_RAM_EXIT_PPI_H_
> +
> +///
> +/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
> +///
> +#define FSP_TEMP_RAM_EXIT_GUID \
> + { \
> +0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c,
> +0xb0, 0x52 } \
> + }
> +
> +//
> +// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
> +//
> +typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
> +
> +/**
> + Silicon function for disabling temporary memory.
> + @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters
> structure.
> + This structure is normally defined in the
> Integration
> + Guide. If it is not defined in the
> Integration Guide,
> + pass NULL.
> + @retval EFI_SUCCESS- Execution was completed successfully.
> + @retval Status - Error status reported by sub-functions if
> implemented.
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *FSP_TEMP_RAM_EXIT) (
> + IN VOID*TempRamExitParamPtr
> + );
> +
> +///
> +/// This PPI provides function to disable temporary memory.
> +///
> +struct _FSP_TEMP_RAM_EXIT_PPI {
> + FSP_TEMP_RAM_EXIT TempRamExit;
> +};
> +
> +extern EFI_GUID gFspTempRamExitPpiGuid;
> +
> +#endif // _FSP_TEMP_RAM_EXIT_PPI_H_
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> index a613079dd4..874cbee7a7 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> @@ -347,6 +347,8 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115,
> 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid = {0xaebffa01,
> 0x7edc,
> 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}}
> gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1,
> 0x89, 0xd0, 0xab, 0x8d}}
> +gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87,
> 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
> +
> ##
> ## SystemAgent
> ##
> --
> 2.19.1.windows.1
>
>
>
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[edk2-devel] [PATCH] Platform/Intel: Dynamic NUMBER_OF_PROCESSORS in build.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1913 To improve build performance by default the maximum processors should be used for building. NUMBER_OF_PROCESSORS in build.cfg is set to 0 so BaseTools can utilize maximum processors for build. Test: tried NUMBER_OF_PROCESSORS 0 and 1 cases and confirmed the build time is half with 0 case. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/build.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index 6c23e5eabc..fc6e4fe824 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -46,7 +46,7 @@ FSP_TEST_RELEASE = FALSE SECURE_BOOT_ENABLE = FALSE REBUILD_MODE = BUILD_ROM_ONLY = -NUMBER_OF_PROCESSORS = 1 +NUMBER_OF_PROCESSORS = 0 [PLATFORMS] -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42346): https://edk2.groups.io/g/devel/message/42346 Mute This Topic: https://groups.io/mt/32049549/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2] Platform/Intel: Dynamic NUMBER_OF_PROCESSORS in build.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1913 To improve build performance by default the maximum processors should be used for building. NUMBER_OF_PROCESSORS in build.cfg is set to 0 so BaseTools can utilize maximum processors for build. Test: tried NUMBER_OF_PROCESSORS 0 and 1 cases and confirmed the build time is half with 0 case. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Cc: Bob Feng Signed-off-by: Chasel Chiu --- Platform/Intel/build.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index 6c23e5eabc..fc6e4fe824 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -46,7 +46,7 @@ FSP_TEST_RELEASE = FALSE SECURE_BOOT_ENABLE = FALSE REBUILD_MODE = BUILD_ROM_ONLY = -NUMBER_OF_PROCESSORS = 1 +NUMBER_OF_PROCESSORS = 0 [PLATFORMS] -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42347): https://edk2.groups.io/g/devel/message/42347 Mute This Topic: https://groups.io/mt/32050132/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] Platform/Intel: Dynamic NUMBER_OF_PROCESSORS in build.
Thanks Bob! I was not aware that BaseTools already handled this.
I just verified and it works so I will update code review which will only touch
build.cfg.
Thanks!
Chasel
> -Original Message-
> From: Feng, Bob C
> Sent: Thursday, June 13, 2019 3:39 PM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: Kubacki, Michael A ; Desimone, Nathaniel L
> ; Gao, Liming
> Subject: RE: [edk2-devel] [PATCH] Platform/Intel: Dynamic
> NUMBER_OF_PROCESSORS in build.
>
> Hi Chasel,
>
> Patch looks good.
>
> For the process number, build.py does the same thing as this patch. If pass
> -n 0 to
> build.py, build.py will set the processor number to
> multiprocessing.cpu_count()
>
> Thanks,
> Bob
>
>
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Chiu,
> Chasel
> Sent: Thursday, June 13, 2019 2:15 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A ; Desimone, Nathaniel L
> ; Gao, Liming
> Subject: [edk2-devel] [PATCH] Platform/Intel: Dynamic
> NUMBER_OF_PROCESSORS in build.
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1913
>
> To improve build performance by default the maximum processors should be
> used for building.
> To support this, NUMBER_OF_PROCESSORS in build.cfg has new definition:
> 0 = AUTO. Maximum of processors will be used.
> non-zero = limit or force the number of processors.
>
> Test: tried several NUMBER_OF_PROCESSORS settings and
> the build parameter can be updated accordingly
> also builds successfully.
>
> Cc: Michael Kubacki
> Cc: Nate DeSimone
> Cc: Liming Gao
> Signed-off-by: Chasel Chiu
> ---
> Platform/Intel/build.cfg | 2 +-
> Platform/Intel/build_bios.py | 8 +++-
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index
> 6c23e5eabc..fc6e4fe824 100644
> --- a/Platform/Intel/build.cfg
> +++ b/Platform/Intel/build.cfg
> @@ -46,7 +46,7 @@ FSP_TEST_RELEASE = FALSE SECURE_BOOT_ENABLE =
> FALSE REBUILD_MODE = BUILD_ROM_ONLY = -NUMBER_OF_PROCESSORS =
> 1
> +NUMBER_OF_PROCESSORS = 0
>
>
> [PLATFORMS]
> diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index
> 09eceddeff..864511ac4d 100644
> --- a/Platform/Intel/build_bios.py
> +++ b/Platform/Intel/build_bios.py
> @@ -21,6 +21,7 @@ import shutil
> import argparse
> import traceback
> import subprocess
> +import multiprocessing
> from importlib import import_module
>
> try:
> @@ -345,7 +346,12 @@ def build(config):
> print(" BUILD_ROM_ONLY = ", config.get("BUILD_ROM_ONLY"))
> print("==")
>
> -command = ["build", "-n", config["NUMBER_OF_PROCESSORS"]]
> +NumberOfProcessors = config["NUMBER_OF_PROCESSORS"]
> +if config["NUMBER_OF_PROCESSORS"] == "0":
> +# 0 means AUTO, maximum number of processors will be set
> +NumberOfProcessors = str(multiprocessing.cpu_count())
> +print ("Number of processors set to " + NumberOfProcessors)
> +command = ["build", "-n", NumberOfProcessors]
>
> if config["REBUILD_MODE"] and config["REBUILD_MODE"] != "":
> command.append(config["REBUILD_MODE"])
> --
> 2.13.3.windows.1
>
>
>
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[edk2-devel] [PATCH 1/2] Platform/Intel: Update Kabylake build steps.
https://bugzilla.tianocore.org/show_bug.cgi?id=1905 KabylakeOpenBoardPkg no longer supported batch file build, it only supports build_bios.py. ReadMe.md should be updated and batch files should be removed. Test: both API mode and Dispatch mode can build successfully by build_bios.py Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/Readme.md | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 443fb409b3..cc0151066e 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -101,7 +101,7 @@ return back to the minimum platform caller. * ``git clone https://github.com/tianocore/edk2-non-osi.git -b devel-MinPlatform`` * FSP repository - * ``git clone https://github.com/IntelFsp/FSP.git -b Kabylake`` + * ``git clone https://github.com/IntelFsp/FSP.git`` ### Build @@ -132,7 +132,8 @@ return back to the minimum platform caller. | --capsule | capsule build enabled | | --silent | silent build enabled| | --performance | performance build enabled | - | --fsp | fsp build enabled | + | --fsp | fsp wrapper build enabled | + | --fspapi | API mode fsp wrapper build enabled | | | * For more information on build options @@ -140,6 +141,8 @@ return back to the minimum platform caller. * Note * Python 2.7.16 and Python 3.7.3 compatible + * Some dependency Python scripts might only support 2.x or 3.x, if that happened use +"py -2" or "py -3" to launch build_bios.py * This python build script has been tested on Windows 10 and Ubuntu 16.04.5 LTS * See [cross-platform limitations](#Known-limitations) @@ -186,12 +189,7 @@ return back to the minimum platform caller. **Building with the batch scripts** -For KabylakeOpenBoardPkg -1. Open command window, go to the workspace directory, e.g. c:\Kabylake. -2. Type "cd edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3". -3. Type "GitEdk2MinKabylake.bat" to setup GIT environment. -4. Type "prep" and make prebuild finish for debug build, "prep r" for release build. -5. Type "bld" to build Kaby Lake reference platform UEFI firmware image. +KabylakeOpenBoardPkg does not support batch scripts, please use build_bios.py. For PurleyOpenBoardPkg 1. Open command window, go to the workspace directory, e.g. c:\Purley. -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42246): https://edk2.groups.io/g/devel/message/42246 Mute This Topic: https://groups.io/mt/32037607/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 0/2] Update Kabylake build steps.
KabylakeOpenBoardPkg no longer supported batch file build, it only supports build_bios.py. ReadMe.md should be updated and batch files should be removed. Test: both API mode and Dispatch mode can build successfully by build_bios.py Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu Chasel Chiu (2): Platform/Intel: Update Kabylake build steps. KabylakeOpenBoardPkg: Update Kabylake build steps. Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat | 79 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat| 159 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/cln.bat| 48 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/postbuild.bat | 39 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prebuild.bat | 215 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prep.bat | 79 --- Platform/Intel/Readme.md| 14 ++ 7 files changed, 6 insertions(+), 627 deletions(-) delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/cln.bat delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/postbuild.bat delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prebuild.bat delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prep.bat -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42245): https://edk2.groups.io/g/devel/message/42245 Mute This Topic: https://groups.io/mt/32037606/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: Update Kabylake build steps.
https://bugzilla.tianocore.org/show_bug.cgi?id=1905 Remove build batch files because they are obsolete. Use build_bios.py from now. Test: both API mode and Dispatch mode can build successfully by build_bios.py Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat | 79 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat| 159 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/cln.bat| 48 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/postbuild.bat | 39 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prebuild.bat | 215 --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prep.bat | 79 --- 6 files changed, 619 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat deleted file mode 100644 index 3bb13df80a..00 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat +++ /dev/null @@ -1,79 +0,0 @@ -@REM @file -@REM -@REM Copyright (c) 2017, Intel Corporation. All rights reserved. -@REM SPDX-License-Identifier: BSD-2-Clause-Patent -@REM - -@echo off - -pushd ..\..\..\..\..\ - -@REM Set WORKSPACE environment. -set WORKSPACE=%cd% -echo. -echo Set WORKSPACE as: %WORKSPACE% -echo. - -@REM Check whether Git has been installed and been added to system path. -git --help >nul 2>nul -if %ERRORLEVEL% NEQ 0 ( - echo. - echo The 'git' command is not recognized. - echo Please make sure that Git is installed and has been added to system path. - echo. - goto :EOF -) - -@REM Create the Conf directory under WORKSPACE -if not exist %WORKSPACE%\Conf ( - mkdir Conf -) - -@REM Set other environments. -@REM Basic Rule: -@REM Platform override Silicon override Core -@REM Source override Binary - -set PACKAGES_PATH=%WORKSPACE%\edk2-platforms\Platform\Intel;%WORKSPACE%\edk2-platforms\Silicon\Intel;%WORKSPACE%\edk2-non-osi\Silicon\Intel;%WORKSPACE%\FSP;%WORKSPACE%\edk2;%WORKSPACE% -set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 - -@if not defined PYTHON_HOME ( - @if exist C:\Python27 ( -set PYTHON_HOME=C:\Python27 - ) -) - -set EDK_SETUP_OPTION= -@rem if python is installed, disable the binary base tools. -if defined PYTHON_HOME ( - set EDK_TOOLS_BIN= - set EDK_SETUP_OPTION=--nt32 -) -pushd %WORKSPACE%\edk2 -call edksetup.bat %EDK_SETUP_OPTION% -popd -pushd %WORKSPACE% -@rem if python is installed, nmake BaseTools source and enable BaseTools source build -@if defined PYTHON_HOME ( - nmake -f %BASE_TOOLS_PATH%\Makefile -) -popd - -set openssl_path=%WORKSPACE% - -popd - -goto :EOF - -:Help -echo. -echo Usage: -echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] (optional) -echo. -echo -wA absolute/relative path to be the workspace. -echo Default value is the current directory. -echo. -echo -bThe branch name of the repository. Currently, only master, udk2015, -echo trunk (same as master) and bp13 (same as udk2015) are supported. -echo Default value is master. -echo. diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat deleted file mode 100644 index 449660b75d..00 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat +++ /dev/null @@ -1,159 +0,0 @@ -@REM @file -@REM -@REM Copyright (c) 2017, Intel Corporation. All rights reserved. -@REM SPDX-License-Identifier: BSD-2-Clause-Patent -@REM - -:: Useage: bld [/s] [/f ] [/r] -:: -:: For a given build command, 3 options may be passed into this batch file via command prompt: -:: 1) /s = Redirects all output to a file called EDK2.log(Prep.log must be existed), which will be located at the root. -:: 2) /f = Defines the passing in of a single override to a feature PCD that is used in the platform -::DSC file. If this parameter is used, it is to be followed immediately after by both the feature -::pcd name and value. FeaturePcd is the full PCD name, like gMinPlatformPkgTokenSpaceGuid.PcdOptimizeCompilerEnable -:: 3) /r = Useful for faster rebuilds when no changes have been made to .inf files. Passes -u to -::build.exe to skip the generation of makefiles. -:: 4) rom =
[edk2-devel] [PATCH v2] IntelFsp2Pkg: add TempRamExitPpi.h.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883
Add header file for FSP_TEMP_RAM_EXIT_PPI which is
defined by FSP 2.1 spec.
Test: Build successfully.
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h | 52
IntelFsp2Pkg/IntelFsp2Pkg.dec | 5 +
2 files changed, 57 insertions(+)
diff --git a/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
new file mode 100644
index 00..0db54dfa45
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
@@ -0,0 +1,52 @@
+/** @file
+ This file defines the Silicon Temp Ram Exit PPI which implements the
+ required programming steps for disabling temporary memory.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
+#define _FSP_TEMP_RAM_EXIT_PPI_H_
+
+///
+/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
+///
+#define FSP_TEMP_RAM_EXIT_GUID \
+ { \
+0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0,
0x52 } \
+ }
+
+//
+// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
+//
+typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
+
+/**
+ Silicon function for disabling temporary memory.
+ @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters
structure.
+ This structure is normally defined in the
Integration
+ Guide. If it is not defined in the
Integration Guide,
+ pass NULL.
+ @retval EFI_SUCCESS- FSP execution environment was initialized
successfully.
+ @retval EFI_INVALID_PARAMETER - Input parameters are invalid.
+ @retval EFI_UNSUPPORTED- The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR - Temporary memory exit.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_EXIT) (
+ IN VOID*TempRamExitParamPtr
+ );
+
+///
+/// This PPI provides function to disable temporary memory.
+///
+struct _FSP_TEMP_RAM_EXIT_PPI {
+ FSP_TEMP_RAM_EXIT TempRamExit;
+};
+
+extern EFI_GUID gFspTempRamExitPpiGuid;
+
+#endif // _FSP_TEMP_RAM_EXIT_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index cc17164742..ad2b7f7fb5 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -49,6 +49,11 @@
#
gFspInApiModePpiGuid = { 0xa1eeab87, 0xc859, 0x479d, {0x89,
0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}
+ #
+ # PPI to tear down the temporary memory set up by TempRamInit ().
+ #
+ gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87,
0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
+
[Guids]
#
# GUID defined in package
--
2.13.3.windows.1
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Re: [edk2-devel] [PATCH] IntelFsp2Pkg: add TempRamExitPpi.h.
Hi Star,
Since FspmArchConfigPpi.h also having Ppi postfix, we would like to align this
for TemPRamExitPpi.h in IntelFsp2Pkg.
Thanks!
Chasel
> -Original Message-
> From: Zeng, Star
> Sent: Monday, June 17, 2019 9:51 AM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: Desimone, Nathaniel L ; Zeng, Star
>
> Subject: RE: [edk2-devel] [PATCH] IntelFsp2Pkg: add TempRamExitPpi.h.
>
> And the 'Ppi' postfix seems not needed in the file name.
>
> Thanks,
> Star
>
> > -Original Message-
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Zeng, Star
> > Sent: Sunday, June 16, 2019 9:11 PM
> > To: Chiu, Chasel ; devel@edk2.groups.io
> > Cc: Desimone, Nathaniel L ; Zeng, Star
> >
> > Subject: Re: [edk2-devel] [PATCH] IntelFsp2Pkg: add TempRamExitPpi.h.
> >
> > Hi Chasel,
> >
> > Two minor feedbacks.
> >
> > 1. The spec defines the return status below, should we follow it?
> >
> > EFI_SUCCESS FSP execution environment was initialized successfully.
> > EFI_INVALID_PARAMETER Input parameters are invalid.
> > EFI_UNSUPPORTED The FSP calling conditions were not met.
> > EFI_DEVICE_ERROR Temporary memory exit.
> >
> >
> > 2. The gFspTempRamExitPpiGuid should be added into IntelFsp2Pkg.dec,
> > right?
> >
> >
> > Thanks,
> > Star
> >
> > > -Original Message-
> > > From: Chiu, Chasel
> > > Sent: Friday, June 14, 2019 5:56 PM
> > > To: devel@edk2.groups.io
> > > Cc: Desimone, Nathaniel L ; Zeng,
> > > Star
> > > Subject: [PATCH] IntelFsp2Pkg: add TempRamExitPpi.h.
> > >
> > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883
> > >
> > > Add header file for FSP_TEMP_RAM_EXIT_PPI which is defined by FSP
> > > 2.1 spec.
> > >
> > > Test: Build successfully.
> > >
> > > Cc: Nate DeSimone
> > > Cc: Star Zeng
> > > Signed-off-by: Chasel Chiu
> > > ---
> > > IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h | 50
> > > ++
> > > 1 file changed, 50 insertions(+)
> > >
> > > diff --git a/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
> > > b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
> > > new file mode 100644
> > > index 00..9e728a5d4d
> > > --- /dev/null
> > > +++ b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
> > > @@ -0,0 +1,50 @@
> > > +/** @file
> > > + This file defines the Silicon Temp Ram Exit PPI which implements
> > > +the
> > > + required programming steps for disabling temporary memory.
> > > +
> > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > > +SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +
> > > +**/
> > > +
> > > +#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
> > > +#define _FSP_TEMP_RAM_EXIT_PPI_H_
> > > +
> > > +///
> > > +/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
> > > +///
> > > +#define FSP_TEMP_RAM_EXIT_GUID \
> > > + { \
> > > +0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9,
> > > +0x0c, 0xb0,
> > > 0x52 } \
> > > + }
> > > +
> > > +//
> > > +// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
> > > +//
> > > +typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
> > > +
> > > +/**
> > > + Silicon function for disabling temporary memory.
> > > + @param[in] TempRamExitParamPtr - Pointer to the TempRamExit
> > > parameters structure.
> > > + This structure is normally defined in
> > > the
> Integration
> > > + Guide. If it is not defined in the
> > > Integration
> Guide,
> > > + pass NULL.
> > > + @retval EFI_SUCCESS- Execution was completed successfully.
> > > + @retval Status - Error status reported by
> > > sub-functions if
> > > implemented.
> > > +**/
> > > +typedef
> > > +EFI_STATUS
> > > +(EFIAPI *FSP_TEMP_RAM_EXIT) (
> > > + IN VOID*TempRamExitParamPtr
> > > + );
> > > +
> > > +///
> > > +/// This PPI provides function to disable temporary memory.
> > > +///
> > > +struct _FSP_TEMP_RAM_EXIT_PPI {
> > > + FSP_TEMP_RAM_EXIT TempRamExit;
> > > +};
> > > +
> > > +extern EFI_GUID gFspTempRamExitPpiGuid;
> > > +
> > > +#endif // _FSP_TEMP_RAM_EXIT_PPI_H_
> > > --
> > > 2.13.3.windows.1
> >
> >
> >
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Re: [edk2-devel] [edk2-platform patch 3/4] KabylakeOpenBoardPkg: Update FDF to use the generic Microcode FFS rule
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Gao, Liming
> Sent: Tuesday, June 11, 2019 1:04 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
>
> Subject: [edk2-platform patch 3/4] KabylakeOpenBoardPkg: Update FDF to use
> the generic Microcode FFS rule
>
> Signed-off-by: Liming Gao
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> ---
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 4
> +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> index 0cff53e308..0f95ee7942 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> @@ -203,9 +203,7 @@ READ_STATUS= FALSE
> READ_LOCK_CAP = TRUE
> READ_LOCK_STATUS = TRUE
>
> -FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
> -
> $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpd
> ates.bin
> -}
> +INF RuleOverride = MICROCODE
> $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
>
> [FV.FvPreMemory]
> BlockSize = $(FLASH_BLOCK_SIZE)
> --
> 2.13.0.windows.1
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Re: [edk2-devel][Patch] IntelFspPkg: Remove them
Just committed this fix. https://edk2.groups.io/g/devel/topic/31860753#41659 Thanks! Chasel > -Original Message- > From: Desimone, Nathaniel L > Sent: Thursday, June 6, 2019 1:59 PM > To: Ni, Ray ; Chiu, Chasel ; Zeng, > Star > > Cc: devel@edk2.groups.io > Subject: RE: [edk2-devel][Patch] IntelFspPkg: Remove > them > > Please commit Chasel's fix for > https://edk2.groups.io/g/devel/topic/31860753#41659 > > Once Chasel's fix is committed... > > Reviewed-by: Nate DeSimone > > -Original Message- > From: Ni, Ray > Sent: Thursday, May 16, 2019 1:38 AM > To: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Cc: devel@edk2.groups.io > Subject: [edk2-devel][Patch] IntelFspPkg: Remove them > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1819 > > Since there are V2 FSP packages (IntelFsp2Pkg, IntelFsp2WrapperPkg), this > patch > removes IntelFspPkg, IntelFspWrapperPkg to remove obsolete code in edk2 > repo. > > Signed-off-by: Ray Ni > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > -- > NOTE: This patch is to completely remove IntelFspPkg and IntelFspWrapperPkg > folder in edk2 repo. > I don't want to flood people's inbox with a big patch just removing every > line of > code in this two packages. > > The patch that modifies Maintainers.txt will be sent out later after > IntelFspPkg > and IntelFspWrapperPkg are removed. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42179): https://edk2.groups.io/g/devel/message/42179 Mute This Topic: https://groups.io/mt/31638674/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI.
Hi Ray, Please see my reply below inline. Thanks! Chasel > -Original Message- > From: Ni, Ray > Sent: Tuesday, June 11, 2019 10:11 AM > To: devel@edk2.groups.io; Desimone, Nathaniel L > ; Chiu, Chasel > Cc: Kubacki, Michael A ; Chaganty, Rangasai V > > Subject: RE: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support > DefaultPolicyInit PPI. > > Chasel, > Where is the code that produces DefaultPolicyInit PPI? > Is the code public available? Only DefaultPolicyInit PPI definition public, no producer code in KabylakeSiliconPkg. The producer code of DefaultPolicyInit PPI is inside FSP binary so it can produce different ConfigBlock structures from different FSP binary, and ConfigBlocks in KabylakeSiliconPkg is only for boot loader to fill UPD buffer in API mode, it is not used in Dispatch mode. > > And in general, I think the patch consists of several changes: > 1. change version compare from "==" to ">=" to support FSP be used in newer > board. > 2. Add definition of SiDefaultPolicyPpi > 3. Update non-FSP version of PeiSiliconPolicyInitLib to consume the > SiDefaultPolicyPpi > 4. Update config block for GFX > 5. Add SiXXXInstallPolicyReadyPpi > 6. maybe more > > Can you please try to separate the changes to small patches? Yes. I will follow this suggestion next time working on big change. > > Regarding to the changes in > KabylakeSiliconPkg\Library\PeiSiPolicyLib\PeiSiPolicyLibPreMem.c: > There are two APIs: SiPreMemInstallPolicyPpi and > SiPreMemInstallPolicyReadyPpi. > > When FSP runs in API mode, the calling flow is as below: > FspWrapperPeim::PeiMemoryDiscoveredNotify > --> MinPlatformPkg/../PeiFspWrapperPlatformLib::UpdateFspsUpdData > --> KabylakeSiliconPkg/.../SiliconPolicyInitPostMem > --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiCreateConfigBlocks > --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiInstallPolicyPpi > > Do you think that it's possible to update > KabylakeSiliconPkg/.../SiliconPolicyInitPostMem() to > call SiDefaultPolicyInitPpi->PeiPolicyInit()? To align the behavior when FSP > runs > in dispatch mode. The actual policy initialization flows are aligned between API mode and Dispatch mode: SiliconPolicyPeiPostMem.efi: SiliconPolicyInitPostMem () -> SiliconPolicyUpdatePostMem () -> SiliconPolicyDonePostMem (). Only the library instances are different: FSP Wrapper running in Dispatch mode: \Silicon\Intel\KabylakeSiliconPkg\Library\PeiSiliconPolicyInitLib\PeiPolicyInit.c (Initialize ConfigBlocks policy) FSP Wrapper running in API mode: \Silicon\Intel\KabylakeSiliconPkg\Library\PeiSiliconPolicyInitLibFsp\PeiFspPolicyInitLib.c (Initialize ConfigBlocks policy first and then fill into UPD buffer) Also when running API mode the PPI produced by FSP binary - "SiDefaultPolicyInitPpi->PeiPolicyInit()" cannot be seen by boot loader as they are running with different PeiCore stacks. > > Thanks, > Ray > > > -Original Message- > > From: devel@edk2.groups.io On Behalf Of Nate > > DeSimone > > Sent: Thursday, June 6, 2019 5:44 PM > > To: Chiu, Chasel ; devel@edk2.groups.io > > Cc: Kubacki, Michael A ; Chaganty, Rangasai V > > > > Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support > > DefaultPolicyInit PPI. > > > > Reviewed-by: Nate DeSimone > > > > -Original Message- > > From: Chiu, Chasel > > Sent: Monday, June 3, 2019 9:47 AM > > To: devel@edk2.groups.io > > Cc: Chiu, Chasel ; Kubacki, Michael A > > ; Chaganty, Rangasai V > > ; Desimone, Nathaniel L > > > > Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. > > > > From: "Chasel, Chiu" > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870 > > > > FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loader to > > consume and install policy with default settings built-in by FSP. > > Boot loader then may patch policy with per-board settings and then install > > PolicyReady PPI to start silicon initialization (policy consumer code) > > > > Since different version FSP has different version policy structure, the > > policy > > revision check code has been extended to support newer revision policy and > > the policy structure boot loader consuming has been aligned with the same > > structure inside FSP. > > (FSP will maintain policy structure backward > > compatibility) > > > > Also removed microcode location searching code from silicon scope because > > silicon code should not access hard-coded flash region unconditionally. > > This should be d
Re: [edk2-devel] [PATCH 1/2] Intel/MinPlatformPkg: Support DXE drivers in FSP 2.1.
Agreed.
Bugzilla filed for enhancement:
https://bugzilla.tianocore.org/show_bug.cgi?id=1892
Thanks!
Chasel
> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Thursday, June 6, 2019 5:54 PM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: Kubacki, Michael A ; Gao, Liming
>
> Subject: RE: [PATCH 1/2] Intel/MinPlatformPkg: Support DXE drivers in FSP 2.1.
>
> The FSP specification allows FSP-S to contain an arbitrary number of Firmware
> Volumes. Your attached patch makes the assumption that it only contains one.
> I'm OK if you decide to commit this as-is for now since it is better than
> nothing,
> but I expect a Bugzilla to be filed to fix the 1 FV assumption.
>
> Reviewed-by: Nate DeSimone
>
> -Original Message-
> From: Chiu, Chasel
> Sent: Monday, June 3, 2019 5:53 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
> ; Desimone, Nathaniel L
> ; Gao, Liming
> Subject: [PATCH 1/2] Intel/MinPlatformPkg: Support DXE drivers in FSP 2.1.
>
> From: "Chasel, Chiu"
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1873
>
> In dispatch mode FSP-S contains DXE drivers so needs to BuildFvHob for DXE
> dispatcher to dispatch this FV.
>
> Test: FSP API mode still boots successfully without impact.
>
> Cc: Michael Kubacki
> Cc: Nate DeSimone
> Cc: Liming Gao
> Signed-off-by: Chasel Chiu
> ---
>
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProce
> ssLib/FspWrapperHobProcessLib.c | 19 ---
>
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProce
> ssLib/PeiFspWrapperHobProcessLib.inf | 5 -
> 2 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobPro
> cessLib/FspWrapperHobProcessLib.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobPro
> cessLib/FspWrapperHobProcessLib.c
> index e8df06dfb7..7ee4d3a31c 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobPro
> cessLib/FspWrapperHobProcessLib.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobP
> +++ rocessLib/FspWrapperHobProcessLib.c
> @@ -1,7 +1,7 @@
> /** @file
>Provide FSP wrapper hob process related function.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -653,8 +653,21 @@ PostFspsHobProcess ( {
>EFI_STATUS Status;
>
> - ProcessFspHobList (FspHobList);
> -
> + if (PcdGet8 (PcdFspModeSelection) == 1) {
> +//
> +// Only in FSP API mode the wrapper has to build hobs basing on FSP
> output
> data.
> +//
> +ASSERT (FspHobList != NULL);
> +ProcessFspHobList (FspHobList);
> + } else {
> +//
> +// Only in FSP Dispatch mode, FSP-S should be reported to DXE dispatcher.
> +//
> +BuildFvHob (
> + (EFI_PHYSICAL_ADDRESS) (UINTN) PcdGet32 (PcdFlashFvFspSBase),
> + PcdGet32 (PcdFlashFvFspSSize)
> + );
> + }
>CheckFspGraphicsDeviceInfoHob ();
>DEBUG_CODE_BEGIN ();
> DumpFspSmbiosMemoryInfoHob ();
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobPro
> cessLib/PeiFspWrapperHobProcessLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobPro
> cessLib/PeiFspWrapperHobProcessLib.inf
> index a76e3195d6..64f3302959 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobPro
> cessLib/PeiFspWrapperHobProcessLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobP
> +++ rocessLib/PeiFspWrapperHobProcessLib.inf
> @@ -1,7 +1,7 @@
> ## @file
> # Provide FSP wrapper hob process related function.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -65,6 +65,9 @@
>gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
>gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
>gMinPlatformPkgTokenSpaceGuid.PcdFspCpuPeiApWakeupBufferAddr
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
>
> [Guids]
>gFspReservedMemoryResourceHobGuid ## CONSUMES ##
> HOB
> --
> 2.13.3.windows.1
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[edk2-devel] [PATCH] KabylakeOpenBoardPkg: Remove PeiMain for Dispatch mode.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1916 In Dispatch mode PeiMain from FSP Binary will be launched so the one from boot loader can be removed. Test: Verified the PeiMain is removed in Dispatch mode and included in API mode. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index 007cb4b28f..abafd8e44d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -226,7 +226,13 @@ READ_LOCK_STATUS = TRUE FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D INF UefiCpuPkg/SecCore/SecCore.inf +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) +# +# PeiMain is needed only for FSP API mode or EDK2 build, +# in FSP dispatch mode the one inside FSP Binary is launched. +# INF MdeModulePkg/Core/Pei/PeiMain.inf +!endif !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42423): https://edk2.groups.io/g/devel/message/42423 Mute This Topic: https://groups.io/mt/32061785/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: add TempRamExitPpi.h.
Hi Ray,
Currently we prefer to duplicate header files so we do not have IntelFsp2Pkg
dependency for non-FSP build.
We will review for how to support FSP/non-FSP builds better.
Thanks!
Chasel
> -Original Message-
> From: Ni, Ray
> Sent: Monday, June 17, 2019 11:27 AM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: Desimone, Nathaniel L ; Zeng, Star
>
> Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2Pkg: add TempRamExitPpi.h.
>
> Chasel,
> I found another instance of this PPI in
> edk2-platforms/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi.
> Will you remove that one after this is checked in?
>
>
> Thanks,
> Ray
>
> > -Original Message-
> > From: devel@edk2.groups.io On Behalf Of Chiu,
> > Chasel
> > Sent: Monday, June 17, 2019 10:42 AM
> > To: devel@edk2.groups.io
> > Cc: Desimone, Nathaniel L ; Zeng, Star
> >
> > Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: add TempRamExitPpi.h.
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883
> >
> > Add header file for FSP_TEMP_RAM_EXIT_PPI which is defined by FSP 2.1
> > spec.
> >
> > Test: Build successfully.
> >
> > Cc: Nate DeSimone
> > Cc: Star Zeng
> > Signed-off-by: Chasel Chiu
> > ---
> > IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h | 52
> >
> > IntelFsp2Pkg/IntelFsp2Pkg.dec | 5 +
> > 2 files changed, 57 insertions(+)
> >
> > diff --git a/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
> > b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
> > new file mode 100644
> > index 00..0db54dfa45
> > --- /dev/null
> > +++ b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
> > @@ -0,0 +1,52 @@
> > +/** @file
> > + This file defines the Silicon Temp Ram Exit PPI which implements
> > +the
> > + required programming steps for disabling temporary memory.
> > +
> > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > +SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
> > +#define _FSP_TEMP_RAM_EXIT_PPI_H_
> > +
> > +///
> > +/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
> > +///
> > +#define FSP_TEMP_RAM_EXIT_GUID \
> > + { \
> > +0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c,
> > +0xb0, 0x52 } \
> > + }
> > +
> > +//
> > +// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
> > +//
> > +typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
> > +
> > +/**
> > + Silicon function for disabling temporary memory.
> > + @param[in] TempRamExitParamPtr - Pointer to the TempRamExit
> > parameters structure.
> > + This structure is normally defined in
> > the
> Integration
> > + Guide. If it is not defined in the
> > Integration Guide,
> > + pass NULL.
> > + @retval EFI_SUCCESS- FSP execution environment was
> > initialized
> > successfully.
> > + @retval EFI_INVALID_PARAMETER - Input parameters are invalid.
> > + @retval EFI_UNSUPPORTED- The FSP calling conditions were not
> met.
> > + @retval EFI_DEVICE_ERROR - Temporary memory exit.
> > +**/
> > +typedef
> > +EFI_STATUS
> > +(EFIAPI *FSP_TEMP_RAM_EXIT) (
> > + IN VOID*TempRamExitParamPtr
> > + );
> > +
> > +///
> > +/// This PPI provides function to disable temporary memory.
> > +///
> > +struct _FSP_TEMP_RAM_EXIT_PPI {
> > + FSP_TEMP_RAM_EXIT TempRamExit;
> > +};
> > +
> > +extern EFI_GUID gFspTempRamExitPpiGuid;
> > +
> > +#endif // _FSP_TEMP_RAM_EXIT_PPI_H_
> > diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec
> > b/IntelFsp2Pkg/IntelFsp2Pkg.dec index cc17164742..ad2b7f7fb5 100644
> > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
> > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
> > @@ -49,6 +49,11 @@
> >#
> >gFspInApiModePpiGuid = { 0xa1eeab87, 0xc859, 0x479d,
> {0x89,
> > 0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}
> >
> > + #
> > + # PPI to tear down the temporary memory set up by TempRamInit ().
> > + #
> > + gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87,
> > 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
> > +
> > [Guids]
> >#
> ># GUID defined in package
> > --
> > 2.13.3.windows.1
> >
> >
> >
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[edk2-devel] [PATCH] IntelFsp2Pkg: FSP Python scripts to support 3.x.
https://bugzilla.tianocore.org/show_bug.cgi?id=1930
Updated FSP Python scripts to support both 2.x and
3.x.
Test:
. Verified with Python 2.7.12 and 3.6.6.
. Verified tool result is the same before the change.
. Both py -2 and py -3 built binary can boot.
Cc: Maurice Ma
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Tools/GenCfgOpt.py | 70
++
IntelFsp2Pkg/Tools/PatchFv.py | 36 +++-
IntelFsp2Pkg/Tools/SplitFspBin.py | 74
+++---
3 files changed, 116 insertions(+), 64 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 450c4e3eb9..e0441966ac 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -1,6 +1,6 @@
## @ GenCfgOpt.py
#
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -10,6 +10,7 @@ import re
import sys
import struct
from datetime import date
+from functools import reduce
# Generated file copyright header
@@ -90,11 +91,11 @@ class CLogicalExpression:
self.string = ''
def errExit(self, err = ''):
-print "ERROR: Express parsing for:"
-print " %s" % self.string
-print " %s^" % (' ' * self.index)
+print ("ERROR: Express parsing for:")
+print (" %s" % self.string)
+print (" %s^" % (' ' * self.index))
if err:
-print "INFO : %s" % err
+print ("INFO : %s" % err)
raise SystemExit
def getNonNumber (self, n1, n2):
@@ -338,15 +339,15 @@ EndList
else:
Error = 0
if self.Debug:
-print "INFO : Macro dictionary:"
+print ("INFO : Macro dictionary:")
for Each in self._MacroDict:
-print " $(%s) = [ %s ]" % (Each ,
self._MacroDict[Each])
+print (" $(%s) = [ %s ]" % (Each ,
self._MacroDict[Each]))
return Error
def EvaulateIfdef (self, Macro):
Result = Macro in self._MacroDict
if self.Debug:
-print "INFO : Eval Ifdef [%s] : %s" % (Macro, Result)
+print ("INFO : Eval Ifdef [%s] : %s" % (Macro, Result))
return Result
def ExpandMacros (self, Input):
@@ -359,7 +360,7 @@ EndList
Line = Line.replace(Each, self._MacroDict[Variable])
else:
if self.Debug:
- print "WARN : %s is not defined" % Each
+ print ("WARN : %s is not defined" % Each)
Line = Line.replace(Each, Each[2:-1])
return Line
@@ -372,7 +373,7 @@ EndList
Line = Line.replace(PcdName, self._PcdsDict[PcdName])
else:
if self.Debug:
- print "WARN : %s is not defined" % PcdName
+ print ("WARN : %s is not defined" % PcdName)
return Line
def EvaluateExpress (self, Expr):
@@ -381,7 +382,7 @@ EndList
LogExpr = CLogicalExpression()
Result = LogExpr.evaluateExpress (ExpExpr)
if self.Debug:
-print "INFO : Eval Express [%s] : %s" % (Expr, Result)
+print ("INFO : Eval Express [%s] : %s" % (Expr, Result))
return Result
def FormatListValue(self, ConfigDict):
@@ -406,9 +407,14 @@ EndList
bytearray = []
for each in dataarray:
value = each
-for loop in xrange(unit):
-bytearray.append("0x%02X" % (value & 0xFF))
-value = value >> 8
+if sys.version_info < (3,0):
+for loop in xrange(unit):
+bytearray.append("0x%02X" % (value & 0xFF))
+value = value >> 8
+else:
+for loop in range(int(unit)):
+bytearray.append("0x%02X" % (value & 0xFF))
+value = value >> 8
newvalue = '{' + ','.join(bytearray) + '}'
ConfigDict['value'] = newvalue
return ""
@@ -548,7 +554,7 @@ EndList
if Match:
self._MacroDict[Match.group(1)] = Match.group(2)
if self.Debug:
-print "INFO : DEFINE %s = [ %s ]" % (Match.group(1),
Match.group(2))
+print ("INFO : DEFINE %s = [ %s ]" % (Match.group(1),
Match.group(2)))
elif IsPcdSect:
#gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE
#gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
@@ -556,7 +562,7 @@ EndList
if Match:
self._PcdsDict[Match.group(1)] = Match.group(2)
[edk2-devel] [PATCH] MinPlatformPkg: FSP Python script to python 3.x.
https://bugzilla.tianocore.org/show_bug.cgi?id=1930
Updated FSP Python script to support both 2.x and
3.x.
Test:
. Verified with Python 2.7.12 and 3.6.6.
. Verified tool result is the same before the change.
. Both py -2 and py -3 built binary can boot.
Cc: Michael Kubacki
Cc: Nate DeSimone
Cc: Liming Gao
Signed-off-by: Chasel Chiu
---
Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py |
34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git
a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
index 167a0e0a4c..406e5ec130 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
@@ -10,16 +10,16 @@ import re
import subprocess
if len(sys.argv) not in [6,7]:
- print "RebaseAndPatchFspBinBaseAddress.py - Error in number of arguments
received"
- print "Usage - RebaseAndPatchFspBinBaseAddress.py
\
-"
+ print ("RebaseAndPatchFspBinBaseAddress.py - Error in number of arguments
received")
+ print ("Usage - RebaseAndPatchFspBinBaseAddress.py
\
+")
exit(1)
flashMapName = sys.argv[1]
fspBinPath= sys.argv[2]
fspBinFile= sys.argv[3]
targetDscFile = sys.argv[4]
-fvOffset = long(sys.argv[5], 16)
+fvOffset = int(sys.argv[5], 16)
fspBinFileRebased = "Fsp_Rebased.fd"
splitFspBinPath =
os.path.join("edk2","IntelFsp2Pkg","Tools","SplitFspBin.py")
@@ -30,21 +30,21 @@ if len(sys.argv) == 7:
# Make sure argument passed or valid
#
if not os.path.exists(flashMapName):
- print "WARNING! " + str(flashMapName) + " is not found."
+ print ("WARNING! " + str(flashMapName) + " is not found.")
exit(1)
fspBinFilePath = fspBinPath + os.sep + fspBinFile
if not os.path.exists(fspBinFilePath):
- print "WARNING! " + str(fspBinFilePath) + " is not found."
+ print ("WARNING! " + str(fspBinFilePath) + " is not found.")
exit(1)
if not os.path.exists(targetDscFile):
- print "WARNING! " + str(targetDscFile) + " is not found."
+ print ("WARNING! " + str(targetDscFile) + " is not found.")
exit(1)
ext_file = str(os.path.splitext(targetDscFile)[-1]).lower()
if ext_file != ".dsc":
- print "WARNING! " + str(targetDscFile) + " is not a dsc file"
+ print ("WARNING! " + str(targetDscFile) + " is not a dsc file")
exit(1)
if not os.path.exists(splitFspBinPath):
- print "WARNING! " + str(splitFspBinPath) + " is not found."
+ print ("WARNING! " + str(splitFspBinPath) + " is not found.")
exit(1)
#
@@ -54,7 +54,7 @@ file = open (flashMapName, "r")
data = file.read ()
# Get the Flash Base Address
-flashBase = long(data.split("FLASH_BASE")[1].split("=")[1].split()[0], 16)
+flashBase = int(data.split("FLASH_BASE")[1].split("=")[1].split()[0], 16)
# Based on Build Target, select the section in the FlashMap file
flashmap = data
@@ -62,11 +62,11 @@ flashmap = data
# Get FSP-S & FSP-M & FSP-T offset & calculate the base
for line in flashmap.split("\n"):
if "PcdFlashFvFspSOffset" in line:
-fspSBaseOffset = long(line.split("=")[1].split()[0], 16)
+fspSBaseOffset = int(line.split("=")[1].split()[0], 16)
if "PcdFlashFvFspMOffset" in line:
-fspMBaseOffset = long(line.split("=")[1].split()[0], 16)
+fspMBaseOffset = int(line.split("=")[1].split()[0], 16)
if "PcdFlashFvFspTOffset" in line:
-fspTBaseOffset = long(line.split("=")[1].split()[0], 16)
+fspTBaseOffset = int(line.split("=")[1].split()[0], 16)
file.close()
#
@@ -78,10 +78,10 @@ if 'PYTHON_HOME' in os.environ:
pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
Process = subprocess.Popen([pythontool, splitFspBinPath,
"info","-f",fspBinFilePath], stdout=subprocess.PIPE)
Output = Process.communicate()[0]
-FsptInfo = Output.rsplit("FSP_M", 1);
-for line in FsptInfo[1].split("\n"):
- if "ImageSize" in line:
-fspMSize = long(line.split("=")[1], 16)
+FsptInfo = Output.rsplit(b"FSP_M", 1);
+for line in FsptInfo[1].split(b"\n"):
+ if b"ImageSize" in line:
+fspMSize = int(line.split(b"=")[1], 16)
break
# Calculate FSP-S/M/T base address, to which re-base has to be done
--
2.13.3.windows.1
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[edk2-devel] [PATCH] Platform/Intel: Dynamic NUMBER_OF_PROCESSORS in build.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1913
To improve build performance by default the maximum
processors should be used for building.
To support this, NUMBER_OF_PROCESSORS in build.cfg has
new definition:
0 = AUTO. Maximum of processors will be used.
non-zero = limit or force the number of processors.
Test: tried several NUMBER_OF_PROCESSORS settings and
the build parameter can be updated accordingly
also builds successfully.
Cc: Michael Kubacki
Cc: Nate DeSimone
Cc: Liming Gao
Signed-off-by: Chasel Chiu
---
Platform/Intel/build.cfg | 2 +-
Platform/Intel/build_bios.py | 8 +++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index 6c23e5eabc..fc6e4fe824 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -46,7 +46,7 @@ FSP_TEST_RELEASE = FALSE
SECURE_BOOT_ENABLE = FALSE
REBUILD_MODE =
BUILD_ROM_ONLY =
-NUMBER_OF_PROCESSORS = 1
+NUMBER_OF_PROCESSORS = 0
[PLATFORMS]
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index 09eceddeff..864511ac4d 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -21,6 +21,7 @@ import shutil
import argparse
import traceback
import subprocess
+import multiprocessing
from importlib import import_module
try:
@@ -345,7 +346,12 @@ def build(config):
print(" BUILD_ROM_ONLY = ", config.get("BUILD_ROM_ONLY"))
print("==")
-command = ["build", "-n", config["NUMBER_OF_PROCESSORS"]]
+NumberOfProcessors = config["NUMBER_OF_PROCESSORS"]
+if config["NUMBER_OF_PROCESSORS"] == "0":
+# 0 means AUTO, maximum number of processors will be set
+NumberOfProcessors = str(multiprocessing.cpu_count())
+print ("Number of processors set to " + NumberOfProcessors)
+command = ["build", "-n", NumberOfProcessors]
if config["REBUILD_MODE"] and config["REBUILD_MODE"] != "":
command.append(config["REBUILD_MODE"])
--
2.13.3.windows.1
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Re: [edk2-devel] [PATCH 1/3 V2] Intel/Readme.md:Add instructions about Binary Cache in Readme.md
Reviewed-by: Chasel Chiu > -Original Message- > From: Fan, ZhijuX > Sent: Monday, June 17, 2019 1:10 PM > To: devel@edk2.groups.io > Cc: Gao, Liming ; Feng, Bob C ; > Shi, Steven ; Lu, Shifei A ; > Zhou, > Bowen ; Oram, Isaac W ; > Chiu, Chasel ; Kubacki, Michael A > ; Desimone, Nathaniel L > > Subject: [PATCH 1/3 V2] Intel/Readme.md:Add instructions about Binary Cache > in Readme.md > > BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1784 > BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1785 > > Add detailed instructions about Binary Cache in Readme.md, Extend options to > support Binary Cache in the Kabylake build bld.bat file, Purley build bld.bat > file, > build_bios.py > > Cc: Liming Gao > Cc: Bob Feng > Cc: Steven Shi > Cc: Shifei A Lu > Cc: Xiaohu Zhou > Cc: Isaac W Oram > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Nate DeSimone > Signed-off-by: Zhiju.Fan > --- > Platform/Intel/Readme.md | 7 ++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index > cc0151066e..d95d0fa54e 100644 > --- a/Platform/Intel/Readme.md > +++ b/Platform/Intel/Readme.md > @@ -134,6 +134,9 @@ return back to the minimum platform caller. >| --performance | performance build enabled | >| --fsp | fsp wrapper build enabled | >| --fspapi | API mode fsp wrapper build enabled | > + | --hash| Enable hash-based caching | > + | --binary-destination | create cache in specified directory | > + | --binary-source | Consume cache from directory| >| | > > * For more information on build options @@ -196,7 +199,9 @@ For > PurleyOpenBoardPkg 2. Type "cd > edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardMtOlympus". > 3. Type "GitEdk2MinMtOlympus.bat" to setup GIT environment. > 4. Type "bld" to build Purley Mt Olympus board UEFI firmware image, "bld > release" for release build, "bld clean" to > - remove intermediate files. > + remove intermediate files."bld cache-produce" Generate a cache of binary > files in the specified directory, > + "bld cache-consume" Consume a cache of binary files from the specified > directory, BINARY_CACHE_PATH is empty, > + used "BinCache" as default path. > > The validated version of iasl compiler that can build MinPurley is 20180629. > Older version may generate ACPI build errors. > -- > 2.14.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42485): https://edk2.groups.io/g/devel/message/42485 Mute This Topic: https://groups.io/mt/32091876/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 2/3 V2] Platform/Intel:Add build parameter to support Binary Cache
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Fan, ZhijuX
> Sent: Monday, June 17, 2019 1:11 PM
> To: devel@edk2.groups.io
> Cc: Gao, Liming ; Feng, Bob C ;
> Shi, Steven ; Lu, Shifei A ;
> Zhou,
> Bowen ; Oram, Isaac W ;
> Chiu, Chasel ; Kubacki, Michael A
> ; Desimone, Nathaniel L
>
> Subject: [PATCH 2/3 V2] Platform/Intel:Add build parameter to support Binary
> Cache
>
> Need extend the options in the Intel/build_bios.py file to support Binary
> Cache.
>
> --hash:
>Enable hash-based caching during build process.
> --binary-destination:
>Generate a cache of binary files in the specified directory.
> --binary-source:
>Consume a cache of binary files from the specified directory.
>
> Cc: Liming Gao
> Cc: Bob Feng
> Cc: Steven Shi
> Cc: Shifei A Lu
> Cc: Xiaohu Zhou
> Cc: Isaac W Oram
> Cc: Chasel Chiu
> Cc: Michael Kubacki
> Cc: Nate DeSimone
> Signed-off-by: Zhiju.Fan
> ---
> Platform/Intel/build_bios.py | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index
> 09eceddeff..c01b953d16 100644
> --- a/Platform/Intel/build_bios.py
> +++ b/Platform/Intel/build_bios.py
> @@ -343,6 +343,7 @@ def build(config):
> print(" SILENT_MODE= ", config.get("SILENT_MODE"))
> print(" REBUILD_MODE = ", config.get("REBUILD_MODE"))
> print(" BUILD_ROM_ONLY = ", config.get("BUILD_ROM_ONLY"))
> +print(" BINARY_CACHE_CMD_LINE = ", config.get("HASH"),
> + config.get("BINARY_CACHE_CMD_LINE"))
> print("==")
>
> command = ["build", "-n", config["NUMBER_OF_PROCESSORS"]] @@
> -353,6 +354,10 @@ def build(config):
> if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "":
> command.append(config["EXT_BUILD_FLAGS"])
>
> +if config.get('BINARY_CACHE_CMD_LINE'):
> +command.append(config['HASH'])
> +command.append(config['BINARY_CACHE_CMD_LINE'])
> +
> if config.get("SILENT_MODE", "FALSE") == "TRUE":
> command.append("--silent")
> command.append("--quiet")
> @@ -858,6 +863,17 @@ def get_cmd_config_arguments(arguments):
> if arguments.fspapi is True:
> result["API_MODE_FSP_WRAPPER_BUILD"] = "TRUE"
>
> +if not arguments.UseHashCache:
> +result['BINARY_CACHE_CMD_LINE'] = ''
> +elif arguments.BinCacheDest:
> +result['HASH'] = '--hash'
> +result['BINARY_CACHE_CMD_LINE'] = '--binary-destination=%s' %
> arguments.BinCacheDest
> +elif arguments.BinCacheSource:
> +result['HASH'] = '--hash'
> +result['BINARY_CACHE_CMD_LINE'] = '--binary-source=%s' %
> arguments.BinCacheSource
> +else:
> +result['BINARY_CACHE_CMD_LINE'] = ''
> +
> return result
>
>
> @@ -934,6 +950,17 @@ def get_cmd_arguments(build_config):
> parser.add_argument("--fspapi", help="API mode fsp wrapper build
> enabled",
> action='store_true', dest="fspapi")
>
> +parser.add_argument("--hash", action="store_true",
> dest="UseHashCache", default=False,
> +help="Enable hash-based caching during build
> + process.")
> +
> +parser.add_argument("--binary-destination", help="Generate a cache of
> binary \
> +files in the specified directory.",
> +action='store', dest="BinCacheDest")
> +
> +parser.add_argument("--binary-source", help="Consume a cache of binary
> files \
> +from the specified directory.",
> +action='store', dest="BinCacheSource")
> +
> return parser.parse_args()
>
>
> --
> 2.14.1.windows.1
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-=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH] Change edk2-platforms/master to BSD+Patent License
Hi Mike, Seems we missed below files, would you please check? .\Platform\Intel\KabylakeOpenBoardPkg\License.txt .\Silicon\Intel\KabylakeSiliconPkg\License.txt With above 2 files updated, Reviewed-by: Chasel Chiu .\Platform\Intel\KabylakeOpenBoardPkg .\Silicon\Intel\KabylakeSiliconPkg Thanks! Chasel > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Michael D Kinney > Sent: Wednesday, May 15, 2019 9:31 AM > To: devel@edk2.groups.io > Cc: leif.lindh...@linaro.org; Ard Biesheuvel (ard.biesheu...@linaro.org) > ; Kubacki, Michael A > ; Gillispie, Thad ; Bu, > Daocheng ; Oram, Isaac W > ; Piwko, Maciej ; Chiu, > Chasel ; Lu, Shifei A ; Zhou, > Bowen ; Sinha, Ankit ; > Chaganty, Rangasai V > Subject: [edk2-devel] [edk2-platforms][PATCH] Change edk2-platforms/master > to BSD+Patent License > > Hello, > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1373 > > This change is based on the following emails: > https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html > https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html > > RFCs with detailed process for the license change: > V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html > V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html > V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html > > I have posted a V1 branch for review for converting the edk2-platforms/master > branch to the BSD + Patent license > > https://github.com/mdkinney/edk2-platforms/tree/Bug_1373_BsdPatentLicen > se_V1 > > The list of commits in the series are here: > > https://github.com/mdkinney/edk2-platforms/commits/Bug_1373_BsdPatent > License_V1 > > I have a couple questions out to maintainers for a few files in this > repository. > Once I have that feedback, I will post a > V2 version with those updates. > > The edk2-platforms/master branch maintainers and package reviewers should > provide review feedback for their packages. The critical part of the review > is: > 1) Any changes that cause build breaks or logic changes. These code >changes are intended to only modify license contents in comment >blocks. > 2) Any file that has been changed to BSD+Patent, but should remain >with the current license. > 3) Any file that that has not changed to BSD+Patent, but should be >changed to BSD+Patent. > > Thanks, > > Mike > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40641): https://edk2.groups.io/g/devel/message/40641 Mute This Topic: https://groups.io/mt/31625434/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Add FSP Dispatch switch.
From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1832 PcdFspModeSelection is used as switch for boot loader to consume FSP in API mode or Dispatch mode. For backward compatibility, if boot loader running in FSP API mode the KabylakeFspBinPkg will be used which does not have FSP 2.1 changes. For FSP Dispatch mode AmberLakeFspBinPkg will be used with FSP 2.1 support. One INF was duplicate to include different DEC file in each build type. Test: Booted Kabylake RVP3 to Windows successfully. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu --- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf | 146 ++ 1 file changed, 146 insertions(+) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf new file mode 100644 index 00..aebd3583bc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf @@ -0,0 +1,146 @@ +### @file +# Library functions for Fsp Policy Initialization Library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +# +# Defines Section - statements that will be processed to create a Makefile. +# + +[Defines] + INF_VERSION= 0x00010005 + BASE_NAME = PeiSiliconPolicyInitLibFspAml + FILE_GUID = 930816C4-D182-4A23-BF21-9AED635AF06C + MODULE_TYPE= BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + + +# +# Sources Section - list of files that are required for the build to succeed. +# + + +[Sources] + PeiFspPolicyInitLib.c + PeiFspSiPolicyInitLib.c + PeiFspPchPolicyInitLib.c + PeiFspCpuPolicyInitLib.c + PeiFspMePolicyInitLib.c + PeiFspSaPolicyInitLib.c + PeiFspMiscUpdInitLib.c + + PeiPolicyInitPreMem.c + PeiPolicyInit.c + PeiPolicyInit.h + + +# +# Package Dependency Section - list of Package files that are required for +# this module. +# + + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + KabylakeSiliconPkg/SiPkg.dec + AmberLakeFspBinPkg/AmberLakeFspBinPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + IoLib + PeiServicesLib + PcdLib + SmbusLib + MmPciLib + ConfigBlockLib + MemoryAllocationLib + DebugPrintErrorLevelLib + FspWrapperApiLib + +[Pcd] + gSiPkgTokenSpaceGuid.PcdTsegSize## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress## CONSUMES + +[Ppis] + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid## CONSUMES + +[Guids] + gTraceHubPreMemConfigGuid ## CONSUMES + gSmbusPreMemConfigGuid## CONSUMES + gDciPreMemConfigGuid ## CONSUMES + gHpetPreMemConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gHsioPreMemConfigGuid ## CONSUMES + gPcieRpPreMemConfigGuid ## CONSUMES + gLpcPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gWatchDogPreMemConfigGuid ## CONSUMES + gLanConfigGuid
[edk2-devel] [PATCH 0/2] Add FSP Dispatch mode switch
Boot loader (FspWrapper/Platform code) now can switch to Dispatch mode defined by FSP 2.1 spec using PcdFspModeSelection. For backward compatibility different FspBinPkg may be consumed in each mode. To support this switch, below are required changes in KabylakeOpenBoardPkg and KabylakeSiliconPkg: 1. In Dispatch mode AmberLakeFspBinPkg will be consumed and KabylakeFspBinPkg is for API mode for backward compatible. 2. Temporary memory arrangement will be different between each mode because in Dispatch mode FSP will share the same stack with boot loader. 3. For now default mode is still API before all implementation completed. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu Chasel, Chiu (2): KabylakeSiliconPkg: Add FSP Dispatch switch. KabylakeOpenBoardPkg: Add FSP Dispatch switch. Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf | 8 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 33 + Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 29 + Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf | 146 ++ 4 files changed, 208 insertions(+), 8 deletions(-) create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41207): https://edk2.groups.io/g/devel/message/41207 Mute This Topic: https://groups.io/mt/31717894/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: Add FSP Dispatch switch.
From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1832 Basing on PcdFspModeSelection setting either KabylakeFspBinPkg or AmberLakeFspBinPkg will be used and temporary memory arrangement will be different as AmberLakeFspBinPkg will share the same stack with boot loader. Also enlarged FSP-T size to support future larger FSP binary. Test: Booted Kabylake RVP3 to Windows successfully. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf | 8 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc| 33 + Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 29 + 3 files changed, 62 insertions(+), 8 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf index 3a28bd4109..6cb49c941c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf @@ -1,7 +1,7 @@ ## @file # FDF file of Platform. # -# Copyright (c) 2017, Intel Corporation. All rights reserved. +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +41,6 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x0006 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x0060 # Flash addr (0xFFE0) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize= 0x000BC000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006BC000 # Flash addr (0xFFEBC000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize= 0x4000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C # Flash addr (0xFFEC) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x0014 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize= 0x00014000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006D # Flash addr (0xFFED) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x0013 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 7f19ad1eed..1dfe49a7ad 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,7 @@ DEFINE PLATFORM_PACKAGE= MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE= KabylakeFspBinPkg + DEFINE PLATFORM_FSP_BIN_PACKAGE= AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg DEFINE BOARD = KabylakeRvp3 DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD) @@ -24,6 +24,21 @@ # Platform On/Off features are defined here # !include OpenBoardPkgConfig.dsc + !include OpenBoardPkgPcd.dsc + +[Defines] +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # For backward compatibility API mode will use KabylakeFspBinPkg. + # KabylakeFspBinPkg only supports API mode. + # + DEFINE PLATFORM_FSP_BIN_PACKAGE= KabylakeFspBinPkg +!else + # + # AmberLakeFspBinPkg supports both API and Dispatch modes + # + DEFINE PLATFORM_FSP_BIN_PACKAGE= AmberLakeFspBinPkg +!endif # @@ -92,8 +107,20 @@ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # Below library are used by FSP API mode + # SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf +!else + # + # Below library are used by FSP Dispatch mode and non-FSP build (EDK2 build) + # + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf
Re: [edk2-devel] [edk2-platforms] [PATCH] Maintainers.txt: Add maintainers
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Nate > DeSimone > Sent: Wednesday, May 22, 2019 2:17 AM > To: devel@edk2.groups.io > Cc: Kubacki, Michael A ; Chaganty, Rangasai V > > Subject: [edk2-devel] [edk2-platforms] [PATCH] Maintainers.txt: Add > maintainers > > Add maintainers for MinPlatformPkg, ClevoOpenBoardPkg, and > KabylakeSiliconPkg > > Cc: Michael Kubacki > Cc: Sai Chaganty > Signed-off-by: Nate DeSimone > --- > Maintainers.txt | 4 > 1 file changed, 4 insertions(+) > > diff --git a/Maintainers.txt b/Maintainers.txt index 927cd5ed93..2fac4a4c30 > 100644 > --- a/Maintainers.txt > +++ b/Maintainers.txt > @@ -68,10 +68,12 @@ R: Nate DeSimone > Platform/Intel/KabylakeOpenBoardPkg > M: Chasel Chiu > M: Michael Kubacki > +M: Nate DeSimone > > Platform/Intel/MinPlatformPkg > M: Michael Kubacki > M: Chasel Chiu > +M: Nate DeSimone > R: Liming Gao > > Platform/Intel/PurleyOpenBoardPkg > @@ -95,6 +97,8 @@ M: Yi Qian > Silicon/Intel/KabylakeSiliconPkg > M: Chasel Chiu > M: Michael A Kubacki > +M: Sai Chaganty > +R: Nate DeSimone > > Silicon/Intel/LewisburgPkg > M: Piwko, Maciej > -- > 2.16.2.windows.1 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41227): https://edk2.groups.io/g/devel/message/41227 Mute This Topic: https://groups.io/mt/31699825/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2] KabylakeOpenBoardPkg: Fixed system hang caused by MemoryTest.
From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1550 OS hang due to non-existing memory reported as usable memory. There are 2 different RVP3 boards and one with 4GB memory down implementation while another one with 8GB. Since rest of the configurations are exactly the same, board detection is added to the same RVP3 BoardInitLib and only SPD policy assigned differently. This also fixed below 2 issues: 1. Fixed build failuire when PcdMultiBoardSupport == FALSE. (Wrong Pcd TokenSpace used in DxeBoardAcpiTableLib.inf) 2. Always failed to read SPD from DIMM because SpdAddressTable policy was not updated properly. Fixed by a notify callback when policy PPI installed. Test: Verified both RVP3 boards can boot to Windows. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c | 103 +++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 17 ++--- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c | 4 ++-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 6 +++--- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3SpdTable.c | 117 - Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.c | 7 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3Detect.c | 83 +++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c | 127 ++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c | 4 ++-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c | 4 ++-- Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/BaseEcLib.c | 330 ++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf | 43 +++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 9 - Platform/Intel/KabylakeOpenBoardPkg/Include/EcCommands.h | 44 Platform/Intel/KabylakeOpenBoardPkg/Include/Library/EcLib.h | 106 ++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 8 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 3 ++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h | 4 +++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 3 ++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 12 ++-- Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/BaseEcLib.inf | 29 + 21 files changed, 1013 insertions(+), 50 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c new file mode 100644 index 00..0fedd81cd0 --- /dev/null +++
Re: [edk2-devel] [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Agyeman, Prince
> Sent: Tuesday, May 21, 2019 11:08 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Agyeman, Prince
> ; Kubacki, Michael A
> ; Kinney, Michael D
> ; Desimone, Nathaniel L
> ; Gao, Liming ; Sinha,
> Ankit
> Subject: [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions
> to EFIAPI
>
> From: Prince Agyeman
>
> This fixes the calling convension issues in gcc
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm
> version
> 2.11.08
>
> Cc: Michael Kubacki
> Cc: Michael D Kinney
> Cc: Nate DeSimone
> Cc: Liming Gao
> Cc: Ankit Sinha
>
> Signed-off-by: Prince Agyeman
> ---
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h | 3
> ++-
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c | 3
> ++-
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h|
> 4 +++-
> .../Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c|
> 4 +++-
> 4 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> index 44f151c..666340e 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> @@ -1,7 +1,7 @@
> /** @file
>Header file for PCH Init SMM Handler
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -205,6 +205,7 @@ PchPcieLinkEqHandlerFunction (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
>IN EFI_HANDLE DispatchHandle,
>IN EFI_SMM_IO_TRAP_CONTEXT*CallbackContext,
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> index aed33bb..847fbfb 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> @@ -1,7 +1,7 @@
> /** @file
>PCH Pcie SMM Driver Entry
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -238,6 +238,7 @@ PchPciePmIoTrapSmiCallback (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
>IN EFI_HANDLEDispatchHandle,
>IN EFI_SMM_IO_TRAP_CONTEXT*CallbackContext,
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> index 508832e..a9f0664 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> +++
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> @@ -1,7 +1,7 @@
> /** @file
>Prototypes and defines for the PCH SMM Dispatcher.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -510,6 +510,7 @@ typedef struct {
>registered and the SMI source has been
> enabled.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreRegister (
>IN PCH_SMM_GENERIC_PROTOCOL *This,
>IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
> @@ -530,6 +531,7 @@ PchSmmCoreRegister (
>@retval EFI_INVALID_PARAMETER Handle is invalid.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreUnRegister (
>IN PCH_SMM_GENERIC_PROTOCOL *This,
>IN EFI_HANDLE *DispatchHandle
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.
> c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.
> c
> index 0c494bf..cb3bfba 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.
> c
> +++
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCo
> +++ re.c
> @@ -2,7 +2,7 @@
>This driver is responsible for the registration of child drivers
>and the abstraction of the PCH SMI sources.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 -
Re: [edk2-devel] [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Thursday, May 23, 2019 3:12 AM
> To: Agyeman, Prince ; devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
> ; Kinney, Michael D
> ; Gao, Liming ; Sinha,
> Ankit
> Subject: RE: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5
> build support
>
> Reviewed-by: Nate DeSimone
>
> -Original Message-
> From: Agyeman, Prince
> Sent: Monday, May 20, 2019 8:08 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Agyeman, Prince
> ; Kubacki, Michael A
> ; Kinney, Michael D
> ; Desimone, Nathaniel L
> ; Gao, Liming ; Sinha,
> Ankit
> Subject: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build
> support
>
> From: Prince Agyeman
>
> Fixes:
> * Replacing .asm and .S with nasm in SecFspWrapperPlatformSecLib for
> cross-platform build support
> * Modified RuleInclude.fdf
> * Modified python files to be OS independent
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm
> version
> 2.11.08
>
> Cc: Michael Kubacki
> Cc: Michael D Kinney
> Cc: Nate DeSimone
> Cc: Liming Gao
> Cc: Ankit Sinha
>
> Signed-off-by: Prince Agyeman
> ---
> .../Ia32/PeiCoreEntry.S| 117 ---
> .../Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} | 46 +--
> .../SecFspWrapperPlatformSecLib/Ia32/SecEntry.S| 342
> -
> .../Ia32/{SecEntry.asm => SecEntry.nasm} | 132
> .../SecFspWrapperPlatformSecLib/Ia32/Stack.S | 67
> .../Ia32/{Stack.asm => Stack.nasm} | 39 ++-
> .../SecFspWrapperPlatformSecLib.inf| 12 +-
> .../MinPlatformPkg/Include/Fdf/RuleInclude.fdf | 6 +-
> .../Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py | 2 +-
> .../MinPlatformPkg/Tools/PatchFv/PatchBinFv.py | 8 +-
> .../MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py| 15 +-
> Platform/Intel/build_bios.py | 28 +-
> 12 files changed, 143 insertions(+), 671 deletions(-) delete mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/PeiCoreEntry.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} (66%) delete mode
> 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/SecEntry.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/{SecEntry.asm => SecEntry.nasm} (72%) delete mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/Stack.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/{Stack.asm => Stack.nasm} (59%)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.S
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.S
> deleted file mode 100644
> index 8c8356f..000
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.S
> +++ /dev/null
> @@ -1,117 +0,0 @@
> -## @file
> -# Find and call SecStartup
> -#
> -# Copyright (c) 2017, Intel Corporation. All rights reserved. -#
> SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
> -
> -ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)
> -ASM_PFX(CallPeiCoreEntryPoint):
> - #
> - # Obtain the hob list pointer
> - #
> - movl0x4(%esp), %eax
> - #
> - # Obtain the stack information
> - # ECX: start of range
> - # EDX: end of range
> - #
> - movl0x8(%esp), %ecx
> - movl0xC(%esp), %edx
> -
> - #
> - # Platform init
> - #
> - pushal
> - pushl %edx
> - pushl %ecx
> - pushl %eax
> - call ASM_PFX(PlatformInit)
> - popl %eax
> - popl %eax
> - popl %eax
> - popal
> -
> - #
> - # Set stack top pointer
> - #
> - movl%edx, %esp
> -
> - #
> - # Push the hob list pointer
> - #
> - pushl %eax
> -
> - #
> - # Save the value
> - # ECX: start of range
> - # EDX: end of range
> - #
> - movl%esp, %ebp
> - pushl %ecx
> - pushl %edx
> -
> - #
> - # Push processor count to stack first, then BIST status (AP then BSP)
> - #
> - movl$1, %eax
> - cpuid
> - shr $16, %ebx
> - andl$0x00FF, %ebx
> - cmp $1, %bl
> - jae PushProcessorCount
> -
> - #
> - # Some processors report 0 logical processors.
Re: [edk2-devel] [edk2-platforms][PATCH V2] Maintainers.txt: Add maintainers
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Nate > DeSimone > Sent: Thursday, May 23, 2019 2:35 AM > To: devel@edk2.groups.io > Cc: Kubacki, Michael A ; Chaganty, Rangasai V > > Subject: [edk2-devel] [edk2-platforms][PATCH V2] Maintainers.txt: Add > maintainers > > Add maintainers for MinPlatformPkg, ClevoOpenBoardPkg, and > KabylakeSiliconPkg > > Cc: Michael Kubacki > Cc: Sai Chaganty > Signed-off-by: Nate DeSimone > --- > Maintainers.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Maintainers.txt b/Maintainers.txt index 927cd5ed93..e900523eee > 100644 > --- a/Maintainers.txt > +++ b/Maintainers.txt > @@ -68,10 +68,12 @@ R: Nate DeSimone > Platform/Intel/KabylakeOpenBoardPkg > M: Chasel Chiu > M: Michael Kubacki > +M: Nate DeSimone > > Platform/Intel/MinPlatformPkg > M: Michael Kubacki > M: Chasel Chiu > +M: Nate DeSimone > R: Liming Gao > > Platform/Intel/PurleyOpenBoardPkg > @@ -95,6 +97,7 @@ M: Yi Qian > Silicon/Intel/KabylakeSiliconPkg > M: Chasel Chiu > M: Michael A Kubacki > +M: Sai Chaganty > > Silicon/Intel/LewisburgPkg > M: Piwko, Maciej > -- > 2.16.2.windows.1 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41255): https://edk2.groups.io/g/devel/message/41255 Mute This Topic: https://groups.io/mt/31723265/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Agyeman, Prince > Sent: Tuesday, May 21, 2019 11:08 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Agyeman, Prince > > Subject: [edk2-devel] [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: > Added GCC5 build support > > From: Prince Agyeman > > Fixed: > * Include file paths in dec > * Gcc build options > > Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm > version > 2.11.08 > > Signed-off-by: Prince Agyeman > --- > .../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc | > 4 +++- > Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec| 6 > +++--- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildO > ption.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuild > Option.dsc > index 04c5786..8e885cc 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildO > ption.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuild > +++ Option.dsc > @@ -1,7 +1,7 @@ > ## @file > # platform build option configuration file. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -102,6 +102,7 @@ > DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $( # For IA32 Specific Build Flag # > GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-unused > -Wl,--allow-multiple-definition > MSFT: *_*_IA32_ASM_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 > -DASF_PEI > MSFT: *_*_IA32_VFRPP_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > @@ -124,6 +125,7 @@ MSFT: *_*_IA32_ASLCC_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_D > # For X64 Specific Build Flag > # > GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused > -Wl,--allow-multiple-definition > MSFT: *_*_X64_ASM_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 > MSFT: *_*_X64_VFRPP_FLAGS= > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > diff --git a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > index e326598..68977d0 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > +++ b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > @@ -5,7 +5,7 @@ > # INF files to generate AutoGen.c and AutoGen.h files # for the build > infrastructure. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,8 +20,8 @@ > PACKAGE_GUID = 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E > > [Includes] > Include > -KabylakeRvp3\Include > -Features\Tbt\Include > +KabylakeRvp3/Include > +Features/Tbt/Include > > [Guids] > > -- > 2.7.4 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41254): https://edk2.groups.io/g/devel/message/41254 Mute This Topic: https://groups.io/mt/31693034/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] Maintainers.txt: Add maintainer for MinPlatformPkg.
Add Chasel Chiu as the maintainer for Platform/Intel/MinPlatformPkg. Signed-off-by: Chasel Chiu Cc: Michael Kubacki Cc: Liming Gao --- Maintainers.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Maintainers.txt b/Maintainers.txt index cf3ede7f0a..927cd5ed93 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -71,7 +71,7 @@ M: Michael Kubacki Platform/Intel/MinPlatformPkg M: Michael Kubacki -R: Chasel Chiu +M: Chasel Chiu R: Liming Gao Platform/Intel/PurleyOpenBoardPkg -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41039): https://edk2.groups.io/g/devel/message/41039 Mute This Topic: https://groups.io/mt/31684728/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 2/2] PurleyOpenBoardPkg/BoardMtOlympus: Extend build to support Binary Cache
Reviewed-by: Chasel Chiu > -Original Message- > From: Shi, Steven > Sent: Thursday, May 9, 2019 11:21 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Lu, Shifei A > ; > Gao, Liming ; Bi, Dandan ; > Kubacki, Michael A > Subject: [PATCH 2/2] PurleyOpenBoardPkg/BoardMtOlympus: Extend build to > support Binary Cache > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1785 > > Extend the options in the Purley build batch file to support Binary Cache > produce > and consume switch. > --- > .../PurleyOpenBoardPkg/BoardMtOlympus/bld.bat | 18 > -- > .../BoardMtOlympus/prebuild.bat| 4 ++-- > 2 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat > b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat > index a66d19e66e..eda749af36 100644 > --- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat > @@ -16,6 +16,11 @@ REM Run setlocal to take a snapshot of the environment > variables. endlocal is c setlocal set SCRIPT_ERROR=0 > > +@if not defined BINARY_CACHE_PATH ( > + echo Info: BINARY_CACHE_PATH is empty, use BinCache as default > + SET BINARY_CACHE_PATH=BinCache > +) > + > REM Do NOT use :: for comments Inside of code blocks() > > ::** > > @@ -34,6 +39,15 @@ if /I "%1"=="clean" ( >goto :EOF > ) > > +if /I "%1"=="cache-produce" ( > + set BINARY_CACHE_CMD_LINE= --hash > +--binary-destination=%BINARY_CACHE_PATH% > +) > + > +if /I "%1"=="cache-consume" ( > + set BINARY_CACHE_CMD_LINE= --hash > --binary-source=%BINARY_CACHE_PATH% > +) > + > + > shift > GOTO :parseCmdLine > > @@ -92,8 +106,8 @@ echo Build Start > echo. > echo > echo. > -echo build %BUILD_CMD_LINE% --log=%BUILD_LOG% > %BUILD_REPORT_FLAGS% -call build %BUILD_CMD_LINE% > --log=%BUILD_LOG% %BUILD_REPORT_FLAGS% > +echo build %BUILD_CMD_LINE% --log=%BUILD_LOG% > %BUILD_REPORT_FLAGS% > +%BINARY_CACHE_CMD_LINE% call build %BUILD_CMD_LINE% > --log=%BUILD_LOG% > +%BUILD_REPORT_FLAGS% %BINARY_CACHE_CMD_LINE% > echo > echo. > echo Build End > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat > b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat > index 81a9634d51..880e6417ac 100644 > --- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat > @@ -188,8 +188,8 @@ set PRE_BUILD_CMD_LINE=%BUILD_CMD_LINE% -D > MAX_SOCKET=%MAX_SOCKET% set > PRE_BUILD_LOG=%WORKSPACE%\Build\prebuild.log > set PRE_BUILD_REPORT=%WORKSPACE%\Build\preBuildReport.txt > > -echo build %PRE_BUILD_CMD_LINE% -m > %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% > --log=%PRE_BUILD_LOG% -call build %PRE_BUILD_CMD_LINE% -m > %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% > --log=%PRE_BUILD_LOG% > +echo build %PRE_BUILD_CMD_LINE% -m > +%BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% > +--log=%PRE_BUILD_LOG% %BINARY_CACHE_CMD_LINE% call build > +%PRE_BUILD_CMD_LINE% -m %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y > +%PRE_BUILD_REPORT% --log=%PRE_BUILD_LOG% > %BINARY_CACHE_CMD_LINE% > if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > > @REM PSYS == FIX0 > -- > 2.17.1.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40409): https://edk2.groups.io/g/devel/message/40409 Mute This Topic: https://groups.io/mt/31551303/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 1/1] MinPlatformPkg: Include Tcg2Smm ACPI table RAW section
Reviewed-by: Chasel Chiu < chasel.c...@intel.com > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38651): https://edk2.groups.io/g/devel/message/38651 Mute This Topic: https://groups.io/mt/30921469/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 4/6] KabylakeOpenBoardPkg/KBLRvp3: Remove the consume of 8259-related PCD
Reviewed-by: Chasel Chiu < chasel.c...@intel.com > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38648): https://edk2.groups.io/g/devel/message/38648 Mute This Topic: https://groups.io/mt/30893897/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 3/6] KabylakeOpenBoardPkg/KBLRvp3: Remove unused PCD 'PcdUseHpetTimer'
Reviewed-by: Chasel Chiu > -Original Message- > From: Wu, Hao A > Sent: Thursday, April 4, 2019 1:57 PM > To: devel@edk2.groups.io > Cc: Wu, Hao A ; Chiu, Chasel ; > Kubacki, Michael A > Subject: [edk2-platforms/devel-MinPlatform][PATCH v1 3/6] > KabylakeOpenBoardPkg/KBLRvp3: Remove unused PCD 'PcdUseHpetTimer' > > For KabylakeRvp3, it is using the HPET timer unconditionally. The PCD > 'PcdUseHpetTimer' is not being used. > > This commit will remove the usage of the above PCD in package DSC files. > > Cc: Chasel Chiu > Cc: Michael Kubacki > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Hao Wu > --- > > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.d > sc | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig > .dsc > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig > .dsc > index bb06ff5a2a..f3d082ce41 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig > .dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfi > +++ g.dsc > @@ -1,7 +1,7 @@ > ## @file > # Platform configuration file. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > # This program and the accompanying materials are licensed and made available > under # the terms and conditions of the BSD License which accompanies this > distribution. > @@ -111,7 +111,6 @@ [PcdsFeatureFlag] >gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE >gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE >gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE > - gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - > HPET / FALSE - 8254 timer is used. >gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE >gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE > > -- > 2.12.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38654): https://edk2.groups.io/g/devel/message/38654 Mute This Topic: https://groups.io/mt/30893896/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2] [PATCH V3] Change EDK II to BSD+Patent License
I'm ok with the changes in below packages. Thanks! Chasel Reviewed-by: Chasel Chiu For IntelFspPkg IntelFspWrapperPkg IntelFsp2Pkg IntelFsp2WrapperPkg > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Liming Gao > Sent: Monday, April 8, 2019 1:10 PM > To: devel@edk2.groups.io; Kinney, Michael D > Subject: Re: [edk2-devel] [edk2] [PATCH V3] Change EDK II to BSD+Patent > License > > Mike: > I also review QuarkPlatformPkg, QuarkSocPkg. The changes look good to me. > Reviewed-by: Liming Gao > > Thanks > Liming > >-Original Message- > >From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > >Michael D Kinney > >Sent: Thursday, April 04, 2019 7:42 AM > >To: devel@edk2.groups.io; Kinney, Michael D > > > >Subject: [edk2-devel] [edk2] [PATCH V3] Change EDK II to BSD+Patent > >License > > > >Hello, > > > >New in V3 > >= > >* Update the base of the patch series from edk2-stable201903 to > > 7ed72121b7 that is after the file add/remove freeze: > > > > https://lists.01.org/pipermail/edk2-devel/2019-April/038574.html > > > >* Replace copyright line in License.txt in root with a single copyright > > for "TianoCore and contributors". > >* Clarify commit message for changes to License.txt to state the text > > differences are larger than expected due to differences in line breaks. > >* There is one less patch in the series than V2 due to the retirement > > of the EdkCompatibilityPkg. > >* The git feature "git range-diff" can be used to compare the V2 and > > V3 branches even though they have different bases. If you have both > > the V2 and V3 branches in your local repo, you can use the following > > command to see the changes. Most are due to the removal of .S files > > in March. If you pipe through grep looking for "diff --git" you will > > see the list of files with differences. > > > > git range-diff edk2-stable201903..Bug_1373_BsdPatentLicense_V2 > >7ed72121b7..Bug_1373_BsdPatentLicense_V3 > > > >New in V2 > >= > >* Remove Cc lines from commit messages > >* Remove branch reference from commit messages > >* Change license in 2 files missed in OvmfPkg > >* Update OvmfPkg/License.txt to BSD+Patent as the default license > >* Move the portions of Contributions.txt in the root of edk2 to > > Readme.md in the root of edk2 that describe how to contribute > > along with the commit message format. > >* Add to Readme.md in the root of edk2 that Signed-off-by means that > > the contributor certifies compliance to the Developer's Certificate > > of Origin 1.1. https://developercertificate.org = > > > >BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1373 > > > >This change is based on the following emails: > > https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html > > https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html > > > >RFCs with detailed process for the license change: > > V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html > > V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html > > V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html > > > >I have posted the patch series for review on the following branch using > >7ed72121b7 as the base for the patch series. > > > > https://github.com/mdkinney/edk2/tree/Bug_1373_BsdPatentLicense_V3 > > > >The commits in patch series can be viewed here: > > > > > >https://github.com/mdkinney/edk2/commits/Bug_1373_BsdPatentLicense_V > >3 > > > >The patch series has one patch per package along with a few patches to > >update the license information in the root of the edk2 repository as > >described in the RFC V3. > > > >Due to the size of the patch series, I prefer to not send the patch > >emails. Instead, please perform code reviews using content from the > >branch. > > > >All EDK II package maintainers and package reviewers should provide > >review feedback for their packages. The critical part of the review > >is: > >1) Any changes that cause build breaks or logic changes. These code > > changes are intended to only modify license contents in comment > > blocks. > >2) Any file that has been changed to BSD+Patent, but should remain > > with the current license. > >3) Any file that that has not changed to BSD+Patent, but should be > > changed to BSD+Patent. > > > >Feedback and Reviewed-by emails should identify the patch the feedback > >applies using the patch summary listed below. The goal is to complete > >all reviews to support the commit of these patches on April 9, 2019. > > > >eece5f8a6e edk2: Remove Contributions.txt and update Readme.md > >224dce1ae5 OvmfPkg: Change License.txt from 2-Clause BSD to BSD+Patent > >f3cbc2ffc7 StdLibPrivateInternalFiles: Replace BSD License with > >BSD+Patent License > >845b945044 StdLib: Replace BSD License with BSD+Patent License > >e55c8532c9 AppPkg: Replace BSD License with BSD+Patent License > >a6df2af909
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 5/6] KabylakeSiliconPkg: Remove unused PCD 'PcdUseHpetTimer'
Reviewed-by: Chasel Chiu > -Original Message- > From: Wu, Hao A > Sent: Thursday, April 4, 2019 1:57 PM > To: devel@edk2.groups.io > Cc: Wu, Hao A ; Chiu, Chasel ; > Kubacki, Michael A > Subject: [edk2-platforms/devel-MinPlatform][PATCH v1 5/6] KabylakeSiliconPkg: > Remove unused PCD 'PcdUseHpetTimer' > > For platforms under KabylakeOpenBoardPkg & ClevoOpenBoardPkg, both of > them are using the HPET timer unconditionally. The PCD 'PcdUseHpetTimer' is > not being used. > > This commit will remove the above PCD within KabylakeSiliconPkg. > > Cc: Chasel Chiu > Cc: Michael A Kubacki > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Hao Wu > --- > Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 3 +-- > Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > index 92b6d492ee..cca1a2e60d 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > @@ -1,7 +1,7 @@ > ## @file > # Component description file for the Silicon Reference Code. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > # This program and the accompanying materials are licensed and made available > under # the terms and conditions of the BSD License which accompanies this > distribution. > @@ -592,7 +592,6 @@ [PcdsFeatureFlag] > gSiPkgTokenSpaceGuid.PcdSerialGpioEnable > |FALSE|BOOLEAN|0xF003 > gSiPkgTokenSpaceGuid.PcdAtaEnable > |FALSE|BOOLEAN|0xF004 > gSiPkgTokenSpaceGuid.PcdSiCsmEnable > |FALSE|BOOLEAN|0xF005 > -gSiPkgTokenSpaceGuid.PcdUseHpetTimer > |FALSE|BOOLEAN|0xF006 > gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE > |BOOLEAN|0xF008 > gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE > |BOOLEAN|0xF009 > gSiPkgTokenSpaceGuid.PcdSourceDebugEnable > |FALSE|BOOLEAN|0xF00B > diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc > b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc > index 7189ce6396..cbb2a8bec4 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc > +++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc > @@ -1,7 +1,7 @@ > ## @file > # Component description file for the SkyLake SiPkg DSC file. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > # This program and the accompanying materials are licensed and made available > under # the terms and conditions of the BSD License which accompanies this > distribution. > @@ -19,7 +19,6 @@ [PcdsFeatureFlag] > gSiPkgTokenSpaceGuid.PcdSerialGpioEnable |FALSE > gSiPkgTokenSpaceGuid.PcdAtaEnable|FALSE > gSiPkgTokenSpaceGuid.PcdSiCsmEnable |FALSE > -gSiPkgTokenSpaceGuid.PcdUseHpetTimer |FALSE > gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE > gSiPkgTokenSpaceGuid.PcdAcpiEnable |FALSE > gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE > -- > 2.12.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38643): https://edk2.groups.io/g/devel/message/38643 Mute This Topic: https://groups.io/mt/30893898/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 5/6] KabylakeSiliconPkg: Remove unused PCD 'PcdUseHpetTimer'
Reviewed-by: Chasel Chiu < chasel.c...@intel.com > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38649): https://edk2.groups.io/g/devel/message/38649 Mute This Topic: https://groups.io/mt/30893898/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 6/6] KabylakeSiliconPkg/SiPkg.dec: Remove Legacy8259 protocol GUID
Reviewed-by: Chasel Chiu < chasel.c...@intel.com > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38637): https://edk2.groups.io/g/devel/message/38637 Mute This Topic: https://groups.io/mt/30893899/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 3/6] KabylakeOpenBoardPkg/KBLRvp3: Remove unused PCD 'PcdUseHpetTimer'
Reviewed-by: Chasel Chiu < chasel.c...@intel.com > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38647): https://edk2.groups.io/g/devel/message/38647 Mute This Topic: https://groups.io/mt/30893896/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 6/6] KabylakeSiliconPkg/SiPkg.dec: Remove Legacy8259 protocol GUID
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, April 4, 2019 1:57 PM
> To: devel@edk2.groups.io
> Cc: Wu, Hao A ; Chiu, Chasel ;
> Kubacki, Michael A
> Subject: [edk2-platforms/devel-MinPlatform][PATCH v1 6/6]
> KabylakeSiliconPkg/SiPkg.dec: Remove Legacy8259 protocol GUID
>
> For modules consumed by platforms within KabylakeOpenBoardPkg &
> ClevoOpenBoardPkg, none of them has the dependency on the Legacy8259
> protocol. Thus, this commit will remove the duplicated Legacy8259 protocol
> GUID within file SiPkg.dec.
>
> Cc: Chasel Chiu
> Cc: Michael A Kubacki
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Hao Wu
> ---
> Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> index cca1a2e60d..078d10c520 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> @@ -268,7 +268,6 @@ [Protocols]
> ##
> gEfiLegacyBiosProtocolGuid = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b,
> 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}} gEfiLegacyInterruptProtocolGuid =
> {0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}
> -gEfiLegacy8259ProtocolGuid = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec,
> 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}} gEfiDataHubProtocolGuid = {0xae80d021,
> 0x618e, 0x11d4, {0xbc, 0xd7, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81}} ## ##
> MdeModulePkg
> --
> 2.12.0.windows.1
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Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH v1 4/6] KabylakeOpenBoardPkg/KBLRvp3: Remove the consume of 8259-related PCD
Reviewed-by: Chasel Chiu > -Original Message- > From: Wu, Hao A > Sent: Thursday, April 4, 2019 1:57 PM > To: devel@edk2.groups.io > Cc: Wu, Hao A ; Chiu, Chasel ; > Kubacki, Michael A > Subject: [edk2-platforms/devel-MinPlatform][PATCH v1 4/6] > KabylakeOpenBoardPkg/KBLRvp3: Remove the consume of 8259-related PCD > > For KabylakeRvp3, none of its consumed modules is using the PCD: > gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask > > Thus, this commit will remove the PCD consumption in the DSC file. > > Cc: Chasel Chiu > Cc: Michael Kubacki > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Hao Wu > --- > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds > c > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds > c > index 35f383ecef..51d4e2ea46 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds > c > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d > +++ sc > @@ -1,7 +1,7 @@ > ## @file > # Platform description. > # > -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > # This program and the accompanying materials are licensed and made available > under # the terms and conditions of the BSD License which accompanies this > distribution. > @@ -194,9 +194,6 @@ [PcdsFixedAtBuild.IA32] >gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x380 > > [PcdsFixedAtBuild.X64] > - gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8 > - > - ># Default platform supported RFC 4646 languages: (American) English > > gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-U > S" > > -- > 2.12.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38639): https://edk2.groups.io/g/devel/message/38639 Mute This Topic: https://groups.io/mt/30893897/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2] [PATCH V3] Change EDK II to BSD+Patent License
Reviewed-by: Chasel Chiu < chasel.c...@intel.com > for below packages: IntelFspPkg IntelFspWrapperPkg IntelFsp2Pkg IntelFsp2WrapperPkg -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#38641): https://edk2.groups.io/g/devel/message/38641 Mute This Topic: https://groups.io/mt/30887153/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform] [patch 2/3] KabylakeOpenBoardPkg/KBLRvp3: Use shell source directly
Reviewed-by: Chasel Chiu
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Dandan Bi
> Sent: Wednesday, April 10, 2019 1:33 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
>
> Subject: [edk2-devel] [edk2-platforms/devel-MinPlatform] [patch 2/3]
> KabylakeOpenBoardPkg/KBLRvp3: Use shell source directly
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1675
>
> In long term we will remove ShellBinPkg, so now update platform to use
> ShellPkg
> directly.
>
> Cc: Chasel Chiu
> Cc: Michael Kubacki
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Dandan Bi
> ---
> .../KabylakeRvp3/OpenBoardPkg.dsc | 22 ++-
> .../KabylakeRvp3/OpenBoardPkg.fdf | 2 +-
> 2 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index d1fb795f15..8602052666 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -261,11 +261,31 @@
>MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
>MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
>MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
>
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.i
> nf
>
> - ShellBinPkg/UefiShell/UefiShell.inf
> + #
> + # Shell
> + #
> + ShellPkg/Application/Shell/Shell.inf {
> +
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comm
> andsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm
> andsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C
> ommandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C
> ommandsLib.inf
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand
> Lib.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLi
> b.inf
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCo
> mmandLib.inf
> +
> ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + }
>
> #
> # Silicon
> #
> !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> index dc2a5d7e12..8e8abab0dc 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> @@ -333,11 +333,11 @@ INF
> MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> INF
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.i
> nf
>
> -INF ShellBinPkg/UefiShell/UefiShell.inf
> +INF ShellPkg/Application/Shell/Shell.inf
>
> INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
>
> INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
> --
> 2.18.0.windows.1
>
>
>
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[edk2-devel] [PATCH] IntelFsp2WrapperPkg: Perform post FSP-S process.
From: "Chasel, Chiu"
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1716
In API mode FSP wrapper will perform some post
FSP-S process but such process was skipped in Dispatch
mode which may impact some of boot loaders.
To align behavior between API and Dispatch, an
End-of-Pei callback is introduced to perform same process
in Dispatch mode.
Test: Verified on internal platform and both
FSP API and Dispatch modes booted successfully.
Cc: Nate DeSimone
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu
---
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 50
+-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index bb126797ae..c1823656ed 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register
MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -179,6 +179,46 @@ FspSiliconInitDoneGetFspHobList (
}
/**
+ This function is for FSP dispatch mode to perform post FSP-S process.
+
+ @param[in] PeiServicesPointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification
event that
+caused this function to execute.
+ @param[in] PpiPointer to the PPI data associated with this
function.
+
+ @retval EFI_STATUSStatus returned by PeiServicesInstallPpi ()
+**/
+EFI_STATUS
+EFIAPI
+FspsWrapperEndOfPeiNotify (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // In Dispatch mode no FspHobList so passing NULL
+ //
+ PostFspsHobProcess (NULL);
+
+ //
+ // Install FspSiliconInitDonePpi so that any other driver can consume this
info.
+ //
+ Status = PeiServicesInstallPpi ();
+ ASSERT_EFI_ERROR(Status);
+
+ return Status;
+}
+
+EFI_PEI_NOTIFY_DESCRIPTOR mFspsWrapperEndOfPeiNotifyDesc = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ ,
+ FspsWrapperEndOfPeiNotify
+};
+
+/**
This function is called after PEI core discover memory and finish migration.
@param[in] PeiServicesPointer to PEI Services Table.
@@ -341,6 +381,8 @@ FspsWrapperPeimEntryPoint (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
+ EFI_STATUS Status;
+
DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
if (PcdGet8 (PcdFspModeSelection) == 1) {
@@ -353,6 +395,12 @@ FspsWrapperPeimEntryPoint (
NULL,
NULL
);
+
+//
+// Register EndOfPei Nofity to run post FSP-S process.
+//
+Status = PeiServicesNotifyPpi ();
+ASSERT_EFI_ERROR (Status);
}
return EFI_SUCCESS;
--
2.13.3.windows.1
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Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH 1/5] KabylakeSiliconPkg/BaseResetSystemLib: Add a new API ResetSystem
Please see below comments inline.
> -Original Message-
> From: Gao, Zhichao
> Sent: Monday, April 15, 2019 11:08 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
>
> Subject: [edk2-platforms/devel-MinPlatform][PATCH 1/5]
> KabylakeSiliconPkg/BaseResetSystemLib: Add a new API ResetSystem
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460
>
> Add a new API ResetSystem to this ResetSystemLib instance.
> It only adds the basic functions from ResetSystemRuntimeDxe.
> Lacking of this interface may cause link error, if some drivers use this new
> API and
> link to this library instance.
> Make the ResetPlatformSpecific's parameters same with the interface in Edk2
> repo.
> Notes:
> This library API only provide a basic function of reset. If the consumers
> want full
> functions, they should use the instance in the MdeModulePkg and make sure the
> depex driver is dispatched.
>
> Cc: Chasel Chiu
> Cc: Michael A Kubacki
> Signed-off-by: Zhichao Gao
> ---
> .../BaseResetSystemLib/BaseResetSystemLib.c | 47 +--
> 1 file changed, 44 insertions(+), 3 deletions(-)
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset
> SystemLib.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRese
> tSystemLib.c
> index ec1a69e4de..0d5c27401d 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset
> SystemLib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/Ba
> +++ seResetSystemLib.c
> @@ -1,7 +1,7 @@
> /** @file
>System reset library services.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made available
> under the terms and conditions of the BSD License that accompanies this
> distribution.
> The full text of the license may be found at @@ -108,7 +108,6 @@
> ResetShutdown (
> /**
>Calling this function causes the system to enter a power state for platform
> specific.
>
> - @param[in] ResetStatus The status code for the reset.
>@param[in] DataSize The size of ResetData in bytes.
>@param[in] ResetDataOptional element used to introduce a
> platform specific reset.
>The exact type of the reset is defined by
> the
> EFI_GUID that follows @@ -118,7 +117,6 @@ ResetShutdown ( VOID EFIAPI
> ResetPlatformSpecific (
> - IN EFI_STATUS ResetStatus,
>IN UINTNDataSize,
>IN VOID *ResetData OPTIONAL
>)
> @@ -142,6 +140,49 @@ EnterS3WithImmediateWake (
>ASSERT (FALSE);
> }
>
> +/**
> + The ResetSystem function resets the entire platform.
> +
> + @param[in] ResetType The type of reset to perform.
> + @param[in] ResetStatusThe status code for the reset.
> + @param[in] DataSize The size, in bytes, of ResetData.
> + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,
> or EfiResetShutdown
> +the data buffer starts with a Null-terminated
> string,
> optionally
> +followed by additional binary data. The string
> is a
> description
> +that the caller may use to further indicate the
> reason for
> the
> +system reset.
> +**/
> +VOID
> +EFIAPI
> +ResetSystem (
> + IN EFI_RESET_TYPE ResetType,
> + IN EFI_STATUS ResetStatus,
> + IN UINTNDataSize,
> + IN VOID *ResetData OPTIONAL
> + )
> +{
> + switch (ResetType) {
> + case EfiResetWarm:
> +ResetWarm ();
> +break;
> +
> + case EfiResetCold:
> +ResetCold ();
> +break;
> +
> + case EfiResetShutdown:
> +ResetShutdown ();
> +return ;
> +
> + case EfiResetPlatformSpecific:
> +ResetPlatformSpecific (DataSize, ResetData);
> +return;
> +
> + default:
> +return ;
> + }
> +}
> +
Where we consuming this new "ResetSystem ()" in Kabylake MinPlatform?
Same question for changes in Pei and Dxe library instances.
Thanks!
Chasel
> /**
>The library constructuor.
>
> --
> 2.21.0.windows.1
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Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH 2/5] KabylakeSiliconPkg/DxeResetSystemLib: Add a new API ResetSystem
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Gao, Zhichao
> Sent: Monday, April 15, 2019 11:08 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
> ; Gao, Liming
> Subject: [edk2-platforms/devel-MinPlatform][PATCH 2/5]
> KabylakeSiliconPkg/DxeResetSystemLib: Add a new API ResetSystem
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460
>
> Add a new API ResetSystem to this ResetSystemLib instance.
> It only adds the basic functions from ResetSystemRuntimeDxe.
> Lacking of this interface may cause link error, if some drivers use this new
> API and
> link to this library instance.
> Make the ResetPlatformSpecific's parameters same with the interface in Edk2
> repo.
> Notes:
> This library API only provide a basic function of reset. If the consumers
> want full
> functions, they should use the instance in the MdeModulePkg and make sure the
> depex driver is dispatched.
>
> Cc: Chasel Chiu
> Cc: Michael A Kubacki
> Cc: Liming Gao
> Signed-off-by: Zhichao Gao
> ---
> .../DxeResetSystemLib/DxeResetSystemLib.c | 47 +--
> 1 file changed, 44 insertions(+), 3 deletions(-)
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetS
> ystemLib.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetS
> ystemLib.c
> index 9526560b95..bb94b66c11 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetS
> ystemLib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/DxeResetSystemLib/Dxe
> +++ ResetSystemLib.c
> @@ -1,7 +1,7 @@
> /** @file
>System reset library services.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made available
> under the terms and conditions of the BSD License that accompanies this
> distribution.
> The full text of the license may be found at @@ -247,7 +247,6 @@
> DxePchGlobalReset (
> /**
>Calling this function causes the system to enter a power state for platform
> specific.
>
> - @param[in] ResetStatus The status code for the reset.
>@param[in] DataSize The size of ResetData in bytes.
>@param[in] ResetDataOptional element used to introduce a
> platform specific reset.
>The exact type of the reset is defined by
> the
> EFI_GUID that follows @@ -257,7 +256,6 @@ DxePchGlobalReset ( VOID
> EFIAPI ResetPlatformSpecific (
> - IN EFI_STATUS ResetStatus,
>IN UINTNDataSize,
>IN VOID *ResetData OPTIONAL
>)
> @@ -292,6 +290,49 @@ EnterS3WithImmediateWake (
>ASSERT (FALSE);
> }
>
> +/**
> + The ResetSystem function resets the entire platform.
> +
> + @param[in] ResetType The type of reset to perform.
> + @param[in] ResetStatusThe status code for the reset.
> + @param[in] DataSize The size, in bytes, of ResetData.
> + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,
> or EfiResetShutdown
> +the data buffer starts with a Null-terminated
> string,
> optionally
> +followed by additional binary data. The string
> is a
> description
> +that the caller may use to further indicate the
> reason for
> the
> +system reset.
> +**/
> +VOID
> +EFIAPI
> +ResetSystem (
> + IN EFI_RESET_TYPE ResetType,
> + IN EFI_STATUS ResetStatus,
> + IN UINTNDataSize,
> + IN VOID *ResetData OPTIONAL
> + )
> +{
> + switch (ResetType) {
> + case EfiResetWarm:
> +ResetWarm ();
> +break;
> +
> + case EfiResetCold:
> +ResetCold ();
> +break;
> +
> + case EfiResetShutdown:
> +ResetShutdown ();
> +return ;
> +
> + case EfiResetPlatformSpecific:
> +ResetPlatformSpecific (DataSize, ResetData);
> +return;
> +
> + default:
> +return ;
> + }
> +}
> +
> /**
>The library constructuor.
>
> --
> 2.21.0.windows.1
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Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH 4/5] KabylakeSiliconPkg/PeiResetSystemLib: Add a new API ResetSystem
Reviewed-by: Chasel Chiu > -Original Message- > From: Gao, Zhichao > Sent: Monday, April 15, 2019 11:08 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael A > ; Gao, Liming > Subject: [edk2-platforms/devel-MinPlatform][PATCH 4/5] > KabylakeSiliconPkg/PeiResetSystemLib: Add a new API ResetSystem > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460 > > Add a new API ResetSystem to this ResetSystemLib instance. > It only adds the basic functions from ResetSystemRuntimeDxe. > Lacking of this interface may cause link error, if some drivers use this new > API and > link to this library instance. > Make the ResetPlatformSpecific's parameters same with the interface in Edk2 > repo. > Also change the caller and declaration at the same time. > Notes: > This library API only provide a basic function of reset. If the consumers > want full > functions, they should use the instance in the MdeModulePkg and make sure the > depex driver is dispatched. > > Cc: Chasel Chiu > Cc: Michael A Kubacki > Cc: Liming Gao > Signed-off-by: Zhichao Gao > --- > .../Pch/Library/PeiPchResetLib/PchReset.c | 7 ++- > .../PeiResetSystemLib/PeiResetSystemLib.c | 47 +-- > 2 files changed, 47 insertions(+), 7 deletions(-) > > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchResetLib/PchReset.c > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchResetLib/PchReset.c > index 79f3f779dc..1a30bf31f6 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchResetLib/PchReset.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchResetLib/PchRes > +++ et.c > @@ -1,7 +1,7 @@ > /** @file >PCH RESET PEIM DRIVER. > > -Copyright (c) 2017, Intel Corporation. All rights reserved. > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > This program and the accompanying materials are licensed and made available > under the terms and conditions of the BSD License that accompanies this > distribution. > The full text of the license may be found at @@ -27,7 +27,6 @@ WITHOUT > WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > VOID > EFIAPI > ResetPlatformSpecific ( > - IN EFI_STATUS ResetStatus, >IN UINTNDataSize, >IN VOID *ResetData OPTIONAL >); > @@ -67,7 +66,7 @@ ResetSystem ( > return; > >case EfiResetPlatformSpecific: > -ResetPlatformSpecific (ResetStatus, DataSize, ResetData); > +ResetPlatformSpecific (DataSize, ResetData); > return; > >default: > @@ -115,7 +114,7 @@ Reset ( > case PchGlobalReset: >CopyMem (, , sizeof (EFI_GUID)); >StrCpyS (ResetData.Description, > PCH_RESET_DATA_STRING_MAX_LENGTH, > PCH_PLATFORM_SPECIFIC_RESET_STRING); > - ResetPlatformSpecific (EFI_SUCCESS, sizeof (PCH_RESET_DATA), > ); > + ResetPlatformSpecific (sizeof (PCH_RESET_DATA), ); >break; > > default: > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiResetSystemLib/PeiResetSys > temLib.c > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiResetSystemLib/PeiResetSys > temLib.c > index 6a017a40a7..92ce6af5cc 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiResetSystemLib/PeiResetSys > temLib.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiResetSystemLib/Pei > +++ ResetSystemLib.c > @@ -1,7 +1,7 @@ > /** @file >System reset library services. > > -Copyright (c) 2017, Intel Corporation. All rights reserved. > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > This program and the accompanying materials are licensed and made available > under the terms and conditions of the BSD License that accompanies this > distribution. > The full text of the license may be found at @@ -239,7 +239,6 @@ > PeiPchGlobalReset ( > /** >Calling this function causes the system to enter a power state for platform > specific. > > - @param[in] ResetStatus The status code for the reset. >@param[in] DataSize The size of ResetData in bytes. >@param[in] ResetDataOptional element used to introduce a > platform specific reset. >The exact type of the reset is defined by > the > EFI_GUID that follows @@ -249,7 +248,6 @@ PeiPchGlobalReset ( VOID > EFIAPI ResetPlatformSpecific ( > - IN EFI_STATUS ResetStatus, >IN UINTNDataSize, >IN VOID *ResetData OPTIONAL >) > @@ -284,3 +282,46 @@ EnterS3WithImmediateWake ( >ASSERT (FALSE); > } > > +/** > + The ResetSystem function resets the en
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform][PATCH 1/5] KabylakeSiliconPkg/BaseResetSystemLib: Add a new API ResetSystem
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Gao, Zhichao
> Sent: Monday, April 15, 2019 11:08 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
>
> Subject: [edk2-platforms/devel-MinPlatform][PATCH 1/5]
> KabylakeSiliconPkg/BaseResetSystemLib: Add a new API ResetSystem
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1460
>
> Add a new API ResetSystem to this ResetSystemLib instance.
> It only adds the basic functions from ResetSystemRuntimeDxe.
> Lacking of this interface may cause link error, if some drivers use this new
> API and
> link to this library instance.
> Make the ResetPlatformSpecific's parameters same with the interface in Edk2
> repo.
> Notes:
> This library API only provide a basic function of reset. If the consumers
> want full
> functions, they should use the instance in the MdeModulePkg and make sure the
> depex driver is dispatched.
>
> Cc: Chasel Chiu
> Cc: Michael A Kubacki
> Signed-off-by: Zhichao Gao
> ---
> .../BaseResetSystemLib/BaseResetSystemLib.c | 47 +--
> 1 file changed, 44 insertions(+), 3 deletions(-)
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset
> SystemLib.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRese
> tSystemLib.c
> index ec1a69e4de..0d5c27401d 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset
> SystemLib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/BaseResetSystemLib/Ba
> +++ seResetSystemLib.c
> @@ -1,7 +1,7 @@
> /** @file
>System reset library services.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made available
> under the terms and conditions of the BSD License that accompanies this
> distribution.
> The full text of the license may be found at @@ -108,7 +108,6 @@
> ResetShutdown (
> /**
>Calling this function causes the system to enter a power state for platform
> specific.
>
> - @param[in] ResetStatus The status code for the reset.
>@param[in] DataSize The size of ResetData in bytes.
>@param[in] ResetDataOptional element used to introduce a
> platform specific reset.
>The exact type of the reset is defined by
> the
> EFI_GUID that follows @@ -118,7 +117,6 @@ ResetShutdown ( VOID EFIAPI
> ResetPlatformSpecific (
> - IN EFI_STATUS ResetStatus,
>IN UINTNDataSize,
>IN VOID *ResetData OPTIONAL
>)
> @@ -142,6 +140,49 @@ EnterS3WithImmediateWake (
>ASSERT (FALSE);
> }
>
> +/**
> + The ResetSystem function resets the entire platform.
> +
> + @param[in] ResetType The type of reset to perform.
> + @param[in] ResetStatusThe status code for the reset.
> + @param[in] DataSize The size, in bytes, of ResetData.
> + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,
> or EfiResetShutdown
> +the data buffer starts with a Null-terminated
> string,
> optionally
> +followed by additional binary data. The string
> is a
> description
> +that the caller may use to further indicate the
> reason for
> the
> +system reset.
> +**/
> +VOID
> +EFIAPI
> +ResetSystem (
> + IN EFI_RESET_TYPE ResetType,
> + IN EFI_STATUS ResetStatus,
> + IN UINTNDataSize,
> + IN VOID *ResetData OPTIONAL
> + )
> +{
> + switch (ResetType) {
> + case EfiResetWarm:
> +ResetWarm ();
> +break;
> +
> + case EfiResetCold:
> +ResetCold ();
> +break;
> +
> + case EfiResetShutdown:
> +ResetShutdown ();
> +return ;
> +
> + case EfiResetPlatformSpecific:
> +ResetPlatformSpecific (DataSize, ResetData);
> +return;
> +
> + default:
> +return ;
> + }
> +}
> +
> /**
>The library constructuor.
>
> --
> 2.21.0.windows.1
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[edk2-devel] [PATCH] IntelFsp2WrapperPkg/FspsWrapperPeim: Fix coding style.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1730
Internal code quality check failed after this commit:
68d47eea422d64eeb9872b927620f579f4ccfc0f, fixed those
coding style issues.
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 9f8ce16023..0f8cd69a0e 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -38,7 +38,7 @@ extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc;
extern EFI_GUID gFspHobGuid;
/**
- This function handles S3 resume task at the end of PEI
+ This function handles S3 resume task at the end of PEI.
@param[in] PeiServicesPointer to PEI Services Table.
@param[in] NotifyDesc Pointer to the descriptor for the Notification
event that
@@ -62,7 +62,7 @@ EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc = {
};
/**
- This function handles S3 resume task at the end of PEI
+ This function handles S3 resume task at the end of PEI.
@param[in] PeiServicesPointer to PEI Services Table.
@param[in] NotifyDesc Pointer to the descriptor for the Notification
event that
@@ -339,7 +339,7 @@ PeiMemoryDiscoveredNotify (
}
/**
- Do FSP initialization in API mode
+ Do FSP initialization in API mode.
@retval EFI_STATUSAlways return EFI_SUCCESS
**/
@@ -370,7 +370,7 @@ FspsWrapperInitApiMode (
}
/**
- Do FSP initialization in Dispatch mode
+ Do FSP initialization in Dispatch mode.
@retval FSP initialization status.
**/
@@ -399,7 +399,7 @@ FspsWrapperInitDispatchMode (
}
/**
- This is the entrypoint of PEIM
+ This is the entrypoint of PEIM.
@param[in] FileHandle Handle of the file being invoked.
@param[in] PeiServices Describes the list of possible PEI Services.
--
2.13.3.windows.1
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Re: [edk2-devel] [PATCH V2 6/8] IntelFsp2WrapperPkg/FspWrapperNotifyDxe: Decrease the name collisions
Reviewed-by: Chasel Chiu > -Original Message- > From: Gao, Zhichao > Sent: Wednesday, April 24, 2019 12:58 PM > To: devel@edk2.groups.io > Cc: Laszlo Ersek ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > ; Gao, Liming ; Bi, Dandan > > Subject: [PATCH V2 6/8] IntelFsp2WrapperPkg/FspWrapperNotifyDxe: Decrease > the name collisions > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1740 > > Add a 'static' descriptor to the global variables that only used in a single > file to > minimize the name collisions. > This is only for the varable named 'mExitBootServicesEvent'. > > Cc: Laszlo Ersek > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Liming Gao > Cc: Dandan Bi > Signed-off-by: Zhichao Gao > --- > IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > index fe344a5327..459acc694b 100644 > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > @@ -39,7 +39,7 @@ extern EFI_GUID gAddPerfRecordProtocolGuid; extern > EFI_GUID gFspHobGuid; extern EFI_GUID gFspApiPerformanceGuid; > > -EFI_EVENT mExitBootServicesEvent = NULL; > +static EFI_EVENT mExitBootServicesEvent = NULL; > > /** >Relocate this image under 4G memory. > -- > 2.21.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39455): https://edk2.groups.io/g/devel/message/39455 Mute This Topic: https://groups.io/mt/31318891/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH V3 6/8] IntelFsp2WrapperPkg/FspWrapperNotifyDxe: make global variable static
Reviewed-by: Chasel Chiu > -Original Message- > From: Gao, Zhichao > Sent: Friday, April 26, 2019 9:04 AM > To: devel@edk2.groups.io > Cc: Laszlo Ersek ; Kinney, Michael D > ; Gao, Liming ; Bi, > Dandan ; Chiu, Chasel ; > Desimone, Nathaniel L > Subject: [PATCH V3 6/8] IntelFsp2WrapperPkg/FspWrapperNotifyDxe: make > global variable static > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1740 > > Add a 'static' storage-class specifier to the global variables that only used > in a > single file to minimize the name collisions. > This is only for the variable named 'mExitBootServicesEvent'. > > Cc: Laszlo Ersek > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Dandan Bi > Signed-off-by: Zhichao Gao > Reviewed-by: Chasel Chiu > Reviewed-by: Nate DeSimone > --- > IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git > a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > index fe344a5327..0af0ec778c 100644 > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > @@ -1,7 +1,7 @@ > /** @file >This driver will register two callbacks to call fsp's notifies. > > - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved. > + Copyright (c) 2014 - 2019, Intel Corporation. All rights > + reserved. >SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -39,7 +39,7 @@ extern EFI_GUID gAddPerfRecordProtocolGuid; extern > EFI_GUID gFspHobGuid; extern EFI_GUID gFspApiPerformanceGuid; > > -EFI_EVENT mExitBootServicesEvent = NULL; > +static EFI_EVENT mExitBootServicesEvent = NULL; > > /** >Relocate this image under 4G memory. > -- > 2.21.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39605): https://edk2.groups.io/g/devel/message/39605 Mute This Topic: https://groups.io/mt/31348683/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms/devel-MinPlatform] [patch 1/2] KabylakeOpenBoardPkg/KBLRvp3: Remove PcdFrameworkCompatibilitySupport usage
Reviewed-by: Chasel Chiu > -Original Message- > From: Bi, Dandan > Sent: Friday, April 26, 2019 11:32 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael A > > Subject: [edk2-platforms/devel-MinPlatform] [patch 1/2] > KabylakeOpenBoardPkg/KBLRvp3: Remove > PcdFrameworkCompatibilitySupport usage > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1464 > > Framework compatibility support is no needed and > PcdFrameworkCompatibilitySupport will be removed from edk2. > So remove the usage of this PCD in platforms firstly. > > Cc: Chasel Chiu > Cc: Michael Kubacki > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Dandan Bi > --- > .../Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 1 - > 1 file changed, 1 deletion(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds > c > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds > c > index 51d4e2ea46..c0d566db21 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds > c > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d > +++ sc > @@ -17,11 +17,10 @@ > # > # Pcd Section - list of all EDK II PCD Entries defined by this Platform # > > > [PcdsFeatureFlag.common] > - > gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRU > E >gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE > > gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionF > irst|FALSE > !if $(TARGET) == RELEASE >gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE > !else > -- > 2.18.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39620): https://edk2.groups.io/g/devel/message/39620 Mute This Topic: https://groups.io/mt/31349693/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH V2] IntelSiliconPkg/IntelVTdDxe: Do global invalidation before boot
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Gao, Zhichao
> Sent: Thursday, May 9, 2019 11:34 AM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen ; Chiu, Chasel ;
> Ni, Ray ; Chaganty, Rangasai V
>
> Subject: [PATCH V2] IntelSiliconPkg/IntelVTdDxe: Do global invalidation before
> boot
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1547
>
> V2:
> Abandon V1.
> Do global invalidation of context-cache and IOTLB at ExitBootServices.
>
> V1:
> Only doing IOTLB invalidation would cause a BSOD
> 'DRIVER_VERIFIER_DMA_VIOLATION' while changing the second level page
> entry's attributes. So always do the global invalidation of context-cache and
> IOTLB.
>
> Cc: Jiewen Yao
> Cc: Chasel Chiu
> Cc: Ray Ni
> Cc: Rangasai V Chaganty
> Signed-off-by: Zhichao Gao
> ---
> .../Feature/VTd/IntelVTdDxe/DmaProtection.c | 13 +++-
> .../Feature/VTd/IntelVTdDxe/DmaProtection.h | 32 ++-
> 2 files changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
> b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
> index f221e45938..956ebb2d3d 100644
> --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
> +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
> @@ -1,6 +1,6 @@
> /** @file
>
> - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights
> + reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -581,9 +581,20 @@ OnExitBootServices (
>IN VOID*Context
>)
> {
> + UINTN VtdIndex;
> +
>DEBUG ((DEBUG_INFO, "Vtd OnExitBootServices\n"));
>DumpVtdRegsAll ();
>
> + DEBUG ((DEBUG_INFO, "Invalidate all\n")); for (VtdIndex = 0;
> + VtdIndex < mVtdUnitNumber; VtdIndex++) {
> +FlushWriteBuffer (VtdIndex);
> +
> +InvalidateContextCache (VtdIndex);
> +
> +InvalidateIOTLB (VtdIndex);
> + }
> +
>if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT1) == 0) {
> DisableDmar ();
> DumpVtdRegsAll ();
> diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
> b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
> index 72426d23c3..a3331db8f7 100644
> --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
> +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
> @@ -1,6 +1,6 @@
> /** @file
>
> - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights
> + reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -168,6 +168,36 @@ DisableDmar (
>VOID
>);
>
> +/**
> + Flush VTd engine write buffer.
> +
> + @param[in] VtdIndex The index used to identify a VTd engine.
> +**/
> +VOID
> +FlushWriteBuffer (
> + IN UINTN VtdIndex
> + );
> +
> +/**
> + Invalidate VTd context cache.
> +
> + @param[in] VtdIndex The index used to identify a VTd engine.
> +**/
> +EFI_STATUS
> +InvalidateContextCache (
> + IN UINTN VtdIndex
> + );
> +
> +/**
> + Invalidate VTd IOTLB.
> +
> + @param[in] VtdIndex The index used to identify a VTd engine.
> +**/
> +EFI_STATUS
> +InvalidateIOTLB (
> + IN UINTN VtdIndex
> + );
> +
> /**
>Invalid VTd global IOTLB.
>
> --
> 2.21.0.windows.1
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[edk2-devel] [PATCH] KabylakeOpenBoardPkg: Fixed system hang caused by MemoryTest.
From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1550 OS hang due to non-existing memory reported as usable memory. There are 2 different RVP3 boards and one with 4GB memory down implementation while another one with 8GB. Since rest of the configurations are exactly the same, board detection is added to the same RVP3 BoardInitLib and only SPD policy assigned differently. This also fixed below 2 issues: 1. Fixed build failuire when PcdMultiBoardSupport == FALSE. (Wrong Pcd TokenSpace used in DxeBoardAcpiTableLib.inf) 2. Always failed to read SPD from DIMM because SpdAddressTable policy was not updated properly. Fixed by a notify callback when policy PPI installed. Test: Verified both RVP3 boards can boot to Windows. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c | 103 +++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 17 ++--- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c | 4 ++-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 6 +++--- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3SpdTable.c | 117 - Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.c | 7 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3Detect.c | 83 +++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c | 127 ++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c | 4 ++-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c | 4 ++-- Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/BaseEcLib.c | 339 +++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf | 43 +++ Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 9 - Platform/Intel/KabylakeOpenBoardPkg/Include/EcCommands.h | 44 Platform/Intel/KabylakeOpenBoardPkg/Include/Library/EcLib.h | 106 ++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 8 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 3 ++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h | 4 +++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 3 ++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 12 ++-- Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/BaseEcLib.inf | 29 + 21 files changed, 1022 insertions(+), 50 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c new file mode 100644 index 00..0fedd81cd0 --- /dev/null +++
Re: [edk2-devel] [edk2-platforms][PATCH V1 1/1] Readme.md: Add Intel platforms
Reviewed-by: Chasel Chiu > -Original Message- > From: Kubacki, Michael A > Sent: Wednesday, May 22, 2019 12:49 AM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Desimone, Nathaniel L > ; Chiu, Chasel ; Gao, > Liming ; Ni, Ray > Subject: [edk2-platforms][PATCH V1 1/1] Readme.md: Add Intel platforms > > Adds information to Readme.md for Intel platforms recently moved to the > edk2-platforms repository. > > Cc: Michael D Kinney > Cc: Nate DeSimone > Cc: Chasel Chiu > Cc: Liming Gao > Cc: Ruiyu Ni > > Signed-off-by: Michael Kubacki > --- > Readme.md | 20 ++-- > 1 file changed, 14 insertions(+), 6 deletions(-) > > diff --git a/Readme.md b/Readme.md > index 59f739e861..e203795d47 100644 > --- a/Readme.md > +++ b/Readme.md > @@ -222,6 +222,20 @@ they will be documented with the platform. > * [D05](Platform/Hisilicon/D05) > * [HiKey](Platform/Hisilicon/HiKey) > > +## [Intel](Platform/Intel/Readme.md) > +### Minimum Platforms > +* [Clevo](Platform/Intel/ClevoOpenBoardPkg) > +* [Kaby Lake](Platform/Intel/KabylakeOpenBoardPkg) > +* [Purley](Platform/Intel/PurleyOpenBoardPkg) > + > +For more information, see the > +[EDK II Minimum Platform > Specification](https://edk2-docs.gitbooks.io/edk-ii-minimum-platform-specific > ation). > +### Other Platforms > +# Intel Quark SoC X1000 based platforms > +* [Galileo](Platform/Intel/QuarkPlatformPkg) > +# Minnowboard Max/Turbot based on Intel Valleyview2 SoC > +* [Minnowboard Max](Platform/Intel/Vlv2TbltDevicePkg) > + > ## Marvell > * [Armada 70x0](Platform/Marvell/Armada) > > @@ -231,12 +245,6 @@ they will be documented with the platform. > ## Socionext > * [SynQuacer](Platform/Socionext/DeveloperBox) > > -## Intel(R) Quark SoC X1000 based platforms > -* [Galileo](Platform/Intel/QuarkPlatformPkg) > - > -## Minnowboard Max/Turbot based on Intel Valleyview2 SoC > -* [Minnowboard Max](Platform/Intel/Vlv2TbltDevicePkg) > - > # Maintainers > > See [Maintainers.txt](Maintainers.txt). > -- > 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41174): https://edk2.groups.io/g/devel/message/41174 Mute This Topic: https://groups.io/mt/31698921/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [[edk2-platforms][PATCH V2] 01/30] edk2-platforms: Add License-History.txt
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Michael D Kinney > Sent: Thursday, May 16, 2019 7:10 AM > To: devel@edk2.groups.io > Cc: Leif Lindholm ; Ard Biesheuvel > ; Gillispie, Thad ; Bu, > Daocheng ; Oram, Isaac W > ; Piwko, Maciej ; Chiu, > Chasel ; Kubacki, Michael A > ; Lu, Shifei A ; Zhou, > Bowen ; Sinha, Ankit ; > Chaganty, Rangasai V > Subject: [edk2-devel] [[edk2-platforms][PATCH V2] 01/30] edk2-platforms: Add > License-History.txt > > Add text file that contains the history of license and contributor agreement > changes. > > https://bugzilla.tianocore.org/show_bug.cgi?id=1373 > > This change is based on the following emails: > > https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html > https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html > > RFCs with detailed process for the license change: > > V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html > V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html > V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html > > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Thad Gillispie > Cc: Daocheng Bu > Cc: Isaac W Oram > Cc: Maciej Piwko > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Shifei A Lu > Cc: Xiaohu Zhou > Cc: Ankit Sinha > Cc: Sai Chaganty > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Michael D Kinney > --- > License-History.txt | 542 > > 1 file changed, 542 insertions(+) > create mode 100644 License-History.txt > > diff --git a/License-History.txt b/License-History.txt new file mode 100644 > index > 00..8ab3f67b53 > --- /dev/null > +++ b/License-History.txt > @@ -0,0 +1,542 @@ > + License-History.txt > + === > + > +This file contains the history of license change and contributor's > +agreement changes. > + > +Unless otherwise noted in a specific file, the EDK2 project is now > +licensed under the terms listed in the License.txt file. Terms under > +which Contributions made prior to the move to the License.txt > +formulation are shown below. Those terms require notice of the terms > +themselves be preserved and presented with the contributions. This > +file serves that preservation purpose as a matter of documenting the history > of > the project. > + > +Key Dates > +-- > +* August 3, 2017 > + > + Update the TianoCore Contribution Agreement from Version 1.0 to > + Version 1.1 to cover open source documentation associated with the > + TianoCore project. > + > + Version 1.0 covers source code files. Version 1.1 is a backwards > + compatible extension that adds support for document files in both > + source form and compiled form. > + > + References: > + https://opensource.org/licenses/BSD-2-Clause > + Complete text of TianoCore Contribution Agreement 1.0 included below > + Complete text of TianoCore Contribution Agreement 1.1 included > + below > + > + Proposals (RFCs): > + https://lists.01.org/pipermail/edk2-devel/2017-March/008654.html > + > + TianoCore Bugzilla: > + https://bugzilla.tianocore.org/show_bug.cgi?id=629 > + > +* April 9, 2019 > + > + Replace BSD 2-Clause License with BSD + Patent License removing the > + need for the TianoCore Contribution Agreement. > + > + References: > + https://opensource.org/licenses/BSD-2-Clause > + Complete text of TianoCore Contribution Agreement 1.0 included below > + Complete text of TianoCore Contribution Agreement 1.1 included below > + https://opensource.org/licenses/BSDplusPatent > + > + Proposals (RFCs): > + https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html > + https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html > + > + TianoCore Bugzilla: > + https://bugzilla.tianocore.org/show_bug.cgi?id=1373 > + > +--- > +- > +License.txt: BSD 2-Clause License > + > +Redistribution and use in source and binary forms, with or without > +modification, are permitted provided that the following conditions > +are met: > + > +* Redistributions of source code must retain the above copyright > + notice, this list of conditions and the following disclaimer. > +* Redistributions in binary form must reproduce t
Re: [edk2-devel] [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions
Reviewed-by: Chasel Chiu > -Original Message- > From: Agyeman, Prince > Sent: Tuesday, May 21, 2019 11:08 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Agyeman, Prince > > Subject: [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme > with linux build instructions > > From: Prince Agyeman > > Signed-off-by: Prince Agyeman > --- > Platform/Intel/Readme.md | 42 -- > 1 file changed, 24 insertions(+), 18 deletions(-) > > diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index > 1da5d0a..443fb40 100644 > --- a/Platform/Intel/Readme.md > +++ b/Platform/Intel/Readme.md > @@ -107,9 +107,13 @@ return back to the minimum platform caller. > > **Building with the python script** > > -1. Open command window, go to the workspace directory, e.g. c:\Kabylake. > -2. Type "cd edk2-platforms\Platform\Intel -3. Type "python build_bios.py -p > REPLACE_WITH_BOARD_NAME" > +1. Open command window, go to the workspace directory, e.g. c:\Kabylake > +or ~/Kabylake in the case of a linux OS 2. If using a linux OS > + * Type "cd edk2" > + * Type "source edksetup.sh" > + * Type "cd ../" to go back to the workspace directory 3. Type "cd > +edk2-platforms/Platform/Intel 4. Type "python build_bios.py -p > +REPLACE_WITH_BOARD_NAME" > > * build_bios.py arguments: > > @@ -132,18 +136,19 @@ return back to the minimum platform caller. >| | > > * For more information on build options > - * ``Type "python build_bios.py -h"`` > + * Type "python build_bios.py -h" > > * Note > - * ``Python 2.7.16 and Python 3.7.3 compatible`` > - * ``These python build scripts have been tested on Windows due to`` > [cross-platform limitations](#Known-limitations) > + * Python 2.7.16 and Python 3.7.3 compatible > + * This python build script has been tested on Windows 10 and Ubuntu > + 16.04.5 LTS > + * See [cross-platform limitations](#Known-limitations) > > * Configuration Files > - * ``The edk2-platforms\Platform\Intel\build.cfg file contains the default > settings used by build_bios.py`` > - * ``The default settings are under the DEFAULT_CONFIG section`` > - * ``Each board can have a settings file that will override the > edk2-platforms\Platform\Intel\build.cfg settings`` > - * ``An example of a board specific settings:`` > -* > ``edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_ > config.cfg`` > + * The edk2-platforms\Platform\Intel\build.cfg file contains the > + default settings used by build_bios.py > + * The default settings are under the DEFAULT_CONFIG section > + * Each board can have a settings file that will override the > + edk2-platforms\Platform\Intel\build.cfg settings > + * An example of a board specific settings: > +* > + > edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_ > + config.cfg > > * Workspace view of the build scripts >* > @@ -212,14 +217,13 @@ Users can also flash the UEFI firmware image to the > highest area of the flash re > > ### **Known limitations** > > -* All firmware projects can only build on Windows with the validated > configuration below. > - * Cross-platform build support is work-in-progress. > - > **KabylakeOpenBoardPkg** > 1. This firmware project has only been tested on the Intel KabylakeRvp3 > board. > 2. This firmware project has only been tested booting to Microsoft Windows 10 > x64 with AHCI mode and Integrated Graphic >Device. > -3. This firmware project build has only been tested using the Microsoft > Visual > Studio 2015 compiler. > +3. The Windows build was tested on Windows 10 with Microsoft Visual Studio > 2015. > +4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0. > +5. The build was tested with NASM version 2.11.08. > > **PurleyOpenBoardPkg** > 1. This firmware project has only been tested on the Microsoft MtOlympus > board. > @@ -228,9 +232,11 @@ Users can also flash the UEFI firmware image to the > highest area of the flash re > > **ClevoOpenBoardPkg** > 1. Currently, support is only being added for the N1xxWU series of boards. > -2. The firmware project build has only been tested using the Microsoft Visual > Studio 2015 compiler. > -3. The firmware project has not been tested on an actual board, it *should > not* > be expected to boot. > -4. The firmware project applies to all Clevo supported board configurations > but > is only being tested on System 76 Galago > +2. The Windows build was tested
Re: [edk2-devel] [edk2-platforms] [PATCH 3/5] KabylakeOpenBoardPkg: Added GCC5 build support
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Agyeman, Prince > Sent: Thursday, May 16, 2019 1:36 AM > To: devel@edk2.groups.io > Cc: Agyeman, Prince > Subject: [edk2-devel] [edk2-platforms] [PATCH 3/5] KabylakeOpenBoardPkg: > Added GCC5 build support > > From: Prince Agyeman > > Fixed: > * Include file paths in dec > * Gcc build options > > Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm > version > 2.11.08 > > Signed-off-by: Prince Agyeman > --- > .../KabylakeRvp3/OpenBoardPkgBuildOption.dsc | 12 > Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec | 14 > -- > 2 files changed, 8 insertions(+), 18 deletions(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildO > ption.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuild > Option.dsc > index 318b057..19d81f7 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildO > ption.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuild > +++ Option.dsc > @@ -1,15 +1,9 @@ > ## @file > # platform build option configuration file. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > -# This program and the accompanying materials are licensed and made available > under -# the terms and conditions of the BSD License which accompanies this > distribution. > -# The full text of the license may be found at -# > http://opensource.org/licenses/bsd-license.php > -# > -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > +#SPDX-License-Identifier: BSD-2-Clause-Patent > # > ## > > @@ -108,6 +102,7 @@ DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $( # For IA32 Specific Build Flag # > GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-unused > -Wl,--allow-multiple-definition > MSFT: *_*_IA32_ASM_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 > -DASF_PEI > MSFT: *_*_IA32_VFRPP_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > @@ -130,6 +125,7 @@ MSFT: *_*_IA32_ASLCC_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_D > # For X64 Specific Build Flag > # > GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused > -Wl,--allow-multiple-definition > MSFT: *_*_X64_ASM_FLAGS = > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 > MSFT: *_*_X64_VFRPP_FLAGS= > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > diff --git a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > index d0fdb10..ddd8b40 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > +++ b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > @@ -5,15 +5,9 @@ > # INF files to generate AutoGen.c and AutoGen.h files # for the build > infrastructure. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved. > # > -# This program and the accompanying materials are licensed and made available > under -# the terms and conditions of the BSD License which accompanies this > distribution. > -# The full text of the license may be found at -# > http://opensource.org/licenses/bsd-license.php > -# > -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > +#SPDX-License-Identifier: BSD-2-Clause-Patent > # > ## > > @@ -26,8 +20,8 @@ PACKAGE_GUID = > 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E > > [Includes] > Include > -KabylakeRvp3\Include > -Features\Tbt\Include > +KabylakeRvp3/Include > +Features/Tbt/Include > > [Guids] > > -- > 2.7.4 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41100): https://edk2.groups.io/g/devel/message/41100 Mute This Topic: https://groups.io/mt/31632305/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms] [PATCH 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI
Reviewed-by: Chasel Chiu
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Agyeman, Prince
> Sent: Thursday, May 16, 2019 1:36 AM
> To: devel@edk2.groups.io
> Cc: Agyeman, Prince ; Kubacki, Michael A
> ; Kinney, Michael D
> ; Desimone, Nathaniel L
> ; Gao, Liming ; Sinha,
> Ankit
> Subject: [edk2-devel] [edk2-platforms] [PATCH 2/5] KabylakeSiliconPkg: Casting
> functions to EFIAPI
>
> From: Prince Agyeman
>
> This fixes the calling convension issues in gcc
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm
> version
> 2.11.08
>
> Cc: Michael Kubacki
> Cc: Michael D Kinney
> Cc: Nate DeSimone
> Cc: Liming Gao
> Cc: Ankit Sinha
>
> Signed-off-by: Prince Agyeman
> ---
> .../Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h| 11 +++
> .../Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c| 11
> +++
> .../KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h | 12
>
> .../KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c | 12
>
> 4 files changed, 14 insertions(+), 32 deletions(-)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> index 58ef567..666340e 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> @@ -1,14 +1,8 @@
> /** @file
>Header file for PCH Init SMM Handler
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved. -This program
> and the accompanying materials are licensed and made available under -the
> terms and conditions of the BSD License that accompanies this distribution.
> -The full text of the license may be found at
> -http://opensource.org/licenses/bsd-license.php.
> -
> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
> OR IMPLIED.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
>
> @@ -211,6 +205,7 @@ PchPcieLinkEqHandlerFunction (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
>IN EFI_HANDLE DispatchHandle,
>IN EFI_SMM_IO_TRAP_CONTEXT*CallbackContext,
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> index b4234f6..847fbfb 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> @@ -1,14 +1,8 @@
> /** @file
>PCH Pcie SMM Driver Entry
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved. -This program
> and the accompanying materials are licensed and made available under -the
> terms and conditions of the BSD License that accompanies this distribution.
> -The full text of the license may be found at
> -http://opensource.org/licenses/bsd-license.php.
> -
> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
> OR IMPLIED.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> #include "PchInitSmm.h"
> @@ -244,6 +238,7 @@ PchPciePmIoTrapSmiCallback (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
>IN EFI_HANDLEDispatchHandle,
>IN EFI_SMM_IO_TRAP_CONTEXT*CallbackContext,
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> index 3eebdc1..a9f0664 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> +++
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> @@ -1,14 +1,8 @@
> /** @file
>Prototypes and defines for the PCH SMM Dispatcher.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved. -This program
> and the accompanying materials are licensed and made available under -the
> terms and conditions of the BSD License that accompanies this distribution.
> -The full text of the license may be found at
> -http://opensource.org/licenses/bsd-license.php.
> -
> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
> OR IMPLIED.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> #ifndef PCH_SMM_H
> @@ -516,6 +510,7 @@ typedef struct {
>registered and the SMI source has been
> enabled.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreRegister (
>IN PCH_SMM_GENERIC_PROTOCOL *This,
>IN
Re: [edk2-devel] [PATCH] IntelFsp2Pkg: FSP Python scripts to support 3.x.
Yes. It works! I will update patch.
Thanks!
Chasel
> -Original Message-
> From: Zeng, Star
> Sent: Friday, June 28, 2019 10:28 AM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: Ma, Maurice ; Desimone, Nathaniel L
> ; Zeng, Star
> Subject: RE: [edk2-devel] [PATCH] IntelFsp2Pkg: FSP Python scripts to support
> 3.x.
>
> It is ok to directly use below code without python version check?
>
> +for loop in range(int(unit)):
> +bytearray.append("0x%02X" % (value & 0xFF))
> +value = value >> 8
>
>
> Thanks,
> Star
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Chiu,
> Chasel
> Sent: Monday, June 24, 2019 10:35 PM
> To: devel@edk2.groups.io
> Cc: Ma, Maurice ; Desimone, Nathaniel L
> ; Zeng, Star
> Subject: [edk2-devel] [PATCH] IntelFsp2Pkg: FSP Python scripts to support 3.x.
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=1930
>
> Updated FSP Python scripts to support both 2.x and 3.x.
>
> Test:
> . Verified with Python 2.7.12 and 3.6.6.
> . Verified tool result is the same before the change.
> . Both py -2 and py -3 built binary can boot.
>
> Cc: Maurice Ma
> Cc: Nate DeSimone
> Cc: Star Zeng
> Signed-off-by: Chasel Chiu
> ---
> IntelFsp2Pkg/Tools/GenCfgOpt.py | 70
> ++
> IntelFsp2Pkg/Tools/PatchFv.py | 36 +++-
> IntelFsp2Pkg/Tools/SplitFspBin.py | 74
> +++--
> -
> 3 files changed, 116 insertions(+), 64 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py
> b/IntelFsp2Pkg/Tools/GenCfgOpt.py index 450c4e3eb9..e0441966ac 100644
> --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
> +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
> @@ -1,6 +1,6 @@
> ## @ GenCfgOpt.py
> #
> -# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2014 - 2019, Intel Corporation. All rights
> +reserved.
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -10,6 +10,7 @@
> import re import sys import struct
> from datetime import date
> +from functools import reduce
>
> # Generated file copyright header
>
> @@ -90,11 +91,11 @@ class CLogicalExpression:
> self.string = ''
>
> def errExit(self, err = ''):
> -print "ERROR: Express parsing for:"
> -print " %s" % self.string
> -print " %s^" % (' ' * self.index)
> +print ("ERROR: Express parsing for:")
> +print (" %s" % self.string)
> +print (" %s^" % (' ' * self.index))
> if err:
> -print "INFO : %s" % err
> +print ("INFO : %s" % err)
> raise SystemExit
>
> def getNonNumber (self, n1, n2):
> @@ -338,15 +339,15 @@ EndList
> else:
> Error = 0
> if self.Debug:
> -print "INFO : Macro dictionary:"
> +print ("INFO : Macro dictionary:")
> for Each in self._MacroDict:
> -print " $(%s) = [ %s ]" % (Each ,
> self._MacroDict[Each])
> +print (" $(%s) = [ %s ]" % (Each ,
> self._MacroDict[Each]))
> return Error
>
> def EvaulateIfdef (self, Macro):
> Result = Macro in self._MacroDict
> if self.Debug:
> -print "INFO : Eval Ifdef [%s] : %s" % (Macro, Result)
> +print ("INFO : Eval Ifdef [%s] : %s" % (Macro, Result))
> return Result
>
> def ExpandMacros (self, Input):
> @@ -359,7 +360,7 @@ EndList
>Line = Line.replace(Each, self._MacroDict[Variable])
>else:
>if self.Debug:
> - print "WARN : %s is not defined" % Each
> + print ("WARN : %s is not defined" % Each)
>Line = Line.replace(Each, Each[2:-1])
> return Line
>
> @@ -372,7 +373,7 @@ EndList
>Line = Line.replace(PcdName, self._PcdsDict[PcdName])
>else:
>if self.Debug:
> - print "WARN : %s is not defined" % PcdName
> + print ("WARN : %s is not defined" % PcdName)
> return Line
>
> def EvaluateExpress (self, Expr):
> @@ -381,7 +382,7 @@ EndList
> LogExp
Re: [edk2-devel] [PATCH] Maintainers.txt: Remove maintainer info for IntelFsp[Wrapper]Pkg
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ni, > Ray > Sent: Wednesday, July 10, 2019 4:05 PM > To: devel@edk2.groups.io > Cc: Andrew Fish ; Laszlo Ersek ; Leif > Lindholm ; Kinney, Michael D > ; Gao, Liming > Subject: [edk2-devel] [PATCH] Maintainers.txt: Remove maintainer info for > IntelFsp[Wrapper]Pkg > > Signed-off-by: Ray Ni > Cc: Andrew Fish > Cc: Laszlo Ersek > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Liming Gao > --- > Maintainers.txt | 12 > 1 file changed, 12 deletions(-) > > diff --git a/Maintainers.txt b/Maintainers.txt index 788b46202c..eb41dba7b1 > 100644 > --- a/Maintainers.txt > +++ b/Maintainers.txt > @@ -130,18 +130,6 @@ M: Chasel Chiu > R: Nate DeSimone > R: Star Zeng > > -IntelFspPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg > -M: Chasel Chiu > -R: Nate DeSimone > -R: Star Zeng > - > -IntelFspWrapperPkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/IntelFspWrapperPkg > -M: Chasel Chiu > -R: Nate DeSimone > -R: Star Zeng > - > MdeModulePkg > W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg > M: Jian J Wang > -- > 2.21.0.windows.1 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#43477): https://edk2.groups.io/g/devel/message/43477 Mute This Topic: https://groups.io/mt/32414115/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] Revert "FmpDevicePkg: Fix various typos"
Revert patch submitted: efa12a3f029bd6ff4d2ada406c285f001b252907 Reapply patch submitted: 91cc60bafc7d6e49b7bc85990f895d6228f51364 Thanks! Chasel > -Original Message- > From: Antoine Cœur [mailto:co...@gmx.fr] > Sent: Thursday, July 11, 2019 5:37 PM > To: devel@edk2.groups.io > Cc: Antoine Cœur ; Zeng, Star ; Chiu, > Chasel > Subject: [PATCH] Revert "FmpDevicePkg: Fix various typos" > > This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b. > Commit message was incorrect. > > Signed-off-by: Coeur > --- > .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- > .../FspSecCore/Ia32/InitializeFpu.nasm| 4 +-- > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 4 +-- > IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 +-- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 +-- > IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- > .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 4 +-- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 8 ++--- > .../Include/Library/FspSecPlatformLib.h | 4 +-- > IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 12 +++ > .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +-- > .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 4 +-- > .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-- > .../PlatformSecLibNull.c | 4 +-- > IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- > IntelFsp2Pkg/Tools/PatchFv.py | 2 +- > .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- > .../Tools/UserManuals/PatchFvUserManual.md| 2 +- > 18 files changed, 52 insertions(+), 52 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > index e7261b41cd..f14c18c7b9 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -194,9 +194,9 @@ StackSetupDone: > >; >; Pass BFV into the PEI Core > - ; It uses relative address to calculate the actual boot FV base > + ; It uses relative address to calucate the actual boot FV base >; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase > and > - ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, > + ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, >; they are different. The code below can handle both cases. >; >callASM_PFX(AsmGetFspBaseAddress) > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > index ebc91c41e4..e1886ea11b 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > @@ -1,6 +1,6 @@ > > ;-- > ; > -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > +; Copyright (c) 2015, Intel Corporation. All rights reserved. > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: > @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): > fldcw[ASM_PFX(mFpuControlWord)] > > ; > -; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index 4c321cbece..b257deb76c 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -1,6 +1,6 @@ > > ;-- > ; > -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > +; Copyright (c) 2015, Intel Corporation. All rights reserved. > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: > @@ -150,7 +150,7 @@ NextAddress: > fldcw [FpuControlWord] > > ; > -; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to > + test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > index 5a7e27c240..d72212ed45 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > @@ -1,6 +1,6 @@ > > ;
Re: [edk2-devel] [PATCH] IntelFsp2Pkg: Fix various typos
Patch pushed: f527942e6bdd9f198db90f2de99a0482e9be5b1b Thanks! Chasel > -Original Message- > From: Antoine Cœur [mailto:co...@gmx.fr] > Sent: Friday, July 5, 2019 10:17 PM > To: devel@edk2.groups.io; Desimone, Nathaniel L > ; Zeng, Star ; Chiu, > Chasel > Cc: Antoine Cœur > Subject: [PATCH] IntelFsp2Pkg: Fix various typos > > Fix various typos in IntelFsp2Pkg. > --- > .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- > .../FspSecCore/Ia32/InitializeFpu.nasm| 2 +- > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 2 +- > IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 2 +- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +- > IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- > .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 2 +- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 6 ++-- > .../Include/Library/FspSecPlatformLib.h | 2 +- > IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 10 +++--- > .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +-- > .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 2 +- > .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- > .../PlatformSecLibNull.c | 2 +- > IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- > IntelFsp2Pkg/Tools/PatchFv.py | 2 +- > .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- > .../Tools/UserManuals/PatchFvUserManual.md| 2 +- > 18 files changed, 41 insertions(+), 41 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > index f14c18c7b9..e7261b41cd 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -194,9 +194,9 @@ StackSetupDone: > >; >; Pass BFV into the PEI Core > - ; It uses relative address to calucate the actual boot FV base > + ; It uses relative address to calculate the actual boot FV base >; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase > and > - ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, > + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, >; they are different. The code below can handle both cases. >; >callASM_PFX(AsmGetFspBaseAddress) > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > index e1886ea11b..c45520c6c1 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): > fldcw[ASM_PFX(mFpuControlWord)] > > ; > -; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index b257deb76c..09cb813497 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -150,7 +150,7 @@ NextAddress: > fldcw [FpuControlWord] > > ; > -; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to > + test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > index d72212ed45..f183d0d10b 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): > mov esp, eax ; From now, esp is pointed to > permanent > memory > > ; > -; Fixup the ebp point to permenent memory > +; Fixup the ebp point to permanent memory > ; > mov eax, ebp > sub eax, ebx > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c > b/IntelFsp2Pkg/FspSecCore/SecFsp.c > index 6497c88ebe..a939b7e836 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c > @@ -169,7 +169,7 @@ FspGlobalDataInit ( >SerialPortInitialize (); > >// > - // Ensure the golbal data pointer is valid > + // Ensure the global data pointer is valid >// >ASSERT (GetFspGlobalDataPointer () == PeiFspData); > > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c > b/IntelFsp2Pkg/FspSecCore/SecMain.c > index cd3ab46ce2..a63
Re: [edk2-devel] [PATCH] IntelFsp2Pkg: Fix various typos
Reviewed-by: Chasel Chiu Thanks!! > -Original Message- > From: Antoine Cœur [mailto:co...@gmx.fr] > Sent: Friday, July 5, 2019 10:17 PM > To: devel@edk2.groups.io; Desimone, Nathaniel L > ; Zeng, Star ; Chiu, > Chasel > Cc: Antoine Cœur > Subject: [PATCH] IntelFsp2Pkg: Fix various typos > > Fix various typos in IntelFsp2Pkg. > --- > .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- > .../FspSecCore/Ia32/InitializeFpu.nasm| 2 +- > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 2 +- > IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 2 +- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +- > IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- > .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 2 +- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 6 ++-- > .../Include/Library/FspSecPlatformLib.h | 2 +- > IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 10 +++--- > .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +-- > .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 2 +- > .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- > .../PlatformSecLibNull.c | 2 +- > IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- > IntelFsp2Pkg/Tools/PatchFv.py | 2 +- > .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- > .../Tools/UserManuals/PatchFvUserManual.md| 2 +- > 18 files changed, 41 insertions(+), 41 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > index f14c18c7b9..e7261b41cd 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -194,9 +194,9 @@ StackSetupDone: > >; >; Pass BFV into the PEI Core > - ; It uses relative address to calucate the actual boot FV base > + ; It uses relative address to calculate the actual boot FV base >; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase > and > - ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, > + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, >; they are different. The code below can handle both cases. >; >callASM_PFX(AsmGetFspBaseAddress) > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > index e1886ea11b..c45520c6c1 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): > fldcw[ASM_PFX(mFpuControlWord)] > > ; > -; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index b257deb76c..09cb813497 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -150,7 +150,7 @@ NextAddress: > fldcw [FpuControlWord] > > ; > -; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to > + test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > index d72212ed45..f183d0d10b 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): > mov esp, eax ; From now, esp is pointed to > permanent > memory > > ; > -; Fixup the ebp point to permenent memory > +; Fixup the ebp point to permanent memory > ; > mov eax, ebp > sub eax, ebx > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c > b/IntelFsp2Pkg/FspSecCore/SecFsp.c > index 6497c88ebe..a939b7e836 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c > @@ -169,7 +169,7 @@ FspGlobalDataInit ( >SerialPortInitialize (); > >// > - // Ensure the golbal data pointer is valid > + // Ensure the global data pointer is valid >// >ASSERT (GetFspGlobalDataPointer () == PeiFspData); > > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c > b/IntelFsp2Pkg/FspSecCore/SecMain.c > index cd3ab46ce2..a63
[edk2-devel] [PATCH v2] MinPlatformPkg: FSP Python script to python 3.x.
https://bugzilla.tianocore.org/show_bug.cgi?id=1930
Updated FSP Python script to support both 2.x and
3.x.
Test:
. Verified with Python 2.7.12 and 3.6.6.
. Verified tool result is the same before the change.
. Both py -2 and py -3 built binary can boot.
Cc: Michael Kubacki
Cc: Nate DeSimone
Cc: Liming Gao
Signed-off-by: Chasel Chiu
---
Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py |
34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git
a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
index 167a0e0a4c..406e5ec130 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
@@ -10,16 +10,16 @@ import re
import subprocess
if len(sys.argv) not in [6,7]:
- print "RebaseAndPatchFspBinBaseAddress.py - Error in number of arguments
received"
- print "Usage - RebaseAndPatchFspBinBaseAddress.py
\
-"
+ print ("RebaseAndPatchFspBinBaseAddress.py - Error in number of arguments
received")
+ print ("Usage - RebaseAndPatchFspBinBaseAddress.py
\
+")
exit(1)
flashMapName = sys.argv[1]
fspBinPath= sys.argv[2]
fspBinFile= sys.argv[3]
targetDscFile = sys.argv[4]
-fvOffset = long(sys.argv[5], 16)
+fvOffset = int(sys.argv[5], 16)
fspBinFileRebased = "Fsp_Rebased.fd"
splitFspBinPath =
os.path.join("edk2","IntelFsp2Pkg","Tools","SplitFspBin.py")
@@ -30,21 +30,21 @@ if len(sys.argv) == 7:
# Make sure argument passed or valid
#
if not os.path.exists(flashMapName):
- print "WARNING! " + str(flashMapName) + " is not found."
+ print ("WARNING! " + str(flashMapName) + " is not found.")
exit(1)
fspBinFilePath = fspBinPath + os.sep + fspBinFile
if not os.path.exists(fspBinFilePath):
- print "WARNING! " + str(fspBinFilePath) + " is not found."
+ print ("WARNING! " + str(fspBinFilePath) + " is not found.")
exit(1)
if not os.path.exists(targetDscFile):
- print "WARNING! " + str(targetDscFile) + " is not found."
+ print ("WARNING! " + str(targetDscFile) + " is not found.")
exit(1)
ext_file = str(os.path.splitext(targetDscFile)[-1]).lower()
if ext_file != ".dsc":
- print "WARNING! " + str(targetDscFile) + " is not a dsc file"
+ print ("WARNING! " + str(targetDscFile) + " is not a dsc file")
exit(1)
if not os.path.exists(splitFspBinPath):
- print "WARNING! " + str(splitFspBinPath) + " is not found."
+ print ("WARNING! " + str(splitFspBinPath) + " is not found.")
exit(1)
#
@@ -54,7 +54,7 @@ file = open (flashMapName, "r")
data = file.read ()
# Get the Flash Base Address
-flashBase = long(data.split("FLASH_BASE")[1].split("=")[1].split()[0], 16)
+flashBase = int(data.split("FLASH_BASE")[1].split("=")[1].split()[0], 16)
# Based on Build Target, select the section in the FlashMap file
flashmap = data
@@ -62,11 +62,11 @@ flashmap = data
# Get FSP-S & FSP-M & FSP-T offset & calculate the base
for line in flashmap.split("\n"):
if "PcdFlashFvFspSOffset" in line:
-fspSBaseOffset = long(line.split("=")[1].split()[0], 16)
+fspSBaseOffset = int(line.split("=")[1].split()[0], 16)
if "PcdFlashFvFspMOffset" in line:
-fspMBaseOffset = long(line.split("=")[1].split()[0], 16)
+fspMBaseOffset = int(line.split("=")[1].split()[0], 16)
if "PcdFlashFvFspTOffset" in line:
-fspTBaseOffset = long(line.split("=")[1].split()[0], 16)
+fspTBaseOffset = int(line.split("=")[1].split()[0], 16)
file.close()
#
@@ -78,10 +78,10 @@ if 'PYTHON_HOME' in os.environ:
pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
Process = subprocess.Popen([pythontool, splitFspBinPath,
"info","-f",fspBinFilePath], stdout=subprocess.PIPE)
Output = Process.communicate()[0]
-FsptInfo = Output.rsplit("FSP_M", 1);
-for line in FsptInfo[1].split("\n"):
- if "ImageSize" in line:
-fspMSize = long(line.split("=")[1], 16)
+FsptInfo = Output.rsplit(b"FSP_M", 1);
+for line in FsptInfo[1].split(b"\n"):
+ if b"ImageSize" in line:
+fspMSize = int(line.split(b"=")[1], 16)
break
# Calculate FSP-S/M/T base address, to which re-base has to be done
--
2.13.3.windows.1
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[edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP Python scripts to support 3.x.
https://bugzilla.tianocore.org/show_bug.cgi?id=1930
Updated FSP Python scripts to support both 2.x and
3.x.
Test:
. Verified with Python 2.7.12 and 3.6.6.
. Verified tool result is the same before the change.
. Both py -2 and py -3 built binary can boot.
Cc: Maurice Ma
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Tools/GenCfgOpt.py | 61
+++--
IntelFsp2Pkg/Tools/PatchFv.py | 36 +++-
IntelFsp2Pkg/Tools/SplitFspBin.py | 74
+++---
3 files changed, 109 insertions(+), 62 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 450c4e3eb9..c4e1e6239d 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -1,6 +1,6 @@
## @ GenCfgOpt.py
#
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -10,6 +10,7 @@ import re
import sys
import struct
from datetime import date
+from functools import reduce
# Generated file copyright header
@@ -90,11 +91,11 @@ class CLogicalExpression:
self.string = ''
def errExit(self, err = ''):
-print "ERROR: Express parsing for:"
-print " %s" % self.string
-print " %s^" % (' ' * self.index)
+print ("ERROR: Express parsing for:")
+print (" %s" % self.string)
+print (" %s^" % (' ' * self.index))
if err:
-print "INFO : %s" % err
+print ("INFO : %s" % err)
raise SystemExit
def getNonNumber (self, n1, n2):
@@ -338,15 +339,15 @@ EndList
else:
Error = 0
if self.Debug:
-print "INFO : Macro dictionary:"
+print ("INFO : Macro dictionary:")
for Each in self._MacroDict:
-print " $(%s) = [ %s ]" % (Each ,
self._MacroDict[Each])
+print (" $(%s) = [ %s ]" % (Each ,
self._MacroDict[Each]))
return Error
def EvaulateIfdef (self, Macro):
Result = Macro in self._MacroDict
if self.Debug:
-print "INFO : Eval Ifdef [%s] : %s" % (Macro, Result)
+print ("INFO : Eval Ifdef [%s] : %s" % (Macro, Result))
return Result
def ExpandMacros (self, Input):
@@ -359,7 +360,7 @@ EndList
Line = Line.replace(Each, self._MacroDict[Variable])
else:
if self.Debug:
- print "WARN : %s is not defined" % Each
+ print ("WARN : %s is not defined" % Each)
Line = Line.replace(Each, Each[2:-1])
return Line
@@ -372,7 +373,7 @@ EndList
Line = Line.replace(PcdName, self._PcdsDict[PcdName])
else:
if self.Debug:
- print "WARN : %s is not defined" % PcdName
+ print ("WARN : %s is not defined" % PcdName)
return Line
def EvaluateExpress (self, Expr):
@@ -381,7 +382,7 @@ EndList
LogExpr = CLogicalExpression()
Result = LogExpr.evaluateExpress (ExpExpr)
if self.Debug:
-print "INFO : Eval Express [%s] : %s" % (Expr, Result)
+print ("INFO : Eval Express [%s] : %s" % (Expr, Result))
return Result
def FormatListValue(self, ConfigDict):
@@ -406,7 +407,7 @@ EndList
bytearray = []
for each in dataarray:
value = each
-for loop in xrange(unit):
+for loop in range(int(unit)):
bytearray.append("0x%02X" % (value & 0xFF))
value = value >> 8
newvalue = '{' + ','.join(bytearray) + '}'
@@ -548,7 +549,7 @@ EndList
if Match:
self._MacroDict[Match.group(1)] = Match.group(2)
if self.Debug:
-print "INFO : DEFINE %s = [ %s ]" % (Match.group(1),
Match.group(2))
+print ("INFO : DEFINE %s = [ %s ]" % (Match.group(1),
Match.group(2)))
elif IsPcdSect:
#gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE
#gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
@@ -556,7 +557,7 @@ EndList
if Match:
self._PcdsDict[Match.group(1)] = Match.group(2)
if self.Debug:
-print "INFO : PCD %s = [ %s ]" % (Match.group(1),
Match.group(2))
+print ("INFO : PCD %s = [ %s ]" % (Match.group(1),
Match.group(2)))
i = 0
while i < len(BuildOptionPcd):
Match = re.match("\s*([\w\.]+)\s*\=\s*(\w+)",
BuildOptionPcd[i])
@@
Re: [edk2-devel] [PATCH] MdeModulePkg SmbiosMeasurementDxe: Add Type4 Voltage field to blacklist
Reviewed-by: Chasel Chiu
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Zeng,
> Star
> Sent: Thursday, June 27, 2019 7:15 PM
> To: devel@edk2.groups.io
> Cc: Zeng, Star ; Wang, Jian J ;
> Wu,
> Hao A ; Ni, Ray ; Kuo, Donald
> ; Chiu, Chasel
> Subject: [edk2-devel] [PATCH] MdeModulePkg SmbiosMeasurementDxe: Add
> Type4 Voltage field to blacklist
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1922
>
> The Type4 Voltage field may be various.
> So this patch adds it into the blacklist.
>
> Signed-off-by: Star Zeng
> Cc: Jian J Wang
> Cc: Hao A Wu
> Cc: Ray Ni
> Cc: Donald Kuo
> Cc: Chasel Chiu
> ---
> .../Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.c| 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
> a/MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementD
> xe.c
> b/MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementD
> xe.c
> index 229d4c5f2c5c..7b5d4731466d 100644
> ---
> a/MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementD
> xe.c
> +++
> b/MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementD
> xe.c
> @@ -64,6 +64,7 @@ SMBIOS_FILTER_TABLE mSmbiosFilterType4BlackList[] = {
>{0x04, OFFSET_OF(SMBIOS_TABLE_TYPE4, CoreCount2),
> FIELD_SIZE_OF(SMBIOS_TABLE_TYPE4, CoreCount2), 0},
>{0x04, OFFSET_OF(SMBIOS_TABLE_TYPE4, EnabledCoreCount2),
> FIELD_SIZE_OF(SMBIOS_TABLE_TYPE4, EnabledCoreCount2),0},
>{0x04, OFFSET_OF(SMBIOS_TABLE_TYPE4, ThreadCount2),
> FIELD_SIZE_OF(SMBIOS_TABLE_TYPE4, ThreadCount2), 0},
> + {0x04, OFFSET_OF(SMBIOS_TABLE_TYPE4, Voltage),
> FIELD_SIZE_OF(SMBIOS_TABLE_TYPE4, Voltage), 0},
> };
> SMBIOS_FILTER_TABLE mSmbiosFilterType17BlackList[] = {
>{0x11, OFFSET_OF(SMBIOS_TABLE_TYPE17, SerialNumber),
> FIELD_SIZE_OF(SMBIOS_TABLE_TYPE17, SerialNumber),
> SMBIOS_FILTER_TABLE_FLAG_IS_STRING},
> --
> 2.21.0.windows.1
>
>
>
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Re: [edk2-devel] [RFC] BZ 2067 BaseTools/Scripts: Add GetUtcDateTime.py for edk2-stable201908 stable tag.
Hi Leif, Thanks for the valuable feedbacks and suggestions. I will re-write script and re-send code review. Regards, Chasel > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Leif > Lindholm > Sent: Wednesday, August 14, 2019 2:30 AM > To: Gao, Liming > Cc: Chiu, Chasel ; r...@edk2.groups.io; Feng, Bob C > ; devel@edk2.groups.io; Cetola, Stephano > ; Laszlo Ersek (ler...@redhat.com) > ; af...@apple.com; Kinney, Michael D > > Subject: Re: [edk2-devel] [RFC] BZ 2067 BaseTools/Scripts: Add > GetUtcDateTime.py for edk2-stable201908 stable tag. > > I am not fundamentally opposed to merging a simple script that does not affect > other code in the tree. > > *But* the fact that we have multiple occurrences of this this time around *is* > a bit of a concern for me. Yes, they won't affect the workings of anything > else > as part of the release. But they will not have had any chance to be actually > used > by others. > > For this particular script, I am also not very keen on the implementation. It > manually parses the command line and prints usage instead of using argparse. > And it contains the sys.exit(Main()) antipattern, which does not play well > with > Python3 asynchronous i/o (and hence is a bad habit to get into). > > Since this script is truly trivial, I am OK for it to be included *if* it is > rewritten > using argparse and not calling sys.exit. > > Best Regards, > > Leif > > On Tue, Aug 13, 2019 at 01:42:23PM +, Gao, Liming wrote: > > This is a small helper script. I am OK to add it for edk2-stable201908 > > stable > tag. > > > > Thanks > > Liming > > From: Chiu, Chasel > > Sent: Monday, August 12, 2019 3:45 PM > > To: r...@edk2.groups.io > > Cc: Gao, Liming ; Feng, Bob C > > ; devel@edk2.groups.io > > Subject: [RFC] BZ 2067 BaseTools/Scripts: Add GetUtcDateTime.py for > edk2-stable201908 stable tag. > > > > > > Hello, > > > > I would like to add below simple script to 201908 stable tag, review was > > sent > on August 8th: > > > > A script that can return UTC date and time in ascii format which is > > convenient > for patching build time information in any binary. > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2067 > > Patch: https://edk2.groups.io/g/devel/topic/32797962#45177 > > > > Thanks! > > Chasel > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45583): https://edk2.groups.io/g/devel/message/45583 Mute This Topic: https://groups.io/mt/32838481/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2] BaseTools/Scripts: Add GetUtcDateTime script.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2067
A script that can return UTC date and time in ascii
format which is convenient for patching build time
information in any binary.
Cc: Bob Feng
Cc: Liming Gao
Cc: Leif Lindholm
Signed-off-by: Chasel Chiu
---
BaseTools/Scripts/GetUtcDateTime.py | 44
1 file changed, 44 insertions(+)
diff --git a/BaseTools/Scripts/GetUtcDateTime.py
b/BaseTools/Scripts/GetUtcDateTime.py
new file mode 100644
index 00..3cfb6ac2ae
--- /dev/null
+++ b/BaseTools/Scripts/GetUtcDateTime.py
@@ -0,0 +1,44 @@
+## @file
+# Get current UTC date and time information and output as ascii code.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+VersionNumber = '0.1'
+import sys
+import datetime
+import argparse
+
+def Main():
+PARSER = argparse.ArgumentParser(
+description='Retrieves UTC date and time information (output ordering:
year, date, time) - Version ' + VersionNumber)
+PARSER.add_argument('--year',
+action='store_true',
+help='Return UTC year of now. [Example output (2019):
39313032]')
+PARSER.add_argument('--date',
+action='store_true',
+help='Return UTC date MMDD of now. [Example output
(7th August): 37303830]')
+PARSER.add_argument('--time',
+action='store_true',
+help='Return 24-hour-format UTC time HHMM of now.
[Example output (14:25): 35323431]')
+
+ARGS = PARSER.parse_args()
+if len(sys.argv) == 1:
+print ("ERROR: At least one argument is required!\n")
+PARSER.print_help()
+
+today = datetime.datetime.utcnow()
+if ARGS.year:
+ReversedNumber = str(today.year)[::-1]
+print (''.join(hex(ord(HexString))[2:] for HexString in
ReversedNumber))
+if ARGS.date:
+ReversedNumber = str(today.strftime("%m%d"))[::-1]
+print (''.join(hex(ord(HexString))[2:] for HexString in
ReversedNumber))
+if ARGS.time:
+ReversedNumber = str(today.strftime("%H%M"))[::-1]
+print (''.join(hex(ord(HexString))[2:] for HexString in
ReversedNumber))
+
+if __name__ == '__main__':
+Main()
--
2.13.3.windows.1
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Re: [edk2-devel] [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
Yes, we will remove them later after confirming no impact to all platforms. Regards, Chasel > -Original Message- > From: Gao, Liming > Sent: Tuesday, July 30, 2019 11:46 AM > To: Chiu, Chasel ; devel@edk2.groups.io > Cc: Kubacki, Michael A ; Sinha, Ankit > ; Desimone, Nathaniel L > > Subject: RE: [PATCH 0/4] Auto configure Fsp*BaseAddress PCD > > Chasel: > This is a good enhancement. With this change, can > RebaseAndPatchFspBinBaseAddress.py and PatchFspBinFvsBaseAddress.py be > removed? > > Thanks > Liming > > -Original Message- > > From: Chiu, Chasel > > Sent: Monday, July 29, 2019 7:07 PM > > To: devel@edk2.groups.io > > Cc: Kubacki, Michael A ; Sinha, Ankit > > ; Desimone, Nathaniel L > > ; Gao, Liming > > Subject: [PATCH 0/4] Auto configure Fsp*BaseAddress PCD > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863 > > > > PcdFsp*BaseAddress now will be updated in FDF basing on flash map. > > DSC will only define types of those PCDs and always having 0 as > > default. > > New script added to only rebase FSP binary without patching DSC file. > > > > Test: interanl platform booted with this patch. > > > > Cc: Michael Kubacki > > Cc: Ankit Sinha > > Cc: Nate DeSimone > > Cc: Liming Gao > > Signed-off-by: Chasel Chiu > > > > Chasel Chiu (4): > > MinPlatformPkg: Auto configure Fsp*BaseAddress PCD > > Platform/Intel: Auto configure Fsp*BaseAddress PCD > > KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD > > ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD > > > > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf > | 3 +++ > > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc > | 12 +--- > > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf > | 3 +++ > > > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > | 12 +--- > > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | > 96 > > > > > > Platform/Intel/build_bios.py | 7 > > ++- > > 6 files changed, 122 insertions(+), 11 deletions(-) create mode > > 100644 > > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py > > > > -- > > 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44587): https://edk2.groups.io/g/devel/message/44587 Mute This Topic: https://groups.io/mt/32640908/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-non-osi/devel-MinPlatform][PATCH] Added cpuid 806EA microcode binary
Reviewed-by: Chasel Chiu
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Agyeman, Prince
> Sent: Tuesday, July 30, 2019 2:05 AM
> To: devel@edk2.groups.io
> Cc: Sinha, Ankit ; Desimone, Nathaniel L
> ; Kubacki, Michael A
> ; Kinney, Michael D
> ; Yao, Jiewen
> Subject: [edk2-devel] [edk2-non-osi/devel-MinPlatform][PATCH] Added cpuid
> 806EA microcode binary
>
> Cc: Ankit Sinha
> Cc: Nate DeSimone
> Cc: Michael Kubacki
> Cc: Michael D Kinney
> Cc: Jiewen Yao
>
> Signed-off-by: Agyeman
> ---
> .../Microcode/MicrocodeUpdates.inf | 1 +
> .../Microcode/mC0806EA_00B4.mcb | Bin 0 -> 99328 bytes
> 2 files changed, 1 insertion(+)
> create mode 100644
> Silicon/Intel/KabylakeSiliconBinPkg/Microcode/mC0806EA_00B4.mcb
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
> b/Silicon/Intel/KabylakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
> index 5673420..a062261 100644
> --- a/Silicon/Intel/KabylakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
> +++ b/Silicon/Intel/KabylakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
> @@ -24,4 +24,5 @@
>mC0406E3_00A0.mcb
>m80406E8_0026.mcb
>mC0806E9_0030.mcb
> + mC0806EA_00B4.mcb
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconBinPkg/Microcode/mC0806EA_00B4.mcb
> b/Silicon/Intel/KabylakeSiliconBinPkg/Microcode/mC0806EA_00B4.mcb
> new file mode 100644
> index
> ..20ff87c8c85df151f29a0246f
> 24441d21c466d7f
> GIT binary patch
> literal 99328
> zcmaHSQ>-vdtnIdK+qP}nwr$(C?fq@rwr$(C^Dt?XX4(P*00
> 1=q
> z2TTG$kV`NKfQf{=alrq0|9_Yd{!a_}U-o}X;eQkm0O|6K z_}_c}f71WoCglI)0PnBhG9dEzFx$Co-$L7t$Co|+k)uQTeulFMHaAQPetALC0%D5
> 3
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> f2hQ
> zjR{jlWo9cY{=b)Ylu1G)|9WV_m)q*;8R*|QJ ud
> z`0rb$^SJOBx%fur!teMf2N5D;q+{s!RXsrDW6K;@i!k7q0yLS(J;n;%`K
> z-{5>sYKKO~8%GGeh=^I%4PFzMNw78I>;UA3y?lfioUo)DyL|`K&3{
> bB
> zkVl^M9tI|GnaoroJVrJ3R-1NVM8bY#j6n)@^gA2E7WCmczxxOCW5oa7%~NDX
> 4~v|*
> zKsfL)DZZMO!?s2Jk@tz1nn|u6?F*(&`l3UwqruxL#ISpTdwymc5iIv3?J=25t0PLH
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> z{I~TF`sjN_l1<~8fOGAdyag~$m(qD%xn%|)QYtLMk(ma|nBuKotl=BoI$P9uZY%G
> T
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> z+Z--!K=1sw31cxe2z-MzM5N)-%`V?0@^?j3y~WwPq8FrXxn(HClK7Nlv?
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Re: [edk2-devel] [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
Thanks for the good catch! I have corrected BZ and will update subject from next patch. Thanks! Chasel > -Original Message- > From: Laszlo Ersek [mailto:ler...@redhat.com] > Sent: Monday, July 29, 2019 9:47 PM > To: devel@edk2.groups.io; Chiu, Chasel > Cc: Kubacki, Michael A ; Sinha, Ankit > ; Desimone, Nathaniel L > ; Gao, Liming > Subject: Re: [edk2-devel] [PATCH 0/4] Auto configure Fsp*BaseAddress PCD > > On 07/29/19 13:07, Chiu, Chasel wrote: > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863 > > > > PcdFsp*BaseAddress now will be updated in FDF basing on flash map. > > DSC will only define types of those PCDs and always having 0 as > > default. > > New script added to only rebase FSP binary without patching DSC file. > > > > Test: interanl platform booted with this patch. > > > > Cc: Michael Kubacki > > Cc: Ankit Sinha > > Cc: Nate DeSimone > > Cc: Liming Gao > > Signed-off-by: Chasel Chiu > > > > Chasel Chiu (4): > > MinPlatformPkg: Auto configure Fsp*BaseAddress PCD > > Platform/Intel: Auto configure Fsp*BaseAddress PCD > > KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD > > ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD > > > > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf > | 3 +++ > > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc > | 12 +--- > > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf > | 3 +++ > > > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > | 12 +--- > > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | > 96 > > > > Platform/Intel/build_bios.py | 7 > > ++- > > 6 files changed, 122 insertions(+), 11 deletions(-) create mode > > 100644 > > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py > > > > I think the classification on TianoCore BZ#1863 is wrong. It should be > "EDK2 Platforms", probably. Please update the BZ. > > > Accordingly, the subject prefix on this patch series should not be "PATCH", > but > "edk2-platforms PATCH". No need to resend the v1 patch series just for this, > but > if you send a v2, please set the correct subject prefix: > > git format-patch -v2 --subject-prefix='edk2-platforms PATCH' ... > > Thanks > Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44575): https://edk2.groups.io/g/devel/message/44575 Mute This Topic: https://groups.io/mt/32640908/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms] [PATCH] Platform/Intel/KabylakeOpenBoardPkg: Fix build.
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Nate DeSimone > Sent: Friday, August 9, 2019 8:47 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael A > > Subject: [edk2-devel] [edk2-platforms] [PATCH] > Platform/Intel/KabylakeOpenBoardPkg: Fix build. > > The build for KabylakeOpenBoardPkg is presently broken due to > WORKSPACE_PLATFORM_BIN being defined to a marco of the same name in > KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg > > Setting this macro to an empty string resolves the issue. > > Cc: Chasel Chiu > Cc: Michael Kubacki > Signed-off-by: Nate DeSimone > --- > .../Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg| 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg > index bf89ea399c..ab1a9a61c2 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg > @@ -7,7 +7,7 @@ > > > [CONFIG] > -WORKSPACE_PLATFORM_BIN = WORKSPACE_PLATFORM_BIN > +WORKSPACE_PLATFORM_BIN = > EDK_SETUP_OPTION = > openssl_path = > PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg > -- > 2.17.1.windows.2 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45342): https://edk2.groups.io/g/devel/message/45342 Mute This Topic: https://groups.io/mt/32805602/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 3/3] IntelFsp2Pkg/FspSecCore: Add missing header file in INF file
Reviewed-by: Chasel Chiu > -Original Message- > From: Zhang, Shenglei > Sent: Monday, August 12, 2019 2:23 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Subject: [PATCH v2 3/3] IntelFsp2Pkg/FspSecCore: Add missing header file in > INF file > > SecFsp.h is used but missing inf file, which will cause generating warning > message. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Shenglei Zhang > Reviewed-by: Chasel Chiu > Reviewed-by: Star Zeng > Reviewed-by: Nate DeSimone > --- > IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf > index 3de09b5b4921..17924b118c83 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf > @@ -1,7 +1,7 @@ > ## @file > # Sec Core for FSP > # > -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved. > +# Copyright (c) 2016 - 2019, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,7 @@ > [Defines] > > [Sources] >SecFspApiChk.c > + SecFsp.h > > [Sources.IA32] >Ia32/Stack.nasm > -- > 2.18.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45402): https://edk2.groups.io/g/devel/message/45402 Mute This Topic: https://groups.io/mt/32838106/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
