[PATCH v1 1/1] rtems-tools: Update rtems-llvm to version 11.1.0
---
rtems/config/6/rtems-llvm.bset | 2 +-
rtems/config/tools/rtems-llvm-11.1.0.cfg | 21 +
source-builder/config/llvm-common-1.cfg | 6 +++---
3 files changed, 25 insertions(+), 4 deletions(-)
create mode 100644 rtems/config/tools/rtems-llvm-11.1.0.cfg
diff --git a/rtems/config/6/rtems-llvm.bset b/rtems/config/6/rtems-llvm.bset
index 2b461a0..b1f5e5a 100644
--- a/rtems/config/6/rtems-llvm.bset
+++ b/rtems/config/6/rtems-llvm.bset
@@ -18,4 +18,4 @@
%define swig_prefix %{_tmproot}/swig
devel/swig
-tools/rtems-llvm-8.0.1
+tools/rtems-llvm-11.1.0
diff --git a/rtems/config/tools/rtems-llvm-11.1.0.cfg
b/rtems/config/tools/rtems-llvm-11.1.0.cfg
new file mode 100644
index 000..3e99ad6
--- /dev/null
+++ b/rtems/config/tools/rtems-llvm-11.1.0.cfg
@@ -0,0 +1,21 @@
+#
+# LLVM
+#
+
+%define llvm_version 11.1.0
+
+%hash sha512 llvm-%{llvm_version}.src.tar.xz
B7+ZczhBUaGNXMKJIQPl8oqIxjLo5JZi/eVtEjYy8u0bNxD6eoe2uCGVXQ7EQWD/NvKqTyM+OJ4U1ijpv43HZA==
+%hash sha512 clang-%{llvm_version}.src.tar.xz
9Lt+Te1h8sSJ4BMQQy2OBi66mS2ZLtZcouaafCDrXQyQ6BlouqpxwBrJ2W+BSi3MpO+Pi/rEzvbXkH7Ozgl9rA==
+%hash sha512 clang-tools-extra-%{llvm_version}.src.tar.xz
tim4uMCjOQu2zSzmCSQqb5f+6pUJFFoutVZtCTWc7lb8UQ8h9fjRUI/11hLsuRdlcuY1jAHNhZD8eZiYw0hztg==
+%hash sha512 compiler-rt-%{llvm_version}.src.tar.xz
mwslnMQ9Xk0gIAZ2vhU96BtIWz/fBlYj/3HH4YlOxcjtnZnBQW9wJGqw9BfLum0dSvnzdp4uZXdABoGnkTRiMQ==
+%hash sha512 libcxx-%{llvm_version}.src.tar.xz
r1Mz2luQ9KRqUYRTIWT0xlIuPAOlgBMWJ8DxZ6uY+z5xs+FVGNbiJBQUFITsWrDRhClK5/EANOv+0o5wcoNrKA==
+%hash sha512 libcxxabi-%{llvm_version}.src.tar.xz
C/OAb9k4LKZ5DKKo6ZFCTK9k6BQVOGh1JDVlA0JD8qx0QsWW48VezoCTLC7Fm3GAHj5BXe3J203Uw/Zraok1WA==
+%hash sha512 libunwind-%{llvm_version}.src.tar.xz
UH8pzxoxjZdh/mMGsum1fAKjQvE4tH7FQg3OUnEyoz96/804aRN5LEcs7rn7HBsQW7oyNKFXWq4PaAJOlMjVlg==
+%hash sha512 lld-%{llvm_version}.src.tar.xz
PiSZFOpzsq+2V13IwY4zn+B2Z4Su3bh827ynP/xHJQlyXjMLnBsn1pCfuRw3VetfKfndHMl/9qWfF/kTMX1YTw==
+%hash sha512 lldb-%{llvm_version}.src.tar.xz
E+oVb0XdlyATyGJDN3CKhHhpMkmCsquIFapdTCUvp17klC5WVZoYTffxxg2PdU4Zi0Vt5+Wc6A3lhY6VEvt3XQ==
+%hash sha512 openmp-%{llvm_version}.src.tar.xz
u+oQP0T0NvK7x9Vr538pI1wVr1eOi2rwLE8WLjRn42wSLaIa2kKPsY0JygPTk6jfmf/QIAhCbcxoDiA7oQPXug==
+
+#
+# The llvm build instructions.
+#
+%include %{_configdir}/llvm-common-1.cfg
diff --git a/source-builder/config/llvm-common-1.cfg
b/source-builder/config/llvm-common-1.cfg
index 629d2bf..37c4341 100644
--- a/source-builder/config/llvm-common-1.cfg
+++ b/source-builder/config/llvm-common-1.cfg
@@ -33,7 +33,7 @@ URL: http://llvm.org/
#
# Packages
#
-%source set cfe%{llvm_url}/cfe-%{llvm_version}.src.tar.xz
+%source set clang%{llvm_url}/clang-%{llvm_version}.src.tar.xz
%source set clang-tools-extra
%{llvm_url}/clang-tools-extra-%{llvm_version}.src.tar.xz
%source set compiler-rt
%{llvm_url}/compiler-rt-%{llvm_version}.src.tar.xz
%source set libcxx %{llvm_url}/libcxx-%{llvm_version}.src.tar.xz
@@ -89,8 +89,8 @@ URL: http://llvm.org/
%source setup llvm -q -E
%{__mv} llvm-%{llvm_version}.src ${source_dir_llvm}
- %source setup cfe -q -E
- %{__mv} cfe-%{llvm_version}.src ${source_dir_llvm}/tools/clang
+ %source setup clang -q -E
+ %{__mv} clang-%{llvm_version}.src ${source_dir_llvm}/tools/clang
%source setup clang-tools-extra -q -E
%{__mv} clang-tools-extra-%{llvm_version}.src
${source_dir_llvm}/tools/clang/extra
--
2.25.1
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/1] Update rtems-llvm to version 11.1.0
Hello, I couldn't get the rtems-llvm buildset to work. As it was building llvm8 which is not that modern, I just tried to build a more recent version with the scripts. It works with llvm11. Are there any objections to updating? And should we keep the rtems-llvm-8.cfg or should I remove this with this patch? Have a nice weekend, Jan Jan Sommer (1): rtems-tools: Update rtems-llvm to version 11.1.0 rtems/config/6/rtems-llvm.bset | 2 +- rtems/config/tools/rtems-llvm-11.1.0.cfg | 21 + source-builder/config/llvm-common-1.cfg | 6 +++--- 3 files changed, 25 insertions(+), 4 deletions(-) create mode 100644 rtems/config/tools/rtems-llvm-11.1.0.cfg -- 2.25.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/1] gpiolib/grgpio: Add support for newer grgpio features
- Use proper typedef for isr (avoid warning in user application)
- Use set input enable register together with pin direction
- Support irqgen == 1 mode if present in capabilities register
---
bsps/include/grlib/gpiolib.h | 7 +--
bsps/include/grlib/grlib.h| 4 +++-
bsps/shared/grlib/drvmgr/ambapp_bus.c | 5 +
bsps/shared/grlib/gpio/gpiolib.c | 2 +-
bsps/shared/grlib/gpio/grgpio.c | 22 --
5 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/bsps/include/grlib/gpiolib.h b/bsps/include/grlib/gpiolib.h
index f82d4fa2c2..37ac140862 100644
--- a/bsps/include/grlib/gpiolib.h
+++ b/bsps/include/grlib/gpiolib.h
@@ -28,6 +28,9 @@ struct gpiolib_config {
#define GPIOLIB_IRQ_POL_LOW 0
#define GPIOLIB_IRQ_POL_HIGH 1
+/* Interrupt Service Routine (ISR) */
+typedef void (*gpiolib_isr)(void *arg);
+
/* Libarary initialize function must be called befor any other */
extern int gpiolib_initialize(void);
@@ -54,7 +57,7 @@ extern int gpiolib_irq_disable(void *handle);
extern int gpiolib_irq_mask(void *handle);
extern int gpiolib_irq_unmask(void *handle);
extern int gpiolib_irq_force(void *handle);
-extern int gpiolib_irq_register(void *handle, void *func, void *arg);
+extern int gpiolib_irq_register(void *handle, gpiolib_isr func, void *arg);
/*** Driver Interface ***/
@@ -66,7 +69,7 @@ struct gpiolib_drv_ops {
int (*config)(void *handle, struct gpiolib_config *cfg);
int (*get)(void *handle, int *val);
int (*irq_opts)(void *handle, unsigned int options);
- int (*irq_register)(void *handle, void *func, void *arg);
+ int (*irq_register)(void *handle, gpiolib_isr func, void
*arg);
int (*open)(void *handle);
int (*set)(void *handle, int dir, int outval);
int (*show)(void *handle);
diff --git a/bsps/include/grlib/grlib.h b/bsps/include/grlib/grlib.h
index 49d807..4aa3e9df4a 100644
--- a/bsps/include/grlib/grlib.h
+++ b/bsps/include/grlib/grlib.h
@@ -17,6 +17,7 @@
#define __GRLIB_H__
#include
+#include
#ifdef __cplusplus
extern "C" {
@@ -125,6 +126,7 @@ struct grgpio_regs {
volatile unsigned int iedge; /* 0x14 Interrupt edge register */
volatile unsigned int bypass; /* 0x18 Bypass register */
volatile unsigned int cap; /* 0x1C Capability register */
+#define GRGPIO_CAP_IRQGEN(reg) BSP_FLD32GET(reg, 8, 12)
volatile unsigned int irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */
volatile unsigned int res_30; /* 0x30 Reserved */
volatile unsigned int res_34; /* 0x34 Reserved */
@@ -132,7 +134,7 @@ struct grgpio_regs {
volatile unsigned int res_3C; /* 0x3C Reserved */
volatile unsigned int iavail; /* 0x40 Interrupt available register */
volatile unsigned int iflag; /* 0x44 Interrupt flag register */
- volatile unsigned int res_48; /* 0x48 Reserved */
+ volatile unsigned int input_en;/* 0x48 Input enable (if present) */
volatile unsigned int pulse; /* 0x4C Pulse register */
volatile unsigned int res_50; /* 0x50 Reserved */
volatile unsigned int output_or; /* 0x54 I/O port output register,
logical-OR */
diff --git a/bsps/shared/grlib/drvmgr/ambapp_bus.c
b/bsps/shared/grlib/drvmgr/ambapp_bus.c
index 3c38fc16e0..0aed29224c 100644
--- a/bsps/shared/grlib/drvmgr/ambapp_bus.c
+++ b/bsps/shared/grlib/drvmgr/ambapp_bus.c
@@ -521,11 +521,8 @@ static int ambapp_dev_fixup(struct drvmgr_dev *dev, struct
amba_dev_info *pnp)
for(core = 0; core < subcores; core++)
drvmgr_dev_register(devs_to_register[core]);
return 1;
- } else if ( (pnp->info.device == GAISLER_GPIO) &&
- (pnp->info.vendor == VENDOR_GAISLER) ) {
- /* PIO[N] is connected to IRQ[N]. */
- pnp->info.irq = 0;
}
+
return 0;
}
diff --git a/bsps/shared/grlib/gpio/gpiolib.c b/bsps/shared/grlib/gpio/gpiolib.c
index cf0038c5bb..0cb76402cc 100644
--- a/bsps/shared/grlib/gpio/gpiolib.c
+++ b/bsps/shared/grlib/gpio/gpiolib.c
@@ -201,7 +201,7 @@ int gpiolib_get(void *handle, int *inval)
}
/*** IRQ Functions ***/
-int gpiolib_irq_register(void *handle, void *func, void *arg)
+int gpiolib_irq_register(void *handle, gpiolib_isr func, void *arg)
{
struct gpiolib_port *port = handle;
diff --git a/bsps/shared/grlib/gpio/grgpio.c b/bsps/shared/grlib/gpio/grgpio.c
index 05504ef020..5bce5f530a 100644
--- a/bsps/shared/grlib/gpio/grgpio.c
+++ b/bsps/shared/grlib/gpio/grgpio.c
@@ -229,6 +229,7 @@ static int grgpio_grpiolib_irq_opts(void *handle, unsigned
int options)
{
struct grgpio_priv *priv;
int portnr;
+ int irq;
drvmgr_isr isr;
void *arg;
@@ -244,33 +245,41 @@ static int grgpio_grpiolib_irq_opts(void *handle,
unsigned int options)
isr =
[PATCH v1 0/1] Add support for newer grgpio features
Hello, I noticed the lack of some features of modern grgpio ip cores in gpiolib. I would also like to backport this to rtems5. The corresponding ticket is here: https://devel.rtems.org/ticket/4464 v2: Fixed tabs/spaces issues. Jan Sommer (1): gpiolib/grgpio: Add support for newer grgpio features bsps/include/grlib/gpiolib.h | 7 +-- bsps/include/grlib/grlib.h| 4 +++- bsps/shared/grlib/drvmgr/ambapp_bus.c | 5 + bsps/shared/grlib/gpio/gpiolib.c | 2 +- bsps/shared/grlib/gpio/grgpio.c | 22 -- 5 files changed, 26 insertions(+), 14 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1] gpiolib/grgpio: Add support for newer grgpio features
- Use proper typedef for isr (avoid warning in user application)
- Use set input enable register together with pin direction
- Support irqgen == 1 mode if present in capabilities register
---
bsps/include/grlib/gpiolib.h | 7 +--
bsps/include/grlib/grlib.h| 4 +++-
bsps/shared/grlib/drvmgr/ambapp_bus.c | 5 +
bsps/shared/grlib/gpio/gpiolib.c | 2 +-
bsps/shared/grlib/gpio/grgpio.c | 22 --
5 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/bsps/include/grlib/gpiolib.h b/bsps/include/grlib/gpiolib.h
index f82d4fa2c2..37ac140862 100644
--- a/bsps/include/grlib/gpiolib.h
+++ b/bsps/include/grlib/gpiolib.h
@@ -28,6 +28,9 @@ struct gpiolib_config {
#define GPIOLIB_IRQ_POL_LOW 0
#define GPIOLIB_IRQ_POL_HIGH 1
+/* Interrupt Service Routine (ISR) */
+typedef void (*gpiolib_isr)(void *arg);
+
/* Libarary initialize function must be called befor any other */
extern int gpiolib_initialize(void);
@@ -54,7 +57,7 @@ extern int gpiolib_irq_disable(void *handle);
extern int gpiolib_irq_mask(void *handle);
extern int gpiolib_irq_unmask(void *handle);
extern int gpiolib_irq_force(void *handle);
-extern int gpiolib_irq_register(void *handle, void *func, void *arg);
+extern int gpiolib_irq_register(void *handle, gpiolib_isr func, void *arg);
/*** Driver Interface ***/
@@ -66,7 +69,7 @@ struct gpiolib_drv_ops {
int (*config)(void *handle, struct gpiolib_config *cfg);
int (*get)(void *handle, int *val);
int (*irq_opts)(void *handle, unsigned int options);
- int (*irq_register)(void *handle, void *func, void *arg);
+ int (*irq_register)(void *handle, gpiolib_isr func, void
*arg);
int (*open)(void *handle);
int (*set)(void *handle, int dir, int outval);
int (*show)(void *handle);
diff --git a/bsps/include/grlib/grlib.h b/bsps/include/grlib/grlib.h
index 49d807..4aa3e9df4a 100644
--- a/bsps/include/grlib/grlib.h
+++ b/bsps/include/grlib/grlib.h
@@ -17,6 +17,7 @@
#define __GRLIB_H__
#include
+#include
#ifdef __cplusplus
extern "C" {
@@ -125,6 +126,7 @@ struct grgpio_regs {
volatile unsigned int iedge; /* 0x14 Interrupt edge register */
volatile unsigned int bypass; /* 0x18 Bypass register */
volatile unsigned int cap; /* 0x1C Capability register */
+#define GRGPIO_CAP_IRQGEN(reg) BSP_FLD32GET(reg, 8, 12)
volatile unsigned int irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */
volatile unsigned int res_30; /* 0x30 Reserved */
volatile unsigned int res_34; /* 0x34 Reserved */
@@ -132,7 +134,7 @@ struct grgpio_regs {
volatile unsigned int res_3C; /* 0x3C Reserved */
volatile unsigned int iavail; /* 0x40 Interrupt available register */
volatile unsigned int iflag; /* 0x44 Interrupt flag register */
- volatile unsigned int res_48; /* 0x48 Reserved */
+ volatile unsigned int input_en;/* 0x48 Input enable (if present) */
volatile unsigned int pulse; /* 0x4C Pulse register */
volatile unsigned int res_50; /* 0x50 Reserved */
volatile unsigned int output_or; /* 0x54 I/O port output register,
logical-OR */
diff --git a/bsps/shared/grlib/drvmgr/ambapp_bus.c
b/bsps/shared/grlib/drvmgr/ambapp_bus.c
index 3c38fc16e0..0aed29224c 100644
--- a/bsps/shared/grlib/drvmgr/ambapp_bus.c
+++ b/bsps/shared/grlib/drvmgr/ambapp_bus.c
@@ -521,11 +521,8 @@ static int ambapp_dev_fixup(struct drvmgr_dev *dev, struct
amba_dev_info *pnp)
for(core = 0; core < subcores; core++)
drvmgr_dev_register(devs_to_register[core]);
return 1;
- } else if ( (pnp->info.device == GAISLER_GPIO) &&
- (pnp->info.vendor == VENDOR_GAISLER) ) {
- /* PIO[N] is connected to IRQ[N]. */
- pnp->info.irq = 0;
}
+
return 0;
}
diff --git a/bsps/shared/grlib/gpio/gpiolib.c b/bsps/shared/grlib/gpio/gpiolib.c
index cf0038c5bb..0cb76402cc 100644
--- a/bsps/shared/grlib/gpio/gpiolib.c
+++ b/bsps/shared/grlib/gpio/gpiolib.c
@@ -201,7 +201,7 @@ int gpiolib_get(void *handle, int *inval)
}
/*** IRQ Functions ***/
-int gpiolib_irq_register(void *handle, void *func, void *arg)
+int gpiolib_irq_register(void *handle, gpiolib_isr func, void *arg)
{
struct gpiolib_port *port = handle;
diff --git a/bsps/shared/grlib/gpio/grgpio.c b/bsps/shared/grlib/gpio/grgpio.c
index 05504ef020..65b75c96cb 100644
--- a/bsps/shared/grlib/gpio/grgpio.c
+++ b/bsps/shared/grlib/gpio/grgpio.c
@@ -229,6 +229,7 @@ static int grgpio_grpiolib_irq_opts(void *handle, unsigned
int options)
{
struct grgpio_priv *priv;
int portnr;
+int irq;
drvmgr_isr isr;
void *arg;
@@ -244,33 +245,41 @@ static int grgpio_grpiolib_irq_opts(void *handle,
unsigned int options)
isr =
[PATCH v2 1/1] bsps/i386: Update calibration of TSC to be more accurate
Closes #4455
---
bsps/i386/pc386/clock/ckinit.c | 71 ++
1 file changed, 38 insertions(+), 33 deletions(-)
diff --git a/bsps/i386/pc386/clock/ckinit.c b/bsps/i386/pc386/clock/ckinit.c
index 09afe73cde..2df1818dd3 100644
--- a/bsps/i386/pc386/clock/ckinit.c
+++ b/bsps/i386/pc386/clock/ckinit.c
@@ -104,48 +104,60 @@ static uint32_t pc386_get_timecount_i8254(struct
timecounter *tc)
/*
* Calibrate CPU cycles per tick. Interrupts should be disabled.
+ * Will also set the PIT, so call this before registering the
+ * periodic timer for rtems tick generation
*/
static void calibrate_tsc(void)
{
uint64_t begin_time;
- uint8_t then_lsb, then_msb, now_lsb, now_msb;
- uint32_t i;
-
- /*
- * We just reset the timer, so we know we're at the beginning of a tick.
- */
-
- /*
- * Count cycles. Watching the timer introduces a several microsecond
- * uncertaintity, so let it cook for a while and divide by the number of
- * ticks actually executed.
- */
+ uint8_t lsb, msb;
+ uint32_t max_timer_value;
+ uint32_t last_tick, cur_tick;
+ int32_t diff, remaining;
+
+ /* Set the timer to free running mode */
+ outport_byte(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_INTTC);
+ /* Reset the 16 timer reload value, first LSB, then MSB */
+ outport_byte(TIMER_CNTR0, 0);
+ outport_byte(TIMER_CNTR0, 0);
+ /* We use the full 16 bit */
+ max_timer_value = 0x;
+ /* Calibrate for 1s, i.e. TIMER_TICK PIT ticks */
+ remaining = TIMER_TICK;
begin_time = rdtsc();
-
- for (i = rtems_clock_get_ticks_per_second() * pc386_isrs_per_tick;
- i != 0; --i ) {
-/* We know we've just completed a tick when timer goes from low to high */
-then_lsb = then_msb = 0xff;
-do {
- READ_8254(now_lsb, now_msb);
- if ((then_msb < now_msb) ||
- ((then_msb == now_msb) && (then_lsb < now_lsb)))
-break;
- then_lsb = now_lsb;
- then_msb = now_msb;
-} while (1);
+ READ_8254(lsb, msb);
+ last_tick = (msb << 8) | lsb;
+ while(remaining > 0) {
+READ_8254(lsb, msb);
+cur_tick = (msb << 8) | lsb;
+/* PIT counts down, so subtract cur from last */
+diff = last_tick - cur_tick;
+last_tick = cur_tick;
+if (diff < 0) {
+diff += max_timer_value;
+}
+remaining -= diff;
}
pc586_tsc_frequency = rdtsc() - begin_time;
#if 0
- printk( "CPU clock at %u MHz\n", (uint32_t)(pc586_tsc_frequency / 100));
+ printk( "CPU clock at %u Hz\n", (uint32_t)(pc586_tsc_frequency ));
#endif
}
static void clockOn(void)
{
+
+ /*
+ * First calibrate the TSC. Do this every time we
+ * turn the clock on in case the CPU clock speed has changed.
+ */
+ if ( x86_has_tsc() ) {
+calibrate_tsc();
+ }
+
rtems_interrupt_lock_context lock_context;
pc386_isrs_per_tick= 1;
pc386_microseconds_per_isr = rtems_configuration_get_microseconds_per_tick();
@@ -171,13 +183,6 @@ static void clockOn(void)
rtems_interrupt_lock_release(_i386_i8254_access_lock, _context);
bsp_interrupt_vector_enable( BSP_PERIODIC_TIMER );
-
- /*
- * Now calibrate cycles per tick. Do this every time we
- * turn the clock on in case the CPU clock speed has changed.
- */
- if ( x86_has_tsc() )
-calibrate_tsc();
}
bool Clock_isr_enabled = false;
--
2.17.1
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 0/1] bsps/i386: Update calibration of TSC to be more accurate
Updated the patch with the suggestions by Gedare. Tests on real hardware yield the same frequency results as returned by FreeBSD on the same hardware. Also, subsequent calibrations only differ by <1 kHz. I would like to backport this fix to RTEMS5. The corresponding ticket is here: https://devel.rtems.org/ticket/4456 Best regards, Jan Jan Sommer (1): bsps/i386: Update calibration of TSC to be more accurate bsps/i386/pc386/clock/ckinit.c | 71 ++ 1 file changed, 38 insertions(+), 33 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1] bsps/i386: Update calibration of TSC to be more accurate
Closes #4455
---
bsps/i386/pc386/clock/ckinit.c | 72 ++
1 file changed, 39 insertions(+), 33 deletions(-)
diff --git a/bsps/i386/pc386/clock/ckinit.c b/bsps/i386/pc386/clock/ckinit.c
index 09afe73cde..cbd2360fde 100644
--- a/bsps/i386/pc386/clock/ckinit.c
+++ b/bsps/i386/pc386/clock/ckinit.c
@@ -104,48 +104,61 @@ static uint32_t pc386_get_timecount_i8254(struct
timecounter *tc)
/*
* Calibrate CPU cycles per tick. Interrupts should be disabled.
+ * Will also set the PIT, so call this before registering the
+ * periodic timer for rtems tick generation
*/
static void calibrate_tsc(void)
{
uint64_t begin_time;
- uint8_t then_lsb, then_msb, now_lsb, now_msb;
- uint32_t i;
-
- /*
- * We just reset the timer, so we know we're at the beginning of a tick.
- */
-
- /*
- * Count cycles. Watching the timer introduces a several microsecond
- * uncertaintity, so let it cook for a while and divide by the number of
- * ticks actually executed.
- */
+ uint8_t lsb, msb;
+ uint32_t max_timer_value;
+ uint32_t last_tick, cur_tick;
+ int32_t diff, remaining;
+
+ /* Set the timer to free running mode */
+ outport_byte(TIMER_MODE, TIMER_SEL0|TIMER_16BIT|TIMER_INTTC);
+ outport_byte(TIMER_CNTR0, 0);
+ outport_byte(TIMER_CNTR0, 0);
+ /* 16 bit counter */
+ max_timer_value = 0x;
+ /* Calibrate for 1s */
+ remaining = TIMER_TICK;
begin_time = rdtsc();
-
- for (i = rtems_clock_get_ticks_per_second() * pc386_isrs_per_tick;
- i != 0; --i ) {
-/* We know we've just completed a tick when timer goes from low to high */
-then_lsb = then_msb = 0xff;
-do {
- READ_8254(now_lsb, now_msb);
- if ((then_msb < now_msb) ||
- ((then_msb == now_msb) && (then_lsb < now_lsb)))
-break;
- then_lsb = now_lsb;
- then_msb = now_msb;
-} while (1);
+ READ_8254(lsb,msb);
+ last_tick = (msb << 8) | lsb;
+ while(remaining > 0) {
+READ_8254(lsb,msb);
+cur_tick = (msb << 8) | lsb;
+/* PIT counts down, so subtract cur from last */
+diff = last_tick - cur_tick;
+last_tick = cur_tick;
+if (diff < 0) {
+diff += max_timer_value;
+}
+remaining -= diff;
}
pc586_tsc_frequency = rdtsc() - begin_time;
#if 0
- printk( "CPU clock at %u MHz\n", (uint32_t)(pc586_tsc_frequency / 100));
+ printk( "CPU clock at %u Hz\n", (uint32_t)(pc586_tsc_frequency ));
#endif
}
static void clockOn(void)
{
+
+ /*
+ * First calibrate the TSC. Do this every time we
+ * turn the clock on in case the CPU clock speed has changed.
+ */
+ for (int i = 0; i<5; ++i)
+ {
+ if ( x86_has_tsc() )
+calibrate_tsc();
+ }
+
rtems_interrupt_lock_context lock_context;
pc386_isrs_per_tick= 1;
pc386_microseconds_per_isr = rtems_configuration_get_microseconds_per_tick();
@@ -171,13 +184,6 @@ static void clockOn(void)
rtems_interrupt_lock_release(_i386_i8254_access_lock, _context);
bsp_interrupt_vector_enable( BSP_PERIODIC_TIMER );
-
- /*
- * Now calibrate cycles per tick. Do this every time we
- * turn the clock on in case the CPU clock speed has changed.
- */
- if ( x86_has_tsc() )
-calibrate_tsc();
}
bool Clock_isr_enabled = false;
--
2.17.1
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[PATCH v1] bsps/riscv: Give enough time for clock driver initialization
- Clock driver initialization for secondary cores had to take less than one tick - If tick time is small (i.e. <= 1ms) setting up all cores could take too long and a fatal error is thrown. - Give at least 10 ms time for clock initialization to avoid this error --- bsps/riscv/riscv/clock/clockdrv.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c index 3afe86576f..102137aeab 100644 --- a/bsps/riscv/riscv/clock/clockdrv.c +++ b/bsps/riscv/riscv/clock/clockdrv.c @@ -211,7 +211,13 @@ static void riscv_clock_initialize(void) tc->interval = interval; cmpval = riscv_clock_read_mtime(>mtime); - cmpval += interval; + /* + * For very short intervals the time of 1 tick is not enough to + * set up the timer on all cores in SMP systems. + * Give the CPU at least 10 ms. + */ + interval = (1 / us_per_tick) * interval; + cmpval += interval; riscv_clock_clint_init(clint, cmpval, 0); riscv_clock_secondary_initialization(clint, cmpval, interval); -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 2/2] i386: Remove unneeded include header files
--- .../sys/i386/include/machine/intr_machdep.h |6 - rtemsbsd/include/x86/bus.h| 1109 rtemsbsd/include/x86/specialreg.h | 1143 - 3 files changed, 2258 deletions(-) delete mode 100644 freebsd/sys/i386/include/machine/intr_machdep.h delete mode 100644 rtemsbsd/include/x86/bus.h delete mode 100644 rtemsbsd/include/x86/specialreg.h diff --git a/freebsd/sys/i386/include/machine/intr_machdep.h b/freebsd/sys/i386/include/machine/intr_machdep.h deleted file mode 100644 index a0b28387.. --- a/freebsd/sys/i386/include/machine/intr_machdep.h +++ /dev/null @@ -1,6 +0,0 @@ -/*- - * This file is in the public domain. - */ -/* $FreeBSD$ */ - -#include diff --git a/rtemsbsd/include/x86/bus.h b/rtemsbsd/include/x86/bus.h deleted file mode 100644 index 2427ae51.. --- a/rtemsbsd/include/x86/bus.h +++ /dev/null @@ -1,1109 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause-NetBSDE - * - * Copyright (c) KATO Takenori, 1999. - * - * All rights reserved. Unpublished rights reserved under the copyright - * laws of Japan. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - *notice, this list of conditions and the following disclaimer as - *the first lines of this file unmodified. - * 2. Redistributions in binary form must reproduce the above copyright - *notice, this list of conditions and the following disclaimer in the - *documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - *derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $*/ - -/*- - * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, - * NASA Ames Research Center. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - *notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - *notice, this list of conditions and the following disclaimer in the - *documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 1996 Charles M. Hannum. All rights reserved. - * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - *notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - *notice, this list of conditions and the following disclaimer in the - *documentation and/or other materials provided with the distribution. - * 3. All advertising
[PATCH v2 1/2] waf_libbsd.py: Apply path-mappings to header-paths
---
libbsd.py | 2 +-
waf_libbsd.py | 27 +--
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/libbsd.py b/libbsd.py
index add91e5a..c9151901 100644
--- a/libbsd.py
+++ b/libbsd.py
@@ -144,6 +144,7 @@ _defaults = {
('freebsd/sys/dev/pci','**/*.h',
'dev/pci'),
('freebsd/sys/dev/nvme', '**/*.h',
'dev/nvme'),
('freebsd/sys/dev/evdev', '**/*.h',
'dev/evdev'),
+ ('freebsd/sys/@CPU@/include', '**/*.h',
''),
('linux/include', '**/*.h',
''),
('mDNSResponder/mDNSCore', 'mDNSDebug.h',
''),
('mDNSResponder/mDNSCore', 'mDNSEmbeddedAPI.h',
''),
@@ -1585,7 +1586,6 @@ class dev_nic(builder.Module):
'sys/arm64/include/cpu.h',
'sys/arm/include/cpufunc.h',
'sys/i386/include/md_var.h',
-'sys/i386/include/intr_machdep.h',
'sys/x86/include/intr_machdep.h',
'sys/i386/include/cpufunc.h',
'sys/x86/include/intr_machdep.h',
diff --git a/waf_libbsd.py b/waf_libbsd.py
index 070d3eac..0bd4fd3d 100644
--- a/waf_libbsd.py
+++ b/waf_libbsd.py
@@ -538,17 +538,24 @@ class Builder(builder.ModuleManager):
if 'header-paths' in config:
headerPaths = config['header-paths']
cpu = bld.get_env()['RTEMS_ARCH']
-if cpu == "i386":
-cpu = 'x86'
for headers in headerPaths:
-# Get the dest path
-ipath = os.path.join(arch_inc_path, headers[2])
-start_dir = bld.path.find_dir(headers[0].replace('@CPU@', cpu))
-if start_dir != None:
-bld.install_files("${PREFIX}/" + ipath,
- start_dir.ant_glob(headers[1]),
- cwd=start_dir,
- relative_trick=True)
+paths = [headers[0].replace('@CPU@', cpu)]
+# Apply the path mappings
+for source, targets in config['path-mappings']:
+if source in paths:
+i = paths.index(source)
+paths.remove(source)
+paths[i:i] = targets
+
+for hp in paths:
+# Get the dest path
+ipath = os.path.join(arch_inc_path, headers[2])
+start_dir = bld.path.find_dir(hp)
+if start_dir != None:
+bld.install_files("${PREFIX}/" + ipath,
+start_dir.ant_glob(headers[1]),
+cwd=start_dir,
+relative_trick=True)
bld.install_files(os.path.join("${PREFIX}", arch_inc_path,
module_header_path),
--
2.17.1
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[PATCH v2 0/2] [libbsd] i386: Install correct machine include headers
Second version for fixing the include header problem for i386. This time not much changes for other BSPs. For i386 no functional header are needed in the rtemsbsd directory anymore. Only headers which redirect. It essentially adds the path mapping feature also to the header-paths of libbsd.py, to fix the issues with the duality of the include paths for i386/x86. Best regards, Jan Jan Sommer (2): waf_libbsd.py: Apply path-mappings to header-paths i386: Remove unneeded include header files .../sys/i386/include/machine/intr_machdep.h |6 - libbsd.py |2 +- rtemsbsd/include/x86/bus.h| 1109 rtemsbsd/include/x86/specialreg.h | 1143 - waf_libbsd.py | 27 +- 5 files changed, 18 insertions(+), 2269 deletions(-) delete mode 100644 freebsd/sys/i386/include/machine/intr_machdep.h delete mode 100644 rtemsbsd/include/x86/bus.h delete mode 100644 rtemsbsd/include/x86/specialreg.h -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/2] rtemsbd: Remove machine dependent files and use the ones from freebsd
- Remove cpufunc.h, bus.h and _bus.h from rtemsbd. Otherwise the same
files will be installed for all target architectures which can lead to
incompatibilities
- Instead use the machine dependent header files from freebsd
---
freebsd/sys/arm/include/machine/_bus.h| 47 +
freebsd/sys/arm/include/machine/bus.h | 769
freebsd/sys/arm64/include/machine/_bus.h | 46 +
freebsd/sys/arm64/include/machine/bus.h | 469 ++
freebsd/sys/powerpc/include/machine/_bus.h| 50 +
freebsd/sys/powerpc/include/machine/bus.h | 467 ++
freebsd/sys/riscv/include/machine/_bus.h | 46 +
freebsd/sys/riscv/include/machine/bus.h | 469 ++
freebsd/sys/riscv/include/machine/cpufunc.h | 135 +++
freebsd/sys/riscv/include/machine/riscvreg.h | 246 +
.../sys/sparc}/include/machine/_bus.h | 0
.../sys/sparc}/include/machine/bus.h | 0
freebsd/sys/sparc/include/machine/cpufunc.h | 0
freebsd/sys/sparc64/include/machine/_bus.h| 41 +
freebsd/sys/sparc64/include/machine/bus.h | 852 ++
rtemsbsd/include/machine/cpufunc.h| 1 -
16 files changed, 3637 insertions(+), 1 deletion(-)
create mode 100644 freebsd/sys/arm/include/machine/_bus.h
create mode 100644 freebsd/sys/arm/include/machine/bus.h
create mode 100644 freebsd/sys/arm64/include/machine/_bus.h
create mode 100644 freebsd/sys/arm64/include/machine/bus.h
create mode 100644 freebsd/sys/powerpc/include/machine/_bus.h
create mode 100644 freebsd/sys/powerpc/include/machine/bus.h
create mode 100644 freebsd/sys/riscv/include/machine/_bus.h
create mode 100644 freebsd/sys/riscv/include/machine/bus.h
create mode 100644 freebsd/sys/riscv/include/machine/cpufunc.h
create mode 100644 freebsd/sys/riscv/include/machine/riscvreg.h
rename {rtemsbsd => freebsd/sys/sparc}/include/machine/_bus.h (100%)
rename {rtemsbsd => freebsd/sys/sparc}/include/machine/bus.h (100%)
create mode 100644 freebsd/sys/sparc/include/machine/cpufunc.h
create mode 100644 freebsd/sys/sparc64/include/machine/_bus.h
create mode 100644 freebsd/sys/sparc64/include/machine/bus.h
delete mode 100644 rtemsbsd/include/machine/cpufunc.h
diff --git a/freebsd/sys/arm/include/machine/_bus.h
b/freebsd/sys/arm/include/machine/_bus.h
new file mode 100644
index ..9bb51e98
--- /dev/null
+++ b/freebsd/sys/arm/include/machine/_bus.h
@@ -0,0 +1,47 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2005 M. Warner Losh.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions, and the following disclaimer,
+ *without modification, immediately at the beginning of the file.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in
+ *the documentation and/or other materials provided with the
+ *distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef ARM_INCLUDE__BUS_H
+#define ARM_INCLUDE__BUS_H
+
+/*
+ * Addresses (in bus space).
+ */
+typedef u_long bus_addr_t;
+typedef u_long bus_size_t;
+
+/*
+ * Access methods for bus space.
+ */
+typedef struct bus_space *bus_space_tag_t;
+typedef u_long bus_space_handle_t;
+
+#endif /* ARM_INCLUDE__BUS_H */
diff --git a/freebsd/sys/arm/include/machine/bus.h
b/freebsd/sys/arm/include/machine/bus.h
new file mode 100644
index ..37994f68
--- /dev/null
+++ b/freebsd/sys/arm/include/machine/bus.h
@@ -0,0 +1,769 @@
+/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions
[PATCH v1 0/2] [libbsd] Install correct machine include headers
Hello,
This is a follow-up on this discussion regarding the installed header files
in libbsd: https://lists.rtems.org/pipermail/devel/2021-April/066211.html
The current situation is, that for example for all machines the bus.h is
installed from
within the rtemsbsd directory
(https://git.rtems.org/rtems-libbsd/tree/rtemsbsd/include/machine/bus.h).
According to the file docu it originates from the amd64 version of this file.
It also has the following section in it which we ran into when compiling Chris'
ptpd2 archive:
#ifdef __i386__
#error "your include paths are wrong"
#endif
This patchset does the following:
- Add the target dependent machine include directory to 'header-paths' in
libbsd.py
- Import (mostly) '_bus.h', 'bus.h' and 'cpufunc.h' for the targets from
freebsd-org
- Remove those header files from rtemsbsd directory
As a result the matching versions for machine dependent header files are now
installed
for each BSP.
Would this be an acceptable solution?
So far I compiled some BSPs for i386, arm, aarch64, powerpc, riscv, sparc and
sparc64 to check that they still compile after the changes.
Are there any other architectures which should be included?
I ran into one problem regarding the compilation of
rtemsbsd/sys/dev/dw_mmc/dw_mmc.c:105
> return (bus_space_read_4(0, sc->bushandle, off));
The first parameter creates an error for riscv (I think because dereferencing a
NULL pointer).
Are there any suggestion how to solve it (I am not familiar with the bus space
and there is a lot of macro magic going on)?
Also, I am not sure if I always added the header files in the right
module in libbsd.py. Any suggestions where to put them instead would be welcome.
Best regards,
Jan
Jan Sommer (2):
rtemsbd: Remove machine dependent files and use the ones from freebsd
machine: Add machine dependent header files to libbsd.py
freebsd/sys/arm/include/machine/_bus.h| 47 +
freebsd/sys/arm/include/machine/bus.h | 769
freebsd/sys/arm64/include/machine/_bus.h | 46 +
freebsd/sys/arm64/include/machine/bus.h | 469 ++
freebsd/sys/powerpc/include/machine/_bus.h| 50 +
freebsd/sys/powerpc/include/machine/bus.h | 467 ++
freebsd/sys/riscv/include/machine/_bus.h | 46 +
freebsd/sys/riscv/include/machine/bus.h | 469 ++
freebsd/sys/riscv/include/machine/cpufunc.h | 135 +++
freebsd/sys/riscv/include/machine/riscvreg.h | 246 +
.../sys/sparc}/include/machine/_bus.h | 0
.../sys/sparc}/include/machine/bus.h | 0
freebsd/sys/sparc/include/machine/cpufunc.h | 0
freebsd/sys/sparc64/include/machine/_bus.h| 41 +
freebsd/sys/sparc64/include/machine/bus.h | 852 ++
libbsd.py | 26 +-
rtemsbsd/include/machine/cpufunc.h| 1 -
waf_libbsd.py | 2 -
18 files changed, 3660 insertions(+), 6 deletions(-)
create mode 100644 freebsd/sys/arm/include/machine/_bus.h
create mode 100644 freebsd/sys/arm/include/machine/bus.h
create mode 100644 freebsd/sys/arm64/include/machine/_bus.h
create mode 100644 freebsd/sys/arm64/include/machine/bus.h
create mode 100644 freebsd/sys/powerpc/include/machine/_bus.h
create mode 100644 freebsd/sys/powerpc/include/machine/bus.h
create mode 100644 freebsd/sys/riscv/include/machine/_bus.h
create mode 100644 freebsd/sys/riscv/include/machine/bus.h
create mode 100644 freebsd/sys/riscv/include/machine/cpufunc.h
create mode 100644 freebsd/sys/riscv/include/machine/riscvreg.h
rename {rtemsbsd => freebsd/sys/sparc}/include/machine/_bus.h (100%)
rename {rtemsbsd => freebsd/sys/sparc}/include/machine/bus.h (100%)
create mode 100644 freebsd/sys/sparc/include/machine/cpufunc.h
create mode 100644 freebsd/sys/sparc64/include/machine/_bus.h
create mode 100644 freebsd/sys/sparc64/include/machine/bus.h
delete mode 100644 rtemsbsd/include/machine/cpufunc.h
--
2.17.1
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[PATCH v1 2/2] machine: Add machine dependent header files to libbsd.py
---
libbsd.py | 26 +++---
waf_libbsd.py | 2 --
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/libbsd.py b/libbsd.py
index add91e5a..248af993 100644
--- a/libbsd.py
+++ b/libbsd.py
@@ -104,6 +104,7 @@ _defaults = {
# (source, [targets..])
# i386
('freebsd/sys/i386/include', ['freebsd/sys/x86/include',
'freebsd/sys/i386/include']),
+('freebsd/sys/i386/include/machine',
['freebsd/sys/x86/include/machine', 'freebsd/sys/i386/include/machine']),
# arm64
('freebsd/sys/aarch64/include', ['freebsd/sys/aarch64/include',
'freebsd/sys/arm64/include']),
],
@@ -124,6 +125,7 @@ _defaults = {
# local path wildcard
dest path
[('rtemsbsd/include', '**/*.h',
''),
('rtemsbsd/@CPU@/include', '**/*.h',
''),
+ ('freebsd/sys/@CPU@/include', '**/*.h',
''),
('freebsd/include','**/*.h',
''),
('freebsd/sys/bsm','**/*.h',
'bsm'),
('freebsd/sys/cam','**/*.h',
'cam'),
@@ -224,7 +226,7 @@ class rtems(builder.Module):
'sys/arm/lpc/lpc_pwr.c',
'sys/dev/atsam/if_atsam.c',
'sys/dev/atsam/if_atsam_media.c',
-'sys/dev/dw_mmc/dw_mmc.c',
+#'sys/dev/dw_mmc/dw_mmc.c',
'sys/dev/ffec/if_ffec_mcf548x.c',
'sys/dev/ffec/if_ffec_mpc8xx.c',
'sys/dev/input/touchscreen/tsc_lpc32xx.c',
@@ -595,6 +597,16 @@ class fdt(builder.Module):
],
mm.generator['source']()
)
+self.addCPUDependentFreeBSDHeaderFiles(
+[
+'sys/arm/include/_bus.h',
+'sys/arm/include/bus.h',
+'sys/arm64/include/_bus.h',
+'sys/arm64/include/bus.h',
+'sys/riscv/include/_bus.h',
+'sys/riscv/include/bus.h',
+]
+)
self.addRTEMSKernelSourceFiles(
[
'rtems/ofw_machdep.c',
@@ -1600,6 +1612,8 @@ class dev_nic(builder.Module):
'sys/sparc64/include/cpufunc.h',
'sys/sparc64/include/asi.h',
'sys/sparc64/include/pstate.h',
+'sys/riscv/include/cpufunc.h',
+'sys/riscv/include/riscvreg.h',
]
)
self.addKernelSpaceSourceFiles(
@@ -2937,6 +2951,10 @@ class pci(builder.Module):
'sys/x86/include/legacyvar.h',
'sys/x86/include/bus.h',
'sys/x86/include/pci_cfgreg.h',
+'sys/powerpc/include/bus.h',
+'sys/powerpc/include/_bus.h',
+'sys/sparc64/include/bus.h',
+'sys/sparc64/include/_bus.h',
]
)
self.addCPUDependentFreeBSDSourceFiles(
@@ -5299,7 +5317,8 @@ class imx(builder.Module):
def generate(self):
mm = self.manager
-self.addKernelSpaceHeaderFiles(
+
+self.addCPUDependentFreeBSDHeaderFiles(
[
'sys/arm/freescale/imx/imx6_anatopreg.h',
'sys/arm/freescale/imx/imx6_anatopvar.h',
@@ -5308,7 +5327,8 @@ class imx(builder.Module):
'sys/arm/freescale/imx/imx_machdep.h',
]
)
-self.addKernelSpaceSourceFiles(
+self.addCPUDependentFreeBSDSourceFiles(
+[ 'arm' ],
[
'sys/arm/freescale/imx/imx6_ccm.c',
'sys/arm/freescale/imx/imx6_usbphy.c',
diff --git a/waf_libbsd.py b/waf_libbsd.py
index 070d3eac..bbbae929 100644
--- a/waf_libbsd.py
+++ b/waf_libbsd.py
@@ -538,8 +538,6 @@ class Builder(builder.ModuleManager):
if 'header-paths' in config:
headerPaths = config['header-paths']
cpu = bld.get_env()['RTEMS_ARCH']
-if cpu == "i386":
-cpu = 'x86'
for headers in headerPaths:
# Get the dest path
ipath = os.path.join(arch_inc_path, headers[2])
--
2.17.1
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 4/5] bsps/xilinx_zynq: Add Xilinx AXI SPI driver to build
Closes #4370 --- bsps/arm/headers.am| 2 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 1 + c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 1 + 3 files changed, 4 insertions(+) diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am index 007412fee0..69a154f6b2 100644 --- a/bsps/arm/headers.am +++ b/bsps/arm/headers.am @@ -41,6 +41,8 @@ include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart-regs.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/cadence-spi-regs.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/cadence-spi.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/xilinx-axi-spi-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/xilinx-axi-spi.h include_libcpudir = $(includedir)/libcpu include_libcpu_HEADERS = diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index a04889d2e3..449053b831 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -73,6 +73,7 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c. # SPI librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/spi/cadence-spi.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/spi/xilinx-axi-spi.c # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 793cd6616c..6686ca4e04 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -68,6 +68,7 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-generic-t # SPI librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/spi/cadence-spi.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/spi/xilinx-axi-spi.c # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 5/5] shell: Add i2c and spi commands
From: Christian Mauderer This adds some commands that are usefull for debugging simple serial interfaces. Even if they are a complete re-implementation, the i2c* commands use a simmilar call like the Linux i2c tools. Closes #4371 --- cpukit/Makefile.am| 4 + cpukit/include/rtems/shellconfig.h| 28 + cpukit/libmisc/shell/main_i2cdetect.c | 107 ++ cpukit/libmisc/shell/main_i2cget.c| 145 cpukit/libmisc/shell/main_i2cset.c| 124 cpukit/libmisc/shell/main_spi.c | 157 ++ 6 files changed, 565 insertions(+) create mode 100644 cpukit/libmisc/shell/main_i2cdetect.c create mode 100644 cpukit/libmisc/shell/main_i2cget.c create mode 100644 cpukit/libmisc/shell/main_i2cset.c create mode 100644 cpukit/libmisc/shell/main_spi.c diff --git a/cpukit/Makefile.am b/cpukit/Makefile.am index 51f38c84c7..18eda95543 100644 --- a/cpukit/Makefile.am +++ b/cpukit/Makefile.am @@ -1483,6 +1483,10 @@ librtemscpu_a_SOURCES += libmisc/shell/login_prompt.c librtemscpu_a_SOURCES += libmisc/shell/login_check.c librtemscpu_a_SOURCES += libmisc/shell/fdisk.c librtemscpu_a_SOURCES += libmisc/shell/main_rtc.c +librtemscpu_a_SOURCES += libmisc/shell/main_spi.c +librtemscpu_a_SOURCES += libmisc/shell/main_i2cdetect.c +librtemscpu_a_SOURCES += libmisc/shell/main_i2cset.c +librtemscpu_a_SOURCES += libmisc/shell/main_i2cget.c librtemscpu_a_SOURCES += libmisc/shell/dd-args.c librtemscpu_a_SOURCES += libmisc/shell/main_dd.c librtemscpu_a_SOURCES += libmisc/shell/dd-conv.c diff --git a/cpukit/include/rtems/shellconfig.h b/cpukit/include/rtems/shellconfig.h index 3e87d472d6..c5fcf4a45e 100644 --- a/cpukit/include/rtems/shellconfig.h +++ b/cpukit/include/rtems/shellconfig.h @@ -78,6 +78,10 @@ extern rtems_shell_cmd_t rtems_shell_DF_Command; extern rtems_shell_cmd_t rtems_shell_MD5_Command; extern rtems_shell_cmd_t rtems_shell_RTC_Command; +extern rtems_shell_cmd_t rtems_shell_SPI_Command; +extern rtems_shell_cmd_t rtems_shell_I2CDETECT_Command; +extern rtems_shell_cmd_t rtems_shell_I2CGET_Command; +extern rtems_shell_cmd_t rtems_shell_I2CSET_Command; extern rtems_shell_cmd_t rtems_shell_SHUTDOWN_Command; extern rtems_shell_cmd_t rtems_shell_CPUINFO_Command; @@ -521,6 +525,30 @@ extern rtems_shell_alias_t * const rtems_shell_Initial_aliases[]; _shell_RTC_Command, #endif +#if (defined(CONFIGURE_SHELL_COMMANDS_ALL) \ + && !defined(CONFIGURE_SHELL_NO_COMMAND_SPI)) \ +|| defined(CONFIGURE_SHELL_COMMAND_SPI) + _shell_SPI_Command, +#endif + +#if (defined(CONFIGURE_SHELL_COMMANDS_ALL) \ + && !defined(CONFIGURE_SHELL_NO_COMMAND_I2CDETECT)) \ +|| defined(CONFIGURE_SHELL_COMMAND_I2CDETECT) + _shell_I2CDETECT_Command, +#endif + +#if (defined(CONFIGURE_SHELL_COMMANDS_ALL) \ + && !defined(CONFIGURE_SHELL_NO_COMMAND_I2CGET)) \ +|| defined(CONFIGURE_SHELL_COMMAND_I2CGET) + _shell_I2CGET_Command, +#endif + +#if (defined(CONFIGURE_SHELL_COMMANDS_ALL) \ + && !defined(CONFIGURE_SHELL_NO_COMMAND_I2CSET)) \ +|| defined(CONFIGURE_SHELL_COMMAND_I2CSET) + _shell_I2CSET_Command, +#endif + /* * System related commands */ diff --git a/cpukit/libmisc/shell/main_i2cdetect.c b/cpukit/libmisc/shell/main_i2cdetect.c new file mode 100644 index 00..e953b4eaef --- /dev/null +++ b/cpukit/libmisc/shell/main_i2cdetect.c @@ -0,0 +1,107 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2020 embedded brains GmbH. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * The command implemented here has
[PATCH 3/5] bsps/xilinx_zynq: Add SPI driver for xilinx-axi-spi
Updates #4370
---
bsps/arm/include/bsp/xilinx-axi-spi-regs.h | 88 +
bsps/arm/include/bsp/xilinx-axi-spi.h | 67
bsps/arm/shared/spi/xilinx-axi-spi.c | 402 +
3 files changed, 557 insertions(+)
create mode 100644 bsps/arm/include/bsp/xilinx-axi-spi-regs.h
create mode 100644 bsps/arm/include/bsp/xilinx-axi-spi.h
create mode 100644 bsps/arm/shared/spi/xilinx-axi-spi.c
diff --git a/bsps/arm/include/bsp/xilinx-axi-spi-regs.h
b/bsps/arm/include/bsp/xilinx-axi-spi-regs.h
new file mode 100644
index 00..6211c5b97f
--- /dev/null
+++ b/bsps/arm/include/bsp/xilinx-axi-spi-regs.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_AXI_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_AXI_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t reserved1[7];
+uint32_t globalirq;
+#define XILINX_AXI_SPI_GLOBAL_IRQ_ENABLE BSP_BIT32(31)
+uint32_t irqstatus;
+uint32_t reserved2;
+uint32_t irqenable;
+#define XILINX_AXI_SPI_IRQ_CMD_ERR BSP_BIT32(13)
+#define XILINX_AXI_SPI_IRQ_LOOP_ERR BSP_BIT32(12)
+#define XILINX_AXI_SPI_IRQ_MSB_ERR BSP_BIT32(11)
+#define XILINX_AXI_SPI_IRQ_SLV_ERR BSP_BIT32(10)
+#define XILINX_AXI_SPI_IRQ_CPOL_CPHA_ERR BSP_BIT32(9)
+#define XILINX_AXI_SPI_IRQ_RXNEMPTY BSP_BIT32(8)
+#define XILINX_AXI_SPI_IRQ_CS_MODE BSP_BIT32(7)
+#define XILINX_AXI_SPI_IRQ_TXHALF BSP_BIT32(6)
+#define XILINX_AXI_SPI_IRQ_RXOVR BSP_BIT32(5)
+#define XILINX_AXI_SPI_IRQ_RXFULL BSP_BIT32(4)
+#define XILINX_AXI_SPI_IRQ_TXUF BSP_BIT32(3)
+#define XILINX_AXI_SPI_IRQ_TXEMPTY BSP_BIT32(2)
+#define XILINX_AXI_SPI_IRQ_SLV_MODF BSP_BIT32(1)
+#define XILINX_AXI_SPI_IRQ_MODF BSP_BIT32(0)
+uint32_t reserved3[5];
+uint32_t reset;
+#define XILINX_AXI_SPI_RESET 0x000a
+uint32_t reserved4[7];
+uint32_t control;
+#define XILINX_AXI_SPI_CONTROL_LSBFIRST BSP_BIT32(9)
+#define XILINX_AXI_SPI_CONTROL_MST_TRANS_INHIBIT BSP_BIT32(8)
+#define XILINX_AXI_SPI_CONTROL_MANUAL_CS BSP_BIT32(7)
+#define XILINX_AXI_SPI_CONTROL_RX_FIFO_RESET BSP_BIT32(6)
+#define XILINX_AXI_SPI_CONTROL_TX_FIFO_RESET BSP_BIT32(5)
+#define XILINX_AXI_SPI_CONTROL_CPHA BSP_BIT32(4)
+#define XILINX_AXI_SPI_CONTROL_CPOL BSP_BIT32(3)
+#define XILINX_AXI_SPI_CONTROL_MSTREN BSP_BIT32(2)
+#define XILINX_AXI_SPI_CONTROL_SPIEN BSP_BIT32(1)
+#define XILINX_AXI_SPI_CONTROL_LOOP BSP_BIT32(0)
+uint32_t status;
+#define XILINX_AXI_SPI_STATUS_CMD_ERR BSP_BIT32(10)
+#define XILINX_AXI_SPI_STATUS_LOOP_ERR BSP_BIT32(9)
+#define XILINX_AXI_SPI_STATUS_MSB_ERR BSP_BIT32(8)
+#define XILINX_AXI_SPI_STATUS_SLV_ERR BSP_BIT32(7)
+#define XILINX_AXI_SPI_STATUS_CPOL_CPHA_ERR BSP_BIT32(6)
+#define XILINX_AXI_SPI_STATUS_SLV_MODE BSP_BIT32(5)
+#define XILINX_AXI_SPI_STATUS_MODF BSP_BIT32(4)
+#define XILINX_AXI_SPI_STATUS_TXFULL BSP_BIT32(3)
+#define XILINX_AXI_SPI_STATUS_TXEMPTY BSP_BIT32(2)
+#define XILINX_AXI_SPI_STATUS_RXFULL BSP_BIT32(1)
+#define XILINX_AXI_SPI_STATUS_RXEMPTY BSP_BIT32(0)
+uint32_t txdata;
+uint32_t rxdata;
+uint32_t cs;
+uint32_t tx_fifo_len;
+uint32_t rx_fifo_len;
+} xilinx_axi_spi;
+
+#endif /* LIBBSP_ARM_XILINX_AXI_SPI_REGS_H */
diff --git a/bsps/arm/include/bsp/xilinx-axi-spi.h
b/bsps/arm/include/bsp/xilinx-axi-spi.h
new file mode 100644
index 00..1f5e2a9989
--- /dev/null
+++ b/bsps/arm/include/bsp/xilinx-axi-spi.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are
[rtems5 PATCH 0/5] Backport zynq SPI drivers to rtems5
This patchset backports: - The cadence SPI driver (see: https://devel.rtems.org/ticket/4369) - The xilinx axi SPI driver (see: https://devel.rtems.org/ticket/4370) - The i2c and spi shell commands (see: https://devel.rtems.org/ticket/4371) For the SPI drivers I didn't change any code (except the include paths) I put them in bsps/arm/shared instead of bsps/shared, since rtems5 has no aarch64 BSPs which could use them. >From Christian's commit I only stripped the part for the waf build system. I found the commands quite handy during driver development and testing. Best regards, Jan Christian Mauderer (1): shell: Add i2c and spi commands Jan Sommer (4): bsps/xilinx_zynq: Add SPI driver for cadence-spi bsps/xilinx_zynq: Add cadence SPI driver to build system bsps/xilinx_zynq: Add SPI driver for xilinx-axi-spi bsps/xilinx_zynq: Add Xilinx AXI SPI driver to build bsps/arm/headers.am | 4 + bsps/arm/include/bsp/cadence-spi-regs.h | 84 bsps/arm/include/bsp/cadence-spi.h| 63 +++ bsps/arm/include/bsp/xilinx-axi-spi-regs.h| 88 bsps/arm/include/bsp/xilinx-axi-spi.h | 67 +++ bsps/arm/shared/spi/cadence-spi.c | 444 ++ bsps/arm/shared/spi/xilinx-axi-spi.c | 402 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 4 + .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 4 + cpukit/Makefile.am| 4 + cpukit/include/rtems/shellconfig.h| 28 ++ cpukit/libmisc/shell/main_i2cdetect.c | 107 + cpukit/libmisc/shell/main_i2cget.c| 145 ++ cpukit/libmisc/shell/main_i2cset.c| 124 + cpukit/libmisc/shell/main_spi.c | 157 +++ 15 files changed, 1725 insertions(+) create mode 100644 bsps/arm/include/bsp/cadence-spi-regs.h create mode 100644 bsps/arm/include/bsp/cadence-spi.h create mode 100644 bsps/arm/include/bsp/xilinx-axi-spi-regs.h create mode 100644 bsps/arm/include/bsp/xilinx-axi-spi.h create mode 100644 bsps/arm/shared/spi/cadence-spi.c create mode 100644 bsps/arm/shared/spi/xilinx-axi-spi.c create mode 100644 cpukit/libmisc/shell/main_i2cdetect.c create mode 100644 cpukit/libmisc/shell/main_i2cget.c create mode 100644 cpukit/libmisc/shell/main_i2cset.c create mode 100644 cpukit/libmisc/shell/main_spi.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/5] bsps/xilinx_zynq: Add SPI driver for cadence-spi
Updates #4369
---
bsps/arm/include/bsp/cadence-spi-regs.h | 84 +
bsps/arm/include/bsp/cadence-spi.h | 63
bsps/arm/shared/spi/cadence-spi.c | 444
3 files changed, 591 insertions(+)
create mode 100644 bsps/arm/include/bsp/cadence-spi-regs.h
create mode 100644 bsps/arm/include/bsp/cadence-spi.h
create mode 100644 bsps/arm/shared/spi/cadence-spi.c
diff --git a/bsps/arm/include/bsp/cadence-spi-regs.h
b/bsps/arm/include/bsp/cadence-spi-regs.h
new file mode 100644
index 00..b4b2366b3d
--- /dev/null
+++ b/bsps/arm/include/bsp/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ uint32_t irqdisable;
+ uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t txdata;
+ uint32_t rxdata;
+ uint32_t slave_idle_count;
+ uint32_t txthreshold;
+ uint32_t rxthreshold;
+ uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/arm/include/bsp/cadence-spi.h
b/bsps/arm/include/bsp/cadence-spi.h
new file mode 100644
index 00..d97ede53c8
--- /dev/null
+++ b/bsps/arm/include/bsp/cadence-spi.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace C
[PATCH 2/5] bsps/xilinx_zynq: Add cadence SPI driver to build system
Closes #4369 --- bsps/arm/headers.am| 2 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++ c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 +++ 3 files changed, 8 insertions(+) diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am index 3d2b09effa..007412fee0 100644 --- a/bsps/arm/headers.am +++ b/bsps/arm/headers.am @@ -39,6 +39,8 @@ include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-timer.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/start.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart-regs.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/cadence-spi-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/cadence-spi.h include_libcpudir = $(includedir)/libcpu include_libcpu_HEADERS = diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index cfd59475c2..a04889d2e3 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -71,6 +71,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore. # I2C librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 0b49990ce7..793cd6616c 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -66,6 +66,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/serial/zynq-uart-poll # Clock librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-generic-timer.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 0/1] Add per cpu clock interrupt
v2: Added check against counter wrap-around during intialization @Gedare: Could you please re-approve? The changes compared to the previous version are just cosmetic. Jan Sommer (1): bsps/riscv: Add per cpu clock interrupt bsps/include/bsp/fatal.h | 1 + bsps/riscv/riscv/clock/clockdrv.c | 64 ++- 2 files changed, 55 insertions(+), 10 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 1/1] bsps/riscv: Add per cpu clock interrupt
- Fixes failure of test smpclock01
---
bsps/include/bsp/fatal.h | 1 +
bsps/riscv/riscv/clock/clockdrv.c | 64 ++-
2 files changed, 55 insertions(+), 10 deletions(-)
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index ec5902755e..54ed4b2027 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -155,6 +155,7 @@ typedef enum {
RISCV_FATAL_INVALID_INTERRUPT_AFFINITY,
RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE,
RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE,
+ RISCV_FATAL_CLOCK_SMP_INIT,
/* GRLIB fatal codes */
GRLIB_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT = BSP_FATAL_CODE_BLOCK(14),
diff --git a/bsps/riscv/riscv/clock/clockdrv.c
b/bsps/riscv/riscv/clock/clockdrv.c
index d085b6bd95..e8a39c8591 100644
--- a/bsps/riscv/riscv/clock/clockdrv.c
+++ b/bsps/riscv/riscv/clock/clockdrv.c
@@ -41,6 +41,7 @@
#include
#include
#include
+#include
#include
@@ -92,13 +93,18 @@ static void riscv_clock_at_tick(riscv_timecounter *tc)
{
volatile RISCV_CLINT_regs *clint;
uint64_t value;
+ uint32_t cpu = 0;
+
+#if defined(RTEMS_SMP)
+ cpu = _CPU_SMP_Get_current_processor();
+#endif
clint = tc->clint;
- value = clint->mtimecmp[0].val_64;
+ value = clint->mtimecmp[cpu].val_64;
value += tc->interval;
- riscv_clock_write_mtimecmp(>mtimecmp[0], value);
+ riscv_clock_write_mtimecmp(>mtimecmp[cpu], value);
}
static void riscv_clock_handler_install(void)
@@ -148,6 +154,47 @@ static uint32_t riscv_clock_get_timebase_frequency(const
void *fdt)
return fdt32_to_cpu(*val);
}
+static void riscv_clock_clint_init(
+ volatile RISCV_CLINT_regs *clint,
+ uint64_t cmpval,
+ uint32_t cpu
+)
+{
+ riscv_clock_write_mtimecmp(
+>mtimecmp[cpu],
+ cmpval
+ );
+
+ /* Enable mtimer interrupts */
+ set_csr(mie, MIP_MTIP);
+}
+
+#if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR)
+static void riscv_clock_secondary_action(void *arg)
+{
+ volatile RISCV_CLINT_regs *clint = riscv_clint;
+ uint64_t *cmpval = arg;
+ uint32_t cpu = _CPU_SMP_Get_current_processor();
+
+ riscv_clock_clint_init(clint, *cmpval, cpu);
+}
+#endif
+
+static void riscv_clock_secondary_initialization(
+ volatile RISCV_CLINT_regs *clint,
+ uint64_t cmpval,
+ uint32_t interval
+)
+{
+#if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR)
+ _SMP_Othercast_action(riscv_clock_secondary_action, );
+
+ if (cmpval - riscv_clock_read_mtime(>mtime) >= interval) {
+bsp_fatal(RISCV_FATAL_CLOCK_SMP_INIT);
+ }
+#endif
+}
+
static void riscv_clock_initialize(void)
{
const char *fdt;
@@ -156,6 +203,7 @@ static void riscv_clock_initialize(void)
uint32_t tb_freq;
uint64_t us_per_tick;
uint32_t interval;
+ uint64_t cmpval;
fdt = bsp_fdt_get();
tb_freq = riscv_clock_get_timebase_frequency(fdt);
@@ -167,13 +215,11 @@ static void riscv_clock_initialize(void)
tc->clint = clint;
tc->interval = interval;
- riscv_clock_write_mtimecmp(
->mtimecmp[0],
-riscv_clock_read_mtime(>mtime) + interval
- );
+ cmpval = riscv_clock_read_mtime(>mtime);
+ cmpval += interval;
- /* Enable mtimer interrupts */
- set_csr(mie, MIP_MTIP);
+ riscv_clock_clint_init(clint, cmpval, 0);
+ riscv_clock_secondary_initialization(clint, cmpval, interval);
/* Initialize timecounter */
tc->base.tc_get_timecount = riscv_clock_get_timecount;
@@ -213,6 +259,4 @@ RTEMS_SYSINIT_ITEM(
#define Clock_driver_support_install_isr(isr) \
riscv_clock_handler_install()
-#define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR
-
#include "../../../shared/dev/clock/clockimpl.h"
--
2.17.1
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[PATCH] bsps/riscv: Add per cpu clock interrupt
- Fixes failure of test smpclock01
---
bsps/riscv/riscv/clock/clockdrv.c | 61 +--
1 file changed, 50 insertions(+), 11 deletions(-)
diff --git a/bsps/riscv/riscv/clock/clockdrv.c
b/bsps/riscv/riscv/clock/clockdrv.c
index d085b6bd95..04abe24545 100644
--- a/bsps/riscv/riscv/clock/clockdrv.c
+++ b/bsps/riscv/riscv/clock/clockdrv.c
@@ -41,6 +41,7 @@
#include
#include
#include
+#include
#include
@@ -92,13 +93,18 @@ static void riscv_clock_at_tick(riscv_timecounter *tc)
{
volatile RISCV_CLINT_regs *clint;
uint64_t value;
+ uint32_t cpu = 0;
+
+#if defined(RTEMS_SMP)
+ cpu = _CPU_SMP_Get_current_processor();
+#endif
clint = tc->clint;
- value = clint->mtimecmp[0].val_64;
+ value = clint->mtimecmp[cpu].val_64;
value += tc->interval;
- riscv_clock_write_mtimecmp(>mtimecmp[0], value);
+ riscv_clock_write_mtimecmp(>mtimecmp[cpu], value);
}
static void riscv_clock_handler_install(void)
@@ -148,6 +154,42 @@ static uint32_t riscv_clock_get_timebase_frequency(const
void *fdt)
return fdt32_to_cpu(*val);
}
+static void riscv_clock_clint_init(
+ volatile RISCV_CLINT_regs *clint,
+ uint64_t cmpval,
+ uint32_t cpu
+)
+{
+ riscv_clock_write_mtimecmp(
+>mtimecmp[cpu],
+ cmpval
+ );
+
+ /* Enable mtimer interrupts */
+ set_csr(mie, MIP_MTIP);
+}
+
+#if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR)
+static void riscv_clock_secondary_action(void *arg)
+{
+ volatile RISCV_CLINT_regs *clint = riscv_clint;
+ uint64_t *cmpval = arg;
+ uint32_t cpu = _CPU_SMP_Get_current_processor();
+
+ riscv_clock_clint_init(clint, *cmpval, cpu);
+}
+#endif
+
+static void riscv_clock_secondary_initialization(
+ volatile RISCV_CLINT_regs *clint,
+ uint64_t cmpval
+)
+{
+#if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR)
+ _SMP_Othercast_action(riscv_clock_secondary_action, );
+#endif
+}
+
static void riscv_clock_initialize(void)
{
const char *fdt;
@@ -156,6 +198,7 @@ static void riscv_clock_initialize(void)
uint32_t tb_freq;
uint64_t us_per_tick;
uint32_t interval;
+ uint64_t cmpval;
fdt = bsp_fdt_get();
tb_freq = riscv_clock_get_timebase_frequency(fdt);
@@ -167,13 +210,11 @@ static void riscv_clock_initialize(void)
tc->clint = clint;
tc->interval = interval;
- riscv_clock_write_mtimecmp(
->mtimecmp[0],
-riscv_clock_read_mtime(>mtime) + interval
- );
-
- /* Enable mtimer interrupts */
- set_csr(mie, MIP_MTIP);
+ cmpval = riscv_clock_read_mtime(>mtime);
+ cmpval += interval;
+
+ riscv_clock_clint_init(clint, cmpval, 0);
+ riscv_clock_secondary_initialization(clint, cmpval);
/* Initialize timecounter */
tc->base.tc_get_timecount = riscv_clock_get_timecount;
@@ -213,6 +254,4 @@ RTEMS_SYSINIT_ITEM(
#define Clock_driver_support_install_isr(isr) \
riscv_clock_handler_install()
-#define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR
-
#include "../../../shared/dev/clock/clockimpl.h"
--
2.17.1
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[PATCH 1/3] bsps/xilinx_zynq: Add SPI driver for xilinx-axi-spi
Updates #4321
---
bsps/include/dev/spi/xilinx-axi-spi-regs.h | 88 +
bsps/include/dev/spi/xilinx-axi-spi.h | 67
bsps/shared/dev/spi/xilinx-axi-spi.c | 402 +
3 files changed, 557 insertions(+)
create mode 100644 bsps/include/dev/spi/xilinx-axi-spi-regs.h
create mode 100644 bsps/include/dev/spi/xilinx-axi-spi.h
create mode 100644 bsps/shared/dev/spi/xilinx-axi-spi.c
diff --git a/bsps/include/dev/spi/xilinx-axi-spi-regs.h
b/bsps/include/dev/spi/xilinx-axi-spi-regs.h
new file mode 100644
index 00..6211c5b97f
--- /dev/null
+++ b/bsps/include/dev/spi/xilinx-axi-spi-regs.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_AXI_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_AXI_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t reserved1[7];
+uint32_t globalirq;
+#define XILINX_AXI_SPI_GLOBAL_IRQ_ENABLE BSP_BIT32(31)
+uint32_t irqstatus;
+uint32_t reserved2;
+uint32_t irqenable;
+#define XILINX_AXI_SPI_IRQ_CMD_ERR BSP_BIT32(13)
+#define XILINX_AXI_SPI_IRQ_LOOP_ERR BSP_BIT32(12)
+#define XILINX_AXI_SPI_IRQ_MSB_ERR BSP_BIT32(11)
+#define XILINX_AXI_SPI_IRQ_SLV_ERR BSP_BIT32(10)
+#define XILINX_AXI_SPI_IRQ_CPOL_CPHA_ERR BSP_BIT32(9)
+#define XILINX_AXI_SPI_IRQ_RXNEMPTY BSP_BIT32(8)
+#define XILINX_AXI_SPI_IRQ_CS_MODE BSP_BIT32(7)
+#define XILINX_AXI_SPI_IRQ_TXHALF BSP_BIT32(6)
+#define XILINX_AXI_SPI_IRQ_RXOVR BSP_BIT32(5)
+#define XILINX_AXI_SPI_IRQ_RXFULL BSP_BIT32(4)
+#define XILINX_AXI_SPI_IRQ_TXUF BSP_BIT32(3)
+#define XILINX_AXI_SPI_IRQ_TXEMPTY BSP_BIT32(2)
+#define XILINX_AXI_SPI_IRQ_SLV_MODF BSP_BIT32(1)
+#define XILINX_AXI_SPI_IRQ_MODF BSP_BIT32(0)
+uint32_t reserved3[5];
+uint32_t reset;
+#define XILINX_AXI_SPI_RESET 0x000a
+uint32_t reserved4[7];
+uint32_t control;
+#define XILINX_AXI_SPI_CONTROL_LSBFIRST BSP_BIT32(9)
+#define XILINX_AXI_SPI_CONTROL_MST_TRANS_INHIBIT BSP_BIT32(8)
+#define XILINX_AXI_SPI_CONTROL_MANUAL_CS BSP_BIT32(7)
+#define XILINX_AXI_SPI_CONTROL_RX_FIFO_RESET BSP_BIT32(6)
+#define XILINX_AXI_SPI_CONTROL_TX_FIFO_RESET BSP_BIT32(5)
+#define XILINX_AXI_SPI_CONTROL_CPHA BSP_BIT32(4)
+#define XILINX_AXI_SPI_CONTROL_CPOL BSP_BIT32(3)
+#define XILINX_AXI_SPI_CONTROL_MSTREN BSP_BIT32(2)
+#define XILINX_AXI_SPI_CONTROL_SPIEN BSP_BIT32(1)
+#define XILINX_AXI_SPI_CONTROL_LOOP BSP_BIT32(0)
+uint32_t status;
+#define XILINX_AXI_SPI_STATUS_CMD_ERR BSP_BIT32(10)
+#define XILINX_AXI_SPI_STATUS_LOOP_ERR BSP_BIT32(9)
+#define XILINX_AXI_SPI_STATUS_MSB_ERR BSP_BIT32(8)
+#define XILINX_AXI_SPI_STATUS_SLV_ERR BSP_BIT32(7)
+#define XILINX_AXI_SPI_STATUS_CPOL_CPHA_ERR BSP_BIT32(6)
+#define XILINX_AXI_SPI_STATUS_SLV_MODE BSP_BIT32(5)
+#define XILINX_AXI_SPI_STATUS_MODF BSP_BIT32(4)
+#define XILINX_AXI_SPI_STATUS_TXFULL BSP_BIT32(3)
+#define XILINX_AXI_SPI_STATUS_TXEMPTY BSP_BIT32(2)
+#define XILINX_AXI_SPI_STATUS_RXFULL BSP_BIT32(1)
+#define XILINX_AXI_SPI_STATUS_RXEMPTY BSP_BIT32(0)
+uint32_t txdata;
+uint32_t rxdata;
+uint32_t cs;
+uint32_t tx_fifo_len;
+uint32_t rx_fifo_len;
+} xilinx_axi_spi;
+
+#endif /* LIBBSP_ARM_XILINX_AXI_SPI_REGS_H */
diff --git a/bsps/include/dev/spi/xilinx-axi-spi.h
b/bsps/include/dev/spi/xilinx-axi-spi.h
new file mode 100644
index 00..1f5e2a9989
--- /dev/null
+++ b/bsps/include/dev/spi/xilinx-axi-spi.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are
[PATCH 3/3] bsps/xilinx_zynq: Add Xilinx AXI SPI driver to autotools build
Closes #4321 --- bsps/headers.am| 2 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 1 + c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 1 + 3 files changed, 4 insertions(+) diff --git a/bsps/headers.am b/bsps/headers.am index 37ce6d6c73..3d95f144d4 100644 --- a/bsps/headers.am +++ b/bsps/headers.am @@ -43,6 +43,8 @@ include_dev_spidir = $(includedir)/dev/spi include_dev_spi_HEADERS = include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi-regs.h include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi.h +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/xilinx-axi-spi-regs.h +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/xilinx-axi-spi.h include_grlibdir = $(includedir)/grlib include_grlib_HEADERS = diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 87950a3e66..f2db456170 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -74,6 +74,7 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c. # SPI librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/xilinx-axi-spi.c # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 393e8e8bd3..e4be0567ab 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -70,6 +70,7 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/arm-generic-tim # SPI librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/xilinx-axi-spi.c # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 0/3] Add spidev driver for Xilinx AXI Quad SPI device
This patchset adds a spidev driver for the Xilinx AXI Quad SPI device. It currently supports Standard SPI mode. Thanks goes to Rick van der Wal for testing the driver with his SPI IMU. Jan Sommer (3): bsps/xilinx_zynq: Add SPI driver for xilinx-axi-spi bsps/shared: Add Xilinx-AXI SPI driver to waf bsps/xilinx_zynq: Add Xilinx AXI SPI driver to autotools build bsps/headers.am | 2 + bsps/include/dev/spi/xilinx-axi-spi-regs.h| 88 bsps/include/dev/spi/xilinx-axi-spi.h | 67 +++ bsps/shared/dev/spi/xilinx-axi-spi.c | 402 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 1 + .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 1 + spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 + spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 + .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 + spec/build/bsps/objdevspixil.yml | 18 + 10 files changed, 585 insertions(+) create mode 100644 bsps/include/dev/spi/xilinx-axi-spi-regs.h create mode 100644 bsps/include/dev/spi/xilinx-axi-spi.h create mode 100644 bsps/shared/dev/spi/xilinx-axi-spi.c create mode 100644 spec/build/bsps/objdevspixil.yml -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/3] bsps/shared: Add Xilinx-AXI SPI driver to waf
Updates #4321
---
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 ++
spec/build/bsps/arm/xilinx-zynq/grp.yml| 2 ++
.../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 ++
spec/build/bsps/objdevspixil.yml | 18 ++
4 files changed, 24 insertions(+)
create mode 100644 spec/build/bsps/objdevspixil.yml
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index c952b4f59e..38b9be59da 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
@@ -35,6 +35,8 @@ links:
uid: ../../objdevserialzynq
- role: build-dependency
uid: ../../objdevspizynq
+- role: build-dependency
+ uid: ../../objdevspixil
- role: build-dependency
uid: ../../optcachedata
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 0bbee1922c..55eab20f84 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -59,6 +59,8 @@ links:
uid: ../../objdevserialzynq
- role: build-dependency
uid: ../../objdevspizynq
+- role: build-dependency
+ uid: ../../objdevspixil
- role: build-dependency
uid: linkcmds
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index b489752420..21a21f3812 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -71,6 +71,8 @@ links:
uid: ../../objdevserialzynq
- role: build-dependency
uid: ../../objdevspizynq
+- role: build-dependency
+ uid: ../../objdevspixil
- role: build-dependency
uid: ../../opto2
- role: build-dependency
diff --git a/spec/build/bsps/objdevspixil.yml b/spec/build/bsps/objdevspixil.yml
new file mode 100644
index 00..c499b4713d
--- /dev/null
+++ b/spec/build/bsps/objdevspixil.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 German Aerospace Center (DLR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/spi
+ source:
+ - bsps/include/dev/spi/xilinx-axi-spi-regs.h
+ - bsps/include/dev/spi/xilinx-axi-spi.h
+links: []
+source:
+- bsps/shared/dev/spi/xilinx-axi-spi.c
+type: build
--
2.17.1
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[PATCH v5 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build
Closes #4320 --- bsps/headers.am| 5 + c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++ c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 +++ 3 files changed, 11 insertions(+) diff --git a/bsps/headers.am b/bsps/headers.am index 1b82382db8..37ce6d6c73 100644 --- a/bsps/headers.am +++ b/bsps/headers.am @@ -39,6 +39,11 @@ include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart-regs.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart.h +include_dev_spidir = $(includedir)/dev/spi +include_dev_spi_HEADERS = +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi-regs.h +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi.h + include_grlibdir = $(includedir)/grlib include_grlib_HEADERS = include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 1416a5c328..87950a3e66 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -72,6 +72,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore. # I2C librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 9d4afcf798..393e8e8bd3 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -68,6 +68,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/zynq-uart-poll librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/clock/arm-generic-timer.c librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/arm-generic-timer-aarch32.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v5 2/3] bsps/xilinx_zynq: Add SPI driver to waf
Updates #4320
---
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 ++
spec/build/bsps/arm/xilinx-zynq/grp.yml| 2 ++
.../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 ++
spec/build/bsps/objdevspizynq.yml | 18 ++
4 files changed, 24 insertions(+)
create mode 100644 spec/build/bsps/objdevspizynq.yml
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index 552723c61c..c952b4f59e 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
@@ -33,6 +33,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../optcachedata
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 74adbd7fa7..0bbee1922c 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -57,6 +57,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: linkcmds
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index b8657b54f8..b489752420 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -69,6 +69,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../opto2
- role: build-dependency
diff --git a/spec/build/bsps/objdevspizynq.yml
b/spec/build/bsps/objdevspizynq.yml
new file mode 100644
index 00..b778e756e1
--- /dev/null
+++ b/spec/build/bsps/objdevspizynq.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 German Aerospace Center (DLR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/spi
+ source:
+ - bsps/include/dev/spi/cadence-spi-regs.h
+ - bsps/include/dev/spi/cadence-spi.h
+links: []
+source:
+- bsps/shared/dev/spi/cadence-spi.c
+type: build
--
2.17.1
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[PATCH v5 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi
Updates #4320
---
bsps/include/dev/spi/cadence-spi-regs.h | 84 +
bsps/include/dev/spi/cadence-spi.h | 63
bsps/shared/dev/spi/cadence-spi.c | 444
3 files changed, 591 insertions(+)
create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h
create mode 100644 bsps/include/dev/spi/cadence-spi.h
create mode 100644 bsps/shared/dev/spi/cadence-spi.c
diff --git a/bsps/include/dev/spi/cadence-spi-regs.h
b/bsps/include/dev/spi/cadence-spi-regs.h
new file mode 100644
index 00..b4b2366b3d
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ uint32_t irqdisable;
+ uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t txdata;
+ uint32_t rxdata;
+ uint32_t slave_idle_count;
+ uint32_t txthreshold;
+ uint32_t rxthreshold;
+ uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/include/dev/spi/cadence-spi.h
b/bsps/include/dev/spi/cadence-spi.h
new file mode 100644
index 00..d97ede53c8
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2021 Jan Sommer, German Aerospace C
[PATCH v5 0/3] Add cadence-SPI driver
v5: - Add some documentation - Thanks for testing by Rick van der Wal - Fix bug in CS logic - Work-around too slow RXNEMPTY flag for some bus frequencies - Created issue in trac: https://devel.rtems.org/ticket/4320 v4: - Use copyright information without UTF-8 characters v3: - Fix wrong changes to spec/build/bsps/arm/xilinx-zynq/obj.yml v2: - Moved source file to bsps/shared/dev/spi - Moved include files to bsps/include/dev/spi - Enabled build in aarch64 BSPs v1: This patchset implements a driver for the cadence-spi device of the Xilinx Zynq-7000 based SoCs using the spidev API. Jan Sommer (3): bsps/xilinx_zynq: Add SPI driver for cadence-spi bsps/xilinx_zynq: Add SPI driver to waf bsps/xilinx_zynq: Add SPI driver to autotools build bsps/headers.am | 5 + bsps/include/dev/spi/cadence-spi-regs.h | 84 bsps/include/dev/spi/cadence-spi.h| 63 +++ bsps/shared/dev/spi/cadence-spi.c | 444 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 + .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 + spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 + spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 + .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 + spec/build/bsps/objdevspizynq.yml | 18 + 10 files changed, 626 insertions(+) create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h create mode 100644 bsps/include/dev/spi/cadence-spi.h create mode 100644 bsps/shared/dev/spi/cadence-spi.c create mode 100644 spec/build/bsps/objdevspizynq.yml -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/2] bsps/shared: Allow setting baud rate for zynq uart
Closes #4236
---
bsps/arm/shared/serial/zynq-uart.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/bsps/arm/shared/serial/zynq-uart.c
b/bsps/arm/shared/serial/zynq-uart.c
index a0dfc0c929..f298719fde 100644
--- a/bsps/arm/shared/serial/zynq-uart.c
+++ b/bsps/arm/shared/serial/zynq-uart.c
@@ -144,14 +144,22 @@ static bool zynq_uart_set_attributes(
{
zynq_uart_context *ctx = (zynq_uart_context *) context;
volatile zynq_uart *regs = ctx->regs;
+ int32_t baud;
uint32_t brgr = 0;
uint32_t bauddiv = 0;
uint32_t mode = 0;
int rc;
- rc = zynq_cal_baud_rate(115200, , , regs->mode);
- if (rc != 0)
-return rc;
+ /*
+ * Determine the baud rate
+ */
+ baud = rtems_termios_baud_to_number(term->c_ospeed);
+
+ if (baud > 0) {
+rc = zynq_cal_baud_rate(baud, , , regs->mode);
+if (rc != 0)
+ return rc;
+ }
/*
* Configure the mode register
@@ -202,8 +210,11 @@ static bool zynq_uart_set_attributes(
regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
regs->mode = mode;
- regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
- regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
+ /* Ignore baud rate of B0. There are no modem control lines to de-assert */
+ if (baud > 0) {
+regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
+regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
+ }
regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
return true;
--
2.17.1
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[5 PATCH 0/2] Backport fixes to zynq uart to RTEMS5
This patchset backports the commits of Kinsey Moore and myself, which fix the stdin behavior for the zynq-uart based console driver. I checked the behavior on hardware with the termios.exe application. Before, the scanf and similar functions do not wait for user input and return immediately. With the patches the application behaves as expected. A corresponding ticket can be found here: https://devel.rtems.org/ticket/4236 Small side note: I noticed that the ARM BSP docs for RTEMS5 list mostly TODO. Should I create a patchset backporting the BSP documentation or do you want to do that in one go as part of the 5.2 release preparation? Best regards, Jan Jan Sommer (1): bsps/shared: Allow setting baud rate for zynq uart Kinsey Moore (1): zynq-uart: Fix set_attributes implementation bsps/arm/include/bsp/zynq-uart.h | 7 +++ bsps/arm/shared/serial/zynq-uart-polled.c | 2 +- bsps/arm/shared/serial/zynq-uart.c| 77 --- 3 files changed, 75 insertions(+), 11 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/2] zynq-uart: Fix set_attributes implementation
From: Kinsey Moore
The zynq-uart set_attributes implementation was configured to always
return false which causes spconsole01 to fail. This restores the
disabled implementation which sets the baud rate registers
appropriately and allows spconsole01 to pass. This also expands the
set_attributes functionality to allow setting of the stop bits,
character width, and parity.
Updates #4236
---
bsps/arm/include/bsp/zynq-uart.h | 7 +++
bsps/arm/shared/serial/zynq-uart-polled.c | 2 +-
bsps/arm/shared/serial/zynq-uart.c| 56 +--
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/include/bsp/zynq-uart.h b/bsps/arm/include/bsp/zynq-uart.h
index 20c3c9b653..5a6c926bec 100644
--- a/bsps/arm/include/bsp/zynq-uart.h
+++ b/bsps/arm/include/bsp/zynq-uart.h
@@ -71,6 +71,13 @@ void zynq_uart_write_polled(
*/
void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
+int zynq_cal_baud_rate(
+ uint32_t baudrate,
+ uint32_t* brgr,
+ uint32_t* bauddiv,
+ uint32_t modereg
+);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/arm/shared/serial/zynq-uart-polled.c
b/bsps/arm/shared/serial/zynq-uart-polled.c
index e6f478ee07..7fc9590832 100644
--- a/bsps/arm/shared/serial/zynq-uart-polled.c
+++ b/bsps/arm/shared/serial/zynq-uart-polled.c
@@ -40,7 +40,7 @@ uint32_t zynq_uart_input_clock(void)
return ZYNQ_CLOCK_UART;
}
-static int zynq_cal_baud_rate(uint32_t baudrate,
+int zynq_cal_baud_rate(uint32_t baudrate,
uint32_t* brgr,
uint32_t* bauddiv,
uint32_t modereg)
diff --git a/bsps/arm/shared/serial/zynq-uart.c
b/bsps/arm/shared/serial/zynq-uart.c
index fc670441b8..a0dfc0c929 100644
--- a/bsps/arm/shared/serial/zynq-uart.c
+++ b/bsps/arm/shared/serial/zynq-uart.c
@@ -142,25 +142,71 @@ static bool zynq_uart_set_attributes(
const struct termios *term
)
{
-#if 0
- volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+ zynq_uart_context *ctx = (zynq_uart_context *) context;
+ volatile zynq_uart *regs = ctx->regs;
uint32_t brgr = 0;
uint32_t bauddiv = 0;
+ uint32_t mode = 0;
int rc;
rc = zynq_cal_baud_rate(115200, , , regs->mode);
if (rc != 0)
return rc;
+ /*
+ * Configure the mode register
+ */
+ mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL);
+
+ /*
+ * Parity
+ */
+ mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE);
+ if (term->c_cflag & PARENB) {
+if (!(term->c_cflag & PARODD)) {
+ mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD);
+} else {
+ mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN);
+}
+ }
+
+ /*
+ * Character Size
+ */
+ switch (term->c_cflag & CSIZE)
+ {
+ case CS5:
+return false;
+ case CS6:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6);
+break;
+ case CS7:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7);
+break;
+ case CS8:
+ default:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+break;
+ }
+
+ /*
+ * Stop Bits
+ */
+ if (term->c_cflag & CSTOPB) {
+/* 2 stop bits */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_2);
+ } else {
+/* 1 stop bit */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_1);
+ }
+
regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
+ regs->mode = mode;
regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
return true;
-#else
- return false;
-#endif
}
const rtems_termios_device_handler zynq_uart_handler = {
--
2.17.1
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[PATCH v2] user/bsps: Mention fixed console baud rate for zynq
--- user/bsps/arm/xilinx-zynq.rst | 12 1 file changed, 12 insertions(+) diff --git a/user/bsps/arm/xilinx-zynq.rst b/user/bsps/arm/xilinx-zynq.rst index 365c336..29f9cb0 100644 --- a/user/bsps/arm/xilinx-zynq.rst +++ b/user/bsps/arm/xilinx-zynq.rst @@ -37,6 +37,18 @@ to return the peripheral clock. Normally this is half the CPU clock. This function is declared ``weak`` so you can override the default behaviour by providing it in your application. +Console +--- + +The console driver for the UARTs will always be initialized to a +baud rate of 115200 with 8 bit characters, 1 stop bit and no parity +bits during start up. +Previous configurations programmed into the hardware by the Xilinx +tools or a bootloader will be overwritten. + +The settings for the console driver can be changed by the user +application through the termios API afterwards. + Debugging with xilinx_zynq_a9_qemu -- -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 0/1] Enable baud rate selection for zynq uart
v3: - Make sure the baud registers are not modified for baud rate B0 v2: - Use rtems_baud_to_number instead of duplicating baud table This patch allows to set the baud rate of the zynq-uart using the termios API. I could change the baud rate successfully on hardware using the termios application. Best regards, Jan Jan Sommer (1): bsps/shared: Allow setting baud rate for zynq uart bsps/shared/dev/serial/zynq-uart.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 1/1] bsps/shared: Allow setting baud rate for zynq uart
---
bsps/shared/dev/serial/zynq-uart.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/bsps/shared/dev/serial/zynq-uart.c
b/bsps/shared/dev/serial/zynq-uart.c
index 8f17d3ca65..cd0d0e7584 100644
--- a/bsps/shared/dev/serial/zynq-uart.c
+++ b/bsps/shared/dev/serial/zynq-uart.c
@@ -144,14 +144,22 @@ static bool zynq_uart_set_attributes(
{
zynq_uart_context *ctx = (zynq_uart_context *) context;
volatile zynq_uart *regs = ctx->regs;
+ int32_t baud;
uint32_t brgr = 0;
uint32_t bauddiv = 0;
uint32_t mode = 0;
int rc;
- rc = zynq_cal_baud_rate(115200, , , regs->mode);
- if (rc != 0)
-return rc;
+ /*
+ * Determine the baud rate
+ */
+ baud = rtems_termios_baud_to_number(term->c_ospeed);
+
+ if (baud > 0) {
+rc = zynq_cal_baud_rate(baud, , , regs->mode);
+if (rc != 0)
+ return rc;
+ }
/*
* Configure the mode register
@@ -202,8 +210,11 @@ static bool zynq_uart_set_attributes(
regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
regs->mode = mode;
- regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
- regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
+ /* Ignore baud rate of B0. There are no modem control lines to de-assert */
+ if (baud > 0) {
+regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
+regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
+ }
regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
return true;
--
2.17.1
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[PATCH] MAINTAINERS: Add myself to write after approval
--- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 29e22357a5..6c9b70bc40 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -53,6 +53,7 @@ Christian Mauderer christian.maude...@embedded-brains.de Hesham Almataryheshamelmat...@gmail.com Amaan Cheval am...@rtems.org Vijay Kumar Banerjee vi...@rtems.org +Jan Sommer j...@rtems.org Localized Write Permission == -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 0/1] Enable baud rate selection for zynq uart
v2: - Use rtems_baud_to_number instead of duplicating baud table This patch allows to set the baud rate of the zynq-uart using the termios API. I could change the baud rate successfully on hardware using the termios application. Best regards, Jan Jan Sommer (1): bsps/shared: Allow setting baud rate for zynq uart bsps/shared/dev/serial/zynq-uart.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 1/1] bsps/shared: Allow setting baud rate for zynq uart
---
bsps/shared/dev/serial/zynq-uart.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/bsps/shared/dev/serial/zynq-uart.c
b/bsps/shared/dev/serial/zynq-uart.c
index 8f17d3ca65..dd5a6e1cb8 100644
--- a/bsps/shared/dev/serial/zynq-uart.c
+++ b/bsps/shared/dev/serial/zynq-uart.c
@@ -144,14 +144,22 @@ static bool zynq_uart_set_attributes(
{
zynq_uart_context *ctx = (zynq_uart_context *) context;
volatile zynq_uart *regs = ctx->regs;
+ int32_t baud;
uint32_t brgr = 0;
uint32_t bauddiv = 0;
uint32_t mode = 0;
int rc;
- rc = zynq_cal_baud_rate(115200, , , regs->mode);
- if (rc != 0)
-return rc;
+ /*
+ * Determine the baud rate
+ */
+ baud = rtems_termios_baud_to_number(term->c_ospeed);
+
+ if (baud > 0) {
+rc = zynq_cal_baud_rate(baud, , , regs->mode);
+if (rc != 0)
+ return rc;
+ }
/*
* Configure the mode register
--
2.17.1
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[PATCH v1 0/1] Enable baud rate selection for zynq uart
This patch allows to set the baud rate of the zynq-uart using the termios API. I could change the baud rate successfully on hardware using the termios application. Best regards, Jan Jan Sommer (1): bsps/shared: Allow setting baud rate for zynq uart bsps/shared/dev/serial/zynq-uart.c | 42 +++--- 1 file changed, 39 insertions(+), 3 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/1] bsps/shared: Allow setting baud rate for zynq uart
---
bsps/shared/dev/serial/zynq-uart.c | 42 +++---
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/bsps/shared/dev/serial/zynq-uart.c
b/bsps/shared/dev/serial/zynq-uart.c
index 8f17d3ca65..124f9e032d 100644
--- a/bsps/shared/dev/serial/zynq-uart.c
+++ b/bsps/shared/dev/serial/zynq-uart.c
@@ -144,14 +144,50 @@ static bool zynq_uart_set_attributes(
{
zynq_uart_context *ctx = (zynq_uart_context *) context;
volatile zynq_uart *regs = ctx->regs;
+ int32_t baud;
uint32_t brgr = 0;
uint32_t bauddiv = 0;
uint32_t mode = 0;
int rc;
- rc = zynq_cal_baud_rate(115200, , , regs->mode);
- if (rc != 0)
-return rc;
+ /*
+ * Determine the baud rate
+ */
+ switch (term->c_ospeed) {
+case B0: baud = 0; break;
+case B50: baud = 50; break;
+case B75: baud = 75; break;
+case B110:baud = 110;break;
+case B134:baud = 134;break;
+case B150:baud = 150;break;
+case B200:baud = 200;break;
+case B300:baud = 300;break;
+case B600:baud = 600;break;
+case B1200: baud = 1200; break;
+case B1800: baud = 1800; break;
+case B2400: baud = 2400; break;
+case B4800: baud = 4800; break;
+case B9600: baud = 9600; break;
+case B19200: baud = 19200; break;
+case B38400: baud = 38400; break;
+case B57600: baud = 57600; break;
+case B115200: baud = 115200; break;
+case B230400: baud = 230400; break;
+case B460800: baud = 460800; break;
+case B921600: baud = 921600; break;
+default: baud = -1; break;
+ }
+
+ if (baud < 0) {
+ errno = EINVAL;
+ return -1;
+ }
+
+ if (baud > 0) {
+rc = zynq_cal_baud_rate(baud, , , regs->mode);
+if (rc != 0)
+ return rc;
+ }
/*
* Configure the mode register
--
2.17.1
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[PATCH v4 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi
---
bsps/include/dev/spi/cadence-spi-regs.h | 84 +
bsps/include/dev/spi/cadence-spi.h | 48 +++
bsps/shared/dev/spi/cadence-spi.c | 437
3 files changed, 569 insertions(+)
create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h
create mode 100644 bsps/include/dev/spi/cadence-spi.h
create mode 100644 bsps/shared/dev/spi/cadence-spi.c
diff --git a/bsps/include/dev/spi/cadence-spi-regs.h
b/bsps/include/dev/spi/cadence-spi-regs.h
new file mode 100644
index 00..2e2f04a91b
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ uint32_t irqdisable;
+ uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t txdata;
+ uint32_t rxdata;
+ uint32_t slave_idle_count;
+ uint32_t txthreshold;
+ uint32_t rxthreshold;
+ uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/include/dev/spi/cadence-spi.h
b/bsps/include/dev/spi/cadence-spi.h
new file mode 100644
index 00..6145aa916a
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, German Aerospace Center (DLR)
+ *
+ * Redi
[PATCH v4 0/3] Add cadence-SPI driver
v4: - Use copyright information without UTF-8 characters v3: - Fix wrong changes to spec/build/bsps/arm/xilinx-zynq/obj.yml v2: - Moved source file to bsps/shared/dev/spi - Moved include files to bsps/include/dev/spi - Enabled build in aarch64 BSPs v1: This patchset implements a driver for the cadence-spi device of the Xilinx Zynq-7000 based SoCs using the spidev API. Jan Sommer (3): bsps/xilinx_zynq: Add SPI driver for cadence-spi bsps/xilinx_zynq: Add SPI driver to waf bsps/xilinx_zynq: Add SPI driver to autotools build bsps/headers.am | 5 + bsps/include/dev/spi/cadence-spi-regs.h | 84 bsps/include/dev/spi/cadence-spi.h| 48 ++ bsps/shared/dev/spi/cadence-spi.c | 437 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 + .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 + spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 + spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 + .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 + spec/build/bsps/objdevspizynq.yml | 18 + 10 files changed, 604 insertions(+) create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h create mode 100644 bsps/include/dev/spi/cadence-spi.h create mode 100644 bsps/shared/dev/spi/cadence-spi.c create mode 100644 spec/build/bsps/objdevspizynq.yml -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v4 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build
--- bsps/headers.am| 5 + c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++ c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 +++ 3 files changed, 11 insertions(+) diff --git a/bsps/headers.am b/bsps/headers.am index 1b82382db8..37ce6d6c73 100644 --- a/bsps/headers.am +++ b/bsps/headers.am @@ -39,6 +39,11 @@ include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart-regs.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart.h +include_dev_spidir = $(includedir)/dev/spi +include_dev_spi_HEADERS = +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi-regs.h +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi.h + include_grlibdir = $(includedir)/grlib include_grlib_HEADERS = include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 8804dc40da..11749acc1b 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -71,6 +71,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore. # I2C librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 21db56a0ea..2d8ccf07cd 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -67,6 +67,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/zynq-uart-poll librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/clock/arm-generic-timer.c librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/arm-generic-timer-aarch32.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v4 2/3] bsps/xilinx_zynq: Add SPI driver to waf
---
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 ++
spec/build/bsps/arm/xilinx-zynq/grp.yml| 2 ++
.../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 ++
spec/build/bsps/objdevspizynq.yml | 18 ++
4 files changed, 24 insertions(+)
create mode 100644 spec/build/bsps/objdevspizynq.yml
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index 552723c61c..c952b4f59e 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
@@ -33,6 +33,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../optcachedata
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 74adbd7fa7..0bbee1922c 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -57,6 +57,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: linkcmds
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 51d3268e99..d4e8cbc1ce 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -69,6 +69,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../opto2
- role: build-dependency
diff --git a/spec/build/bsps/objdevspizynq.yml
b/spec/build/bsps/objdevspizynq.yml
new file mode 100644
index 00..b778e756e1
--- /dev/null
+++ b/spec/build/bsps/objdevspizynq.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 German Aerospace Center (DLR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/spi
+ source:
+ - bsps/include/dev/spi/cadence-spi-regs.h
+ - bsps/include/dev/spi/cadence-spi.h
+links: []
+source:
+- bsps/shared/dev/spi/cadence-spi.c
+type: build
--
2.17.1
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http://lists.rtems.org/mailman/listinfo/devel
[PATCH rtems-docs] user/bsps: Mention fixed console baud rate for zynq
--- user/bsps/arm/xilinx-zynq.rst | 14 ++ 1 file changed, 14 insertions(+) diff --git a/user/bsps/arm/xilinx-zynq.rst b/user/bsps/arm/xilinx-zynq.rst index 365c336..dcc0649 100644 --- a/user/bsps/arm/xilinx-zynq.rst +++ b/user/bsps/arm/xilinx-zynq.rst @@ -37,6 +37,20 @@ to return the peripheral clock. Normally this is half the CPU clock. This function is declared ``weak`` so you can override the default behaviour by providing it in your application. +Console +--- + +The console driver for the UARTs will always be set to a baud rate +of 115200 with 8 bit characters, 1 stop bit and no parity bits +during start up. +Previous configurations programmed into the hardware by the Xilinx +tools or a bootloader will be overwritten. + +The settings for parity and stop bits can be changes by the user +application. The baud rate is hard coded to 115200 and can not be +changed. + + Debugging with xilinx_zynq_a9_qemu -- -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 2/3] bsps/xilinx_zynq: Add SPI driver to waf
---
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 ++
spec/build/bsps/arm/xilinx-zynq/grp.yml| 2 ++
.../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 ++
spec/build/bsps/objdevspizynq.yml | 18 ++
4 files changed, 24 insertions(+)
create mode 100644 spec/build/bsps/objdevspizynq.yml
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index 552723c61c..c952b4f59e 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
@@ -33,6 +33,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../optcachedata
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 74adbd7fa7..0bbee1922c 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -57,6 +57,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: linkcmds
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 51d3268e99..d4e8cbc1ce 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -69,6 +69,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../opto2
- role: build-dependency
diff --git a/spec/build/bsps/objdevspizynq.yml
b/spec/build/bsps/objdevspizynq.yml
new file mode 100644
index 00..b778e756e1
--- /dev/null
+++ b/spec/build/bsps/objdevspizynq.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 German Aerospace Center (DLR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/spi
+ source:
+ - bsps/include/dev/spi/cadence-spi-regs.h
+ - bsps/include/dev/spi/cadence-spi.h
+links: []
+source:
+- bsps/shared/dev/spi/cadence-spi.c
+type: build
--
2.17.1
___
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[PATCH v3 0/3] Add cadence-SPI driver
v3: - Fix wrong changes to spec/build/bsps/arm/xilinx-zynq/obj.yml v2: - Moved source file to bsps/shared/dev/spi - Moved include files to bsps/include/dev/spi - Enabled build in aarch64 BSPs v1: This patchset implements a driver for the cadence-spi device of the Xilinx Zynq-7000 based SoCs using the spidev API. Jan Sommer (3): bsps/xilinx_zynq: Add SPI driver for cadence-spi bsps/xilinx_zynq: Add SPI driver to waf bsps/xilinx_zynq: Add SPI driver to autotools build bsps/headers.am | 5 + bsps/include/dev/spi/cadence-spi-regs.h | 84 bsps/include/dev/spi/cadence-spi.h| 48 ++ bsps/shared/dev/spi/cadence-spi.c | 437 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 + .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 + spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 + spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 + .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 + spec/build/bsps/objdevspizynq.yml | 18 + 10 files changed, 604 insertions(+) create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h create mode 100644 bsps/include/dev/spi/cadence-spi.h create mode 100644 bsps/shared/dev/spi/cadence-spi.c create mode 100644 spec/build/bsps/objdevspizynq.yml -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi
---
bsps/include/dev/spi/cadence-spi-regs.h | 84 +
bsps/include/dev/spi/cadence-spi.h | 48 +++
bsps/shared/dev/spi/cadence-spi.c | 437
3 files changed, 569 insertions(+)
create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h
create mode 100644 bsps/include/dev/spi/cadence-spi.h
create mode 100644 bsps/shared/dev/spi/cadence-spi.c
diff --git a/bsps/include/dev/spi/cadence-spi-regs.h
b/bsps/include/dev/spi/cadence-spi-regs.h
new file mode 100644
index 00..2851c88df1
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und Raumfahrt e.
V. (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ uint32_t irqdisable;
+ uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t txdata;
+ uint32_t rxdata;
+ uint32_t slave_idle_count;
+ uint32_t txthreshold;
+ uint32_t rxthreshold;
+ uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/include/dev/spi/cadence-spi.h
b/bsps/include/dev/spi/cadence-spi.h
new file mode 100644
index 00..7d7ecd3885
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für
[PATCH v3 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build
--- bsps/headers.am| 5 + c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++ c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 +++ 3 files changed, 11 insertions(+) diff --git a/bsps/headers.am b/bsps/headers.am index 1b82382db8..37ce6d6c73 100644 --- a/bsps/headers.am +++ b/bsps/headers.am @@ -39,6 +39,11 @@ include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart-regs.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart.h +include_dev_spidir = $(includedir)/dev/spi +include_dev_spi_HEADERS = +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi-regs.h +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi.h + include_grlibdir = $(includedir)/grlib include_grlib_HEADERS = include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 8804dc40da..11749acc1b 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -71,6 +71,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore. # I2C librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 21db56a0ea..2d8ccf07cd 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -67,6 +67,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/zynq-uart-poll librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/clock/arm-generic-timer.c librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/arm-generic-timer-aarch32.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build
--- bsps/headers.am| 5 + c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++ c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 +++ 3 files changed, 11 insertions(+) diff --git a/bsps/headers.am b/bsps/headers.am index 1b82382db8..37ce6d6c73 100644 --- a/bsps/headers.am +++ b/bsps/headers.am @@ -39,6 +39,11 @@ include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart-regs.h include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart.h +include_dev_spidir = $(includedir)/dev/spi +include_dev_spi_HEADERS = +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi-regs.h +include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi.h + include_grlibdir = $(includedir)/grlib include_grlib_HEADERS = include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 8804dc40da..11749acc1b 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -71,6 +71,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore. # I2C librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 21db56a0ea..2d8ccf07cd 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -67,6 +67,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/zynq-uart-poll librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/clock/arm-generic-timer.c librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/arm-generic-timer-aarch32.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 2/3] bsps/xilinx_zynq: Add SPI driver to waf
---
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 ++
spec/build/bsps/arm/xilinx-zynq/grp.yml| 2 ++
spec/build/bsps/arm/xilinx-zynq/obj.yml| 4 ++--
.../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 ++
spec/build/bsps/objdevspizynq.yml | 18 ++
5 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 spec/build/bsps/objdevspizynq.yml
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index 552723c61c..c952b4f59e 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
@@ -33,6 +33,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../optcachedata
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 74adbd7fa7..0bbee1922c 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -57,6 +57,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: linkcmds
- role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml
b/spec/build/bsps/arm/xilinx-zynq/obj.yml
index 6602b20a03..8b7e65ed40 100644
--- a/spec/build/bsps/arm/xilinx-zynq/obj.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml
@@ -14,9 +14,9 @@ install:
- bsps/arm/xilinx-zynq/include/tm27.h
- destination: ${BSP_INCLUDEDIR}/bsp
source:
- - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
- - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
- bsps/arm/xilinx-zynq/include/bsp/i2c.h
+ - bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
+ - bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
- bsps/arm/xilinx-zynq/include/bsp/irq.h
links: []
source:
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 51d3268e99..d4e8cbc1ce 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -69,6 +69,8 @@ links:
uid: ../../objirq
- role: build-dependency
uid: ../../objdevserialzynq
+- role: build-dependency
+ uid: ../../objdevspizynq
- role: build-dependency
uid: ../../opto2
- role: build-dependency
diff --git a/spec/build/bsps/objdevspizynq.yml
b/spec/build/bsps/objdevspizynq.yml
new file mode 100644
index 00..b778e756e1
--- /dev/null
+++ b/spec/build/bsps/objdevspizynq.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 German Aerospace Center (DLR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/spi
+ source:
+ - bsps/include/dev/spi/cadence-spi-regs.h
+ - bsps/include/dev/spi/cadence-spi.h
+links: []
+source:
+- bsps/shared/dev/spi/cadence-spi.c
+type: build
--
2.17.1
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devel mailing list
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http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi
---
bsps/include/dev/spi/cadence-spi-regs.h | 84 +
bsps/include/dev/spi/cadence-spi.h | 48 +++
bsps/shared/dev/spi/cadence-spi.c | 437
3 files changed, 569 insertions(+)
create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h
create mode 100644 bsps/include/dev/spi/cadence-spi.h
create mode 100644 bsps/shared/dev/spi/cadence-spi.c
diff --git a/bsps/include/dev/spi/cadence-spi-regs.h
b/bsps/include/dev/spi/cadence-spi-regs.h
new file mode 100644
index 00..2851c88df1
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und Raumfahrt e.
V. (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ uint32_t irqdisable;
+ uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t txdata;
+ uint32_t rxdata;
+ uint32_t slave_idle_count;
+ uint32_t txthreshold;
+ uint32_t rxthreshold;
+ uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/include/dev/spi/cadence-spi.h
b/bsps/include/dev/spi/cadence-spi.h
new file mode 100644
index 00..7d7ecd3885
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für
[PATCH v2 0/3] bsps/zynq: Add cadence-SPI driver
v2: - Moved source file to bsps/shared/dev/spi - Moved include files to bsps/include/dev/spi - Enabled build in aarch64 BSPs v1: This patchset implements a driver for the cadence-spi device of the Xilinx Zynq-7000 based SoCs using the spidev API. Jan Sommer (3): bsps/xilinx_zynq: Add SPI driver for cadence-spi bsps/xilinx_zynq: Add SPI driver to waf bsps/xilinx_zynq: Add SPI driver to autotools build bsps/headers.am | 5 + bsps/include/dev/spi/cadence-spi-regs.h | 84 bsps/include/dev/spi/cadence-spi.h| 48 ++ bsps/shared/dev/spi/cadence-spi.c | 437 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 + .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 + spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 + spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 + spec/build/bsps/arm/xilinx-zynq/obj.yml | 4 +- .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 2 + spec/build/bsps/objdevspizynq.yml | 18 + 11 files changed, 606 insertions(+), 2 deletions(-) create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h create mode 100644 bsps/include/dev/spi/cadence-spi.h create mode 100644 bsps/shared/dev/spi/cadence-spi.c create mode 100644 spec/build/bsps/objdevspizynq.yml -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi
---
.../include/bsp/cadence-spi-regs.h| 84
.../arm/xilinx-zynq/include/bsp/cadence-spi.h | 48 ++
bsps/arm/xilinx-zynq/spi/cadence-spi.c| 437 ++
3 files changed, 569 insertions(+)
create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
create mode 100644 bsps/arm/xilinx-zynq/spi/cadence-spi.c
diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
new file mode 100644
index 00..2851c88df1
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und Raumfahrt e.
V. (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ uint32_t irqdisable;
+ uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t txdata;
+ uint32_t rxdata;
+ uint32_t slave_idle_count;
+ uint32_t txthreshold;
+ uint32_t rxthreshold;
+ uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
new file mode 100644
index 00..7d7ecd3885
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
@@
[PATCH 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build
--- bsps/arm/xilinx-zynq/headers.am | 2 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++ 2 files changed, 5 insertions(+) diff --git a/bsps/arm/xilinx-zynq/headers.am b/bsps/arm/xilinx-zynq/headers.am index 47738c62be..c70be4 100644 --- a/bsps/arm/xilinx-zynq/headers.am +++ b/bsps/arm/xilinx-zynq/headers.am @@ -10,4 +10,6 @@ include_bsp_HEADERS = include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/irq.h diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 8804dc40da..ffde6cd579 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -71,6 +71,9 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore. # I2C librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +# SPI +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/spi/cadence-spi.c + # Cache librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/3] bsps/xilinx_zynq: Add SPI driver to waf
--- spec/build/bsps/arm/xilinx-zynq/obj.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml b/spec/build/bsps/arm/xilinx-zynq/obj.yml index 6602b20a03..c41ba9af98 100644 --- a/spec/build/bsps/arm/xilinx-zynq/obj.yml +++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml @@ -17,6 +17,8 @@ install: - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h - bsps/arm/xilinx-zynq/include/bsp/i2c.h + - bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h + - bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h - bsps/arm/xilinx-zynq/include/bsp/irq.h links: [] source: @@ -30,6 +32,7 @@ source: - bsps/arm/xilinx-zynq/console/console-init.c - bsps/arm/xilinx-zynq/console/debug-console.c - bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +- bsps/arm/xilinx-zynq/spi/cadence-spi.c - bsps/arm/xilinx-zynq/start/bspreset.c - bsps/arm/xilinx-zynq/start/bspstart.c - bsps/arm/xilinx-zynq/start/bspstarthooks.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 0/3] bsps/zynq: Add cadence-SPI driver
This patchset implements a driver for the cadence-spi device of the Xilinx Zynq-7000 based SoCs using the spidev API. Jan Sommer (3): bsps/xilinx_zynq: Add SPI driver for cadence-spi bsps/xilinx_zynq: Add SPI driver to waf bsps/xilinx_zynq: Add SPI driver to autotools build bsps/arm/xilinx-zynq/headers.am | 2 + .../include/bsp/cadence-spi-regs.h| 84 .../arm/xilinx-zynq/include/bsp/cadence-spi.h | 48 ++ bsps/arm/xilinx-zynq/spi/cadence-spi.c| 437 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 + spec/build/bsps/arm/xilinx-zynq/obj.yml | 3 + 6 files changed, 577 insertions(+) create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h create mode 100644 bsps/arm/xilinx-zynq/spi/cadence-spi.c -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/1] misc: tools: fix mkimage.py script type processing
From: Andre Nahrwold
---
misc/tools/mkimage.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/misc/tools/mkimage.py b/misc/tools/mkimage.py
index fd75f0a..111e224 100755
--- a/misc/tools/mkimage.py
+++ b/misc/tools/mkimage.py
@@ -121,6 +121,16 @@ outputfile.seek(struct.size);
inputcrc = 0;
+if options.type in 'script':
+
+filler_struct = Struct("!II")
+inputblock = filler_struct.pack(inputsize, 0)
+
+inputcrc = binascii.crc32(inputblock, inputcrc)
+outputfile.write(inputblock)
+
+inputsize = inputsize + 8
+
while True:
inputblock = inputfile.read(4096)
if not inputblock: break
--
2.17.1
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[PATCH 0/1] misc: tools: fix mkimage.py script type processing
Here is the patch from Andre also in git send-email format. It would be great if we could integrate it in master and the 5 braches. Best regards, Jan Andre Nahrwold (1): misc: tools: fix mkimage.py script type processing misc/tools/mkimage.py | 10 ++ 1 file changed, 10 insertions(+) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/1] zynq-uart: Fix set_attributes implementation
From: Kinsey Moore
The zynq-uart set_attributes implementation was configured to always
return false which causes spconsole01 to fail. This restores the
disabled implementation which sets the baud rate registers
appropriately and allows spconsole01 to pass. This also expands the
set_attributes functionality to allow setting of the stop bits,
character width, and parity.
---
bsps/arm/include/bsp/zynq-uart.h | 7 +++
bsps/arm/shared/serial/zynq-uart-polled.c | 2 +-
bsps/arm/shared/serial/zynq-uart.c| 56 +--
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/include/bsp/zynq-uart.h b/bsps/arm/include/bsp/zynq-uart.h
index 20c3c9b653..5a6c926bec 100644
--- a/bsps/arm/include/bsp/zynq-uart.h
+++ b/bsps/arm/include/bsp/zynq-uart.h
@@ -71,6 +71,13 @@ void zynq_uart_write_polled(
*/
void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
+int zynq_cal_baud_rate(
+ uint32_t baudrate,
+ uint32_t* brgr,
+ uint32_t* bauddiv,
+ uint32_t modereg
+);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/arm/shared/serial/zynq-uart-polled.c
b/bsps/arm/shared/serial/zynq-uart-polled.c
index e6f478ee07..7fc9590832 100644
--- a/bsps/arm/shared/serial/zynq-uart-polled.c
+++ b/bsps/arm/shared/serial/zynq-uart-polled.c
@@ -40,7 +40,7 @@ uint32_t zynq_uart_input_clock(void)
return ZYNQ_CLOCK_UART;
}
-static int zynq_cal_baud_rate(uint32_t baudrate,
+int zynq_cal_baud_rate(uint32_t baudrate,
uint32_t* brgr,
uint32_t* bauddiv,
uint32_t modereg)
diff --git a/bsps/arm/shared/serial/zynq-uart.c
b/bsps/arm/shared/serial/zynq-uart.c
index fc670441b8..a0dfc0c929 100644
--- a/bsps/arm/shared/serial/zynq-uart.c
+++ b/bsps/arm/shared/serial/zynq-uart.c
@@ -142,25 +142,71 @@ static bool zynq_uart_set_attributes(
const struct termios *term
)
{
-#if 0
- volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+ zynq_uart_context *ctx = (zynq_uart_context *) context;
+ volatile zynq_uart *regs = ctx->regs;
uint32_t brgr = 0;
uint32_t bauddiv = 0;
+ uint32_t mode = 0;
int rc;
rc = zynq_cal_baud_rate(115200, , , regs->mode);
if (rc != 0)
return rc;
+ /*
+ * Configure the mode register
+ */
+ mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL);
+
+ /*
+ * Parity
+ */
+ mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE);
+ if (term->c_cflag & PARENB) {
+if (!(term->c_cflag & PARODD)) {
+ mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD);
+} else {
+ mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN);
+}
+ }
+
+ /*
+ * Character Size
+ */
+ switch (term->c_cflag & CSIZE)
+ {
+ case CS5:
+return false;
+ case CS6:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6);
+break;
+ case CS7:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7);
+break;
+ case CS8:
+ default:
+mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
+break;
+ }
+
+ /*
+ * Stop Bits
+ */
+ if (term->c_cflag & CSTOPB) {
+/* 2 stop bits */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_2);
+ } else {
+/* 1 stop bit */
+mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_1);
+ }
+
regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
+ regs->mode = mode;
regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
return true;
-#else
- return false;
-#endif
}
const rtems_termios_device_handler zynq_uart_handler = {
--
2.17.1
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[PATCH 0/1] bsps/zynq: Fix termios console driver in RTEMS5
Hello, in RTEMS5 the termios console driver does not seem to work correctly when reading from stdin. This has been fixed by the commit from Kinsey Moore in master. Could someone please push this commit to the 5 branch too? I checked locally and with this patch applied for example the termios test application works again as expected. I opened a corresponding ticket for tracking the change to 5.1: https://devel.rtems.org/ticket/4236 Best regards, Jan Kinsey Moore (1): zynq-uart: Fix set_attributes implementation bsps/arm/include/bsp/zynq-uart.h | 7 +++ bsps/arm/shared/serial/zynq-uart-polled.c | 2 +- bsps/arm/shared/serial/zynq-uart.c| 56 +-- 3 files changed, 59 insertions(+), 6 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 1/1] bsp/xilinx_zynq: Enable support for 4kiB MMU pages
- Disabled by default
- Enable using ARM_MMU_USE_SMALL_PAGES option
---
c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 4
spec/build/bsps/arm/optmmusmallpages.yml | 17 +++--
spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 +-
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
index 6599b34292..51e4a121e0 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
@@ -70,11 +70,15 @@
RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M])
RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M])
RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
+RTEMS_BSPOPTS_SET([ARM_MMU_USE_SMALL_PAGES],[*],[0])
+RTEMS_BSPOPTS_HELP([ARM_MMU_USE_SMALL_PAGES],[use MMU with small pages (4KiB)])
+
RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M])
RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region])
ZYNQ_RAM_ORIGIN="0x0010"
ZYNQ_RAM_MMU_LENGTH="16k"
+AS_IF([test "x${ARM_MMU_USE_SMALL_PAGES}" == x1],
[ZYNQ_RAM_MMU_LENGTH="(16k+4M)"])
ZYNQ_RAM_INT_0_ORIGIN="0x"
ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
ZYNQ_RAM_INT_1_ORIGIN="0x"
diff --git a/spec/build/bsps/arm/optmmusmallpages.yml
b/spec/build/bsps/arm/optmmusmallpages.yml
index 5ef991e7d5..e42d1a9e2f 100644
--- a/spec/build/bsps/arm/optmmusmallpages.yml
+++ b/spec/build/bsps/arm/optmmusmallpages.yml
@@ -2,11 +2,24 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- define-condition: null
+- script: |
+if conf.is_defined('ARM_MMU_TRANSLATION_TABLE_SIZE'):
+conf.fatal("ARM_MMU_TRANSLATION_TABLE_SIZE already defined by
conflicting spec.")
+
+tbl_sz = 16*1024
+if value:
+tbl_sz += 4*1024*1024
+
+conf.env["ARM_MMU_TRANSLATION_TABLE_SIZE"] = tbl_sz
+
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default: false
+default-by-variant:
+- value: true
+ variants:
+ - arm/realview_pbx_a9_qemu
description: |
Use MMU with small pages (4KiB)
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 264308e6ad..b7efedc17b 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -42,7 +42,7 @@ links:
- role: build-dependency
uid: optint1ori
- role: build-dependency
- uid: ../optmmusz
+ uid: ../optmmusmallpages
- role: build-dependency
uid: optnocachelen
- role: build-dependency
--
2.17.1
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[PATCH v2 0/1] xilinx_zynq: Enable support for 4kiB MMU pages
Changes in v2: - Disable the option by default for xilinx_zynq (keep enabled for realview) - Created corresponding ticket: https://devel.rtems.org/ticket/4192 Jan Sommer (1): bsp/xilinx_zynq: Enable support for 4kiB MMU pages c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 4 spec/build/bsps/arm/optmmusmallpages.yml | 17 +++-- spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 +- 3 files changed, 20 insertions(+), 3 deletions(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/1] xilinx_zynq: Enable support for 4kiB MMU pages
Hello, Thanks to the suggestions from Sebastian, here my first try to edit things in the new build system. This should enable the support for small MMU tables for the xilinx_zynq based BSPs and enable it by default. Would this also be something to backport to RTEMS5? I could prepare a patch where it is not enabled by default, so that there is no difference for users of 5.1. Ideally, the patch here https://lists.rtems.org/pipermail/devel/2020-November/063461.html is merged beforehand. Best regards, Jan Jan Sommer (1): bsp/xilinx_zynq: Enable support for 4kiB MMU pages c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 4 spec/build/bsps/arm/optmmusmallpages.yml | 10 ++ spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/1] bsp/xilinx_zynq: Enable support for 4kiB MMU pages
---
c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 4
spec/build/bsps/arm/optmmusmallpages.yml | 10 ++
spec/build/bsps/arm/xilinx-zynq/grp.yml | 2 +-
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
index 6599b34292..86e50d1503 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
@@ -70,11 +70,15 @@
RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M])
RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M])
RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
+RTEMS_BSPOPTS_SET([ARM_MMU_USE_SMALL_PAGES],[*],[1])
+RTEMS_BSPOPTS_HELP([ARM_MMU_USE_SMALL_PAGES],[use MMU with small pages (4KiB)])
+
RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M])
RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region])
ZYNQ_RAM_ORIGIN="0x0010"
ZYNQ_RAM_MMU_LENGTH="16k"
+AS_IF([test "x${ARM_MMU_USE_SMALL_PAGES}" == x1],
[ZYNQ_RAM_MMU_LENGTH="(16k+4M)"])
ZYNQ_RAM_INT_0_ORIGIN="0x"
ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
ZYNQ_RAM_INT_1_ORIGIN="0x"
diff --git a/spec/build/bsps/arm/optmmusmallpages.yml
b/spec/build/bsps/arm/optmmusmallpages.yml
index 5ef991e7d5..18d07255c6 100644
--- a/spec/build/bsps/arm/optmmusmallpages.yml
+++ b/spec/build/bsps/arm/optmmusmallpages.yml
@@ -2,6 +2,16 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- define-condition: null
+- script: |
+if conf.is_defined('ARM_MMU_TRANSLATION_TABLE_SIZE'):
+conf.fatal("ARM_MMU_TRANSLATION_TABLE_SIZE already defined by
conflicting spec.")
+
+tbl_sz = 16*1024
+if value:
+tbl_sz += 4*1024*1024
+
+conf.env["ARM_MMU_TRANSLATION_TABLE_SIZE"] = tbl_sz
+
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 264308e6ad..b7efedc17b 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -42,7 +42,7 @@ links:
- role: build-dependency
uid: optint1ori
- role: build-dependency
- uid: ../optmmusz
+ uid: ../optmmusmallpages
- role: build-dependency
uid: optnocachelen
- role: build-dependency
--
2.17.1
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[PATCH v1 1/1] bsps/arm: Fix MMU small pages support
- For small tables only round to the next 4kiB instead of 1MiB --- bsps/arm/include/bsp/arm-cp15-start.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/arm/include/bsp/arm-cp15-start.h b/bsps/arm/include/bsp/arm-cp15-start.h index c4686fbbd4..86c4f8afcb 100644 --- a/bsps/arm/include/bsp/arm-cp15-start.h +++ b/bsps/arm/include/bsp/arm-cp15-start.h @@ -119,7 +119,7 @@ arm_cp15_start_set_translation_table_entries( pt = [ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT]; i = ARM_MMU_SMALL_PAGE_GET_INDEX(config->begin); -iend = ARM_MMU_SMALL_PAGE_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); +iend = ARM_MMU_SMALL_PAGE_GET_INDEX(ARM_MMU_SMALL_PAGE_MVA_ALIGN_UP(config->end)); index_mask = (1U << (32 - ARM_MMU_SMALL_PAGE_BASE_SHIFT)) - 1U; flags = ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE(config->flags); -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/1] bsps/arm: Fix MMU small pages support
Following the discussion on the mailinglist (https://lists.rtems.org/pipermail/users/2020-November/067978.html) here is a patch which rounds the address range of a section only to next 4kiB boundary for the ARM MMU if small pages are enabled. This should close the following tickets: - https://devel.rtems.org/ticket/4184 - https://devel.rtems.org/ticket/4185 Best regards, Jan Jan Sommer (1): bsps/arm: Fix MMU small pages support bsps/arm/include/bsp/arm-cp15-start.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/1] confdefs: Add extern C guards to libpci.h
Hello, We had linking problems with some tests of the testsuite (at least spcxx01) when using libpci. pci_read_config was mangled. Adding those guards fixes the problem. Could also please add the commit to the 5-branch? I will create a corresponding ticket. Best regards, Jan Jan Sommer (1): confdefs: Add extern C guards to libpci.h cpukit/include/rtems/confdefs/libpci.h | 8 1 file changed, 8 insertions(+) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/1] confdefs: Add extern C guards to libpci.h
---
cpukit/include/rtems/confdefs/libpci.h | 8
1 file changed, 8 insertions(+)
diff --git a/cpukit/include/rtems/confdefs/libpci.h
b/cpukit/include/rtems/confdefs/libpci.h
index a68eea1903..05731f5686 100644
--- a/cpukit/include/rtems/confdefs/libpci.h
+++ b/cpukit/include/rtems/confdefs/libpci.h
@@ -21,6 +21,10 @@
#error "Do not include this file directly, use instead"
#endif
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
/*
* Select PCI Configuration Library
*/
@@ -67,4 +71,8 @@
#endif
#endif
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
#endif /* _RTEMS_CONFDEFS_LIBPCI_H */
--
2.17.1
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[PATCH v1] bsps/pc386: Add missing license header
--- bsps/i386/pc386/start/bspsmp.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/bsps/i386/pc386/start/bspsmp.c b/bsps/i386/pc386/start/bspsmp.c index 026f86916fd..2e09b36a8a9 100644 --- a/bsps/i386/pc386/start/bspsmp.c +++ b/bsps/i386/pc386/start/bspsmp.c @@ -1,3 +1,29 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und Raumfahrt e. V. (DLR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ #include -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/1] bsp/xilinx-zynq: Flush TX-Buffer before initializing uart
Closes #4055 Closes #4056 --- bsps/arm/shared/serial/zynq-uart-polled.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bsps/arm/shared/serial/zynq-uart-polled.c b/bsps/arm/shared/serial/zynq-uart-polled.c index 4e0ca46aca..e6f478ee07 100644 --- a/bsps/arm/shared/serial/zynq-uart-polled.c +++ b/bsps/arm/shared/serial/zynq-uart-polled.c @@ -122,6 +122,8 @@ void zynq_uart_initialize(rtems_termios_device_context *base) uint32_t brgr = 0x3e; uint32_t bauddiv = 0x6; + zynq_uart_reset_tx_flush(ctx); + zynq_cal_baud_rate(ZYNQ_UART_DEFAULT_BAUD, , , regs->mode); regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN); -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/1] bsp/xilinx-zynq: Flush TX-Buffer before initializing uart
We experienced that u-boot (at least from Xilinx repositories) does not wait until all its output has left the TX Buffer of the stdout uart, before handing over to the RTEMS application This causes some garbage output at the begin of the RTEMS application in some cases and corrupts the test begin marker prohibiting rtems-test to recognize the test correctly. See also https://lists.rtems.org/pipermail/users/2020-August/067783.html This patch waits until the TX buffer of the uart is flushed before working with it. The corresponding tickets for integration in master and 5 branches are https://devel.rtems.org/ticket/4055 and https://devel.rtems.org/ticket/4056 Best regards, Jan Jan Sommer (1): bsp/xilinx-zynq: Flush TX-Buffer before initializing uart bsps/arm/shared/serial/zynq-uart-polled.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 3/6] i386: Add missing files to build system
- Update FreeBSD files in libbsd.py to required by i386 based BSPs - Add missing files e1000 network driver (iflib*) --- libbsd.py | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/libbsd.py b/libbsd.py index e02226f3..08931401 100644 --- a/libbsd.py +++ b/libbsd.py @@ -1506,10 +1506,14 @@ class dev_net(builder.Module): 'sys/net/if_types.h', 'sys/net/if_var.h', 'sys/net/vnet.h', +'sys/net/mp_ring.h', +'sys/net/iflib_private.h', ] ) self.addKernelSpaceSourceFiles( [ +'sys/net/iflib.c', +'sys/net/mp_ring.c', 'sys/arm/ti/cpsw/if_cpsw.c', 'sys/dev/ffec/if_ffec.c', 'sys/dev/mii/mii.c', @@ -1562,12 +1566,13 @@ class dev_nic(builder.Module): self.addCPUDependentFreeBSDHeaderFiles( [ 'sys/arm/include/cpufunc.h', -'sys/i386/include/specialreg.h', 'sys/i386/include/md_var.h', 'sys/i386/include/intr_machdep.h', 'sys/x86/include/intr_machdep.h', -'sys/x86/include/metadata.h', 'sys/i386/include/cpufunc.h', +'sys/x86/include/intr_machdep.h', +'sys/x86/include/specialreg.h', +'sys/x86/include/x86_var.h', 'sys/mips/include/cpufunc.h', 'sys/mips/include/cpuregs.h', 'sys/powerpc/include/cpufunc.h', @@ -2753,7 +2758,6 @@ class pci(builder.Module): self.addCPUDependentFreeBSDHeaderFiles( [ 'sys/i386/include/_bus.h', -'sys/i386/include/bus.h', 'sys/x86/include/legacyvar.h', 'sys/x86/include/bus.h', 'sys/x86/include/pci_cfgreg.h', -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 6/6] i386: Delete old machine dependent files
- The files in the i386 directory have been moved to common x86 directories by
FreeBSD:
- freebsd/sys/i386/include/machine/bus.h
- freebsd/sys/x86/include/machine/legacyvar.h
- freebsd/sys/x86/include/machine/specialreg.h
- Add header files in rtemsbsd directory to direct compiler to new files
---
freebsd/sys/i386/include/machine/bus.h| 6 -
freebsd/sys/i386/include/machine/legacyvar.h | 63
freebsd/sys/i386/include/machine/specialreg.h | 6 -
rtemsbsd/include/x86/x86_var.h| 146 +-
4 files changed, 1 insertion(+), 220 deletions(-)
delete mode 100644 freebsd/sys/i386/include/machine/bus.h
delete mode 100644 freebsd/sys/i386/include/machine/legacyvar.h
delete mode 100644 freebsd/sys/i386/include/machine/specialreg.h
diff --git a/freebsd/sys/i386/include/machine/bus.h
b/freebsd/sys/i386/include/machine/bus.h
deleted file mode 100644
index f1af2cf6..
--- a/freebsd/sys/i386/include/machine/bus.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*-
- * This file is in the public domain.
- */
-/* $FreeBSD$ */
-
-#include
diff --git a/freebsd/sys/i386/include/machine/legacyvar.h
b/freebsd/sys/i386/include/machine/legacyvar.h
deleted file mode 100644
index 14dd9e03..
--- a/freebsd/sys/i386/include/machine/legacyvar.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*-
- * Copyright (c) 2000 Peter Wemm
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _MACHINE_LEGACYVAR_H_
-#define_MACHINE_LEGACYVAR_H_
-
-enum legacy_device_ivars {
- LEGACY_IVAR_PCIDOMAIN,
- LEGACY_IVAR_PCIBUS,
- LEGACY_IVAR_PCISLOT,
- LEGACY_IVAR_PCIFUNC
-};
-
-#define LEGACY_ACCESSOR(var, ivar, type) \
-__BUS_ACCESSOR(legacy, var, LEGACY, ivar, type)
-
-LEGACY_ACCESSOR(pcidomain, PCIDOMAIN, uint32_t)
-LEGACY_ACCESSOR(pcibus,PCIBUS, uint32_t)
-LEGACY_ACCESSOR(pcislot, PCISLOT,int)
-LEGACY_ACCESSOR(pcifunc, PCIFUNC,int)
-
-#undef LEGACY_ACCESSOR
-
-intlegacy_pcib_maxslots(device_t dev);
-uint32_t legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int
func,
-u_int reg, int bytes);
-intlegacy_pcib_read_ivar(device_t dev, device_t child, int which,
-uintptr_t *result);
-void legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int
func,
-u_int reg, u_int32_t data, int bytes);
-intlegacy_pcib_write_ivar(device_t dev, device_t child, int which,
-uintptr_t value);
-struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child,
-int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
-intlegacy_pcib_map_msi(device_t pcib, device_t dev, int irq,
-uint64_t *addr, uint32_t *data);
-
-#endif /* !_MACHINE_LEGACYVAR_H_ */
diff --git a/freebsd/sys/i386/include/machine/specialreg.h
b/freebsd/sys/i386/include/machine/specialreg.h
deleted file mode 100644
index aace4bfd..
--- a/freebsd/sys/i386/include/machine/specialreg.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*-
- * This file is in the public domain.
- */
-/* $FreeBSD$ */
-
-#include
diff --git a/rtemsbsd/include/x86/x86_var.h b/rtemsbsd/include/x86/x86_var.h
index 2028d739..5819205a 100644
--- a/rtemsbsd/include/x86/x86_var.h
+++ b/rtemsbsd/include/x86/x86_var.h
@@ -1,145 +1 @@
-/*-
- * Copyright (c) 1995 Bruce D. Evans.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and
[PATCH v1 5/6] iflib.c: Deactivate use of ifc_cpus
- cpusets and SMP are currently not supported in libbsd for RTEMS
- Disable the ifc_cpus context variable and replace its usage,
essentially hard-coding for cpu 0
---
freebsd/sys/dev/e1000/if_em.c | 6 ++
freebsd/sys/net/iflib.c | 22 ++
2 files changed, 28 insertions(+)
diff --git a/freebsd/sys/dev/e1000/if_em.c b/freebsd/sys/dev/e1000/if_em.c
index 32eb4afe..4fc6e7b6 100644
--- a/freebsd/sys/dev/e1000/if_em.c
+++ b/freebsd/sys/dev/e1000/if_em.c
@@ -1837,8 +1837,14 @@ em_if_update_admin_status(if_ctx_t ctx)
if (adapter->hw.mac.type < em_mac_min)
lem_smartspeed(adapter);
+#ifdef __rtems__
+ else if (hw->mac.type == e1000_82574 &&
+ adapter->intr_type == IFLIB_INTR_MSIX)
+ E1000_WRITE_REG(>hw, E1000_IMS, EM_MSIX_LINK |
E1000_IMS_LSC);
+#else /* __rtems__ */
E1000_WRITE_REG(>hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
+#endif /* __rtems__ */
}
static void
diff --git a/freebsd/sys/net/iflib.c b/freebsd/sys/net/iflib.c
index 7183e1e5..733172dc 100644
--- a/freebsd/sys/net/iflib.c
+++ b/freebsd/sys/net/iflib.c
@@ -159,7 +159,9 @@ struct iflib_ctx {
device_t ifc_dev;
if_t ifc_ifp;
+#ifndef __rtems__
cpuset_t ifc_cpus;
+#endif /* __rtems__ */
if_shared_ctx_t ifc_sctx;
struct if_softc_ctx ifc_softc_ctx;
@@ -4498,6 +4500,7 @@ get_ctx_core_offset(if_ctx_t ctx)
qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
mtx_lock(_offset_mtx);
+#ifndef __rtems__
SLIST_FOREACH(op, _offsets, entries) {
if (CPU_CMP(>ifc_cpus, >set) == 0) {
ret = op->offset;
@@ -4507,6 +4510,7 @@ get_ctx_core_offset(if_ctx_t ctx)
break;
}
}
+#endif /* __rtems__ */
if (ret == CORE_OFFSET_UNSPECIFIED) {
ret = 0;
op = malloc(sizeof(struct cpu_offset), M_IFLIB,
@@ -4517,7 +4521,9 @@ get_ctx_core_offset(if_ctx_t ctx)
} else {
op->offset = qc;
op->refcount = 1;
+#ifndef __rtems__
CPU_COPY(>ifc_cpus, >set);
+#endif /* __rtems__ */
SLIST_INSERT_HEAD(_offsets, op, entries);
}
}
@@ -4533,7 +4539,11 @@ unref_ctx_core_offset(if_ctx_t ctx)
mtx_lock(_offset_mtx);
SLIST_FOREACH_SAFE(op, _offsets, entries, top) {
+#ifndef __rtems__
if (CPU_CMP(>ifc_cpus, >set) == 0) {
+#else /* __rtems__ */
+ {
+#endif /* __rtems__ */
MPASS(op->refcount > 0);
op->refcount--;
if (op->refcount == 0) {
@@ -4647,12 +4657,14 @@ iflib_device_register(device_t dev, void *sc,
if_shared_ctx_t sctx, if_ctx_t *ct
taskqgroup_attach(qgroup_if_config_tqg, >ifc_admin_task, ctx,
NULL, NULL, "admin");
+#ifndef __rtems__
/* Set up cpu set. If it fails, use the set of all CPUs. */
if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), >ifc_cpus)
!= 0) {
device_printf(dev, "Unable to fetch CPU list\n");
CPU_COPY(_cpus, >ifc_cpus);
}
MPASS(CPU_COUNT(>ifc_cpus) > 0);
+#endif /* __rtems__ */
/*
** Now set up MSI or MSI-X, should return us the number of supported
@@ -5484,7 +5496,9 @@ iflib_queues_alloc(if_ctx_t ctx)
txq->ift_br_offset = 0;
}
/* XXX fix this */
+#ifndef __rtems__
txq->ift_timer.c_cpu = cpu;
+#endif /* __rtems__ */
if (iflib_txsd_alloc(txq)) {
device_printf(dev, "Critical Failure setting up TX
buffers\n");
@@ -6291,11 +6305,19 @@ iflib_msix_init(if_ctx_t ctx)
#else
queues = queuemsgs;
#endif
+#ifndef __rtems__
queues = imin(CPU_COUNT(>ifc_cpus), queues);
+#else /* __rtems__ */
+ queues = imin(1, queues);
+#endif /* __rtems__ */
if (bootverbose)
device_printf(dev,
"intr CPUs: %d queue msgs: %d admincnt: %d\n",
+#ifndef __rtems__
CPU_COUNT(>ifc_cpus), queuemsgs, admincnt);
+#else /* __rtems__ */
+ 1, queuemsgs, admincnt);
+#endif /* __rtems__ */
#ifdef RSS
/* If we're doing RSS, clamp at the number of RSS buckets */
if (queues > rss_getnumbuckets())
--
2.17.1
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[PATCH v1 0/6] [libbsd] Fix e1000 driver for i386 in master and 5
Hello, I finally got around to port the e1000 driver fixes which are already present in the 5-freebsd-12 branch of rtems-libbsd also for the master (and 5) branch. I created two corresponding tickets for it: https://devel.rtems.org/ticket/4052 and https://devel.rtems.org/ticket/4053. Could someone please check and push them? Best regards, Jan Jan Sommer (6): e1000: Add missing files waf: Add path-mappings feature i386: Add missing files to build system Callout: Redefine callout_reset_on for rtems iflib.c: Deactivate use of ifc_cpus i386: Delete old machine dependent files freebsd/sys/dev/e1000/if_em.c |6 + freebsd/sys/i386/include/machine/bus.h|6 - freebsd/sys/i386/include/machine/legacyvar.h | 63 - freebsd/sys/i386/include/machine/specialreg.h |6 - freebsd/sys/net/iflib.c | 6827 + freebsd/sys/net/iflib_private.h | 70 + freebsd/sys/net/mp_ring.c | 554 ++ freebsd/sys/net/mp_ring.h | 75 + freebsd/sys/sys/callout.h |6 + freebsd/sys/x86/include/machine/specialreg.h | 1143 +++ freebsd/sys/x86/include/machine/x86_var.h | 145 + libbsd.py | 18 +- rtemsbsd/include/x86/x86_var.h| 146 +- waf_libbsd.py | 13 +- 14 files changed, 8853 insertions(+), 225 deletions(-) delete mode 100644 freebsd/sys/i386/include/machine/bus.h delete mode 100644 freebsd/sys/i386/include/machine/legacyvar.h delete mode 100644 freebsd/sys/i386/include/machine/specialreg.h create mode 100644 freebsd/sys/net/iflib.c create mode 100644 freebsd/sys/net/iflib_private.h create mode 100644 freebsd/sys/net/mp_ring.c create mode 100644 freebsd/sys/net/mp_ring.h create mode 100644 freebsd/sys/x86/include/machine/specialreg.h create mode 100644 freebsd/sys/x86/include/machine/x86_var.h -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 4/6] Callout: Redefine callout_reset_on for rtems
- callout_reset_on takes a cpu which is ignored by the subsequent call to callout_reset_sbt_on in RTEMS. - The macro is redefined to discard the cpu argument directly which enables uses of it with cpu-dependent variables (disabled in RETMS) without further changes, e.g. in iflib.c. --- freebsd/sys/sys/callout.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/freebsd/sys/sys/callout.h b/freebsd/sys/sys/callout.h index e5e5df85..d7b9965a 100644 --- a/freebsd/sys/sys/callout.h +++ b/freebsd/sys/sys/callout.h @@ -112,9 +112,15 @@ intcallout_reset_sbt_on(struct callout *, sbintime_t, sbintime_t, #definecallout_reset_sbt_curcpu(c, sbt, pr, fn, arg, flags) \ callout_reset_sbt_on((c), (sbt), (pr), (fn), (arg), PCPU_GET(cpuid),\ (flags)) +#ifndef __rtems__ #definecallout_reset_on(c, to_ticks, fn, arg, cpu) \ callout_reset_sbt_on((c), tick_sbt * (to_ticks), 0, (fn), (arg), \ (cpu), C_HARDCLOCK) +#else /* __rtems__ */ +#definecallout_reset_on(c, to_ticks, fn, arg, cpu) \ +callout_reset_sbt_on((c), tick_sbt * (to_ticks), 0, (fn), (arg), \ +-1, C_HARDCLOCK) +#endif /* __rtems__ */ #definecallout_reset(c, on_tick, fn, arg) \ callout_reset_on((c), (on_tick), (fn), (arg), -1) #definecallout_reset_curcpu(c, on_tick, fn, arg) \ -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 2/6] waf: Add path-mappings feature
- path-mappings allow to fix autogenerated include paths for some corner
cases of target platforms without the need to change the build system
- Currently used for i386 based bsps
---
libbsd.py | 8
waf_libbsd.py | 13 +++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/libbsd.py b/libbsd.py
index 511de7af..e02226f3 100644
--- a/libbsd.py
+++ b/libbsd.py
@@ -90,6 +90,14 @@ _defaults = {
'cpu-include-paths': ['rtemsbsd/@CPU@/include',
'freebsd/sys/@CPU@/include'],
+#
+# Map paths based on RTEMS naming to FreeBSD naming.
+#
+'path-mappings': [ # (source, targets)
+# i386
+('freebsd/sys/i386/include', ['freebsd/sys/x86/include',
'freebsd/sys/i386/include']),
+],
+
# The path where headers will be copied during build.
'build-include-path': ['build-include'],
diff --git a/waf_libbsd.py b/waf_libbsd.py
index 9ac5bf35..14f2ae78 100644
--- a/waf_libbsd.py
+++ b/waf_libbsd.py
@@ -210,8 +210,6 @@ class Builder(builder.ModuleManager):
buildinclude = 'build-include'
if 'cpu-include-paths' in config:
cpu = bld.get_env()['RTEMS_ARCH']
-if cpu == "i386":
-includes += ['freebsd/sys/x86/include']
for i in config['cpu-include-paths']:
includes += [i.replace('@CPU@', cpu)]
if 'include-paths' in config:
@@ -222,6 +220,17 @@ class Builder(builder.ModuleManager):
buildinclude = buildinclude[0]
includes += [buildinclude]
+#
+# Path mappings
+#
+if 'path-mappings' in config:
+for source, target in config['path-mappings']:
+if source in includes:
+target = [target] if isinstance(target, str) else target
+i = includes.index(source)
+includes.remove(source)
+includes[i:i] = target
+
#
# Collect the libbsd uses
#
--
2.17.1
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[PATCH v1 1/1] i386: Fix possible race condition on first context restore
Make sure that the esp is restored before the eflags register. When the init task is initially restored, system interrupts are activated when the eflags register is loaded. If the esp register still points to an address in the interrupt stack area (from early system initlization) the ISR might overwrite its own stack. Closes #4030 Closes #4031 --- cpukit/score/cpu/i386/cpu_asm.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpukit/score/cpu/i386/cpu_asm.S b/cpukit/score/cpu/i386/cpu_asm.S index 6031f6914e..23360959f5 100644 --- a/cpukit/score/cpu/i386/cpu_asm.S +++ b/cpukit/score/cpu/i386/cpu_asm.S @@ -83,9 +83,9 @@ SYM (_CPU_Context_switch): .L_restore: movl I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE(eax),ecx movl ecx,PER_CPU_ISR_DISPATCH_DISABLE(edx) +movl REG_ESP(eax),esp /* restore stack pointer */ pushl REG_EFLAGS(eax) /* push eflags */ popf /* restore eflags */ -movl REG_ESP(eax),esp /* restore stack pointer */ movl REG_EBP(eax),ebp /* restore base pointer */ movl REG_EBX(eax),ebx /* restore ebx */ movl REG_ESI(eax),esi /* restore source register */ -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/1] i386: Fix possible race condition on first context restore
Ran into this problem sometimes when testing examples of rtems-libbsd, but it should be general. I opened tickets https://devel.rtems.org/ticket/4030 and https://devel.rtems.org/ticket/4031 correspondintly. Cheers, Jan Jan Sommer (1): i386: Fix possible race condition on first context restore cpukit/score/cpu/i386/cpu_asm.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/1] bsps/pc386: Fix IPI for non-consecutive Apic IDs
Hi,
I had some time for more hardware testing of the SMP functionality on a
PC.
It turns out I missed a few places where the APICID <-> cpuid needed to be
translated.
This only occurs if the APIC Ids of different cores are not numbered
consecutively, which qemu does.
With this patch I can now run 52 examples on an Intel Atom with 4 cores.
The patch should apply to master and the 5 branch.
Did I understand it correctly, that for integrating the patch in the
RTEMS5 release, I need to first create a ticketr?
Best regards,
Jan
Jan Sommer (1):
bsps/pc386: Fix IPI for non-consecutive APICIDs
bsps/i386/pc386/start/smp-imps.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
--
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[PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs
- properly use the cpu <-> apic maps for IPIs
---
bsps/i386/pc386/start/smp-imps.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index 0985b8f08f..763ac0afc7 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -226,9 +226,11 @@ get_checksum(unsigned start, int length)
int
send_ipi(unsigned int dst, unsigned int v)
{
- int to, send_status;
+ int to, send_status, apicid;
- IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24));
+ apicid = imps_cpu_apic_map[dst];
+
+ IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (apicid << 24));
IMPS_LAPIC_WRITE(LAPIC_ICR, v);
/* Wait for send to finish */
@@ -251,9 +253,11 @@ static int
boot_cpu(imps_processor *proc)
{
int apicid = proc->apic_id, success = 1;
+ int cpuid;
unsigned bootaddr;
unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR);
+ cpuid = imps_apic_cpu_map[apicid];
/*
* Copy boot code for secondary CPUs here. Find it in between
* "patch_code_start" and "patch_code_end" symbols. The other CPUs
@@ -276,7 +280,7 @@ boot_cpu(imps_processor *proc)
/* Pass start function, stack region and gdtdescr to AP
* see startAP.S for location */
reset[1] = (uint32_t)secondary_cpu_initialize;
- reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)->interrupt_stack_high;
+ reset[2] = (uint32_t)_Per_CPU_Get_by_index(cpuid)->interrupt_stack_high;
memcpy(
(char*) [3],
,
@@ -295,13 +299,13 @@ boot_cpu(imps_processor *proc)
/* assert INIT IPI */
send_ipi(
-apicid,
+cpuid,
LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT
);
UDELAY(1);
/* de-assert INIT IPI */
- send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT);
+ send_ipi(cpuid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT);
UDELAY(1);
@@ -312,7 +316,7 @@ boot_cpu(imps_processor *proc)
if (proc->apic_ver >= APIC_VER_NEW) {
int i;
for (i = 1; i <= 2; i++) {
- send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF));
+ send_ipi(cpuid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF));
UDELAY(1000);
}
}
--
2.17.1
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[PATCH v1 8/9] smpsignal01: Change state before sending the signal
The signal handler of the consumer might start executing
before rtems_signal_send of the producer returns.
Therefore change the state to SIG_1_SENT before sending the signal.
---
testsuites/smptests/smpsignal01/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/testsuites/smptests/smpsignal01/init.c
b/testsuites/smptests/smpsignal01/init.c
index 36a66bea9b..025e84c6a2 100644
--- a/testsuites/smptests/smpsignal01/init.c
+++ b/testsuites/smptests/smpsignal01/init.c
@@ -81,10 +81,10 @@ static void signal_send(test_context *ctx, test_state
new_state)
{
rtems_status_code sc;
+ change_state(ctx, new_state);
sc = rtems_signal_send(ctx->consumer, TEST_SIGNAL);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
- change_state(ctx, new_state);
}
static void check_consumer_processor(const test_context *ctx)
--
2.12.3
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[PATCH v1 3/9] bsp/pc386: Update GDT to work for SMP
Create a GS segment in the GDT for each processor for storing TLS.
This makes the GDT in startAP.S obsolete as all processors now share the
same GDT, which is passed to each AP at startup.
The correct segment for each processor is calculated in cpu_asm.S.
Update #3335
---
bsps/i386/pc386/include/bsp/tblsizes.h| 8 ++-
bsps/i386/pc386/start/getcpuid.c | 2 +-
bsps/i386/pc386/start/ldsegs.S| 4 +++-
bsps/i386/pc386/start/smp-imps.c | 15
bsps/i386/pc386/start/startAP.S | 39 +--
cpukit/score/cpu/i386/cpu_asm.S | 11 +
cpukit/score/cpu/i386/include/rtems/asm.h | 26 +
7 files changed, 59 insertions(+), 46 deletions(-)
diff --git a/bsps/i386/pc386/include/bsp/tblsizes.h
b/bsps/i386/pc386/include/bsp/tblsizes.h
index 13429dc85f..978cde2b3e 100644
--- a/bsps/i386/pc386/include/bsp/tblsizes.h
+++ b/bsps/i386/pc386/include/bsp/tblsizes.h
@@ -20,5 +20,11 @@
#include
#define IDT_SIZE (256)
-#define NUM_SYSTEM_GDT_DESCRIPTORS 4
+/* We have 3 fixed segments (NULL, text, data) + a GS segment for TLS */
+#ifdef RTEMS_SMP
+/* Need one GS segment for each processor (x86 can have up to 256 processors)
*/
+#define NUM_SYSTEM_GDT_DESCRIPTORS 3+256
+#else
+#define NUM_SYSTEM_GDT_DESCRIPTORS 3+1
+#endif
#define GDT_SIZE (NUM_SYSTEM_GDT_DESCRIPTORS + NUM_APP_DRV_GDT_DESCRIPTORS)
diff --git a/bsps/i386/pc386/start/getcpuid.c b/bsps/i386/pc386/start/getcpuid.c
index c5284d0069..4918a2a970 100644
--- a/bsps/i386/pc386/start/getcpuid.c
+++ b/bsps/i386/pc386/start/getcpuid.c
@@ -17,6 +17,6 @@ unsigned imps_lapic_addr = ((unsigned)(_dummy)) -
LAPIC_ID;
uint32_t _CPU_SMP_Get_current_processor( void )
{
- return APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
+ return imps_apic_cpu_map[APIC_ID(IMPS_LAPIC_READ(LAPIC_ID))];
}
diff --git a/bsps/i386/pc386/start/ldsegs.S b/bsps/i386/pc386/start/ldsegs.S
index b56bf836f0..9ed66ef1a3 100644
--- a/bsps/i386/pc386/start/ldsegs.S
+++ b/bsps/i386/pc386/start/ldsegs.S
@@ -191,9 +191,11 @@ SYM (_Global_descriptor_table):
.word 0x, 0
.byte 0, 0x92, 0xcf, 0
- /* gs segment */
+ /* gs segment(s) */
+ .rept (NUM_SYSTEM_GDT_DESCRIPTORS - 3)
.word 0x, 0
.byte 0, 0x92, 0xcf, 0
+ .endr
/* allocated space for user segments */
.rept (GDT_SIZE - NUM_SYSTEM_GDT_DESCRIPTORS)
diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index 58d9178f90..6480c0d25e 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -83,6 +83,7 @@
#include
extern void _pc386_delay(void);
+extern uint32_t* gdtdesc;
/* #define KERNEL_PRINT(_format) printk(_format) */
@@ -258,10 +259,10 @@ boot_cpu(imps_processor *proc)
* under the 1MB boundary.
*/
- uint32_t *reset;
+ volatile uint32_t *reset;
bootaddr = (512-64)*1024;
- reset= (uint32_t *)bootaddr;
+ reset= (volatile uint32_t *)bootaddr;
memcpy(
(char *) bootaddr,
@@ -269,9 +270,14 @@ boot_cpu(imps_processor *proc)
(size_t)_binary_appstart_bin_size
);
+ /* Pass start function, stack region and gdtdescr to AP
+ * see startAP.S for location */
reset[1] = (uint32_t)secondary_cpu_initialize;
reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)->interrupt_stack_high;
-
+ memcpy(
+ (char*) [3],
+ ,
+ 6);
/*
* Generic CPU startup sequence starts here.
*/
@@ -325,8 +331,6 @@ boot_cpu(imps_processor *proc)
CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0);
*((volatile unsigned *) bios_reset_vector) = 0;
- printk("\n");
-
return success;
}
@@ -359,6 +363,7 @@ add_processor(imps_processor *proc)
/* AP booted successfully, increase number of available cores */
imps_num_cpus++;
+printk("#%d Application Processor (AP)\n", imps_apic_cpu_map[apicid]);
}
}
diff --git a/bsps/i386/pc386/start/startAP.S b/bsps/i386/pc386/start/startAP.S
index 0f81c03144..024c1f70fb 100644
--- a/bsps/i386/pc386/start/startAP.S
+++ b/bsps/i386/pc386/start/startAP.S
@@ -73,9 +73,12 @@ app_processor_start:
*/
.align 4
app_cpu_start:
- .long 0
+.long 0
app_cpu_stack:
- .long 0
+.long 0
+app_gdt_descr:
+.word 0 /* GDT size */
+.long 0 /* GDT location */
setup_processor:
movw%cs, %ax # Initialize the rest of
@@ -87,7 +90,7 @@ setup_processor:
| Bare PC machines boot in real mode! We have to turn protected mode
on.
+-*/
-lgdtgdtptr - app_processor_start # load Global Descriptor Table
+lgdtapp_gdt_descr - app_processor_start # load Global Descriptor
Table
movl%cr0, %eax
orl $CR0_PE, %eax
@@ -113,33 +116,3 @@ start_32bit:
movl$0, app_cpu_stack
/* Switch to the higher level
[PATCH v1 6/9] bsps/pc386: Fix Clock_isr for SMP
- Do not forward Clock_isr through Clock_driver_support_at_tick as this will cause every processor to send IPIs with Clock_isr therby creating an infinie loop - Instead the processor handling the clock interrupt causes all other processors to call rtems_timecounter_tick to update their tick count --- bsps/i386/pc386/clock/ckinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/i386/pc386/clock/ckinit.c b/bsps/i386/pc386/clock/ckinit.c index d6e4b4..09afe73cde 100644 --- a/bsps/i386/pc386/clock/ckinit.c +++ b/bsps/i386/pc386/clock/ckinit.c @@ -73,7 +73,7 @@ extern volatile uint32_t Clock_driver_ticks; Processor_mask targets; \ _Processor_mask_Assign(, _SMP_Get_online_processors()); \ _Processor_mask_Clear(, _SMP_Get_current_processor()); \ -_SMP_Multicast_action(, Clock_isr, NULL); \ +_SMP_Multicast_action(, rtems_timecounter_tick, NULL); \ } while (0) #endif -- 2.12.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 4/9] bsp/pc386: Update context switch and restore
Uses similar flow in cpu_asm.S for i386 as for arm.
---
cpukit/score/cpu/i386/cpu_asm.S | 63 +++--
cpukit/score/cpu/i386/include/rtems/score/cpu.h | 4 +-
2 files changed, 51 insertions(+), 16 deletions(-)
diff --git a/cpukit/score/cpu/i386/cpu_asm.S b/cpukit/score/cpu/i386/cpu_asm.S
index 9e1e848bbd..6031f6914e 100644
--- a/cpukit/score/cpu/i386/cpu_asm.S
+++ b/cpukit/score/cpu/i386/cpu_asm.S
@@ -51,6 +51,8 @@
SYM (_CPU_Context_switch):
movl RUNCONTEXT_ARG(esp),eax /* eax = running threads context */
+GET_SELF_CPU_CONTROL edx /* edx has address for per_CPU
information */
+movl PER_CPU_ISR_DISPATCH_DISABLE(edx),ecx
pushf /* push eflags */
popl REG_EFLAGS(eax) /* save eflags */
movl esp,REG_ESP(eax) /* save stack pointer */
@@ -58,26 +60,29 @@ SYM (_CPU_Context_switch):
movl ebx,REG_EBX(eax) /* save ebx */
movl esi,REG_ESI(eax) /* save source register */
movl edi,REG_EDI(eax) /* save destination register */
+movl ecx, I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE(eax)
-#ifdef RTEMS_SMP
-/* The executing context no longer executes on this processor */
-movb $0, I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax)
-#endif
-
+movl eax,ecx /* ecx = running threads context */
movl HEIRCONTEXT_ARG(esp),eax /* eax = heir threads context */
#ifdef RTEMS_SMP
-/* Wait for heir context to stop execution */
-1:
-movb I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax), bl
-testb bl, bl
-jne 1b
-
-/* The heir context executes now on this processor */
-movb $1, I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax)
+ /*
+ * The executing thread no longer executes on this processor. Switch
+ * the stack to the temporary interrupt stack of this processor. Mark
+ * the context of the executing thread as not executing.
+ */
+leal PER_CPU_INTERRUPT_FRAME_AREA +
CPU_INTERRUPT_FRAME_SIZE(edx),esp
+movb $0, I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(ecx)
+
+.L_check_is_executing:
+lock bts $0,I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax) /*
Indicator in carry flag */
+jc.L_get_potential_new_heir
#endif
-restore:
+/* Start restoring context */
+.L_restore:
+movl I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE(eax),ecx
+movl ecx,PER_CPU_ISR_DISPATCH_DISABLE(edx)
pushl REG_EFLAGS(eax) /* push eflags */
popf /* restore eflags */
movl REG_ESP(eax),esp /* restore stack pointer */
@@ -110,7 +115,35 @@ restore:
SYM (_CPU_Context_restore):
movl NEWCONTEXT_ARG(esp),eax /* eax = running threads context */
-jmp restore
+GET_SELF_CPU_CONTROL edx /* edx has address for per_CPU
information */
+jmp .L_restore
+
+#ifdef RTEMS_SMP
+
+.L_get_potential_new_heir:
+
+/* We may have a new heir */
+
+/* Read the executing and heir */
+movlPER_CPU_OFFSET_EXECUTING(edx),ebx
+movlPER_CPU_OFFSET_HEIR(edx),esi
+
+/*
+ * Update the executing only if necessary to avoid cache line
+ * monopolization.
+ */
+cmp esi,ebx
+je .L_check_is_executing
+
+/* Calculate the heir context pointer */
+addlesi,eax
+sublebx,eax
+
+/* Update the executing */
+movlesi,PER_CPU_OFFSET_EXECUTING(edx)
+
+jmp .L_check_is_executing
+#endif
/*void _CPU_Context_save_fp_context( _context_ptr )
* void _CPU_Context_restore_fp_context( _context_ptr )
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h
b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
index 5d14455563..7669c4a0cf 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
@@ -115,9 +115,10 @@ extern "C" {
#define I386_CONTEXT_CONTROL_EDI_OFFSET 20
#define I386_CONTEXT_CONTROL_GS_0_OFFSET 24
#define I386_CONTEXT_CONTROL_GS_1_OFFSET 28
+#define I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 32
#ifdef RTEMS_SMP
- #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32
+ #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 36
#endif
/* structures */
@@ -136,6 +137,7 @@ typedef struct {
uint32_tesi;/* extended source index register*/
uint32_tedi;/* extended destination index flags register */
segment_descriptors gs; /* gs segment descriptor */
+ uint32_t isr_dispatch_disable;
#ifdef RTEMS_SMP
volatile bool is_executing;
#endif
--
2.12.3
___
devel mailing list
devel@rtems.org
[PATCH v1 9/9] bsp/pc386: Disable interrupt nesting for job handler
- Fixes timeout for smpipi01 where:
+ Main thread sends perform jobs to worker cpu while it is already
performing jobs
+ Interrupt on worker cpu performs jobs, but with empty job list
+ Worker cpu continues to execut previous job and adds new job list
to itself, which is never performed, since the interrupt has already
been handled
+ Main thread blocks forever on barrier D
---
bsps/i386/pc386/start/smp-imps.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index de593f3c40..0985b8f08f 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -768,7 +768,17 @@ static void bsp_inter_processor_interrupt(void *arg)
smp_apic_ack();
+ /*
+ * Disallow nesting.
+ */
+ __asm__ __volatile__("cli");
+
_SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
+
+ /*
+ * Allow nesting.
+ */
+ __asm__ __volatile__("sti");
}
void
--
2.12.3
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http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 2/9] bsp/pc386: Turn start16.S into a startAP.S
start16.S is now only used for SMP configurations to start the
application processors.
This commit removes all unnecessary parts for this job,
i.e. video conssole initalisation, A20 gate activation
and all non-AP related code.
Update #3335
---
bsps/i386/pc386/start/smp-imps.c| 14 +-
bsps/i386/pc386/start/start16.S | 254
bsps/i386/pc386/start/startAP.S | 145 ++
c/src/lib/libbsp/i386/pc386/Makefile.am | 4 +-
4 files changed, 159 insertions(+), 258 deletions(-)
delete mode 100644 bsps/i386/pc386/start/start16.S
create mode 100644 bsps/i386/pc386/start/startAP.S
diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index 0543b17ec5..58d9178f90 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -309,6 +309,11 @@ boot_cpu(imps_processor *proc)
}
/*
+ * Wait until AP is in protected mode before starting the next AP
+ */
+ while (reset[2] != 0);
+
+ /*
* Generic CPU startup sequence ends here, the rest is cleanup.
*/
@@ -342,12 +347,17 @@ add_processor(imps_processor *proc)
printk("#0 BootStrap Processor (BSP)\n");
return;
}
+ /* Setup the apic/cpu maps before booting the APs
+ * otherwise calls to _Get_current_processor can deliver
+ * wrong values if the BSP gets interrupted
+ */
+ imps_cpu_apic_map[imps_num_cpus] = apicid;
+ imps_apic_cpu_map[apicid] = imps_num_cpus;
if (boot_cpu(proc)) {
/* X add OS-specific setup for secondary CPUs here */
-imps_cpu_apic_map[imps_num_cpus] = apicid;
-imps_apic_cpu_map[apicid] = imps_num_cpus;
+/* AP booted successfully, increase number of available cores */
imps_num_cpus++;
}
}
diff --git a/bsps/i386/pc386/start/start16.S b/bsps/i386/pc386/start/start16.S
deleted file mode 100644
index 3d46f40ed6..00
--- a/bsps/i386/pc386/start/start16.S
+++ /dev/null
@@ -1,254 +0,0 @@
-/*--+
- * start16.s v1.0 - PC386 BSP - 1998/04/13
- *--+
- * This file contains the entry point for the application.
- * The name of this entry point is compiler dependent.
- * It jumps to the BSP which is responsible for performing all initialization.
- *--+
- * (C) Copyright 1997 -
- * - NavIST Group - Real-Time Distributed Systems and Industrial Automation
- *
- * http://pandora.ist.utl.pt
- *
- * Instituto Superior Tecnico * Lisboa * PORTUGAL
- *--+
- * Disclaimer:
- *
- * This file is provided "AS IS" without warranty of any kind, either
- * expressed or implied.
- *--+
- */
-
-/*
- * COPYRIGHT (c) 2011.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-
-#include
-
-/*---+
-| Constants
-+*/
-
-#if defined(SMP_SECONDARY_CORE)
-.set PROT_CODE_SEG, 0x08# offset of code segment descriptor into GDT
-#else
-.set PROT_CODE_SEG, 0x0 # offset of code segment descriptor into GDT
-#endif
-
-.set PROT_DATA_SEG, 0x10# offset of code segment descriptor into GDT
-.set CR0_PE,1 # protected mode flag on CR0 register
-.set HDRSTART, HEADERADDR # address of start of bin2boot header
-.set HDROFF,0x24# offset into bin2boot header of start32 addr
-.set STACKOFF, 0x200-0x10 # offset to load into %esp, from start of image
-
-/* #define NEW_GAS */
-#ifdef NEW_GAS
- #define LJMPL ljmpl
-#else
- #define LJMPL ljmp
-#endif
-
-/*+
-| CODE section
-+*/
-
-.text
-#if defined(SMP_SECONDARY_CORE)
-.globl app_processor_start# entry point
-app_processor_start:
-#else
-.globl _start16 # entry point
-.globl start16
-start16:
-_start16:
-#endif
-
-.code16
-cli # DISABLE INTERRUPTS!!!
-#if defined(SMP_SECONDARY_CORE)
-jmp 1f
- .align 4
-app_cpu_start:
- .long 0
-app_cpu_stack:
- .long 0
-1:
-#endif
-movw%cs, %ax # Initialize the rest of
-movw%ax, %ds # segment registers
-movw%ax, %es
-movw%ax, %ss
-
-#if !defined(SMP_SECONDARY_CODE) && (RTEMS_VIDEO_80x50 == 1)
-movl$0x0040,%eax# use 32 bit
[PATCH v1 5/9] bsp/pc386: Define interrupt stack frame for smp
- Defines CPU_Interrupt_frame in cpu_impl.h - Updates isq_asm.S to save/restore registers in matching order to interrupt frame --- bsps/i386/shared/irq/irq_asm.S | 102 +++-- cpukit/score/cpu/i386/include/rtems/score/cpu.h| 28 +++--- .../score/cpu/i386/include/rtems/score/cpuimpl.h | 2 + 3 files changed, 73 insertions(+), 59 deletions(-) diff --git a/bsps/i386/shared/irq/irq_asm.S b/bsps/i386/shared/irq/irq_asm.S index 2d65a79fe2..6a399f0c15 100644 --- a/bsps/i386/shared/irq/irq_asm.S +++ b/bsps/i386/shared/irq/irq_asm.S @@ -25,17 +25,19 @@ #endif /* Stack frame we use for intermediate storage */ -#define ARG_OFF0 -#define MSK_OFF 4/* not used any more*/ -#define EBX_OFF 8/* ebx */ -#define EBP_OFF 12 /* code restoring ebp/esp relies on */ -#define ESP_OFF 16 /* esp being on top of ebp! */ +#define ARG_OFF 0 +#define EBX_OFF 4/* ebx */ +#define EBP_OFF 8 /* code restoring ebp/esp relies on */ +#define ESP_OFF 12 /* esp being on top of ebp! */ #ifdef __SSE__ +#ifdef RTEMS_SMP +#error SMP with SSE support has not been tested. Use at your own risk. +#endif /* need to be on 16 byte boundary for SSE, add 12 to do that */ #define FRM_SIZ (20+12+512) #define SSE_OFF 32 #else -#define FRM_SIZ 20 +#define FRM_SIZ 16 #endif BEGIN_CODE @@ -59,7 +61,7 @@ SYM (_ISR_Handler): * NOTE: If the previous values of the segment registers are * pushed, do not forget to adjust SAVED_REGS. * -* NOTE: Make sure the exit code which restores these +* NOTE: Make sure the Lthread_dispatch_done code restores these * when this type of code is needed. */ @@ -72,17 +74,15 @@ SYM (_ISR_Handler): /* * Establish an aligned stack frame * original sp - * saved ebx * saved ebp -* saved irq mask +* saved ebx * vector arg to BSP_dispatch_isr <- aligned SP */ movl esp, eax subl $FRM_SIZ, esp - andl $ - CPU_STACK_ALIGNMENT, esp - movl ebx, EBX_OFF(esp) movl eax, ESP_OFF(esp) movl ebp, EBP_OFF(esp) + movl ebx, EBX_OFF(esp) /* * GCC versions starting with 4.3 no longer place the cld @@ -100,10 +100,10 @@ SYM (_ISR_Handler): /* We save SSE here (on the task stack) because we possibly * call other C-code (besides the ISR, namely _Thread_Dispatch()) */ -/* don't wait here; a possible exception condition will eventually be - * detected when the task resumes control and executes a FP instruction + /* don't wait here; a possible exception condition will eventually be +* detected when the task resumes control and executes a FP instruction fwait - */ +*/ fxsave SSE_OFF(esp) fninit /* clean-slate FPU*/ movl $0x1f80, ARG_OFF(esp)/* use ARG_OFF as scratch space */ @@ -118,15 +118,9 @@ PUBLIC (ISR_STOP) ISR_STOP: .check_stack_switch: movl esp, ebp /* ebp = previous stack pointer */ + andl $ - CPU_STACK_ALIGNMENT, esp /* Make sure esp is 16 byte aligned */ -#ifdef RTEMS_SMP - call SYM(_CPU_SMP_Get_current_processor) - sall $PER_CPU_CONTROL_SIZE_LOG2, eax - addl $SYM(_Per_CPU_Information), eax - movl eax, ebx -#else - movl $SYM(_Per_CPU_Information), ebx -#endif + GET_SELF_CPU_CONTROL ebx /* is this the outermost interrupt? */ cmpl $0, PER_CPU_ISR_NEST_LEVEL(ebx) @@ -161,32 +155,48 @@ nested: */ movl ebp, esp - decl PER_CPU_ISR_NEST_LEVEL(ebx) /* one less ISR nest level */ - /* If interrupts are nested, */ - /* then dispatching is disabled */ - - decl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx) - /* unnest multitasking */ - /* Is dispatch disabled */ - jne .exit /* Yes, then exit */ - - cmpb $0, PER_CPU_DISPATCH_NEEDED(ebx) - /* Is task switch necessary? */ - jne .schedule /* Yes, then call the scheduler */ - jmp .exit /* No, exit */ - -.schedule: - /* -* the scratch registers have already been saved and we are already -* back on the thread system stack. So we can call _Thread_Dispatch -* directly -*/ - call _Thread_Dispatch /* -* fall through exit to restore complete
[PATCH v1 1/9] bsp/pc386: Fix Makefile for building with SMP
--- c/src/lib/libbsp/i386/pc386/Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/c/src/lib/libbsp/i386/pc386/Makefile.am b/c/src/lib/libbsp/i386/pc386/Makefile.am index 354ad0b23e..218e6bc065 100644 --- a/c/src/lib/libbsp/i386/pc386/Makefile.am +++ b/c/src/lib/libbsp/i386/pc386/Makefile.am @@ -118,7 +118,7 @@ appcpustart.$(OBJEXT): ../../../../../../bsps/i386/pc386/start/start16.S $(CPPASCOMPILE) $(AM_CPPFLAGS) -DSMP_SECONDARY_CORE -o $@ -c $< appstart.$(OBJEXT): appcpustart.$(OBJEXT) - $(LD) -r -N -T $(top_srcdir)/../../../../../../bsps/i386/pc386/start/linkcmds \ + $(LD) -N \ -Ttext 0x7 -e app_processor_start -nostdlib \ -o appstart_tmp.exe $< $(OBJCOPY) -O binary appstart_tmp.exe appstart.bin -- 2.12.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 0/9] Enable SMP for pc386 based bsps
Hello, Here is a patch set which should enable SMP again for the pc386-based BSPs (mainly tested with pc686). So far I only tested it with qemu. Tests on real hardware are pending. To me it looks like there are no regressions for the standard non-SMP version of the BSP, but it is difficult to say for sure. Subsequent runs of the testsuite with a current master build already produce different numbers of failed/timeout/invalid tests. However, even with the patch set applied the amount of passed tests continues to range from 550-557 and the failed/timeout/invalid tests seem to be generally the same. Regarding smptests, the current status with qemu-4.2.0 and 4 cores looks like this: Passed:55 Failed: 1 User Input: 0 Expected Fail: 0 Indeterminate: 0 Benchmark: 0 Timeout:2 Invalid:1 Wrong Version: 0 Wrong Build:0 Wrong Tools:0 - Total: 59 Failures: smpatomic01.exe Timeouts: smpclock01.exe smpopenmp01.exe Invalid: smpfatal09.exe Some details on the missing tests: --- smpfatal09: This test actually does pass, but because the fatal error handler is executed before the console is initialized, no output is produced. smpclock01.exe: Here CPU0 disables its local interrupts and waits for a barrier release of CPU1. This means it doesn't handle timer interrupts anymore and doesn't send corresponding IPIs to other CPUs. At the same time CPU1 is waiting for a timer event before releasing the barrier. Any hints how to resolve this are very welcome. smpatomic01: This test seems very large and a bit complicated to me. I will have a look at it next, but any suggestions are welcome. It fails with this information: ] === atomic or/and test case === ] worker 0 value: 1 ] worker 1 value: 0 ] atomic value: expected = 1, actual = 1 ] ../../../../../../smp-refex-rtems/c/src/../../testsuites/smptests/smpatomic01/init.c: 404 n - s < LONG_MAX ] ] *** FATAL *** smpopenmp01: I don't know more about openmp then what is on wikipedia. It has currently a low priority for me. Some details regarding the patch set: - - The first 3 commits are basically cleaning the original start16.S to be used for starting the application processors only and updating the general bring up infrastructure. - The next 2 commits are updating the low level context switch and isr handling in assembly. I used the ARM implementation as a template and tried to stay comparably close to it. - The last 4 commits are smaller changes made after debugging certain test cases. My next step would be to test the SMP functionality on HW. My goal would be to get the final revision published as part of the RTEMS5 release. If you would like to see any logs from a testsuite run with certain parameters, just tell me. Best regards, Jan Jan Sommer (9): bsp/pc386: Fix Makefile for building with SMP bsp/pc386: Turn start16.S into a startAP.S bsp/pc386: Update GDT to work for SMP bsp/pc386: Update context switch and restore bsp/pc386: Define interrupt stack frame for smp bsps/pc386: Fix Clock_isr for SMP bsps/pc386: Separate smp API functions. Makes smpfatal08 link smpsignal01: Change state before sending the signal bsp/pc386: Disable interrupt nesting for job handler bsps/i386/include/bsp/smp-imps.h | 3 + bsps/i386/pc386/clock/ckinit.c | 2 +- bsps/i386/pc386/include/bsp.h | 7 + bsps/i386/pc386/include/bsp/tblsizes.h | 8 +- bsps/i386/pc386/start/bspsmp.c | 43 bsps/i386/pc386/start/getcpuid.c | 22 -- bsps/i386/pc386/start/ldsegs.S | 4 +- bsps/i386/pc386/start/smp-imps.c | 79 --- bsps/i386/pc386/start/start16.S| 254 - bsps/i386/pc386/start/startAP.S| 118 ++ bsps/i386/shared/irq/irq_asm.S | 102 + c/src/lib/libbsp/i386/pc386/Makefile.am| 8 +- cpukit/score/cpu/i386/cpu_asm.S| 74 -- cpukit/score/cpu/i386/include/rtems/asm.h | 26 +++ cpukit/score/cpu/i386/include/rtems/score/cpu.h| 32 +-- .../score/cpu/i386/include/rtems/score/cpuimpl.h | 2 + testsuites/smptests/smpsignal01/init.c | 2 +- 17 files changed, 382 insertions(+), 404 deletions(-) create mode 100644 bsps/i386/pc386/start/bspsmp.c delete mode 100644 bsps/i386/pc386/start/getcpuid.c delete mode 100644 bsps/i386/pc386/start/start16.S create mode 100644 bsps/i386/pc386/start/startAP.S -- 2.12.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 7/9] bsps/pc386: Separate smp API functions. Makes smpfatal08 link
---
bsps/i386/include/bsp/smp-imps.h| 3 +++
bsps/i386/pc386/include/bsp.h | 7 ++
bsps/i386/pc386/start/bspsmp.c | 43 +
bsps/i386/pc386/start/getcpuid.c| 22 -
bsps/i386/pc386/start/smp-imps.c| 40 ++
c/src/lib/libbsp/i386/pc386/Makefile.am | 2 +-
6 files changed, 61 insertions(+), 56 deletions(-)
create mode 100644 bsps/i386/pc386/start/bspsmp.c
delete mode 100644 bsps/i386/pc386/start/getcpuid.c
diff --git a/bsps/i386/include/bsp/smp-imps.h b/bsps/i386/include/bsp/smp-imps.h
index 03434b81ef..7b023ddcfc 100644
--- a/bsps/i386/include/bsp/smp-imps.h
+++ b/bsps/i386/include/bsp/smp-imps.h
@@ -233,6 +233,9 @@ extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
extern char _binary_appstart_bin_start[];
extern char _binary_appstart_bin_size[];
+/** @brief base address of the local apic. Usually 0xFEE0 */
+extern unsigned imps_lapic_addr;
+
/*
* Defines that use variables
*/
diff --git a/bsps/i386/pc386/include/bsp.h b/bsps/i386/pc386/include/bsp.h
index 7989b880a9..1ed92e469a 100644
--- a/bsps/i386/pc386/include/bsp.h
+++ b/bsps/i386/pc386/include/bsp.h
@@ -252,6 +252,13 @@ uint32_t BSP_irq_count_dump(FILE *f);
void raw_idt_notify(void);
void C_dispatch_isr(int vector);
+#ifdef RTEMS_SMP
+ /* CPU specific functions used by the SMP API */
+ int imps_probe(void);
+ void ipi_install_irq(void);
+ int send_ipi(unsigned int dst, unsigned int v);
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/bsps/i386/pc386/start/bspsmp.c b/bsps/i386/pc386/start/bspsmp.c
new file mode 100644
index 00..026f86916f
--- /dev/null
+++ b/bsps/i386/pc386/start/bspsmp.c
@@ -0,0 +1,43 @@
+
+#include
+
+#include
+#include
+#include
+#include
+
+void _CPU_SMP_Prepare_start_multitasking( void )
+{
+ /* Do nothing */
+}
+
+bool _CPU_SMP_Start_processor( uint32_t cpu_index )
+{
+ (void) cpu_index;
+
+ return true;
+}
+
+
+uint32_t _CPU_SMP_Get_current_processor( void )
+{
+ return imps_apic_cpu_map[APIC_ID(IMPS_LAPIC_READ(LAPIC_ID))];
+}
+
+uint32_t _CPU_SMP_Initialize( void )
+{
+ /* XXX need to deal with finding too many cores */
+
+ return (uint32_t) imps_probe();
+}
+
+void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
+{
+ if ( cpu_count > 1 )
+ipi_install_irq();
+}
+
+void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
+{
+ send_ipi( target_processor_index, 0x30 );
+}
diff --git a/bsps/i386/pc386/start/getcpuid.c b/bsps/i386/pc386/start/getcpuid.c
deleted file mode 100644
index 4918a2a970..00
--- a/bsps/i386/pc386/start/getcpuid.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * COPYRIGHT (c) 2011.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include
-
-#include
-#include
-
-static int lapic_dummy = 0;
-unsigned imps_lapic_addr = ((unsigned)(_dummy)) - LAPIC_ID;
-
-uint32_t _CPU_SMP_Get_current_processor( void )
-{
- return imps_apic_cpu_map[APIC_ID(IMPS_LAPIC_READ(LAPIC_ID))];
-}
-
diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index 6480c0d25e..de593f3c40 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -85,6 +85,9 @@
extern void _pc386_delay(void);
extern uint32_t* gdtdesc;
+static int lapic_dummy = 0;
+unsigned imps_lapic_addr = ((unsigned)(_dummy)) - LAPIC_ID;
+
/* #define KERNEL_PRINT(_format) printk(_format) */
static void CMOS_WRITE_BYTE(
@@ -220,7 +223,7 @@ get_checksum(unsigned start, int length)
/*
* APIC ICR write and status check function.
*/
-static int
+int
send_ipi(unsigned int dst, unsigned int v)
{
int to, send_status;
@@ -698,7 +701,7 @@ imps_force(int ncpus)
*
* Function finished.
*/
-static int
+int
imps_probe(void)
{
/*
@@ -768,7 +771,8 @@ static void bsp_inter_processor_interrupt(void *arg)
_SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
}
-static void ipi_install_irq(void)
+void
+ipi_install_irq(void)
{
rtems_status_code status;
@@ -802,33 +806,3 @@ static void secondary_cpu_initialize(void)
_SMP_Start_multitasking_on_secondary_processor( _Per_CPU_Get() );
}
-
-uint32_t _CPU_SMP_Initialize( void )
-{
- /* XXX need to deal with finding too many cores */
-
- return (uint32_t) imps_probe();
-}
-
-void _CPU_SMP_Prepare_start_multitasking( void )
-{
- /* Do nothing */
-}
-
-bool _CPU_SMP_Start_processor( uint32_t cpu_index )
-{
- (void) cpu_index;
-
- return true;
-}
-
-void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
-{
- if ( cpu_count > 1 )
-ipi_install_irq();
-}
-
-void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
-{
- send_ipi( target_processor_index, 0x30 );
-}
diff --git a/c/src/lib/libbsp/i386/pc386/Makefile.am
b/c/src/lib/libbsp/i386/pc386/Makefile.am
[PATCH 1/1] smpsignal01: Change state before sending the signal
The signal handler of the consumer might start executing
before rtems_signal_send of the producer returns.
Therefore change the state to SIG_1_SENT before sending the signal.
---
testsuites/smptests/smpsignal01/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/testsuites/smptests/smpsignal01/init.c
b/testsuites/smptests/smpsignal01/init.c
index 36a66bea9b..025e84c6a2 100644
--- a/testsuites/smptests/smpsignal01/init.c
+++ b/testsuites/smptests/smpsignal01/init.c
@@ -81,10 +81,10 @@ static void signal_send(test_context *ctx, test_state
new_state)
{
rtems_status_code sc;
+ change_state(ctx, new_state);
sc = rtems_signal_send(ctx->consumer, TEST_SIGNAL);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
- change_state(ctx, new_state);
}
static void check_consumer_processor(const test_context *ctx)
--
2.12.3
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[PATCH 0/1] smpsignal01: Change state before sending signal
I noticed during running the smpsignal test that it sometimes succeeds and sometimes fails when running with qemu. It looks like the signal handler sometimes starts execution faster than the sender can update the state variable. This patch updates the variable right before sending, so that the state always has the correct value for the handler to process. Best regards, Jan Jan Sommer (1): smpsignal01: Change state before sending the signal testsuites/smptests/smpsignal01/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.12.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v5 0/7] [5-freebsd-12] Fix compilation for i386
This is the backport for the 5-freebsd-12 branch to make rtems-libbsd compile
for i386 again:
- It also introduces path-mappings to waf_libbsd.py as introduced here:
https://lists.rtems.org/pipermail/devel/2020-February/057457.html
Changes compared to v4:
- Split up the changes in more reasonable commits
- header files in rtemsbsd/include/x86 are now only stubs forwarding to
the correct file
Changes compared to v3:
- iflib.c: Properly deactivate usage of ifc_cpus
- subr_gtaskqueue.c: Deactivate BSD_ASSERT for i386 (will open a
discussion for that)
- Could successfully run network tests (e.g. dhcpcd0x.exe on hardware)
Changes compared to v2:
- callout.h: Change the callout_reset_on macro
- iflib.c: Do not use different callout* macro, but use the changed one
Best regards,
Jan
Jan Sommer (7):
i386: Add missing files from FreeBSD
waf: Add path-mappings feature
i386: Add missing files to build system
Callout: Redefine callout_reset_on for rtems
iflib.c: Deactivate use of ifc_cpus
i386: Delete old machine dependent files
i386: Port to RTEMS
freebsd/sbin/sysctl/sysctl.c |8 +
freebsd/sys/dev/pci/pci_pci.c |2 +
freebsd/sys/i386/include/machine/cpufunc.h |2 +
freebsd/sys/i386/include/machine/specialreg.h |6 -
freebsd/sys/kern/subr_gtaskqueue.c |4 +
freebsd/sys/net/iflib.c| 6771
freebsd/sys/net/iflib_private.h| 76 +
freebsd/sys/net/mp_ring.c | 554 ++
freebsd/sys/net/mp_ring.h | 75 +
freebsd/sys/sys/callout.h |6 +
freebsd/sys/x86/include/machine/intr_machdep.h | 180 +
.../sys/{i386 => x86}/include/machine/legacyvar.h | 26 +-
freebsd/sys/x86/include/machine/specialreg.h | 1083
freebsd/sys/x86/include/machine/x86_var.h | 166 +
freebsd/sys/{i386/i386 => x86/x86}/legacy.c| 77 +-
libbsd.py | 20 +-
rtemsbsd/i386/include/machine/clock.h |2 +
rtemsbsd/include/rtems/bsd/local/opt_acpi.h|0
rtemsbsd/include/x86/legacyvar.h |1 +
rtemsbsd/include/x86/x86_var.h |1 +
waf_libbsd.py | 13 +-
21 files changed, 9027 insertions(+), 46 deletions(-)
delete mode 100644 freebsd/sys/i386/include/machine/specialreg.h
create mode 100644 freebsd/sys/net/iflib.c
create mode 100644 freebsd/sys/net/iflib_private.h
create mode 100644 freebsd/sys/net/mp_ring.c
create mode 100644 freebsd/sys/net/mp_ring.h
create mode 100644 freebsd/sys/x86/include/machine/intr_machdep.h
rename freebsd/sys/{i386 => x86}/include/machine/legacyvar.h (76%)
create mode 100644 freebsd/sys/x86/include/machine/specialreg.h
create mode 100644 freebsd/sys/x86/include/machine/x86_var.h
rename freebsd/sys/{i386/i386 => x86/x86}/legacy.c (89%)
create mode 100644 rtemsbsd/i386/include/machine/clock.h
create mode 100644 rtemsbsd/include/rtems/bsd/local/opt_acpi.h
create mode 100644 rtemsbsd/include/x86/legacyvar.h
create mode 100644 rtemsbsd/include/x86/x86_var.h
--
2.12.3
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[PATCH v5 7/7] i386: Port to RTEMS
- Update imported files to compile rtems-libbsd for i386 based BSPs
- Mostly commenting out parts which create compile or link errors in
RTEMS, but aren't needed
---
freebsd/sbin/sysctl/sysctl.c| 8
freebsd/sys/dev/pci/pci_pci.c | 2 ++
freebsd/sys/i386/include/machine/cpufunc.h | 2 ++
freebsd/sys/kern/subr_gtaskqueue.c | 4
rtemsbsd/i386/include/machine/clock.h | 2 ++
rtemsbsd/include/rtems/bsd/local/opt_acpi.h | 0
6 files changed, 18 insertions(+)
create mode 100644 rtemsbsd/i386/include/machine/clock.h
create mode 100644 rtemsbsd/include/rtems/bsd/local/opt_acpi.h
diff --git a/freebsd/sbin/sysctl/sysctl.c b/freebsd/sbin/sysctl/sysctl.c
index 30ebe5fd..035c1db2 100644
--- a/freebsd/sbin/sysctl/sysctl.c
+++ b/freebsd/sbin/sysctl/sysctl.c
@@ -69,7 +69,9 @@ static const char rcsid[] =
#endif
#if defined(__amd64__) || defined(__i386__)
+#ifndef __rtems__
#include
+#endif /* __rtems__ */
#endif
#include
@@ -832,6 +834,7 @@ S_efi_map(size_t l2, void *p)
#endif
#if defined(__amd64__) || defined(__i386__)
+#ifndef __rtems__
static int
S_bios_smap_xattr(size_t l2, void *p)
{
@@ -850,6 +853,7 @@ S_bios_smap_xattr(size_t l2, void *p)
(uintmax_t)smap->length);
return (0);
}
+#endif /* __rtems__ */
#endif
static int
@@ -1061,7 +1065,11 @@ show_var(int *oid, int nlen)
#endif
#if defined(__amd64__) || defined(__i386__)
else if (strcmp(fmt, "S,bios_smap_xattr") == 0)
+#ifndef __rtems__
func = S_bios_smap_xattr;
+#else /* __rtems__ */
+ func = NULL;
+#endif /* __rtems__ */
#endif
else {
func = NULL;
diff --git a/freebsd/sys/dev/pci/pci_pci.c b/freebsd/sys/dev/pci/pci_pci.c
index 43c71461..5ba3e9a0 100644
--- a/freebsd/sys/dev/pci/pci_pci.c
+++ b/freebsd/sys/dev/pci/pci_pci.c
@@ -1593,6 +1593,7 @@ pcib_attach_common(device_t dev)
sc->flags |= PCIB_SUBTRACTIVE;
break;
+#ifndef __rtems__
#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
/* Compaq R3000 BIOS sets wrong subordinate bus number. */
case 0x00dd10de:
@@ -1620,6 +1621,7 @@ pcib_attach_common(device_t dev)
break;
}
#endif
+#endif /* __rtems__ */
}
if (pci_msi_device_blacklisted(dev))
diff --git a/freebsd/sys/i386/include/machine/cpufunc.h
b/freebsd/sys/i386/include/machine/cpufunc.h
index a029da3b..e50ef9d7 100644
--- a/freebsd/sys/i386/include/machine/cpufunc.h
+++ b/freebsd/sys/i386/include/machine/cpufunc.h
@@ -233,11 +233,13 @@ fls(int mask)
#defineHAVE_INLINE_FLSL
+#ifndef __rtems__
static __inline __pure2 int
flsl(long mask)
{
return (fls((int)mask));
}
+#endif /* __rtems__ */
#endif /* _KERNEL */
diff --git a/freebsd/sys/kern/subr_gtaskqueue.c
b/freebsd/sys/kern/subr_gtaskqueue.c
index c061c6b0..4ef05e0a 100644
--- a/freebsd/sys/kern/subr_gtaskqueue.c
+++ b/freebsd/sys/kern/subr_gtaskqueue.c
@@ -744,7 +744,9 @@ taskqgroup_attach(struct taskqgroup *qgroup, struct
grouptask *gtask,
__func__, gtask->gt_name, error);
} else
#else /* __rtems__ */
+#ifndef __i386__
BSD_ASSERT(irq == -1);
+#endif /* __i386 */
#endif /* __rtems__ */
mtx_unlock(>tqg_lock);
}
@@ -776,7 +778,9 @@ taskqgroup_attach_deferred(struct taskqgroup *qgroup,
struct grouptask *gtask)
}
#else /* __rtems__ */
+#ifndef __i386__
BSD_ASSERT(gtask->gt_irq == -1);
+#endif /* __i386 */
#endif /* __rtems__ */
qgroup->tqg_queue[qid].tgc_cnt++;
LIST_INSERT_HEAD(>tqg_queue[qid].tgc_tasks, gtask, gt_list);
diff --git a/rtemsbsd/i386/include/machine/clock.h
b/rtemsbsd/i386/include/machine/clock.h
new file mode 100644
index ..415e2b55
--- /dev/null
+++ b/rtemsbsd/i386/include/machine/clock.h
@@ -0,0 +1,2 @@
+extern int tsc_is_invariant;
+extern uint64_t tsc_freq;
diff --git a/rtemsbsd/include/rtems/bsd/local/opt_acpi.h
b/rtemsbsd/include/rtems/bsd/local/opt_acpi.h
new file mode 100644
index ..e69de29b
--
2.12.3
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[PATCH v5 4/7] Callout: Redefine callout_reset_on for rtems
- callout_reset_on takes a cpu which is ignored by the subsequent call to callout_reset_sbt_on in RTEMS. - The macro is redefined to discard the cpu argument directly which enables uses of it with cpu-dependent variables (disabled in RETMS) without further changes, e.g. in iflib.c. --- freebsd/sys/sys/callout.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/freebsd/sys/sys/callout.h b/freebsd/sys/sys/callout.h index e5e5df85..d7b9965a 100644 --- a/freebsd/sys/sys/callout.h +++ b/freebsd/sys/sys/callout.h @@ -112,9 +112,15 @@ intcallout_reset_sbt_on(struct callout *, sbintime_t, sbintime_t, #definecallout_reset_sbt_curcpu(c, sbt, pr, fn, arg, flags) \ callout_reset_sbt_on((c), (sbt), (pr), (fn), (arg), PCPU_GET(cpuid),\ (flags)) +#ifndef __rtems__ #definecallout_reset_on(c, to_ticks, fn, arg, cpu) \ callout_reset_sbt_on((c), tick_sbt * (to_ticks), 0, (fn), (arg), \ (cpu), C_HARDCLOCK) +#else /* __rtems__ */ +#definecallout_reset_on(c, to_ticks, fn, arg, cpu) \ +callout_reset_sbt_on((c), tick_sbt * (to_ticks), 0, (fn), (arg), \ +-1, C_HARDCLOCK) +#endif /* __rtems__ */ #definecallout_reset(c, on_tick, fn, arg) \ callout_reset_on((c), (on_tick), (fn), (arg), -1) #definecallout_reset_curcpu(c, on_tick, fn, arg) \ -- 2.12.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
