Re: [Dorset] Meaning of ‘DT File’ in Schematic/PCB/Simulation Context.
Hi Patrick, > On second thoughts, I wonder if they could be talking about generating > a "device tree". Which sounds plausible, thanks. Grant Likely was heavily involved in Device Tree's addition to Linux on ARM and it's a declarative description of common hardware on embedded systems so it would be handy to be able to take a schematic design and have the kernel know what devices are available and how to access them. https://www.devicetree.org > At the end of the question, the speaker agrees with someone by saying > "you would need a lot of SFC awareness"; perhaps another relevant > search term (I couldn't find anything quickly with that though). No, me neither. Serial Flash Controller? Doesn't sound right. -- Cheers, Ralph. -- Next meeting: BEC, Bournemouth, Tuesday, 2020-02-04 20:00 Check to whom you are replying Meetings, mailing list, IRC, ... http://dorset.lug.org.uk/ New thread, don't hijack: mailto:dorset@mailman.lug.org.uk
Re: [Dorset] Meaning of ‘DT File’ in Schematic/PCB/Simulation Context.
On Sun, 23 Feb 2020 11:38:04 +, Ralph Corderoy wrote: > A test plan that can be executed? That was my first thought, but I'm not aware of any kind of testing that might use the abbreviation "DT". On second thoughts, I wonder if they could be talking about generating a "device tree". At the end of the question, the speaker agrees with someone by saying "you would need a lot of SFC awareness"; perhaps another relevant search term (I couldn't find anything quickly with that though). -- Next meeting: BEC, Bournemouth, Tuesday, 2020-02-04 20:00 Check to whom you are replying Meetings, mailing list, IRC, ... http://dorset.lug.org.uk/ New thread, don't hijack: mailto:dorset@mailman.lug.org.uk
Re: [Dorset] Meaning of ‘DT File’ in Schematic/PCB/Simulation Context.
Hi Terry, > I'm not skilled in the art of PCB design, but my partially informed guess > would be 'Drilling Template' layer. Thanks for the informed guess. :-) I think the Gerber file can contain information about a drilling layer, or if not some other CNC-related format. And ‘drilling template’ wouldn't seem to tie in with the ‘What's the state of code generation’ bit; that suggests the questioner thinks code for something could be produced. A simulator, like Spice? A test plan that can be executed? -- Cheers, Ralph. -- Next meeting: BEC, Bournemouth, Tuesday, 2020-02-04 20:00 Check to whom you are replying Meetings, mailing list, IRC, ... http://dorset.lug.org.uk/ New thread, don't hijack: mailto:dorset@mailman.lug.org.uk
Re: [Dorset] Meaning of ‘DT File’ in Schematic/PCB/Simulation Context.
On Sunday, 23 February 2020 11:14:43 GMT Terry Coles wrote: > I'm not skilled in the art of PCB design, but my partially informed guess > would be 'Drilling Template' layer. On re-reading the original discussion, I see that the reference is to a DT file, rather than a DT Layer. In the context of PCB fabrication the file that we always sent to the PCB manufacturer was a 'Gerber File' (https://en.wikipedia.org/wiki/Gerber_format[1]). You will see from the link that the drilling data forms part of the Gerber file content. However, the further discussion in your message says: >‘KiCAD works at the level of schematic and it doesn't have a whole > lot in terms of what the logical flow of the device is so what it > would need is some way to describe the logical connections between > the devices and then from that be able to generate a DT file. That > would be incredibly useful. It would be possible I think to create > an ad-hoc tool using a convention on the signal names so going > through level shifters would be able to use a signal-name convention > to associate components with buses and then from there generate a DT > file.’ This doesn't seem to refer to a drilling template at all and the OP seems to think that it would be useful to allow auto-routing. At the moment I have no idea whether KiCAD can do that, let alone provide the drilling data. BTW, auto-routing is when the software provides the tools to draw the circuit diagram of the product and the PCB layout is automatically produced with all tracks, layers and plated-through holes included. There are free web tools that can do that and at one point in the WMT development cycle we were evaluating these two: upverter.com
Re: [Dorset] Meaning of ‘DT File’ in Schematic/PCB/Simulation Context.
On Sunday, 23 February 2020 10:49:42 GMT Ralph Corderoy wrote: > Anyway, the point of this email is one of the Q about fifty minutes > referred to what sounded like a ‘DT layer’ and I don't know what that > is. I'm not skilled in the art of PCB design, but my partially informed guess would be 'Drilling Template' layer. When PCB CAD software lays out the tracks there are numerous holes needed to insert the component legs through; each of these has a solder pad in the layout, so it is important that the hole ends up in the middle of the pad :-) There are other holes needed; plated through holes to link tracks to tracks on other layers, holes to secure large components to the board with screws etc and holes to secure the PCB into the enclosure. That what I would understand if someone talked to me about a Drilling Template. I don't recall our draughtsmen ever referring to a DT Layer, but there was probably no reason why they would to me. -- Terry Coles -- Next meeting: BEC, Bournemouth, Tuesday, 2020-02-04 20:00 Check to whom you are replying Meetings, mailing list, IRC, ... http://dorset.lug.org.uk/ New thread, don't hijack: mailto:dorset@mailman.lug.org.uk
[Dorset] Meaning of ‘DT File’ in Schematic/PCB/Simulation Context.
Hi, I recently watched ‘Hardware Design for Linux Engineers’, 52 minutes, https://www.youtube.com/watch?v=ziHhcBoRjQk. It was okay, more interesting towards the end where the programmer talked about the issues he'd had with his hardware design, like getting oscillations from his transparent level shifters when taking I²C signals off the board. The main point of the video was KiCAD is a lot better now than a few years ago, https://www.kicad-pcb.org. CERN have been putting money into it, it's recently joined the Linux Foundation, etc. Version 6 later this year is meant to be a big improvement again. Eagle's two-layer limitation in its free-beer version has seen more people move to KiCAD as it has improved and that feedback has helped further. Features include routing of differential pairs, a push-and-shove router that will move traces out of the way as you draw, and interactive trace-length tuning. Anyway, the point of this email is one of the Q about fifty minutes referred to what sounded like a ‘DT layer’ and I don't know what that is. ‘What's the state of code generation for tools like KiCAD? Like are we at the point where we can turn out DT files based on the schematic yet.’ ‘No.’ ‘Is anyone trying that?’ ‘I don't think so.’ ‘KiCAD works at the level of schematic and it doesn't have a whole lot in terms of what the logical flow of the device is so what it would need is some way to describe the logical connections between the devices and then from that be able to generate a DT file. That would be incredibly useful. It would be possible I think to create an ad-hoc tool using a convention on the signal names so going through level shifters would be able to use a signal-name convention to associate components with buses and then from there generate a DT file.’ Anyone here know? -- Cheers, Ralph. -- Next meeting: BEC, Bournemouth, Tuesday, 2020-02-04 20:00 Check to whom you are replying Meetings, mailing list, IRC, ... http://dorset.lug.org.uk/ New thread, don't hijack: mailto:dorset@mailman.lug.org.uk
