[Bug 96602] [radeonsi] Dreamfall Chapters: one shader fails to compile, minor visual corruption

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=96602

Kai  changed:

   What|Removed |Added

 Resolution|FIXED   |---
 Status|RESOLVED|REOPENED

--- Comment #4 from Kai  ---
<http://reviews.llvm.org/D21551> needs some more work and hasn't landed yet on
LLVM trunk, I closed this bug a bit prematurely, since the issue at hand was
fixed fore *me* after applying the patch.

I'm sure Nicolai will close it again, once he had time to address the
outstanding comments on his patch.

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[Bug 96731] [RADEONSI] [LLVM] [bisected] GPU lockups when running Alien: Isolation

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=96731

Bug ID: 96731
   Summary: [RADEONSI] [LLVM] [bisected] GPU lockups when running
Alien: Isolation
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: arek.rusi at gmail.com
QA Contact: dri-devel at lists.freedesktop.org

Created attachment 124784
  --> https://bugs.freedesktop.org/attachment.cgi?id=124784=edit
gpu lockups part from dmesg

Hi, GPU trying reset few times but hang at the end.

ArchLinux 64
Radeon HD 7770
mesa  latest from git
kernel 4.7rc
libdrm latest from git


first bad commit is:

r273467 | arsenm | 2016-06-22 22:15:28 +0200 |

AMDGPU: Fix verifier errors in SILowerControlFlow

The main sin this was committing was using terminator
instructions in the middle of the block, and then
not updating the block successors / predecessors.
Split the blocks up to avoid this and introduce new
pseudo instructions for branches taken with exec masking.

Also use a pseudo instead of emitting s_endpgm and erasing
it in the special case of a non-void return.

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[PATCH 1/3] drm: bridge: add DesignWare HDMI I2S audio support

[Yakir Yang]

Kuninori,

On 06/24/2016 10:40 AM, Kuninori Morimoto wrote:
> From: Kuninori Morimoto 
>
> Current dw-hdmi is supporting sound via AHB bus, but it has
> I2S audio feature too. This patch adds I2S audio support to dw-hdmi.
> This HDMI I2S is supported by using ALSA SoC common HDMI encoder
> driver.
>
> Signed-off-by: Kuninori Morimoto 
> ---
>   drivers/gpu/drm/bridge/Kconfig |   8 ++
>   drivers/gpu/drm/bridge/Makefile|   1 +
>   drivers/gpu/drm/bridge/dw-hdmi-audio.h |   7 ++
>   drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c | 123 
> +
>   drivers/gpu/drm/bridge/dw-hdmi.c   |  22 +-
>   drivers/gpu/drm/bridge/dw-hdmi.h   |  21 +
>   6 files changed, 180 insertions(+), 2 deletions(-)
>   create mode 100644 drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 8f7423f..8e2a22d 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -32,6 +32,14 @@ config DRM_DW_HDMI_AHB_AUDIO
> Designware HDMI block.  This is used in conjunction with
> the i.MX6 HDMI driver.
>   
> +config DRM_DW_HDMI_I2S_AUDIO
> + tristate "Synopsis Designware I2S Audio interface"
> + depends on DRM_DW_HDMI
> + select SND_SOC_HDMI_CODEC
> + help
> +   Support the I2S Audio interface which is part of the Synopsis
> +   Designware HDMI block.
> +
>   config DRM_NXP_PTN3460
>   tristate "NXP PTN3460 DP/LVDS bridge"
>   depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 96b13b3..1af92ad 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -3,6 +3,7 @@ ccflags-y := -Iinclude/drm
>   obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
> +obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>   obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>   obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
>   obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
> diff --git a/drivers/gpu/drm/bridge/dw-hdmi-audio.h 
> b/drivers/gpu/drm/bridge/dw-hdmi-audio.h
> index 91f631b..fd1f745 100644
> --- a/drivers/gpu/drm/bridge/dw-hdmi-audio.h
> +++ b/drivers/gpu/drm/bridge/dw-hdmi-audio.h
> @@ -11,4 +11,11 @@ struct dw_hdmi_audio_data {
>   u8 *eld;
>   };
>   
> +struct dw_hdmi_i2s_audio_data {
> + struct dw_hdmi *hdmi;
> +
> + void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
> + u8 (*read)(struct dw_hdmi *hdmi, int offset);
> +};
> +
>   #endif
> diff --git a/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c 
> b/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c
> new file mode 100644
> index 000..df1519c
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c
> @@ -0,0 +1,123 @@
> +/*
> + * dw-hdmi-i2s-audio.c
> + *
> + * Copyright (c) 2016 Kuninori Morimoto 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include 
> +
> +#include 
> +
> +#include "dw-hdmi.h"
> +#include "dw-hdmi-audio.h"
> +
> +#define DRIVER_NAME "dw-hdmi-i2s-audio"
> +
> +static inline void hdmi_write(struct dw_hdmi_i2s_audio_data *audio, u8 val, 
> int offset)
> +{
> + struct dw_hdmi *hdmi = audio->hdmi;
> +
> + audio->write(hdmi, val, offset);
> +}
> +
> +static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset)
> +{
> + struct dw_hdmi *hdmi = audio->hdmi;
> +
> + return audio->read(hdmi, offset);
> +}
> +
> +static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
> +  struct hdmi_codec_daifmt *fmt,
> +  struct hdmi_codec_params *hparms)
> +{
> + struct dw_hdmi_i2s_audio_data *audio = data;
> + struct dw_hdmi *hdmi = audio->hdmi;
> + u8 conf0 = 0;
> + u8 conf1 = 0;
> + u8 inputclkfs = 0;
> +
> + /* it cares I2S only */
> + if ((fmt->fmt != HDMI_I2S) ||
> + (fmt->bit_clk_master | fmt->frame_clk_master)) {
> + dev_err(dev, "unsupported format/settings\n");
> + return -EINVAL;
> + }
> +
> + inputclkfs  = HDMI_AUD_INPUTCLKFS_64FS;
> + conf0   = HDMI_AUD_CONF0_I2S_ALL_ENABLE;
> +
> + switch(hparms->sample_width) {
> + case 16:
> + conf1 = HDMI_AUD_CONF1_WIDTH_16;
> + break;
> + case 24:
> + case 32:
> + conf1 = HDMI_AUD_CONF1_WIDTH_24;
> + break;
> + }
> +
> + dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
> +
> + hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
> + hdmi_write(audio, conf0, HDMI_AUD_CONF0);
> + hdmi_write(audio, conf1, HDMI_AUD_CONF1);
> +
> + dw_hdmi_audio_enable(hdmi);
> +
> + return 

[Bug 92248] [KBL/SKL/BYT/BXT] igt/kms_plane_scaling fail

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92248

--- Comment #26 from Humberto Israel Perez Rodriguez 
 ---
The following tests cases fail with the next configuration

Tests cases

igt at kms_plane_scaling


Software information

Kernel version  :
4.7.0-rc4-drm-intel-nightly-ww26-commit-5c244f4+
Linux distribution  : Ubuntu 16.04 LTS
Architecture: 64-bit

Hardware information

Platform: BXT-P
Motherboard model   : Broxton P
Motherboard type: NOTEBOOK Hand Held
Motherboard manufacturer: Intel Corp.
CPU family  : B1
CPU information : 06/5c
GPU Card: Intel Corporation Device 5a84 (rev 0a)
(prog-if 00 [VGA controller])
Memory ram  : 16 GB

Firmwares information

DMC fw loaded   : yes
DMC version : 1.7
GUC fw loaded   : SUCCESS
GUC version wanted  : 8.7
GUC version found   : 8.7


 --> Component : drm 
 url : http://cgit.freedesktop.org/mesa/drm 
 tag : libdrm-2.4.68-9-g625d181 
 commit : 625d181 
 --> Component : cairo 
 url : http://cgit.freedesktop.org/cairo 
 tag : 1.15.2 
 commit : db8a7f1 
 --> Component : intel-gpu-tools 
 url : http://cgit.freedesktop.org/xorg/app/intel-gpu-tools 
 tag : intel-gpu-tools-1.15-54-g88c1f7c 
 commit : 88c1f7c 

Kernel information

commit 5c244f4b128c6274755007e080d46e0a61b71534
Author: Chris Wilson 
Date:   Fri Jun 24 16:17:56 2016 +0100

drm-intel-nightly: 2016y-06m-24d-15h-17m-32s UTC integration manifest

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[PATCH v4 11/11] dt-bindings: analogix_dp: rockchip: correct the wrong compatible name

[Yakir Yang]

The document about rockchip platform make a mistaken in available
compatible name of "rk3288-edp", we should correct it to "rk3288-dp"
which correspond to the compatible name in driver.

This mistaken was introduced in commit be91c36247089 ("dt-bindings:
add document for rockchip variant of analogix_dp").

Reported-by: Tomasz Figa 
Signed-off-by: Yakir Yang 
Reviewed-by: Douglas Anderson 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Add reviewed flag from Doug.
- Add reviewed flag from Tomasz.

Changes in v3:
- Add this patch in v3

 .../devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index 0b39256..01cced1 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -2,7 +2,7 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
 

 Required properties:
-- compatible: "rockchip,rk3288-edp",
+- compatible: "rockchip,rk3288-dp",
  "rockchip,rk3399-edp";

 - reg: physical base address of the controller and length
-- 
1.9.1

[PATCH v4 10/11] drm/rockchip: analogix_dp: introduce the pclk for grf

[Yakir Yang]

For RK3399's GRF module, if we want to operate the graphic related grf
registers, we need to enable the pclk_vio_grf which supply power for VIO
GRF IOs, so it's better to introduce an optional grf clock in driver.

Signed-off-by: Yakir Yang 
Reviewed-by: Douglas Anderson 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Add reviewed flag from Doug.
- Add reviewed flag from Tomasz.
- Fix compiled error, sorry.
  "dp->cgfclk"  -->  'dp->grfclk'
- Check the the error code properly, 'EPROBE_DEFER' should be returned,
  'ENOENT' should assign a NULL point to grfclk, other errors should be
  regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 249]
- Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at Google 
Gerrit)
[https://chromium-review.googlesource.com/#/c/351821/]

Changes in v3:
- Add this patch in v3

 .../display/rockchip/analogix_dp-rockchip.txt  |  6 ++
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c| 23 +++---
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index 726c945..0b39256 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -28,6 +28,12 @@ Required properties:
 Port 0: contained 2 endpoints, connecting to the output of vop.
 Port 1: contained 1 endpoint, connecting to the input of panel.

+Optional property for different chips:
+- clocks: from common clock binding: handle to grf_vio clock.
+
+- clock-names: from common clock binding:
+  Required elements: "grf"
+
 For the below properties, please refer to Analogix DP binding document:
  * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 - phys (required)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 850edc4..e81e19a 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -64,6 +64,7 @@ struct rockchip_dp_device {
struct drm_display_mode  mode;

struct clk   *pclk;
+   struct clk   *grfclk;
struct regmap*grf;
struct reset_control *rst;

@@ -160,11 +161,17 @@ static void rockchip_dp_drm_encoder_enable(struct 
drm_encoder *encoder)

dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

-   ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
-   if (ret != 0) {
-   dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+   ret = clk_prepare_enable(dp->grfclk);
+   if (ret < 0) {
+   dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
return;
}
+
+   ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
+   if (ret != 0)
+   dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+
+   clk_disable_unprepare(dp->grfclk);
 }

 static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
@@ -234,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
return PTR_ERR(dp->grf);
}

+   dp->grfclk = devm_clk_get(dev, "grf");
+   if (PTR_ERR(dp->grfclk) == -ENOENT) {
+   dp->grfclk = NULL;
+   } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
+   return -EPROBE_DEFER;
+   } else if (IS_ERR(dp->grfclk)) {
+   dev_err(dev, "failed to get grf clock\n");
+   return PTR_ERR(dp->grfclk);
+   }
+
dp->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(dp->pclk)) {
dev_err(dev, "failed to get pclk property\n");
-- 
1.9.1

[PATCH v4 09/11] drm/bridge: analogix_dp: fix no drm hpd event when panel plug in

[Yakir Yang]

The enum value of DP_IRQ_TYPE_HP_CABLE_IN is zero, but driver only
send drm hp event when the irq_type and the enum value is true.

if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN || ...)
drm_helper_hpd_irq_event(dp->drm_dev);

So there would no drm hpd event when cable plug in, to fix that
just need to assign all hotplug enum with no-zero values.

Reported-by: Dan Carpenter 
Signed-off-by: Yakir Yang 
Reviewed-by: Sean Paul 
Reviewed-by: Stéphane Marchesin 
Reviewed-by: Tomasz Figa 
Tested-by: Javier Martinez Canillas 
---
Changes in v4:
- Add reviewed flag from Sean.
- Add reviewed flag from Tomasz.

Changes in v3:
- Add reviewed flag from Stéphane.
[https://chromium-review.googlesource.com/#/c/346319/15]
- Add tested flag from Javier

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index f09275d..b456380 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -127,10 +127,10 @@ enum analog_power_block {
 };

 enum dp_irq_type {
-   DP_IRQ_TYPE_HP_CABLE_IN,
-   DP_IRQ_TYPE_HP_CABLE_OUT,
-   DP_IRQ_TYPE_HP_CHANGE,
-   DP_IRQ_TYPE_UNKNOWN,
+   DP_IRQ_TYPE_HP_CABLE_IN  = BIT(0),
+   DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),
+   DP_IRQ_TYPE_HP_CHANGE= BIT(2),
+   DP_IRQ_TYPE_UNKNOWN  = BIT(3),
 };

 struct video_info {
-- 
1.9.1

[PATCH v4 08/11] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode

[Yakir Yang]

The hardware IC designed that VOP must output the RGB10 video format to
eDP contoller, and if eDP panel only support RGB8, then eDP contoller
should cut down the video data, not via VOP contoller, that's why we need
to hardcode the VOP output mode to RGA10 here.

Signed-off-by: Yakir Yang 
Acked-by: Mark Yao 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Correct the misspell of 'contoller'. (Sean)

Changes in v3:
- Add the reviewed flag from Tomasz.
[https://chromium-review.googlesource.com/#/c/346853/12]
- Add the acked flag from Mark.

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 16 +---
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 0a0fb3a..850edc4 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -182,17 +182,11 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder 
*encoder,
int ret;

/*
-* FIXME(Yakir): driver should configure the CRTC output video
-* mode with the display information which indicated the monitor
-* support colorimetry.
-*
-* But don't know why the CRTC driver seems could only output the
-* RGBaaa rightly. For example, if connect the "innolux,n116bge"
-* eDP screen, EDID would indicated that screen only accepted the
-* 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
-* screen would show a blue picture (RGB888 show a green picture).
-* But if I configure CTRC to RGBaaa, and eDP driver still keep
-* RGB666 input video mode, then screen would works prefect.
+* The hardware IC designed that VOP must output the RGB10 video
+* format to eDP controller, and if eDP panel only support RGB8,
+* then eDP controller should cut down the video data, not via VOP
+* controller, that's why we need to hardcode the VOP output mode
+* to RGA10 here.
 */

s->output_mode = ROCKCHIP_OUT_MODE_;
-- 
1.9.1

[PATCH v4 07/11] drm/rockchip: analogix_dp: correct the connector display color format and bpc

[Yakir Yang]

Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we need to hack
it down to RGB888.

Signed-off-by: Yakir Yang 
Acked-by: Mark Yao 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Using mask variable to collect the YUV video format. (Sean)
- Add reviewed flag from Tomasz.

Changes in v3:
- Hook the connector's color_formats in .get_modes directly. (Tomasz, reviewed 
at Google Gerrit)
[https://chromium-review.googlesource.com/#/c/346317/15]
- Add the acked flag from Mark.

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 0755573..0a0fb3a 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -110,6 +110,23 @@ static int rockchip_dp_powerdown(struct 
analogix_dp_plat_data *plat_data)
return 0;
 }

+static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
+struct drm_connector *connector)
+{
+   struct drm_display_info *di = >display_info;
+   /* VOP couldn't output YUV video format for eDP rightly */
+   u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
+
+   if ((di->color_formats & mask)) {
+   DRM_DEBUG_KMS("Swapping display color format from YUV to 
RGB\n");
+   di->color_formats &= ~mask;
+   di->color_formats |= DRM_COLOR_FORMAT_RGB444;
+   di->bpc = 8;
+   }
+
+   return 0;
+}
+
 static bool
 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
   const struct drm_display_mode *mode,
@@ -310,6 +327,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
device *master,
dp->plat_data.dev_type = dp->data->chip_type;
dp->plat_data.power_on = rockchip_dp_poweron;
dp->plat_data.power_off = rockchip_dp_powerdown;
+   dp->plat_data.get_modes = rockchip_dp_get_modes;

return analogix_dp_bind(dev, dp->drm_dev, >plat_data);
 }
-- 
1.9.1

[PATCH v4 06/11] drm/bridge: analogix_dp: passing the connector as an argument in .get_modes()

[Yakir Yang]

It's better to pass the connector to platform driver in .get_modes()
callback, just like what the .get_modes() helper function designed.

Signed-off-by: Yakir Yang 
Reviewed-by: Sean Paul 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Add reviewed flag from Sean.
- Add reviewed flag from Tomasz.

Changes in v3:
- Avoid to change any internal driver state in .mode_valid interface. (Tomasz, 
reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346318/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 113]

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 +-
 drivers/gpu/drm/exynos/exynos_dp.c | 4 ++--
 include/drm/bridge/analogix_dp.h   | 3 ++-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7699597..a5e5ae4 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -938,7 +938,7 @@ int analogix_dp_get_modes(struct drm_connector *connector)
num_modes += drm_panel_get_modes(dp->plat_data->panel);

if (dp->plat_data->get_modes)
-   num_modes += dp->plat_data->get_modes(dp->plat_data);
+   num_modes += dp->plat_data->get_modes(dp->plat_data, connector);

return num_modes;
 }
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c 
b/drivers/gpu/drm/exynos/exynos_dp.c
index 468498e..8a555ed 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -67,10 +67,10 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data 
*plat_data)
return exynos_dp_crtc_clock_enable(plat_data, false);
 }

-static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data)
+static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
+  struct drm_connector *connector)
 {
struct exynos_dp_device *dp = to_dp(plat_data);
-   struct drm_connector *connector = >connector;
struct drm_display_mode *mode;
int num_modes = 0;

diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index fc4aea3..261b86d 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -34,7 +34,8 @@ struct analogix_dp_plat_data {
int (*power_off)(struct analogix_dp_plat_data *);
int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
  struct drm_connector *);
-   int (*get_modes)(struct analogix_dp_plat_data *);
+   int (*get_modes)(struct analogix_dp_plat_data *,
+struct drm_connector *);
 };

 int analogix_dp_resume(struct device *dev);
-- 
1.9.1

[PATCH v4 05/11] drm/rockchip: analogix_dp: make panel detect to an optional action

[Yakir Yang]

Some boards don't need to declare a panel device node, like the
display interface is DP monitors, so it's necessary to make the
panel detect to an optional action.

Signed-off-by: Yakir Yang 
Acked-by: Mark Yao 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Move of_node_put(panel_node) directly below of_drm_find_panel (Sean)
- Add reviewed flag from Tomasz

Changes in v3:
- Add the acked flag from Mark.

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 47 +++--
 1 file changed, 21 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 8557a08..0755573 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -329,38 +329,33 @@ static int rockchip_dp_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
struct device_node *panel_node, *port, *endpoint;
+   struct drm_panel *panel = NULL;
struct rockchip_dp_device *dp;
-   struct drm_panel *panel;

port = of_graph_get_port_by_id(dev->of_node, 1);
-   if (!port) {
-   dev_err(dev, "can't find output port\n");
-   return -EINVAL;
-   }
-
-   endpoint = of_get_child_by_name(port, "endpoint");
-   of_node_put(port);
-   if (!endpoint) {
-   dev_err(dev, "no output endpoint found\n");
-   return -EINVAL;
-   }
-
-   panel_node = of_graph_get_remote_port_parent(endpoint);
-   of_node_put(endpoint);
-   if (!panel_node) {
-   dev_err(dev, "no output node found\n");
-   return -EINVAL;
-   }
-
-   panel = of_drm_find_panel(panel_node);
-   if (!panel) {
-   DRM_ERROR("failed to find panel\n");
+   if (port) {
+   endpoint = of_get_child_by_name(port, "endpoint");
+   of_node_put(port);
+   if (!endpoint) {
+   dev_err(dev, "no output endpoint found\n");
+   return -EINVAL;
+   }
+
+   panel_node = of_graph_get_remote_port_parent(endpoint);
+   of_node_put(endpoint);
+   if (!panel_node) {
+   dev_err(dev, "no output node found\n");
+   return -EINVAL;
+   }
+
+   panel = of_drm_find_panel(panel_node);
of_node_put(panel_node);
-   return -EPROBE_DEFER;
+   if (!panel) {
+   DRM_ERROR("failed to find panel\n");
+   return -EPROBE_DEFER;
+   }
}

-   of_node_put(panel_node);
-
dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
if (!dp)
return -ENOMEM;
-- 
1.9.1

[PATCH v4 04/11] drm/rockchip: analogix_dp: add rk3399 eDP support

[Yakir Yang]

RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.

Signed-off-by: Yakir Yang 
Acked-by: Mark Yao 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Improved the overly complicated .atomic_check function. (Sean)
- Add reviewed flag from Tomasz

Changes in v3:
- Give the "rk3399-edp" a separate line for clarity in document (Tomasz, 
reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346314/10/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
 at 5]
- Move 'output_type' setting before the return statement (Tomasz, reviewed at 
Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346314/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 154]
- Add the acked flag from Mark.

 .../bindings/display/bridge/analogix_dp.txt|  1 +
 .../display/rockchip/analogix_dp-rockchip.txt  |  3 ++-
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c| 23 ++
 include/drm/bridge/analogix_dp.h   |  3 ++-
 4 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt 
b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
index 4f2ba8c..4a0f4f7 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -5,6 +5,7 @@ Required properties for dp-controller:
platform specific such as:
 * "samsung,exynos5-dp"
 * "rockchip,rk3288-dp"
+* "rockchip,rk3399-edp"
-reg:
physical base address of the controller and length
of memory mapped region.
diff --git 
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index e832ff9..726c945 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
 

 Required properties:
-- compatible: "rockchip,rk3288-edp";
+- compatible: "rockchip,rk3288-edp",
+ "rockchip,rk3399-edp";

 - reg: physical base address of the controller and length

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 0a30931..8557a08 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -36,6 +36,8 @@

 #define RK3288_GRF_SOC_CON60x25c
 #define RK3288_EDP_LCDC_SELBIT(5)
+#define RK3399_GRF_SOC_CON20   0x6250
+#define RK3399_EDP_LCDC_SELBIT(5)

 #define HIWORD_UPDATE(val, mask)   (val | (mask) << 16)

@@ -159,6 +161,8 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder 
*encoder,
  struct drm_connector_state *conn_state)
 {
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+   struct rockchip_dp_device *dp = to_dp(encoder);
+   int ret;

/*
 * FIXME(Yakir): driver should configure the CRTC output video
@@ -173,8 +177,19 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder 
*encoder,
 * But if I configure CTRC to RGBaaa, and eDP driver still keep
 * RGB666 input video mode, then screen would works prefect.
 */
+
s->output_mode = ROCKCHIP_OUT_MODE_;
s->output_type = DRM_MODE_CONNECTOR_eDP;
+   if (dp->data->chip_type == RK3399_EDP) {
+   /*
+* For RK3399, VOP Lit must code the out mode to RGB888,
+* VOP Big must code the out mode to RGB10.
+*/
+   ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
+   encoder);
+   if (ret > 0)
+   s->output_mode = ROCKCHIP_OUT_MODE_P888;
+   }

return 0;
 }
@@ -378,6 +393,13 @@ static const struct dev_pm_ops rockchip_dp_pm_ops = {
 #endif
 };

+static const struct rockchip_dp_chip_data rk3399_edp = {
+   .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
+   .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
+   .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
+   .chip_type = RK3399_EDP,
+};
+
 static const struct rockchip_dp_chip_data rk3288_dp = {
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
@@ -387,6 +409,7 @@ static const struct rockchip_dp_chip_data rk3288_dp = {

 static const struct of_device_id rockchip_dp_dt_ids[] = {
{.compatible = "rockchip,rk3288-dp", .data = _dp },
+   {.compatible = "rockchip,rk3399-edp", .data = 

[PATCH v4 03/11] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting

[Yakir Yang]

As vendor document indicate, when REF_CLK bit set 0, then DP
phy's REF_CLK should switch to 24M source clock.

But due to IC PHY layout mistaken, some chips need to flip this
bit(like RK3288), and unfortunately they didn't indicate in the
DP version register. That's why we have to make this little hack.

Signed-off-by: Yakir Yang 
Reviewed-by: Tomasz Figa 
Tested-by: Javier Martinez Canillas 
---
Changes in v4:
- Remove subdev_type number, and add 'is_rockchip(type)' helper function (Sean)
- Add reviewed flag from Tomasz.

Changes in v3:
- Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
  reg = ~reg & REF_CLK_MASK;  --->  reg ^= REF_CLK_MASK;

[https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 at 80]
- Add tested flag from Javier

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 12 
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h |  1 +
 include/drm/bridge/analogix_dp.h  |  5 +
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 49205ef..48030f0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -74,8 +74,12 @@ void analogix_dp_init_analog_param(struct analogix_dp_device 
*dp)
reg = SEL_24M | TX_DVDD_BIT_1_0625V;
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);

-   if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
-   writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+   if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
+   reg = REF_CLK_24M;
+   if (dp->plat_data->dev_type == RK3288_DP)
+   reg ^= REF_CLK_MASK;
+
+   writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
@@ -244,7 +248,7 @@ void analogix_dp_set_analog_power_down(struct 
analogix_dp_device *dp,
u32 reg;
u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;

-   if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+   if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
phy_pd_addr = ANALOGIX_DP_PD;

switch (block) {
@@ -448,7 +452,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
analogix_dp_reset_aux(dp);

/* Disable AUX transaction H/W retry */
-   if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+   if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
  AUX_HW_RETRY_COUNT_SEL(3) |
  AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 88d56ad..cdcc6c5 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -165,6 +165,7 @@
 /* ANALOGIX_DP_PLL_REG_1 */
 #define REF_CLK_24M(0x1 << 0)
 #define REF_CLK_27M(0x0 << 0)
+#define REF_CLK_MASK   (0x1 << 0)

 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 25afb31..790ab5d 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -18,6 +18,11 @@ enum analogix_dp_devtype {
RK3288_DP,
 };

+static inline bool is_rockchip(enum analogix_dp_devtype type)
+{
+   return type == RK3288_DP;
+}
+
 struct analogix_dp_plat_data {
enum analogix_dp_devtype dev_type;
struct drm_panel *panel;
-- 
1.9.1

[PATCH v4 02/11] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

[Yakir Yang]

There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Signed-off-by: Yakir Yang 
Reviewed-by: Sean Paul 
Reviewed-by: Tomasz Figa 
Tested-by: Javier Martinez Canillas 
---
Changes in v4:
- Add reviewed flag from Sean

Changes in v3:
- Add reviewed flag from Tomasz.
[https://chromium-review.googlesource.com/#/c/346315/15]
- Add tested flag from Javier

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 337912b..88d56ad 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -163,8 +163,8 @@
 #define HSYNC_POLARITY_CFG (0x1 << 0)

 /* ANALOGIX_DP_PLL_REG_1 */
-#define REF_CLK_24M(0x1 << 1)
-#define REF_CLK_27M(0x0 << 1)
+#define REF_CLK_24M(0x1 << 0)
+#define REF_CLK_27M(0x0 << 0)

 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
-- 
1.9.1

[PATCH v4 01/11] drm/rockchip: analogix_dp: split the lcdc select setting into device data

[Yakir Yang]

eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.

But different chips have different GRF register address, so we need to
create a device data to declare the GRF messages for each chips.

Signed-off-by: Yakir Yang 
Acked-by: Mark Yao 
Reviewed-by: Tomasz Figa 
---
Changes in v4:
- Assigned the GRF setting magic numbers to a #define that corresponds to
  a TRM name. (Sean & Heiko)
- Pass the chip type to device type directly. (Sean)
- Add reviewed flag from Tomasz.

Changes in v3:
- Write a kerneldoc-style comment explaining the chips data fields (Tomasz, 
reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 39]
- Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed at 
Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 382]
- Add acked flag from Mark.

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 49 -
 1 file changed, 39 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index c120172..0a30931 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -14,6 +14,7 @@

 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -33,13 +34,26 @@
 #include "rockchip_drm_drv.h"
 #include "rockchip_drm_vop.h"

+#define RK3288_GRF_SOC_CON60x25c
+#define RK3288_EDP_LCDC_SELBIT(5)
+
+#define HIWORD_UPDATE(val, mask)   (val | (mask) << 16)
+
 #define to_dp(nm)  container_of(nm, struct rockchip_dp_device, nm)

-/* dp grf register offset */
-#define GRF_SOC_CON60x025c
-#define GRF_EDP_LCD_SEL_MASKBIT(5)
-#define GRF_EDP_SEL_VOP_LIT BIT(5)
-#define GRF_EDP_SEL_VOP_BIG 0
+/**
+ * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
+ * @lcdsel_grf_reg: grf register offset of lcdc select
+ * @lcdsel_big: reg value of selecting vop big for eDP
+ * @lcdsel_lit: reg value of selecting vop little for eDP
+ * @chip_type: specific chip type
+ */
+struct rockchip_dp_chip_data {
+   u32 lcdsel_grf_reg;
+   u32 lcdsel_big;
+   u32 lcdsel_lit;
+   u32 chip_type;
+};

 struct rockchip_dp_device {
struct drm_device*drm_dev;
@@ -51,6 +65,8 @@ struct rockchip_dp_device {
struct regmap*grf;
struct reset_control *rst;

+   const struct rockchip_dp_chip_data *data;
+
struct analogix_dp_plat_data plat_data;
 };

@@ -119,13 +135,13 @@ static void rockchip_dp_drm_encoder_enable(struct 
drm_encoder *encoder)
return;

if (ret)
-   val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+   val = dp->data->lcdsel_lit;
else
-   val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+   val = dp->data->lcdsel_big;

dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

-   ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+   ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
if (ret != 0) {
dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
return;
@@ -246,6 +262,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
device *master,
void *data)
 {
struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+   const struct rockchip_dp_chip_data *dp_data;
struct drm_device *drm_dev = data;
int ret;

@@ -256,10 +273,15 @@ static int rockchip_dp_bind(struct device *dev, struct 
device *master,
 */
dev_set_drvdata(dev, NULL);

+   dp_data = of_device_get_match_data(dev);
+   if (!dp_data)
+   return -ENODEV;
+
ret = rockchip_dp_init(dp);
if (ret < 0)
return ret;

+   dp->data = dp_data;
dp->drm_dev = drm_dev;

ret = rockchip_dp_drm_create_encoder(dp);
@@ -270,7 +292,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
device *master,

dp->plat_data.encoder = >encoder;

-   dp->plat_data.dev_type = RK3288_DP;
+   dp->plat_data.dev_type = dp->data->chip_type;
dp->plat_data.power_on = rockchip_dp_poweron;
dp->plat_data.power_off = rockchip_dp_powerdown;

@@ -356,8 +378,15 @@ static const struct dev_pm_ops rockchip_dp_pm_ops = {
 #endif
 };

+static const struct rockchip_dp_chip_data rk3288_dp = {
+   .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
+   .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
+   .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
+   .chip_type = RK3288_DP,
+};
+
 static const struct of_device_id 

[PATCH 2/2] drm/vmwgfx: Add an option to change assumed FB bpp

[Sinclair Yeh]

Offer an option for advanced users who want larger modes at 16bpp.

This becomes necessary after the fix: "Work around mode set
failure in 2D VMs."  Without this patch, there would be no way
for existing advanced users to get to a high res mode.

Signed-off-by: Sinclair Yeh 
Reviewed-by: Thomas Hellstrom 
Cc: 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 5 +
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 1 +
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index fc9ad00..8d528fc 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -233,6 +233,7 @@ static int vmw_force_iommu;
 static int vmw_restrict_iommu;
 static int vmw_force_coherent;
 static int vmw_restrict_dma_mask;
+static int vmw_assume_16bpp;

 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 static void vmw_master_init(struct vmw_master *);
@@ -249,6 +250,8 @@ MODULE_PARM_DESC(force_coherent, "Force coherent TTM 
pages");
 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
+MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
+module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);


 static void vmw_print_capabilities(uint32_t capabilities)
@@ -660,6 +663,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned 
long chipset)
dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);

+   dev_priv->assume_16bpp = !!vmw_assume_16bpp;
+
dev_priv->enable_fb = enable_fbdev;

vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h 
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 1980e2a..89fb194 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -386,6 +386,7 @@ struct vmw_private {
spinlock_t hw_lock;
spinlock_t cap_lock;
bool has_dx;
+   bool assume_16bpp;

/*
 * VGA registers.
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 077f16d..e29da45 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1555,6 +1555,9 @@ int vmw_du_connector_fill_modes(struct drm_connector 
*connector,
int i;
u32 assumed_bpp = 4;

+   if (dev_priv->assume_16bpp)
+   assumed_bpp = 2;
+
if (dev_priv->active_display_unit == vmw_du_screen_target) {
max_width  = min(max_width,  dev_priv->stdu_max_width);
max_height = min(max_height, dev_priv->stdu_max_height);
-- 
2.7.4

[PATCH 1/2] drm/vmwgfx: Work around mode set failure in 2D VMs

[Sinclair Yeh]

In a low-memory 2D VM, fbdev can take up a large percentage of
available memory, making them unavailable for other DRM clients.

Since we do not take fbdev into account when filtering modes,
we end up claiming to support more modes than we actually do.

The current mode filtering mechanism keys off of
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB, i.e. the maximum amount
of surface memory we have.  Since this value is a performance
suggestion, not a hard limit, and since there should not be much
of a performance impact for a 2D VM, rather than filtering out
more modes, we will just allow ourselves to exceed the SVGA's
performance suggestion.

Also changed assumed bpp to 32 from 16 to make sure we can
actually support all the modes listed.

Signed-off-by: Sinclair Yeh 
Reviewed-by: Thomas Hellstrom 
Cc: 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 7 +++
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 9 +
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 9fcd820..fc9ad00 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -706,6 +706,13 @@ static int vmw_driver_load(struct drm_device *dev, 
unsigned long chipset)
vmw_read(dev_priv,
 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);

+   /*
+* Workaround for low memory 2D VMs to compensate for the
+* allocation taken by fbdev
+*/
+   if (!(dev_priv->capabilities & SVGA_CAP_3D))
+   mem_size *= 2;
+
dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
dev_priv->prim_bb_mem =
vmw_read(dev_priv,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 55231cc..077f16d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1553,14 +1553,7 @@ int vmw_du_connector_fill_modes(struct drm_connector 
*connector,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
};
int i;
-   u32 assumed_bpp = 2;
-
-   /*
-* If using screen objects, then assume 32-bpp because that's what the
-* SVGA device is assuming
-*/
-   if (dev_priv->active_display_unit == vmw_du_screen_object)
-   assumed_bpp = 4;
+   u32 assumed_bpp = 4;

if (dev_priv->active_display_unit == vmw_du_screen_target) {
max_width  = min(max_width,  dev_priv->stdu_max_width);
-- 
2.7.4

[PATCH 0/2] drm/vmwgfx: Fix various black screen issues

[Sinclair Yeh]

This series is to address various unrecoverable black screen
issues:  after mode set or during initial installation.  To work
around these issues, we have to be conservative about which
modes to make available.  This approach may potentially cause a
regression for advanced users who want higher-res modes at a lower
color format (bpp).

To prevent this regression, we introduced a new vmwgfx kernel
parameter.

Cc: 

[PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver

[Yakir Yang]

RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.

Also same misc fix to analogix_dp driver:
- Hotplug invalid which report by Dan Carpenter
- Make panel detect to an optional action
- correct the register bit define error in ANALOGIX_DP_PLL_REG_1

Changes in v4:
- Assigned the GRF setting magic numbers to a #define that corresponds to
  a TRM name. (Sean & Heiko)
- Pass the chip type to device type directly. (Sean)
- Add reviewed flag from Tomasz.
- Add reviewed flag from Sean
- Remove subdev_type number, and add 'is_rockchip(type)' helper function (Sean)
- Add reviewed flag from Tomasz.
- Improved the overly complicated .atomic_check function. (Sean)
- Add reviewed flag from Tomasz
- Move of_node_put(panel_node) directly below of_drm_find_panel (Sean)
- Add reviewed flag from Tomasz
- Add reviewed flag from Sean.
- Add reviewed flag from Tomasz.
- Using mask variable to collect the YUV video format. (Sean)
- Add reviewed flag from Tomasz.
- Correct the misspell of 'contoller'. (Sean)
- Add reviewed flag from Sean.
- Add reviewed flag from Tomasz.
- Add reviewed flag from Doug.
- Add reviewed flag from Tomasz.
- Fix compiled error, sorry.
  "dp->cgfclk"  -->  'dp->grfclk'
- Check the the error code properly, 'EPROBE_DEFER' should be returned,
  'ENOENT' should assign a NULL point to grfclk, other errors should be
  regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 249]
- Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at Google 
Gerrit)
[https://chromium-review.googlesource.com/#/c/351821/]
- Add reviewed flag from Doug.
- Add reviewed flag from Tomasz.

Changes in v3:
- Write a kerneldoc-style comment explaining the chips data fields (Tomasz, 
reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 39]
- Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed at 
Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 382]
- Add acked flag from Mark.
- Add reviewed flag from Tomasz.
[https://chromium-review.googlesource.com/#/c/346315/15]
- Add tested flag from Javier
- Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
  reg = ~reg & REF_CLK_MASK;  --->  reg ^= REF_CLK_MASK;

[https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 at 80]
- Add tested flag from Javier
- Give the "rk3399-edp" a separate line for clarity in document (Tomasz, 
reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346314/10/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
 at 5]
- Move 'output_type' setting before the return statement (Tomasz, reviewed at 
Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346314/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 154]
- Add the acked flag from Mark.
- Add the acked flag from Mark.
- Avoid to change any internal driver state in .mode_valid interface. (Tomasz, 
reviewed at Google Gerrit)

[https://chromium-review.googlesource.com/#/c/346318/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 at 113]
- Hook the connector's color_formats in .get_modes directly. (Tomasz, reviewed 
at Google Gerrit)
[https://chromium-review.googlesource.com/#/c/346317/15]
- Add the acked flag from Mark.
- Add the reviewed flag from Tomasz.
[https://chromium-review.googlesource.com/#/c/346853/12]
- Add the acked flag from Mark.
- Add reviewed flag from Stéphane.
[https://chromium-review.googlesource.com/#/c/346319/15]
- Add tested flag from Javier
- Add this patch in v3
- Add this patch in v3

Yakir Yang (11):
  drm/rockchip: analogix_dp: split the lcdc select setting into device
data
  drm/bridge: analogix_dp: correct the register bit define error in
ANALOGIX_DP_PLL_REG_1
  drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit
setting
  drm/rockchip: analogix_dp: add rk3399 eDP support
  drm/rockchip: analogix_dp: make panel detect to an optional action
  drm/bridge: analogix_dp: passing the connector as an argument in
.get_modes()
  drm/rockchip: analogix_dp: correct the connector display color format
and bpc
  drm/rockchip: analogix_dp: update the comments about why need to
hardcode VOP output mode
  drm/bridge: analogix_dp: fix no drm hpd event when panel plug in
  drm/rockchip: analogix_dp: introduce the pclk for grf
  dt-bindings: analogix_dp: rockchip: correct the wrong compatible name

 .../bindings/display/bridge/analogix_dp.txt|   1 +
 .../display/rockchip/analogix_dp-rockchip.txt  |   9 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c |   2 +-
 

[PATCH] drm/hisilicon: add select HISI_KIRIN_DW_DSI

[Xinliang Liu]

Hi,

On 22 June 2016 at 20:59, Thierry Reding  wrote:
> On Wed, Jun 22, 2016 at 08:54:02AM +0800, Guodong Xu wrote:
>> On 21 June 2016 at 21:34, Thierry Reding  wrote:
>> > On Mon, Jun 20, 2016 at 11:59:03AM +0800, Xinliang Liu wrote:
>> >> From: Guodong Xu 
>> >>
>> >> Add select HISI_KIRIN_DW_DSI to Kconfig.
>> >> The DRM driver depends on dsi sub-driver.
>> >>
>> >> Signed-off-by: Zoltan Kuscsik 
>> >> ---
>> >>  drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 +
>> >>  1 file changed, 1 insertion(+)
>> >
>> > You've got the Signed-off-by area messed up. If Guodong wrote this patch
>>
>> Hi, Xinliang,
>>
>> To clarify this, you don't need my Signed-off. Zoltan is the author,
>> and I am just the person who ever integrated that patch into my local
>> tree.
>
> If Zoltan is the author, then his name should be in the From: line
> above. As it is, git am will apply this with you as author. Also, see
> section 11) in Documentation/SubmittingPatches on why you need to add
> your S-o-b as well.

Thierry, that's right. I will resent the patch in the author of zoltan
and adding my s-o-b.

Thanks,
-xinliang

>
> Thierry

[PATCH] drm: mediatek: fix prototypes after API change

[Arnd Bergmann]

The newly added mediatek HDMI driver clashes with an API change
for struct hdmi_codec_ops, causing an 'allmodconfig' build to fail:

drivers/gpu/drm/mediatek/mtk_hdmi.c:1653:15: error: initialization from 
incompatible pointer type [-Werror=incompatible-pointer-types]
drivers/gpu/drm/mediatek/mtk_hdmi.c:1654:19: error: initialization from 
incompatible pointer type [-Werror=incompatible-pointer-types]
drivers/gpu/drm/mediatek/mtk_hdmi.c:1655:20: error: initialization from 
incompatible pointer type [-Werror=incompatible-pointer-types]
drivers/gpu/drm/mediatek/mtk_hdmi.c:1656:18: error: initialization from 
incompatible pointer type [-Werror=incompatible-pointer-types]
drivers/gpu/drm/mediatek/mtk_hdmi.c:1657:13: error: initialization from 
incompatible pointer type [-Werror=incompatible-pointer-types]

This changes the API accordingly for the mediatek driver.

Signed-off-by: Arnd Bergmann 
Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Fixes: efc9194bcff8 ("ASoC: hdmi-codec: callback function will be called with 
private data")
---
The new driver is currently part of Dave Airlie's drm-next tree,
while the API change is in Mark Brown's asoc-next tree, so my
fix has to be done on top of both.

I can see two ways out of this:

a) Stephen Rothwell could add my fixup on top of linux-next
   as a merge fix, and the fix gets sent to Linus Torvalds along
   with the second of the two branches

b) efc9194bcff8 gets merged into drm-next along with my change
   in the merge commit. It is currently a standalone patch
   in its own branch in the ASoC tree.
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c 
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index ba812ef2c9d1..334562d06731 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1535,7 +1535,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
  * HDMI audio codec callbacks
  */

-static int mtk_hdmi_audio_hw_params(struct device *dev,
+static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
struct hdmi_codec_daifmt *daifmt,
struct hdmi_codec_params *params)
 {
@@ -1604,7 +1604,7 @@ static int mtk_hdmi_audio_hw_params(struct device *dev,
return 0;
 }

-static int mtk_hdmi_audio_startup(struct device *dev)
+static int mtk_hdmi_audio_startup(struct device *dev, void *data)
 {
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);

@@ -1615,7 +1615,7 @@ static int mtk_hdmi_audio_startup(struct device *dev)
return 0;
 }

-static void mtk_hdmi_audio_shutdown(struct device *dev)
+static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
 {
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);

@@ -1624,7 +1624,7 @@ static void mtk_hdmi_audio_shutdown(struct device *dev)
mtk_hdmi_audio_disable(hdmi);
 }

-int mtk_hdmi_audio_digital_mute(struct device *dev, bool enable)
+int mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
 {
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);

@@ -1638,7 +1638,7 @@ int mtk_hdmi_audio_digital_mute(struct device *dev, bool 
enable)
return 0;
 }

-static int mtk_hdmi_audio_get_eld(struct device *dev, uint8_t *buf, size_t len)
+static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t 
*buf, size_t len)
 {
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);

-- 
2.9.0

Congrats AMD-Team! --- RX480 + Mesa-git + 4.7-rcX

[Dieter Nützel]

Well done!

Best wishes.

Dieter

[PATCH v2 2/2] drm/fsl-dcu: update panel syntax to of_graph dt binding

[Meng Yi]

add of_graph dt binding for panel, and "fsl,panel" property
is deprecated

Signed-off-by: Meng Yi 
---
Changes in V2:
-dropp the unit address of port
---
 arch/arm/boot/dts/ls1021a-twr.dts | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/ls1021a-twr.dts 
b/arch/arm/boot/dts/ls1021a-twr.dts
index 75ecaed..cbd92c8 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -108,12 +108,22 @@

panel: panel {
compatible = "nec,nl4827hc19-05b";
+   port {
+   panel_out: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
};
 };

  {
-   fsl,panel = <>;
status = "okay";
+
+   port: port {
+   dcu_out: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
 };

  {
-- 
2.1.0.27.g96db324

[PATCH v2 1/2] drm/fsl-dcu: update the panel dt binding document

[Meng Yi]

dropped the old "fsl,panel" property, using the of_graph dt
binding syntax

Signed-off-by: Meng Yi 
---
Changes in V2:
-drop the unit address of port
---
 Documentation/devicetree/bindings/display/fsl,dcu.txt | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt 
b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ae55cde..c96ec1f 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -12,7 +12,7 @@ Required properties:
 - clock-names: Should be "dcu" and "pix"
See ../clocks/clock-bindings.txt for details.
 - big-endian   Boolean property, LS1021A DCU registers are big-endian.
-- fsl,panel:   The phandle to panel node.
+- port Video port for the panel output

 Optional properties:
 - fsl,tcon:The phandle to the timing controller node.
@@ -24,6 +24,11 @@ dcu: dcu at 2ce {
clocks = <_clk 0>, <_clk 0>;
clock-names = "dcu", "pix";
big-endian;
-   fsl,panel = <>;
fsl,tcon = <>;
+
+   port: port {
+   dcu_out: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
 };
-- 
2.1.0.27.g96db324

[PATCH v3 04/10] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting

[Yakir Yang]

Sean,

On 06/23/2016 09:27 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang  wrote:
>> As vendor document indicate, when REF_CLK bit set 0, then DP
>> phy's REF_CLK should switch to 24M source clock.
>>
>> But due to IC PHY layout mistaken, some chips need to flip this
>> bit(like RK3288), and unfortunately they didn't indicate in the
>> DP version register. That's why we have to make this little hack.
>>
>> Signed-off-by: Yakir Yang 
>> Tested-by: Javier Martinez Canillas 
>> ---
>> Changes in v3:
>> - Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
>>reg = ~reg & REF_CLK_MASK;  --->  reg ^= REF_CLK_MASK;
>>  
>> [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>>  at 80]
>> - Add tested flag from Javier
>>
>> Changes in v2:
>> - new patch in v2
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 6 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 1 +
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c   | 3 +++
>>   include/drm/bridge/analogix_dp.h  | 5 +
>>   4 files changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c 
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index 931a76c..97ced6b 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -75,7 +75,11 @@ void analogix_dp_init_analog_param(struct 
>> analogix_dp_device *dp)
>>  writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
>>
>>  if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP)) {
>> -   writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
>> +   reg = REF_CLK_24M;
>> +   if (dp->plat_data->subdev_type == RK3288_DP)
>> +   reg ^= REF_CLK_MASK;
>> +
>> +   writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
>>  writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
>>  writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
>>  writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h 
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> index 88d56ad..cdcc6c5 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> @@ -165,6 +165,7 @@
>>   /* ANALOGIX_DP_PLL_REG_1 */
>>   #define REF_CLK_24M(0x1 << 0)
>>   #define REF_CLK_27M(0x0 << 0)
>> +#define REF_CLK_MASK   (0x1 << 0)
>>
>>   /* ANALOGIX_DP_LANE_MAP */
>>   #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> index 3855f46..315ebba 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -46,6 +46,7 @@ struct rockchip_dp_chip_data {
>>  u32 lcdsel_grf_reg;
>>  u32 lcdsel_big;
>>  u32 lcdsel_lit;
>> +   u32 chip_type;
>>   };
>>
>>   struct rockchip_dp_device {
>> @@ -286,6 +287,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
>> device *master,
>>  dp->plat_data.encoder = >encoder;
>>
>>  dp->plat_data.dev_type = ROCKCHIP_DP;
>> +   dp->plat_data.subdev_type = dp_data->chip_type;
>>  dp->plat_data.power_on = rockchip_dp_poweron;
>>  dp->plat_data.power_off = rockchip_dp_powerdown;
>>
>> @@ -384,6 +386,7 @@ static const struct rockchip_dp_chip_data rk3288_dp = {
>>  .lcdsel_grf_reg = 0x025c,
>>  .lcdsel_big = 0 | BIT(21),
>>  .lcdsel_lit = BIT(5) | BIT(21),
>> +   .chip_type = RK3288_DP,
>>   };
>>
>>   static const struct of_device_id rockchip_dp_dt_ids[] = {
>> diff --git a/include/drm/bridge/analogix_dp.h 
>> b/include/drm/bridge/analogix_dp.h
>> index 9e5d013..06c0250 100644
>> --- a/include/drm/bridge/analogix_dp.h
>> +++ b/include/drm/bridge/analogix_dp.h
>> @@ -18,8 +18,13 @@ enum analogix_dp_devtype {
>>  ROCKCHIP_DP,
>>   };
>>
>> +enum analogix_dp_sub_devtype {
>> +   RK3288_DP,
>> +};
>> +
>>   struct analogix_dp_plat_data {
>>  enum analogix_dp_devtype dev_type;
>> +   enum analogix_dp_sub_devtype subdev_type;
>
> So this is what I was talking about in my review of the first patch of
> the series.
>
> I don't personally think the dev and subdev types add any clarity
> here, just more state. I'd prefer that you put the product number in
> the top level devtype, and add a helper function like:
>
> static bool is_rockchip(enum analogix_dp_devtype type) {
>return type == ... || type == ...
> }

Good idea, done.

Thanks,
- Yakir

> Sean
>
>>  struct drm_panel *panel;
>>  struct drm_encoder 

[PATCH v3 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

[Yakir Yang]

Sean,

On 06/23/2016 10:33 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang  wrote:
>> There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
>> by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
>> registers setting").
>>
>> The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
>> BIT 0, not BIT 1.
>>
>> Signed-off-by: Yakir Yang 
>> Reviewed-by: Tomasz Figa 
>> Tested-by: Javier Martinez Canillas 
> Reviewed-by: Sean Paul 

Thanks

>> ---
>> Changes in v3:
>> - Add reviewed flag from Tomasz.
>>  [https://chromium-review.googlesource.com/#/c/346315/15]
>> - Add tested flag from Javier
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h 
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> index 337912b..88d56ad 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> @@ -163,8 +163,8 @@
>>   #define HSYNC_POLARITY_CFG (0x1 << 0)
>>
>>   /* ANALOGIX_DP_PLL_REG_1 */
>> -#define REF_CLK_24M(0x1 << 1)
>> -#define REF_CLK_27M(0x0 << 1)
>> +#define REF_CLK_24M(0x1 << 0)
>> +#define REF_CLK_27M(0x0 << 0)
>>
>>   /* ANALOGIX_DP_LANE_MAP */
>>   #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
>> --
>> 1.9.1
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>

[PATCH v3 02/10] drm/rockchip: analogix_dp: split the lcdc select setting into device data[Involving remittance information, please pay attention to the safety of property]

[Yakir Yang]

Heiko & Sean

On 06/24/2016 12:16 AM, Heiko Stuebner wrote:
> Am Donnerstag, 23. Juni 2016, 10:32:53 schrieb Sean Paul:
>> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang  wrote:
>>> eDP controller need to declare which vop provide the video source,
>>> and it's defined in GRF registers.
>>>
>>> But different chips have different GRF register address, so we need to
>>> create a device data to declare the GRF messages for each chips.
>>>
>>> Signed-off-by: Yakir Yang 
>>> Acked-by: Mark Yao 
>>> ---
>>> Changes in v3:
>>> - Write a kerneldoc-style comment explaining the chips data fields
>>> (Tomasz, reviewed at Google Gerrit)>
>>>  [https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/
>>>  drm/rockchip/analogix_dp-rockchip.c at 39]>
>>> - Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed
>>> at Google Gerrit)>
>>>  [https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/
>>>  drm/rockchip/analogix_dp-rockchip.c at 382]>
>>> - Add acked flag from Mark.
>>>
>>> Changes in v2: None
>>>
>>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 39
>>>   +++-- 1 file changed, 30 insertions(+), 9
>>>   deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index
>>> 2bc8a7e..3855f46 100644
>>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> @@ -14,6 +14,7 @@
>>>
>>>   #include 
>>>   #include 
>>>
>>> +#include 
>>>
>>>   #include 
>>>   #include 
>>>   #include 
>>>
>>> @@ -35,11 +36,17 @@
>>>
>>>   #define to_dp(nm)  container_of(nm, struct rockchip_dp_device, nm)
>>>
>>> -/* dp grf register offset */
>>> -#define GRF_SOC_CON60x025c
>>> -#define GRF_EDP_LCD_SEL_MASKBIT(5)
>>> -#define GRF_EDP_SEL_VOP_LIT BIT(5)
>>> -#define GRF_EDP_SEL_VOP_BIG 0
>>> +/**
>>> + * struct rockchip_dp_chip_data - splite the grf setting of kind of
>>> chips + * @lcdsel_grf_reg: grf register offset of lcdc select
>>> + * @lcdsel_big: reg value of selecting vop big for eDP
>>> + * @lcdsel_lit: reg value of selecting vop little for eDP
>>> + */
>>> +struct rockchip_dp_chip_data {
>>> +   u32 lcdsel_grf_reg;
>>> +   u32 lcdsel_big;
>>> +   u32 lcdsel_lit;
>>> +};
>>>
>>>   struct rockchip_dp_device {
>>>   
>>>  struct drm_device*drm_dev;
>>>
>>> @@ -51,6 +58,8 @@ struct rockchip_dp_device {
>>>
>>>  struct regmap*grf;
>>>  struct reset_control *rst;
>>>
>>> +   const struct rockchip_dp_chip_data *data;
>>> +
>>>
>>>  struct analogix_dp_plat_data plat_data;
>>>   
>>>   };
>>>
>>> @@ -119,13 +128,13 @@ static void rockchip_dp_drm_encoder_enable(struct
>>> drm_encoder *encoder)>
>>>  return;
>>>  
>>>  if (ret)
>>>
>>> -   val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK <<
>>> 16);
>>> +   val = dp->data->lcdsel_lit;
>>>
>>>  else
>>>
>>> -   val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK <<
>>> 16);
>>> +   val = dp->data->lcdsel_big;
>>>
>>>  dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" :
>>>  "BIG");
>>>
>>> -   ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
>>> +   ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
>>>
>>>  if (ret != 0) {
>>>  
>>>  dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
>>>  return;
>>>
>>> @@ -246,6 +255,7 @@ static int rockchip_dp_bind(struct device *dev,
>>> struct device *master,>
>>>  void *data)
>>>   
>>>   {
>>>   
>>>  struct rockchip_dp_device *dp = dev_get_drvdata(dev);
>>>
>>> +   const struct rockchip_dp_chip_data *dp_data;
>>>
>>>  struct drm_device *drm_dev = data;
>>>  int ret;
>>>
>>> @@ -256,10 +266,15 @@ static int rockchip_dp_bind(struct device *dev,
>>> struct device *master,>
>>>   */
>>>  
>>>  dev_set_drvdata(dev, NULL);
>>>
>>> +   dp_data = of_device_get_match_data(dev);
>>> +   if (!dp_data)
>>> +   return -ENODEV;
>>> +
>>>
>>>  ret = rockchip_dp_init(dp);
>>>  if (ret < 0)
>>>  
>>>  return ret;
>>>
>>> +   dp->data = dp_data;
>>>
>>>  dp->drm_dev = drm_dev;
>>>  
>>>  ret = rockchip_dp_drm_create_encoder(dp);
>>>
>>> @@ -365,8 +380,14 @@ static const struct dev_pm_ops rockchip_dp_pm_ops =
>>> {>
>>>  SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
>>>   
>>>   };
>>>
>>> +static const struct rockchip_dp_chip_data rk3288_dp = {
>>> +   .lcdsel_grf_reg = 0x025c,
>>> +   .lcdsel_big = 0 | BIT(21),
>>> +   .lcdsel_lit = BIT(5) | BIT(21),
>> I'm not sure what convention is in other drivers, but 

[PATCH v3 1/2] drm/panel: simple: Add support for Sharp LQ101K1LY04

[Joshua Clayton]

Thierry, David,
Can these patches be pulled in?
Do I need anything additional?
the Documentation bit has been Acked by Rob Herring.

On 06/01/2016 08:35 AM, Joshua Clayton wrote:
> Trivial patch to add Sharp LQ101K1LY04i to simple-panel
>
> Support the Sharp LQ101K1LY04i, a 10 inch WXGA (1280x800) lvds panel.
>
> Signed-off-by: Joshua Clayton 
> ---
>
>  This trivial addition and its documenatation patch was reviewed for 4.5;
>  the only problems then were alphabetization. 
>
>  They slipped through the cracks and I haven't had the time to rebase and
>  repost them until now. hopefully we can get these into 4.8?
>
>  drivers/gpu/drm/panel/panel-simple.c | 27 +++
>  1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c 
> b/drivers/gpu/drm/panel/panel-simple.c
> index 3a7bdf1..c2d377c 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1270,6 +1270,30 @@ static const struct panel_desc samsung_ltn140at29_301 
> = {
>   },
>  };
>  
> +static const struct display_timing sharp_lq101k1ly04_timing = {
> + .pixelclock = { 6000, 6500, 8000 },
> + .hactive = { 1280, 1280, 1280 },
> + .hfront_porch = { 20, 20, 20 },
> + .hback_porch = { 20, 20, 20 },
> + .hsync_len = { 10, 10, 10 },
> + .vactive = { 800, 800, 800 },
> + .vfront_porch = { 4, 4, 4 },
> + .vback_porch = { 4, 4, 4 },
> + .vsync_len = { 4, 4, 4 },
> + .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
> +};
> +
> +static const struct panel_desc sharp_lq101k1ly04 = {
> + .timings = _lq101k1ly04_timing,
> + .num_timings = 1,
> + .bpc = 8,
> + .size = {
> + .width = 217,
> + .height = 136,
> + },
> + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
> +};
> +
>  static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
>   .clock = 33300,
>   .hdisplay = 800,
> @@ -1487,6 +1511,9 @@ static const struct of_device_id platform_of_match[] = {
>   .compatible = "samsung,ltn140at29-301",
>   .data = _ltn140at29_301,
>   }, {
> + .compatible = "sharp,lq101k1ly04",
> + .data = _lq101k1ly04,
> + }, {
>   .compatible = "shelly,sca07010-bfn-lnn",
>   .data = _sca07010_bfn_lnn,
>   }, {

[Bug 13170] Macbook 5,2 only boots with acpi=off, or nosmp, or maxcpus=1

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=13170

--- Comment #72 from morten vermund  ---
(In reply to Francisco from comment #63)
> Hi, I've been following this bug for a while since I've a macbook 5,2. I've
> been able to use linux (ubuntu) with refit+grub-efi+nvidia driver for a
> while. Last week I reinstalled everything, Snow Leopard, Win7 and Ubuntu
> natty, everything works PERFECT using the same approach.
> 
> Today, I've upgraded the RAM, from 2 to 4 Gigs (removed 2x1Gb and put
> 2x2Gb). Linux doesn't boot anymore with refit+grub-efi, only using maxcpus=1
> or acpi=off (still with Nvidia). The ram is OK, passes memtest86+, and win
> and snow leopard work without any problem. If I remove ANY one of the memory
> chips (1x2Gb 800Mhz) linux can boot again with grub-efi.
> 
> I guess this is probably a problem of grub-efi, but as it is related I
> wanted to post it here, sorry if it's the wrong place.
> 
> Here you can see the boot error from grub-efi when booting with 4Gb.
> http://www.billigalaan.se
> 
> Please let me know if you want me to test anything in particular.
> I have Natty with Nvidia 270.41.06, with uname -r: 2.6.38-10-generic
> 
> Sadly now I have to give up one CORE for 2gb of extra RAM :(
> 
> Thanks!
> Francisco

-- 
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[PATCH] drm/msm/mdp5: Remove "pipe < 0" check

[Vedran Miletić]

From: David Binderman 

For usingned int pipe, pipe < 0 is always true.
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 484b4d1..352b7ad 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -542,7 +542,7 @@ static int mdp5_get_vblank_timestamp(struct drm_device 
*dev, unsigned int pipe,
struct msm_drm_private *priv = dev->dev_private;
struct drm_crtc *crtc;

-   if (pipe < 0 || pipe >= priv->num_crtcs) {
+   if (pipe >= priv->num_crtcs) {
DRM_ERROR("Invalid crtc %d\n", pipe);
return -EINVAL;
}
@@ -564,7 +564,7 @@ static u32 mdp5_get_vblank_counter(struct drm_device *dev, 
unsigned int pipe)
struct drm_crtc *crtc;
struct drm_encoder *encoder;

-   if (pipe < 0 || pipe >= priv->num_crtcs)
+   if (pipe >= priv->num_crtcs)
return 0;

crtc = priv->crtcs[pipe];
-- 
2.8.1

[PATCH] drm/msm/mdp5: Remove "pipe < 0" check

[Vedran Miletić]

From: David Binderman 

For usingned int pipe, pipe < 0 is always true.
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 484b4d1..352b7ad 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -542,7 +542,7 @@ static int mdp5_get_vblank_timestamp(struct drm_device 
*dev, unsigned int pipe,
struct msm_drm_private *priv = dev->dev_private;
struct drm_crtc *crtc;

-   if (pipe < 0 || pipe >= priv->num_crtcs) {
+   if (pipe >= priv->num_crtcs) {
DRM_ERROR("Invalid crtc %d\n", pipe);
return -EINVAL;
}
@@ -564,7 +564,7 @@ static u32 mdp5_get_vblank_counter(struct drm_device *dev, 
unsigned int pipe)
struct drm_crtc *crtc;
struct drm_encoder *encoder;

-   if (pipe < 0 || pipe >= priv->num_crtcs)
+   if (pipe >= priv->num_crtcs)
return 0;

crtc = priv->crtcs[pipe];
-- 
2.8.1

[PATCH v3 06/10] drm/rockchip: analogix_dp: make panel detect to an optional action

[Yakir Yang]

Sean,

On 06/23/2016 10:10 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang  wrote:
>> Some boards don't need to declare a panel device node, like the
>> display interface is DP monitors, so it's necessary to make the
>> panel detect to an optional action.
>>
>> Signed-off-by: Yakir Yang 
>> Acked-by: Mark Yao 
>> ---
>> Changes in v3:
>> - Add the acked flag from Mark.
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 48 
>> -
>>   1 file changed, 22 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> index bcd9ecc..da2e844 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -332,38 +332,34 @@ static int rockchip_dp_probe(struct platform_device 
>> *pdev)
>>   {
>>  struct device *dev = >dev;
>>  struct device_node *panel_node, *port, *endpoint;
>> +   struct drm_panel *panel = NULL;
>>  struct rockchip_dp_device *dp;
>> -   struct drm_panel *panel;
>>
>>  port = of_graph_get_port_by_id(dev->of_node, 1);
>> -   if (!port) {
>> -   dev_err(dev, "can't find output port\n");
>> -   return -EINVAL;
>> -   }
>> -
>> -   endpoint = of_get_child_by_name(port, "endpoint");
>> -   of_node_put(port);
>> -   if (!endpoint) {
>> -   dev_err(dev, "no output endpoint found\n");
>> -   return -EINVAL;
>> -   }
>> -
>> -   panel_node = of_graph_get_remote_port_parent(endpoint);
>> -   of_node_put(endpoint);
>> -   if (!panel_node) {
>> -   dev_err(dev, "no output node found\n");
>> -   return -EINVAL;
>> -   }
>> -
>> -   panel = of_drm_find_panel(panel_node);
>> -   if (!panel) {
>> -   DRM_ERROR("failed to find panel\n");
>> +   if (port) {
>> +   endpoint = of_get_child_by_name(port, "endpoint");
>> +   of_node_put(port);
>> +   if (!endpoint) {
>> +   dev_err(dev, "no output endpoint found\n");
>> +   return -EINVAL;
>> +   }
>> +
>> +   panel_node = of_graph_get_remote_port_parent(endpoint);
>> +   of_node_put(endpoint);
>> +   if (!panel_node) {
>> +   dev_err(dev, "no output node found\n");
>> +   return -EINVAL;
>> +   }
>> +
>> +   panel = of_drm_find_panel(panel_node);
>> +   if (!panel) {
>> +   DRM_ERROR("failed to find panel\n");
>> +   of_node_put(panel_node);
>> +   return -EPROBE_DEFER;
>> +   }
>>  of_node_put(panel_node);
> Minor nit: Move of_node_put(panel_node) directly below
> of_drm_find_panel to avoid duplicating it in both error and normal
> paths (like you've done above).

Yep, done.

Thanks,
- Yakir

> Sean
>
>> -   return -EPROBE_DEFER;
>>  }
>>
>> -   of_node_put(panel_node);
>> -
>>  dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>>  if (!dp)
>>  return -ENOMEM;
>> --
>> 1.9.1
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>

[PATCH v3 09/10] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode

[Yakir Yang]

Sean,

On 06/23/2016 10:22 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang  wrote:
>> The hardware IC designed that VOP must output the RGB10 video format to
>> eDP contoller, and if eDP panel only support RGB8, then eDP contoller
>> should cut down the video data, not via VOP contoller, that's why we need
>> to hardcode the VOP output mode to RGA10 here.
>>
>> Signed-off-by: Yakir Yang 
>> Acked-by: Mark Yao 
>> Reviewed-by: Tomasz Figa 
>> ---
>> Changes in v3:
>> - Add the reviewed flag from Tomasz.
>>  [https://chromium-review.googlesource.com/#/c/346853/12]
>> - Add the acked flag from Mark.
>>
>> Changes in v2:
>> - new patch in v2
>>
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 16 +---
>>   1 file changed, 5 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> index 95a6f60..2ceb3f9 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -173,17 +173,11 @@ rockchip_dp_drm_encoder_atomic_check(struct 
>> drm_encoder *encoder,
>>  int ret;
>>
>>  /*
>> -* FIXME(Yakir): driver should configure the CRTC output video
>> -* mode with the display information which indicated the monitor
>> -* support colorimetry.
>> -*
>> -* But don't know why the CRTC driver seems could only output the
>> -* RGBaaa rightly. For example, if connect the "innolux,n116bge"
>> -* eDP screen, EDID would indicated that screen only accepted the
>> -* 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
>> -* screen would show a blue picture (RGB888 show a green picture).
>> -* But if I configure CTRC to RGBaaa, and eDP driver still keep
>> -* RGB666 input video mode, then screen would works prefect.
>> +* The hardware IC designed that VOP must output the RGB10 video
>> +* format to eDP contoller, and if eDP panel only support RGB8,
>> +* then eDP contoller should cut down the video data, not via VOP
>> +* contoller, that's why we need to hardcode the VOP output mode
>> +* to RGA10 here.
> s/contoller/controller/
>

Done,

>>   */
>>
>>  ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
>> --
>> 1.9.1
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>

[PATCH v3 08/10] drm/rockchip: analogix_dp: correct the connector display color format and bpc

[Yakir Yang]

Sean,

On 06/23/2016 10:19 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang  wrote:
>> Rockchip VOP couldn't output YUV video format for eDP controller, so
>> when driver detect connector support YUV video format, we need to hack
>> it down to RGB888.
>>
>> Signed-off-by: Yakir Yang 
>> Acked-by: Mark Yao 
>> ---
>> Changes in v3:
>> - Hook the connector's color_formats in .get_modes directly. (Tomasz, 
>> reviewed at Google Gerrit)
>>  [https://chromium-review.googlesource.com/#/c/346317/15]
>> - Add the acked flag from Mark.
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 17 +
>>   1 file changed, 17 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> index da2e844..95a6f60 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -102,6 +102,22 @@ static int rockchip_dp_powerdown(struct 
>> analogix_dp_plat_data *plat_data)
>>  return 0;
>>   }
>>
>> +static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>> +struct drm_connector *connector)
>> +{
>> +   struct drm_display_info *di = >display_info;
>> +
>> +   if (di->color_formats & DRM_COLOR_FORMAT_YCRCB444 ||
>> +   di->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
>> +   di->color_formats &= ~(DRM_COLOR_FORMAT_YCRCB422 |
>> +  DRM_COLOR_FORMAT_YCRCB444);
>> +   di->color_formats |= DRM_COLOR_FORMAT_RGB444;
>> +   di->bpc = 8;
> Probably a stupid question, but are you guaranteed that the panel will
> support this color format?

Hmm... I'm not sure, but it works on my several panels. I guess RGB is 
more common then YUV, so if panel support YUV format, it should support 
RGB888 too.

>> +   }
>> +
> I think this can be simplified as follows:
>
> /* A comment here about why we're doing this */
> u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
> if ((di->color_formats & mask)) {
>  DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
>  di->color_formats &= ~mask;
>  di->color_formats |= DRM_COLOR_FORMAT_RGB444;
>  di->bpc = 8;
> }

Done, good idea.

Thanks,
- Yakir

>> +   return 0;
>> +}
>> +
>>   static bool
>>   rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
>> const struct drm_display_mode *mode,
>> @@ -313,6 +329,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
>> device *master,
>>  dp->plat_data.subdev_type = dp_data->chip_type;
>>  dp->plat_data.power_on = rockchip_dp_poweron;
>>  dp->plat_data.power_off = rockchip_dp_powerdown;
>> +   dp->plat_data.get_modes = rockchip_dp_get_modes;
>>
>>  return analogix_dp_bind(dev, dp->drm_dev, >plat_data);
>>   }
>> --
>> 1.9.1
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>

[Bug 96588] [regression] [amdgpu] Errors scheduling IBs

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=96588

Vedran Miletić  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #16 from Vedran Miletić  ---
Marking as resolved per comment #15 and
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.8-wip=ce774d0254ed05ff6d3e3ce2c598aa4f79d45c3c

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[PATCH V2 06/11] dt-bindings: i2c: Add support for 'i2c-bus' subnode

[Wolfram Sang]

On Wed, Jun 29, 2016 at 10:17:52AM +0100, Jon Hunter wrote:
> The I2C driver core for boards using device-tree assumes any subnode of
> an I2C adapter in the device-tree blob is an I2C slave device. Although
> this makes complete sense, some I2C adapters may have subnodes which
> are not I2C slaves but subnodes presenting other features. For example
> some Tegra devices have an I2C interface which may share its pins with
> other devices. In order to share these pins using the pinctrl framework,
> it is necessary to add subnodes to the I2C device node that represent
> these pins.
> 
> To allow I2C adapters to have non-I2C specific subnodes in device-tree
> that are not parsed by the I2C driver core, add support for an optional
> 'i2c-bus' subnode where I2C slaves can be placed. If the 'i2c-bus'
> subnode is present then all I2C slaves must be placed under this
> subnode.
> 
> Signed-off-by: Jon Hunter 
> Acked-by: Thierry Reding 
> Acked-by: Rob Herring 

Acked-by: Wolfram Sang 

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[PATCH 2/2 v16] drm/bridge: Add I2C based driver for ps8640 bridge

[Daniel Kurtz]

Hi Emil,

One answer inline below.  The rest I leave to Jitao...

[snip...]

On Fri, Jun 17, 2016 at 3:14 AM, Emil Velikov  
wrote:

>> +static ssize_t ps8640_update_fw_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t count)
>> +{
>> +   struct i2c_client *client = to_i2c_client(dev);
>> +   struct ps8640 *ps_bridge = i2c_get_clientdata(client);
>> +   const struct firmware *fw;
>> +   int error;
>> +
>> +   error = request_firmware(, PS_FW_NAME, dev);
> Can the device operate without a firmware ? If not, why is the
> firmware loaded so later/after user interaction (via sysfs) ? I don't
> recall any other driver in DRM to use such an approach.

The PS8640 has internal flash, so it should always already have a
working firmware.
This sysfs interface is useful for user space initiated field firmware updates.

Regards,
-Daniel

> Regards,
> Emil
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

[pull] amdgpu drm-fixes-4.7

[Alex Deucher]

Hi Dave,

Just a few more late fixes for Polaris cards.

The following changes since commit 270d013659ddab52a6fd0eacae452c422d08aa39:

  drm/amd/powerplay: enable clock stretch feature for polaris (2016-06-21 
10:22:42 -0400)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.7

for you to fetch changes up to a7f14a184e0e8e94becfc3f9608f6b0f9c339572:

  drm/amd/powerplay: workaround for UVD clock issue (2016-06-29 12:12:26 -0400)


Ken Wang (1):
  drm/amdgpu: add ACLK_CNTL setting for polaris10

Rex Zhu (6):
  drm/amd/powerplay: add some definition for FFC feature on polaris.
  drm/amd/powerplay: disable FFC.
  drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation
  drm/amd/powerplay: Workaround for Memory EDC Error on Polaris10.
  drm/amd/powerplay: fix issue uvd dpm can't enabled on Polaris11.
  drm/amd/powerplay: workaround for UVD clock issue

 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|   4 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |   3 +
 .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  | 179 ++---
 .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h  |   1 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |   2 +
 .../gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h|   2 +
 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h |   3 +-
 7 files changed, 138 insertions(+), 56 deletions(-)

[PATCH] drm/hisilicon: add select HISI_KIRIN_DW_DSI

[Zoltan Kuscsik]

 Add select HISI_KIRIN_DW_DSI to Kconfig.
 The DRM driver depends on dsi sub-driver.

Signed-off-by: Zoltan Kuscsik 
Signed-off-by: Xinliang Liu 
---
 drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig 
b/drivers/gpu/drm/hisilicon/kirin/Kconfig
index ea0df61..499f644 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
+++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
@@ -4,6 +4,7 @@ config DRM_HISI_KIRIN
select DRM_KMS_HELPER
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
+   select HISI_KIRIN_DW_DSI
help
  Choose this option if you have a hisilicon Kirin chipsets(hi6220).
  If M is selected the module will be called kirin-drm.
-- 
1.9.1

[PATCH v3 10/10] drm/bridge: analogix_dp: fix no drm hpd event when panel plug in

[Yakir Yang]

Sean,

On 06/23/2016 10:24 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang  wrote:
>> The enum value of DP_IRQ_TYPE_HP_CABLE_IN is zero, but driver only
>> send drm hp event when the irq_type and the enum value is true.
>>
>> if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN || ...)
>>  drm_helper_hpd_irq_event(dp->drm_dev);
>>
>> So there would no drm hpd event when cable plug in, to fix that
>> just need to assign all hotplug enum with no-zero values.
>>
>> Reported-by: Dan Carpenter 
>> Signed-off-by: Yakir Yang 
>> Reviewed-by: Stéphane Marchesin 
>> Tested-by: Javier Martinez Canillas 
> Reviewed-by: Sean Paul 
>

Thanks  ;)

>> ---
>> Changes in v3:
>> - Add reviewed flag from Stéphane.
>>  [https://chromium-review.googlesource.com/#/c/346319/15]
>> - Add tested flag from Javier
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 8 
>>   1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h 
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index f09275d..b456380 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -127,10 +127,10 @@ enum analog_power_block {
>>   };
>>
>>   enum dp_irq_type {
>> -   DP_IRQ_TYPE_HP_CABLE_IN,
>> -   DP_IRQ_TYPE_HP_CABLE_OUT,
>> -   DP_IRQ_TYPE_HP_CHANGE,
>> -   DP_IRQ_TYPE_UNKNOWN,
>> +   DP_IRQ_TYPE_HP_CABLE_IN  = BIT(0),
>> +   DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),
>> +   DP_IRQ_TYPE_HP_CHANGE= BIT(2),
>> +   DP_IRQ_TYPE_UNKNOWN  = BIT(3),
>>   };
>>
>>   struct video_info {
>> --
>> 1.9.1
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>

[PATCH v4.1 1/2] drm/rockchip: analogix_dp: introduce the pclk for grf

[Yakir Yang]

Doug,

On 06/23/2016 01:16 PM, Doug Anderson wrote:
> Yakir,
>
> On Wed, Jun 22, 2016 at 6:58 PM, Yakir Yang  wrote:
>> For RK3399's GRF module, if we want to operate the graphic related grf
>> registers, we need to enable the pclk_vio_grf which supply power for VIO
>> GRF IOs, so it's better to introduce an optional grf clock in driver.
>>
>> Signed-off-by: Yakir Yang 
>> ---
>> Hi all,
>>
>> This is an external patch for analogix_dp misc cleanup thread [0]
>> [0]: https://patchwork.kernel.org/patch/9175613/
>>
>> BR,
>> - Yakir
>>
>> Changes in v4.1:
>> - Fix compiled error, sorry.
>>"dp->cgfclk"  -->  'dp->grfclk'
>>
>> Changes in v4:
>> - Check the the error code properly, 'EPROBE_DEFER' should be returned,
>>'ENOENT' should assign a NULL point to grfclk, other errors should be
>>regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit)
>>  
>> [https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>  at 249]
>> - Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at 
>> Google Gerrit)
>>  [https://chromium-review.googlesource.com/#/c/351821/]
>>
>> Changes in v3:
>> - Add this patch in v3
>>
>>   .../display/rockchip/analogix_dp-rockchip.txt  |  6 ++
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c| 23 
>> +++---
>>   2 files changed, 26 insertions(+), 3 deletions(-)
> I probably would have split into two patches so the bindings was its
> own patch, but I don't think it's strictly required.
>
> In any case, this seems good to me.
>
> Reviewed-by: Douglas Anderson 
>
This is not big change, so collect them into one patch should be more 
cleaner, thanks for your reviewed ;)
>

[PATCH v4 2/2] dt-bindings: analogix_dp: rockchip: correct the wrong compatible name

[Yakir Yang]

Doug,

On 06/23/2016 01:17 PM, Doug Anderson wrote:
> Hi,
>
> On Wed, Jun 22, 2016 at 6:47 PM, Yakir Yang  wrote:
>> The document about rockchip platform make a mistaken in available
>> compatible name of "rk3288-edp", we should correct it to "rk3288-dp"
>> which correspond to the compatible name in driver.
>>
>> This mistaken was introduced in commit be91c36247089 ("dt-bindings:
>> add document for rockchip variant of analogix_dp").
>>
>> Reported-by: Tomasz Figa 
>> Signed-off-by: Yakir Yang 
>> ---
>> Hi all,
>>
>> This is an external patch for analogix_dp misc cleanup thread [0]
>> [0]: https://patchwork.kernel.org/patch/9175613/
>>
>> BR,
>> - Yakir
>>
>> Changes in v4: None
>> Changes in v3:
>> - Add this patch in v3
>>
>>   .../devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt   | 
>> 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
> Reviewed-by: Douglas Anderson 
Thanks ;)
>
>

[PATCH v1 1/5] dt-bindings: Add support for LG LP079QX1-SP0V 1536x2048 panel

[Yakir Yang]

Rob,

On 06/29/2016 04:59 AM, Rob Herring wrote:
> On Tue, Jun 28, 2016 at 12:51:12PM +0800, Yakir Yang wrote:
>> The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
>> 32 pins eDP interface. This module supports 1536x2048 mode.
>>
>> Signed-off-by: Yakir Yang 
>> ---
>>   .../devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt | 7 
>> +++
>>   1 file changed, 7 insertions(+)
>>   create mode 100644 
>> Documentation/devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt
> Acked-by: Rob Herring 
>
Thanks for your fast respond ;)
>

DMA, CMA and SWIOTLB

[Jose Abreu]

Hi all,

I am writing a very simple KMS driver that uses Xilinx VDMA to
transfer data between the host and a FPGA. To handle memory
allocation for DMA I am using the CMA helpers available in the
DRM subsystem. When setting for low video modes (small memory
requirements) everything works fine, but if I try to set a large
video mode (specifically a 4k HDMI mode) I get SWIOTLB errors
saying the buffer is full.

The distinction between CMA and SWIOTLB is not clear to me, but
these are two different allocation engines, right?

One important aspect in my configuration is that the Xilinx VDMA
can only access up to 28 bits of the host memory so I set the DMA
mask to 28 bits and force the CMA region to be allocated bellow
these 28 bits. I also tried increasing the CMA size and the
SWIOTLB size without success.

Any comments on this?

Thanks in advance for your help.

Best regards,
Jose Miguel Abreu

[PATCH V2 11/11] arm64: tegra: Add DPAUX pinctrl bindings

[Jon Hunter]

Add the DPAUX pinctrl states for the DPAUX nodes defining all three
possible states of "aux", "i2c" and "off". Also add the 'i2c-bus'
node for the DPAUX nodes so that the I2C driver core does not attempt
to parse the pinctrl state nodes.

Populate the nodes for the pinctrl clients of the DPAUX pin controller.
There are two clients for each DPAUX instance, namely the SOR and one of
the I2C adapters. The SOR clients may used the DPAUX pins in either AUX
or I2C modes and so for these devices we don't define any of the generic
pinctrl states (default, idle, etc) because the SOR driver will directly
set the state needed. For I2C clients only the I2C mode is used and so
we can simplify matters by using the generic pinctrl states for default
and idle.

Signed-off-by: Jon Hunter 
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 54 
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi 
b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index ef317f0d773f..65b829b762bb 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -36,6 +36,26 @@
reset-names = "dpaux";
power-domains = <_sor>;
status = "disabled";
+
+   state_dpaux1_aux: pinmux-aux {
+   groups = "dpaux-io";
+   function = "aux";
+   };
+
+   state_dpaux1_i2c: pinmux-i2c {
+   groups = "dpaux-io";
+   function = "i2c";
+   };
+
+   state_dpaux1_off: pinmux-off {
+   groups = "dpaux-io";
+   function = "off";
+   };
+
+   i2c-bus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
};

vi at 5408 {
@@ -155,6 +175,10 @@
clock-names = "sor", "parent", "dp", "safe";
resets = <_car 182>;
reset-names = "sor";
+   pinctrl-0 = <_dpaux_aux>;
+   pinctrl-1 = <_dpaux_i2c>;
+   pinctrl-2 = <_dpaux_off>;
+   pinctrl-names = "aux", "i2c", "off";
power-domains = <_sor>;
status = "disabled";
};
@@ -170,6 +194,10 @@
clock-names = "sor", "parent", "dp", "safe";
resets = <_car 183>;
reset-names = "sor";
+   pinctrl-0 = <_dpaux1_aux>;
+   pinctrl-1 = <_dpaux1_i2c>;
+   pinctrl-2 = <_dpaux1_off>;
+   pinctrl-names = "aux", "i2c", "off";
power-domains = <_sor>;
status = "disabled";
};
@@ -185,6 +213,26 @@
reset-names = "dpaux";
power-domains = <_sor>;
status = "disabled";
+
+   state_dpaux_aux: pinmux-aux {
+   groups = "dpaux-io";
+   function = "aux";
+   };
+
+   state_dpaux_i2c: pinmux-i2c {
+   groups = "dpaux-io";
+   function = "i2c";
+   };
+
+   state_dpaux_off: pinmux-off {
+   groups = "dpaux-io";
+   function = "off";
+   };
+
+   i2c-bus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
};

isp at 5460 {
@@ -482,6 +530,9 @@
reset-names = "i2c";
dmas = < 26>, < 26>;
dma-names = "rx", "tx";
+   pinctrl-0 = <_dpaux1_i2c>;
+   pinctrl-1 = <_dpaux1_off>;
+   pinctrl-names = "default", "idle";
status = "disabled";
};

@@ -512,6 +563,9 @@
reset-names = "i2c";
dmas = < 30>, < 30>;
dma-names = "rx", "tx";
+   pinctrl-0 = <_dpaux_i2c>;
+   pinctrl-1 = <_dpaux_off>;
+   pinctrl-names = "default", "idle";
status = "disabled";
};

-- 
2.1.4

[PATCH V2 10/11] arm64: tegra: Add SOR power-domain node

[Jon Hunter]

Add node for SOR power-domain for Tegra210 and populate the SOR
power-domain phandle for SOR and DPAUX nodes that are dependent
on this power-domain.

Please note that although neither the SOR or DPAUX drivers currently
support runtime power-management, by populating the power-domain node
the SOR power-domain will be turned on before probing SOR or DPAUX
devices and kept on while the devices are bound.

Signed-off-by: Jon Hunter 
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 24 
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi 
b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index ebf44f4059f8..ef317f0d773f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -34,6 +34,7 @@
clock-names = "dpaux", "parent";
resets = <_car 207>;
reset-names = "dpaux";
+   power-domains = <_sor>;
status = "disabled";
};

@@ -154,6 +155,7 @@
clock-names = "sor", "parent", "dp", "safe";
resets = <_car 182>;
reset-names = "sor";
+   power-domains = <_sor>;
status = "disabled";
};

@@ -168,6 +170,7 @@
clock-names = "sor", "parent", "dp", "safe";
resets = <_car 183>;
reset-names = "sor";
+   power-domains = <_sor>;
status = "disabled";
};

@@ -180,6 +183,7 @@
clock-names = "dpaux", "parent";
resets = <_car 181>;
reset-names = "dpaux";
+   power-domains = <_sor>;
status = "disabled";
};

@@ -592,6 +596,26 @@
resets = <_car 198>;
#power-domain-cells = <0>;
};
+
+   pd_sor: sor {
+   clocks = <_car TEGRA210_CLK_SOR0>,
+<_car TEGRA210_CLK_SOR1>,
+<_car TEGRA210_CLK_CSI>,
+<_car TEGRA210_CLK_DSIA>,
+<_car TEGRA210_CLK_DSIB>,
+<_car TEGRA210_CLK_DPAUX>,
+<_car TEGRA210_CLK_DPAUX1>,
+<_car TEGRA210_CLK_MIPI_CAL>;
+   resets = <_car TEGRA210_CLK_SOR0>,
+<_car TEGRA210_CLK_SOR1>,
+<_car TEGRA210_CLK_CSI>,
+<_car TEGRA210_CLK_DSIA>,
+<_car TEGRA210_CLK_DSIB>,
+<_car TEGRA210_CLK_DPAUX>,
+<_car TEGRA210_CLK_DPAUX1>,
+<_car TEGRA210_CLK_MIPI_CAL>;
+   #power-domain-cells = <0>;
+   };
};
};

-- 
2.1.4

[PATCH V2 09/11] drm/tegra: Add pinctrl support for DPAUX

[Jon Hunter]

The DPAUX pins are shared with an internal I2C controller. To allow
these pins to be muxed to the I2C controller, register a pinctrl device
for the DPAUX device. Make Tegra DRM support dependent on PINCTRL to
avoid any compilation issues.

This is based upon work by Thierry Reding .

Signed-off-by: Jon Hunter 
---
 drivers/gpu/drm/tegra/dpaux.c | 122 --
 1 file changed, 119 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 61821f457209..7b2abaf33a7a 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -12,6 +12,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -44,6 +47,11 @@ struct tegra_dpaux {
struct completion complete;
struct work_struct work;
struct list_head list;
+
+#ifdef CONFIG_PINCTRL
+   struct pinctrl_dev *pinctrl;
+   struct pinctrl_desc desc;
+#endif
 };

 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
@@ -267,6 +275,12 @@ static irqreturn_t tegra_dpaux_irq(int irq, void *data)
return ret;
 }

+enum tegra_dpaux_functions {
+   DPAUX_PADCTL_FUNC_AUX,
+   DPAUX_PADCTL_FUNC_I2C,
+   DPAUX_PADCTL_FUNC_OFF,
+};
+
 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
 {
u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
@@ -290,18 +304,21 @@ static int tegra_dpaux_pad_config(struct tegra_dpaux 
*dpaux, unsigned function)
u32 value;

switch (function) {
-   case DPAUX_HYBRID_PADCTL_MODE_AUX:
+   case DPAUX_PADCTL_FUNC_AUX:
value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
DPAUX_HYBRID_PADCTL_MODE_AUX;
break;
-   case DPAUX_HYBRID_PADCTL_MODE_I2C:
+   case DPAUX_PADCTL_FUNC_I2C:
value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
DPAUX_HYBRID_PADCTL_MODE_I2C;
break;
+   case DPAUX_PADCTL_FUNC_OFF:
+   tegra_dpaux_pad_power_down(dpaux);
+   return 0;
default:
return -ENOTSUPP;
}
@@ -312,6 +329,91 @@ static int tegra_dpaux_pad_config(struct tegra_dpaux 
*dpaux, unsigned function)
return 0;
 }

+#ifdef CONFIG_PINCTRL
+static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
+   PINCTRL_PIN(0, "DP_AUX_CHx_P"),
+   PINCTRL_PIN(1, "DP_AUX_CHx_N"),
+};
+
+static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
+
+static const char * const tegra_dpaux_groups[] = {
+   "dpaux-io",
+};
+
+static const char * const tegra_dpaux_functions[] = {
+   "aux",
+   "i2c",
+   "off",
+};
+
+static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
+{
+   return ARRAY_SIZE(tegra_dpaux_groups);
+}
+
+static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
+ unsigned int group)
+{
+   return tegra_dpaux_groups[group];
+}
+
+static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
+ unsigned group, const unsigned **pins,
+ unsigned *num_pins)
+{
+   *pins = tegra_dpaux_pin_numbers;
+   *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
+
+   return 0;
+}
+
+static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
+   .get_groups_count = tegra_dpaux_get_groups_count,
+   .get_group_name = tegra_dpaux_get_group_name,
+   .get_group_pins = tegra_dpaux_get_group_pins,
+   .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+   .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
+{
+   return ARRAY_SIZE(tegra_dpaux_functions);
+}
+
+static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
+unsigned int function)
+{
+   return tegra_dpaux_functions[function];
+}
+
+static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
+  unsigned int function,
+  const char * const **groups,
+  unsigned * const num_groups)
+{
+   *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
+   *groups = tegra_dpaux_groups;
+
+   return 0;
+}
+
+static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
+  unsigned int function, unsigned int group)
+{
+   struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
+
+   return tegra_dpaux_pad_config(dpaux, function);
+}
+
+static const 

[PATCH V2 08/11] dt-bindings: Add bindings for Tegra DPAUX pinctrl driver

[Jon Hunter]

On Tegra124, Tegra132 and Tegra210 devices the pads used by the Display
Port Auxiliary (DPAUX) channel are multiplexed such that they can also
be used by one of the internal I2C controllers. Note that this is
different from I2C-over-AUX supported by the DPAUX controller. The
register that configures these pads is part of the DPAUX controllers
register set and so a pinctrl driver is being added for the DPAUX device
to share these pads. Add the device-tree binding documentation for the
DPAUX pad controller.

Although there is only one group of pads associated with the DPAUX that
can be multiplexed, the group still needs to be described by the binding.
If the 'groups' property is not present in the binding, then the pads
will not be allocated by the pinctrl core for a client and this would
allow another client to re-configure the same pads that may already be
in-use.

Please note that although the "off" function for the DPAUX pads is not
technically a pin-mux setting but more of a pin-conf setting it is
simpler to expose these as a function so that the user can simply select
either "aux", "i2c" or "off" as the current function/mode.

Update the main DPAUX binding documentation to reference the DPAUX pad
controller binding document and add the 'i2c-bus' subnode. The 'i2c-bus'
subnode is used for populating I2C slaves for the DPAUX device so that
the I2C driver core does not attempt to add the DPAUX pad controller
nodes as I2C slaves.

Signed-off-by: Jon Hunter 
Acked-by: Rob Herring 
---
 .../display/tegra/nvidia,tegra20-host1x.txt|  6 +++
 .../pinctrl/nvidia,tegra124-dpaux-padctl.txt   | 60 ++
 2 files changed, 66 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt

diff --git 
a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt 
b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
index 275f45680892..d0f1dc62550a 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -241,6 +241,12 @@ of the following host1x client modules:
   - reset-names: Must include the following entries:
 - dpaux
   - vdd-supply: phandle of a supply that powers the DisplayPort link
+  - i2c-bus: Subnode where I2C slave devices are listed. This subnode
+must be always present. If there are no I2C slave devices, an empty
+node should be added. See ../../i2c/i2c.txt for more information.
+
+  See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
+  regarding the DPAUX pad controller bindings.

 Example:

diff --git 
a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt 
b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
new file mode 100644
index ..f2abdaee9022
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
@@ -0,0 +1,60 @@
+Device tree binding for NVIDIA Tegra DPAUX pad controller
+
+
+The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
+which can be assigned to either the DPAUX channel or to an I2C
+controller.
+
+This document defines the device-specific binding for the DPAUX pad
+controller. Refer to pinctrl-bindings.txt in this directory for generic
+information about pin controller device tree bindings. Please refer to
+the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
+details on the DPAUX binding.
+
+Pin muxing:
+---
+
+Child nodes contain the pinmux configurations following the conventions
+from the pinctrl-bindings.txt document.
+
+Since only three configurations are possible, only three child nodes are
+needed to describe the pin mux'ing options for the DPAUX pads.
+Furthermore, given that the pad functions are only applicable to a
+single set of pads, the child nodes only need to describe the pad group
+the functions are being applied to rather than the individual pads.
+
+Required properties:
+- groups: Must be "dpaux-io"
+- function: Must be either "aux", "i2c" or "off".
+
+Example:
+
+
+   dpaux at 545c {
+   ...
+
+   state_dpaux_aux: pinmux-aux {
+   groups = "dpaux-io";
+   function = "aux";
+   };
+
+   state_dpaux_i2c: pinmux-i2c {
+   groups = "dpaux-io";
+   function = "i2c";
+   };
+
+   state_dpaux_off: pinmux-off {
+   groups = "dpaux-io";
+   function = "off";
+   };
+   };
+
+   ...
+
+   i2c at 7000d100 {
+   ...
+   pinctrl-0 = <_dpaux_i2c>;
+   pinctrl-1 = <_dpaux_off>;
+   pinctrl-names = "default", "idle";
+   status = "disabled";
+   

[PATCH V2 07/11] i2c: core: Add support for 'i2c-bus' subnode

[Jon Hunter]

If the 'i2c-bus' device-tree node is present for an I2C adapter then
parse this subnode for I2C slaves.

Signed-off-by: Jon Hunter 
Acked-by: Wolfram Sang 
---
 drivers/i2c/i2c-core.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 952d2f0c02c5..71ad532be1d8 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -1452,7 +1452,7 @@ static struct i2c_client *of_i2c_register_device(struct 
i2c_adapter *adap,

 static void of_i2c_register_devices(struct i2c_adapter *adap)
 {
-   struct device_node *node;
+   struct device_node *bus, *node;

/* Only register child devices if the adapter has a node pointer set */
if (!adap->dev.of_node)
@@ -1460,11 +1460,17 @@ static void of_i2c_register_devices(struct i2c_adapter 
*adap)

dev_dbg(>dev, "of_i2c: walking child nodes\n");

-   for_each_available_child_of_node(adap->dev.of_node, node) {
+   bus = of_get_child_by_name(adap->dev.of_node, "i2c-bus");
+   if (!bus)
+   bus = of_node_get(adap->dev.of_node);
+
+   for_each_available_child_of_node(bus, node) {
if (of_node_test_and_set_flag(node, OF_POPULATED))
continue;
of_i2c_register_device(adap, node);
}
+
+   of_node_put(bus);
 }

 static int of_dev_node_match(struct device *dev, void *data)
-- 
2.1.4

[PATCH V2 06/11] dt-bindings: i2c: Add support for 'i2c-bus' subnode

[Jon Hunter]

The I2C driver core for boards using device-tree assumes any subnode of
an I2C adapter in the device-tree blob is an I2C slave device. Although
this makes complete sense, some I2C adapters may have subnodes which
are not I2C slaves but subnodes presenting other features. For example
some Tegra devices have an I2C interface which may share its pins with
other devices. In order to share these pins using the pinctrl framework,
it is necessary to add subnodes to the I2C device node that represent
these pins.

To allow I2C adapters to have non-I2C specific subnodes in device-tree
that are not parsed by the I2C driver core, add support for an optional
'i2c-bus' subnode where I2C slaves can be placed. If the 'i2c-bus'
subnode is present then all I2C slaves must be placed under this
subnode.

Signed-off-by: Jon Hunter 
Acked-by: Thierry Reding 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/i2c/i2c.txt | 8 
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt 
b/Documentation/devicetree/bindings/i2c/i2c.txt
index f31b2ad1552b..5fa691e6f638 100644
--- a/Documentation/devicetree/bindings/i2c/i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c.txt
@@ -32,6 +32,14 @@ wants to support one of the below features, it should adapt 
the bindings below.
 - clock-frequency
frequency of bus clock in Hz.

+- i2c-bus
+   For I2C adapters that have child nodes that are a mixture of both I2C
+   devices and non-I2C devices, the 'i2c-bus' subnode can be used for
+   populating I2C devices. If the 'i2c-bus' subnode is present, only
+   subnodes of this will be considered as I2C slaves. The properties,
+   '#address-cells' and '#size-cells' must be defined under this subnode
+   if present.
+
 - i2c-scl-falling-time-ns
Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
specification.
-- 
2.1.4

[PATCH V2 05/11] drm/tegra: Prepare DPAUX for supporting generic PM domains

[Jon Hunter]

To utilise the DPAUX on Tegra, the SOR power partition must be enabled.
Now that Tegra supports the generic PM domain framework we manage the
SOR power partition via this framework for DPAUX. However, the sequence
for gating/ungating the SOR power partition requires that the DPAUX
reset is asserted/de-asserted at the time the SOR power partition is
gated/ungated, respectively. Now that the reset control core assumes
that resets are exclusive, the Tegra generic PM domain code and the
DPAUX driver cannot request the same reset unless we mark the resets as
shared. Sharing resets we will not work in this case because we cannot
guarantee that the reset is asserted/de-asserted at the appropriate
time. Therefore, given that the Tegra generic PM domain code will handle
the DPAUX reset, do not request the reset in the DPAUX driver if the
DPAUX device has a PM domain associated.

Signed-off-by: Jon Hunter 
---
 drivers/gpu/drm/tegra/dpaux.c | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 4014ec57ed31..61821f457209 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -339,11 +339,14 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
return -ENXIO;
}

-   dpaux->rst = devm_reset_control_get(>dev, "dpaux");
-   if (IS_ERR(dpaux->rst)) {
-   dev_err(>dev, "failed to get reset control: %ld\n",
-   PTR_ERR(dpaux->rst));
-   return PTR_ERR(dpaux->rst);
+   if (!pdev->dev.pm_domain) {
+   dpaux->rst = devm_reset_control_get(>dev, "dpaux");
+   if (IS_ERR(dpaux->rst)) {
+   dev_err(>dev,
+   "failed to get reset control: %ld\n",
+   PTR_ERR(dpaux->rst));
+   return PTR_ERR(dpaux->rst);
+   }
}

dpaux->clk = devm_clk_get(>dev, NULL);
@@ -360,7 +363,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
return err;
}

-   reset_control_deassert(dpaux->rst);
+   if (dpaux->rst)
+   reset_control_deassert(dpaux->rst);

dpaux->clk_parent = devm_clk_get(>dev, "parent");
if (IS_ERR(dpaux->clk_parent)) {
@@ -438,7 +442,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
 disable_parent_clk:
clk_disable_unprepare(dpaux->clk_parent);
 assert_reset:
-   reset_control_assert(dpaux->rst);
+   if (dpaux->rst)
+   reset_control_assert(dpaux->rst);
clk_disable_unprepare(dpaux->clk);

return err;
@@ -460,7 +465,8 @@ static int tegra_dpaux_remove(struct platform_device *pdev)
cancel_work_sync(>work);

clk_disable_unprepare(dpaux->clk_parent);
-   reset_control_assert(dpaux->rst);
+   if (dpaux->rst)
+   reset_control_assert(dpaux->rst);
clk_disable_unprepare(dpaux->clk);

return 0;
-- 
2.1.4

[PATCH V2 04/11] dt-bindings: display: Update Tegra DPAUX documentation

[Jon Hunter]

Update the DPAUX compatibility string information for Tegra124, Tegra132
and Tegra210.

Signed-off-by: Jon Hunter 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt 
b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
index a3bd8c050c4e..275f45680892 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -226,9 +226,9 @@ of the following host1x client modules:
   - nvidia,dpaux: phandle to a DispayPort AUX interface

 - dpaux: DisplayPort AUX interface
-  - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux".  Otherwise,
-must contain '"nvidia,-dpaux", "nvidia,tegra124-dpaux"', where
- is tegra132.
+  - compatible : Should contain one of the following:
+- "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
+- "nvidia,tegra210-dpaux": for Tegra210
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
   - clocks: Must contain an entry for each entry in clock-names.
-- 
2.1.4

[PATCH V2 03/11] drm/tegra: Add helper functions for setting up DPAUX pads

[Jon Hunter]

In preparation for adding pinctrl support for the DPAUX pads, add
helpers functions for configuring the pads and controlling the power
for the pads.

Please note that although a simple if-statement could be used instead
of a case statement for configuring the pads as there are only two
possible modes, a case statement is used because when integrating with
the pinctrl framework, we need to be able to handle invalid modes that
could be passed.

Signed-off-by: Jon Hunter 
---
 drivers/gpu/drm/tegra/dpaux.c | 81 +++
 1 file changed, 51 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 0874a7e5b37b..4014ec57ed31 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -267,6 +267,51 @@ static irqreturn_t tegra_dpaux_irq(int irq, void *data)
return ret;
 }

+static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
+{
+   u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
+
+   value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
+
+   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
+}
+
+static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
+{
+   u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
+
+   value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
+
+   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
+}
+
+static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
+{
+   u32 value;
+
+   switch (function) {
+   case DPAUX_HYBRID_PADCTL_MODE_AUX:
+   value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
+   DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
+   DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
+   DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
+   DPAUX_HYBRID_PADCTL_MODE_AUX;
+   break;
+   case DPAUX_HYBRID_PADCTL_MODE_I2C:
+   value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
+   DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
+   DPAUX_HYBRID_PADCTL_MODE_I2C;
+   break;
+   default:
+   return -ENOTSUPP;
+   }
+
+   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
+   tegra_dpaux_pad_power_up(dpaux);
+
+   return 0;
+}
+
 static int tegra_dpaux_probe(struct platform_device *pdev)
 {
struct tegra_dpaux *dpaux;
@@ -372,15 +417,9 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
 * is no possibility to perform the I2C mode configuration in the
 * HDMI path.
 */
-   value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
-   value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
-   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
-
-   value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_PADCTL);
-   value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
-   DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
-   DPAUX_HYBRID_PADCTL_MODE_I2C;
-   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
+   err = tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_I2C);
+   if (err < 0)
+   return err;

/* enable and clear all interrupts */
value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
@@ -408,12 +447,9 @@ assert_reset:
 static int tegra_dpaux_remove(struct platform_device *pdev)
 {
struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
-   u32 value;

/* make sure pads are powered down when not in use */
-   value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
-   value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
-   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
+   tegra_dpaux_pad_power_down(dpaux);

drm_dp_aux_unregister(>aux);

@@ -538,30 +574,15 @@ enum drm_connector_status drm_dp_aux_detect(struct 
drm_dp_aux *aux)
 int drm_dp_aux_enable(struct drm_dp_aux *aux)
 {
struct tegra_dpaux *dpaux = to_dpaux(aux);
-   u32 value;
-
-   value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
-   DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
-   DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
-   DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
-   DPAUX_HYBRID_PADCTL_MODE_AUX;
-   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);

-   value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
-   value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
-   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
-
-   return 0;
+   return tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_AUX);
 }

 int drm_dp_aux_disable(struct drm_dp_aux *aux)
 {
struct tegra_dpaux *dpaux = to_dpaux(aux);
-   u32 value;

-   value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
-   value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
-   tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
+   tegra_dpaux_pad_power_down(dpaux);

return 0;
 }
-- 

[PATCH V2 02/11] drm/tegra: Clean-up if probing DPAUX fails

[Jon Hunter]

If the probing of the DPAUX fails, then clocks are left enabled and the
DPAUX reset de-asserted. Add code to perform the necessary clean-up on
probe failure by disabling clocks and asserting the reset.

Signed-off-by: Jon Hunter 
---
 drivers/gpu/drm/tegra/dpaux.c | 22 --
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index b24a0f14821a..0874a7e5b37b 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -321,28 +321,30 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
if (IS_ERR(dpaux->clk_parent)) {
dev_err(>dev, "failed to get parent clock: %ld\n",
PTR_ERR(dpaux->clk_parent));
-   return PTR_ERR(dpaux->clk_parent);
+   err = PTR_ERR(dpaux->clk_parent);
+   goto assert_reset;
}

err = clk_prepare_enable(dpaux->clk_parent);
if (err < 0) {
dev_err(>dev, "failed to enable parent clock: %d\n",
err);
-   return err;
+   goto assert_reset;
}

err = clk_set_rate(dpaux->clk_parent, 27000);
if (err < 0) {
dev_err(>dev, "failed to set clock to 270 MHz: %d\n",
err);
-   return err;
+   goto disable_parent_clk;
}

dpaux->vdd = devm_regulator_get(>dev, "vdd");
if (IS_ERR(dpaux->vdd)) {
dev_err(>dev, "failed to get VDD supply: %ld\n",
PTR_ERR(dpaux->vdd));
-   return PTR_ERR(dpaux->vdd);
+   err = PTR_ERR(dpaux->vdd);
+   goto disable_parent_clk;
}

err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
@@ -350,7 +352,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
if (err < 0) {
dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
dpaux->irq, err);
-   return err;
+   goto disable_parent_clk;
}

disable_irq(dpaux->irq);
@@ -360,7 +362,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev)

err = drm_dp_aux_register(>aux);
if (err < 0)
-   return err;
+   goto disable_parent_clk;

/*
 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
@@ -393,6 +395,14 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, dpaux);

return 0;
+
+disable_parent_clk:
+   clk_disable_unprepare(dpaux->clk_parent);
+assert_reset:
+   reset_control_assert(dpaux->rst);
+   clk_disable_unprepare(dpaux->clk);
+
+   return err;
 }

 static int tegra_dpaux_remove(struct platform_device *pdev)
-- 
2.1.4

[PATCH V2 01/11] soc/tegra: pmc: Initialise resets associated with a power partition

[Jon Hunter]

When registering the Tegra power partitions with the generic PM domain
framework, the current state of the each partition is checked and used
as the default state for the partition. However, the state of each reset
associated with the partition is not initialised and so it is possible
that the state of the resets are not in the expected state. For example,
if a partition is on, then the resets should be de-asserted and if the
partition is off, the resets should be asserted.

There have been cases where the bootloader has powered on a partition
and only de-asserted some of the resets to some of the devices in the
partition. This can cause accesses to these devices to hang the system
when the kernel boots and attempts to probe these devices.

Ideally, the driver for the device should ensure the reset has been
de-asserted when probing, but the resets cannot be shared between the
PMC driver (that needs to de-assert/assert the reset when turning the
partition on or off) and another driver because we cannot ensure the
reset is in the correct state.

To ensure the resets are in the correct state, when using the generic
PM domain framework, put each reset associated with the partition in
the correct state (based upon the partition's current state) when
obtaining the resets for a partition.

Signed-off-by: Jon Hunter 
---
 drivers/soc/tegra/pmc.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index d13516981629..8a421a0b1ece 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -738,7 +738,7 @@ err:
 }

 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
-struct device_node *np)
+struct device_node *np, bool off)
 {
struct reset_control *rst;
unsigned int i, count;
@@ -758,6 +758,16 @@ static int tegra_powergate_of_get_resets(struct 
tegra_powergate *pg,
err = PTR_ERR(pg->resets[i]);
goto error;
}
+
+   if (off)
+   err = reset_control_assert(pg->resets[i]);
+   else
+   err = reset_control_deassert(pg->resets[i]);
+
+   if (err) {
+   reset_control_put(pg->resets[i]);
+   goto error;
+   }
}

pg->num_resets = count;
@@ -798,14 +808,14 @@ static void tegra_powergate_add(struct tegra_pmc *pmc, 
struct device_node *np)
pg->genpd.power_on = tegra_genpd_power_on;
pg->pmc = pmc;

+   off = !tegra_powergate_is_powered(pg->id);
+
if (tegra_powergate_of_get_clks(pg, np))
goto set_available;

-   if (tegra_powergate_of_get_resets(pg, np))
+   if (tegra_powergate_of_get_resets(pg, np, off))
goto remove_clks;

-   off = !tegra_powergate_is_powered(pg->id);
-
pm_genpd_init(>genpd, NULL, off);

if (of_genpd_add_provider_simple(np, >genpd))
-- 
2.1.4

[PATCH V2 00/11] Add support for Tegra DPAUX pinctrl

[Jon Hunter]

The Display Port Auxiliary (DPAUX) channel pads can be shared with an
internal I2C controller. Add pinctrl support for these pads so that the
I2C controller can request and use these pads.

This series has been tested with Thierry's patches for correcting the
parent clock for the DPAUX devices [0].

Changes from V1:
- Updated dt node names to use '-' instead of '_' per Rob H's feedback.
- Updated commit message and dt-binding description for 'i2c-bus' node
  per Wolfram's feedback.
- Note the pinctrl patch to add a helper function for freeing mappings [1]
  is not included in this latest version of the series as this has already
  been picked up by Linus W.

Changes from initial RFC:
- Dropped patches for adding sor-safe clocks to DPAUX in favour of the
  patches from Thierry [0].
- Split the DPAUX function to enable the DPAUX pads into two functions:
  one for turning on and one for turning off the pads.
- Updated the description for the 'i2c-bus' node based upon Mark R's
  feedback.
- Dropped the second test if the i2c-core when checking for the presence
  of the 'i2c-bus' node based upon Thierry's feedback.
- Removed depedency on CONFIG_PINCTRL in the DPAUX driver in favour of
  using #ifdef's per Thierry's feedback (note by removing the dependency
  on CONFIG_PINCTRL I had to use #ifdefs as all the structures, function
  tables, and functions may not be defined).
- Updated SOR power partition device-tree node to include all clocks and
  resets as described in the Tegra210 TRM.

[0] http://marc.info/?l=linux-tegra=146667915802019=2
[1] http://marc.info/?l=linux-tegra=146669759407988=2

Jon Hunter (11):
  soc/tegra: pmc: Initialise resets associated with a power partition
  drm/tegra: Clean-up if probing DPAUX fails
  drm/tegra: Add helper functions for setting up DPAUX pads
  dt-bindings: display: Update Tegra DPAUX documentation
  drm/tegra: Prepare DPAUX for supporting generic PM domains
  dt-bindings: i2c: Add support for 'i2c-bus' subnode
  i2c: core: Add support for 'i2c-bus' subnode
  dt-bindings: Add bindings for Tegra DPAUX pinctrl driver
  drm/tegra: Add pinctrl support for DPAUX
  arm64: tegra: Add SOR power-domain node
  arm64: tegra: Add DPAUX pinctrl bindings

 .../display/tegra/nvidia,tegra20-host1x.txt|  12 +-
 Documentation/devicetree/bindings/i2c/i2c.txt  |   8 +
 .../pinctrl/nvidia,tegra124-dpaux-padctl.txt   |  60 ++
 arch/arm64/boot/dts/nvidia/tegra210.dtsi   |  78 +++
 drivers/gpu/drm/tegra/dpaux.c  | 239 +
 drivers/i2c/i2c-core.c |  10 +-
 drivers/soc/tegra/pmc.c|  18 +-
 7 files changed, 373 insertions(+), 52 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt

-- 
2.1.4

[PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver

[Sean Paul]

On Wed, Jun 29, 2016 at 5:14 AM, Yakir Yang  wrote:
>
> RK3399 and RK3288 shared the same eDP IP controller, only some light
> difference with VOP configure and GRF configure.
>

The whole set looks good to me. All patches should have my R-b now,
thanks for the update.

Sean



> Also same misc fix to analogix_dp driver:
> - Hotplug invalid which report by Dan Carpenter
> - Make panel detect to an optional action
> - correct the register bit define error in ANALOGIX_DP_PLL_REG_1
>
> Changes in v4:
> - Assigned the GRF setting magic numbers to a #define that corresponds to
>   a TRM name. (Sean & Heiko)
> - Pass the chip type to device type directly. (Sean)
> - Add reviewed flag from Tomasz.
> - Add reviewed flag from Sean
> - Remove subdev_type number, and add 'is_rockchip(type)' helper function 
> (Sean)
> - Add reviewed flag from Tomasz.
> - Improved the overly complicated .atomic_check function. (Sean)
> - Add reviewed flag from Tomasz
> - Move of_node_put(panel_node) directly below of_drm_find_panel (Sean)
> - Add reviewed flag from Tomasz
> - Add reviewed flag from Sean.
> - Add reviewed flag from Tomasz.
> - Using mask variable to collect the YUV video format. (Sean)
> - Add reviewed flag from Tomasz.
> - Correct the misspell of 'contoller'. (Sean)
> - Add reviewed flag from Sean.
> - Add reviewed flag from Tomasz.
> - Add reviewed flag from Doug.
> - Add reviewed flag from Tomasz.
> - Fix compiled error, sorry.
>   "dp->cgfclk"  -->  'dp->grfclk'
> - Check the the error code properly, 'EPROBE_DEFER' should be returned,
>   'ENOENT' should assign a NULL point to grfclk, other errors should be
>   regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 249]
> - Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at 
> Google Gerrit)
> [https://chromium-review.googlesource.com/#/c/351821/]
> - Add reviewed flag from Doug.
> - Add reviewed flag from Tomasz.
>
> Changes in v3:
> - Write a kerneldoc-style comment explaining the chips data fields (Tomasz, 
> reviewed at Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 39]
> - Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed at 
> Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 382]
> - Add acked flag from Mark.
> - Add reviewed flag from Tomasz.
> [https://chromium-review.googlesource.com/#/c/346315/15]
> - Add tested flag from Javier
> - Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
>   reg = ~reg & REF_CLK_MASK;  --->  reg ^= REF_CLK_MASK;
> 
> [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>  at 80]
> - Add tested flag from Javier
> - Give the "rk3399-edp" a separate line for clarity in document (Tomasz, 
> reviewed at Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346314/10/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>  at 5]
> - Move 'output_type' setting before the return statement (Tomasz, reviewed at 
> Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346314/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 154]
> - Add the acked flag from Mark.
> - Add the acked flag from Mark.
> - Avoid to change any internal driver state in .mode_valid interface. 
> (Tomasz, reviewed at Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346318/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 113]
> - Hook the connector's color_formats in .get_modes directly. (Tomasz, 
> reviewed at Google Gerrit)
> [https://chromium-review.googlesource.com/#/c/346317/15]
> - Add the acked flag from Mark.
> - Add the reviewed flag from Tomasz.
> [https://chromium-review.googlesource.com/#/c/346853/12]
> - Add the acked flag from Mark.
> - Add reviewed flag from Stéphane.
> [https://chromium-review.googlesource.com/#/c/346319/15]
> - Add tested flag from Javier
> - Add this patch in v3
> - Add this patch in v3
>
> Yakir Yang (11):
>   drm/rockchip: analogix_dp: split the lcdc select setting into device
> data
>   drm/bridge: analogix_dp: correct the register bit define error in
> ANALOGIX_DP_PLL_REG_1
>   drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit
> setting
>   drm/rockchip: analogix_dp: add rk3399 eDP support
>   drm/rockchip: analogix_dp: make panel detect to an optional action
>   drm/bridge: analogix_dp: passing the connector as an argument in
> .get_modes()
>   drm/rockchip: analogix_dp: correct the connector display color format
> and bpc
>   drm/rockchip: analogix_dp: update the comments about why need to
> hardcode VOP output mode
>   drm/bridge: analogix_dp: fix no drm hpd event when 

[PATCH v4 08/11] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode

[Sean Paul]

On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang  wrote:
> The hardware IC designed that VOP must output the RGB10 video format to
> eDP contoller, and if eDP panel only support RGB8, then eDP contoller
> should cut down the video data, not via VOP contoller, that's why we need
> to hardcode the VOP output mode to RGA10 here.
>
> Signed-off-by: Yakir Yang 
> Acked-by: Mark Yao 
> Reviewed-by: Tomasz Figa 


Reviewed-by: Sean Paul 

> ---
> Changes in v4:
> - Correct the misspell of 'contoller'. (Sean)
>
> Changes in v3:
> - Add the reviewed flag from Tomasz.
> [https://chromium-review.googlesource.com/#/c/346853/12]
> - Add the acked flag from Mark.
>
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 16 +---
>  1 file changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index 0a0fb3a..850edc4 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -182,17 +182,11 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder 
> *encoder,
> int ret;
>
> /*
> -* FIXME(Yakir): driver should configure the CRTC output video
> -* mode with the display information which indicated the monitor
> -* support colorimetry.
> -*
> -* But don't know why the CRTC driver seems could only output the
> -* RGBaaa rightly. For example, if connect the "innolux,n116bge"
> -* eDP screen, EDID would indicated that screen only accepted the
> -* 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
> -* screen would show a blue picture (RGB888 show a green picture).
> -* But if I configure CTRC to RGBaaa, and eDP driver still keep
> -* RGB666 input video mode, then screen would works prefect.
> +* The hardware IC designed that VOP must output the RGB10 video
> +* format to eDP controller, and if eDP panel only support RGB8,
> +* then eDP controller should cut down the video data, not via VOP
> +* controller, that's why we need to hardcode the VOP output mode
> +* to RGA10 here.
>  */
>
> s->output_mode = ROCKCHIP_OUT_MODE_;
> --
> 1.9.1
>
>

[PATCH v4 07/11] drm/rockchip: analogix_dp: correct the connector display color format and bpc

[Sean Paul]

On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang  wrote:
> Rockchip VOP couldn't output YUV video format for eDP controller, so
> when driver detect connector support YUV video format, we need to hack
> it down to RGB888.
>
> Signed-off-by: Yakir Yang 
> Acked-by: Mark Yao 
> Reviewed-by: Tomasz Figa 

Reviewed-by: Sean Paul 


> ---
> Changes in v4:
> - Using mask variable to collect the YUV video format. (Sean)
> - Add reviewed flag from Tomasz.
>
> Changes in v3:
> - Hook the connector's color_formats in .get_modes directly. (Tomasz, 
> reviewed at Google Gerrit)
> [https://chromium-review.googlesource.com/#/c/346317/15]
> - Add the acked flag from Mark.
>
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 18 ++
>  1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index 0755573..0a0fb3a 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -110,6 +110,23 @@ static int rockchip_dp_powerdown(struct 
> analogix_dp_plat_data *plat_data)
> return 0;
>  }
>
> +static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
> +struct drm_connector *connector)
> +{
> +   struct drm_display_info *di = >display_info;
> +   /* VOP couldn't output YUV video format for eDP rightly */
> +   u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
> +
> +   if ((di->color_formats & mask)) {
> +   DRM_DEBUG_KMS("Swapping display color format from YUV to 
> RGB\n");
> +   di->color_formats &= ~mask;
> +   di->color_formats |= DRM_COLOR_FORMAT_RGB444;
> +   di->bpc = 8;
> +   }
> +
> +   return 0;
> +}
> +
>  static bool
>  rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
>const struct drm_display_mode *mode,
> @@ -310,6 +327,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
> device *master,
> dp->plat_data.dev_type = dp->data->chip_type;
> dp->plat_data.power_on = rockchip_dp_poweron;
> dp->plat_data.power_off = rockchip_dp_powerdown;
> +   dp->plat_data.get_modes = rockchip_dp_get_modes;
>
> return analogix_dp_bind(dev, dp->drm_dev, >plat_data);
>  }
> --
> 1.9.1
>
>

[PATCH v4 05/11] drm/rockchip: analogix_dp: make panel detect to an optional action

[Sean Paul]

On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang  wrote:
> Some boards don't need to declare a panel device node, like the
> display interface is DP monitors, so it's necessary to make the
> panel detect to an optional action.
>
> Signed-off-by: Yakir Yang 
> Acked-by: Mark Yao 
> Reviewed-by: Tomasz Figa 


Reviewed-by: Sean Paul 

> ---
> Changes in v4:
> - Move of_node_put(panel_node) directly below of_drm_find_panel (Sean)
> - Add reviewed flag from Tomasz
>
> Changes in v3:
> - Add the acked flag from Mark.
>
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 47 
> +++--
>  1 file changed, 21 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index 8557a08..0755573 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -329,38 +329,33 @@ static int rockchip_dp_probe(struct platform_device 
> *pdev)
>  {
> struct device *dev = >dev;
> struct device_node *panel_node, *port, *endpoint;
> +   struct drm_panel *panel = NULL;
> struct rockchip_dp_device *dp;
> -   struct drm_panel *panel;
>
> port = of_graph_get_port_by_id(dev->of_node, 1);
> -   if (!port) {
> -   dev_err(dev, "can't find output port\n");
> -   return -EINVAL;
> -   }
> -
> -   endpoint = of_get_child_by_name(port, "endpoint");
> -   of_node_put(port);
> -   if (!endpoint) {
> -   dev_err(dev, "no output endpoint found\n");
> -   return -EINVAL;
> -   }
> -
> -   panel_node = of_graph_get_remote_port_parent(endpoint);
> -   of_node_put(endpoint);
> -   if (!panel_node) {
> -   dev_err(dev, "no output node found\n");
> -   return -EINVAL;
> -   }
> -
> -   panel = of_drm_find_panel(panel_node);
> -   if (!panel) {
> -   DRM_ERROR("failed to find panel\n");
> +   if (port) {
> +   endpoint = of_get_child_by_name(port, "endpoint");
> +   of_node_put(port);
> +   if (!endpoint) {
> +   dev_err(dev, "no output endpoint found\n");
> +   return -EINVAL;
> +   }
> +
> +   panel_node = of_graph_get_remote_port_parent(endpoint);
> +   of_node_put(endpoint);
> +   if (!panel_node) {
> +   dev_err(dev, "no output node found\n");
> +   return -EINVAL;
> +   }
> +
> +   panel = of_drm_find_panel(panel_node);
> of_node_put(panel_node);
> -   return -EPROBE_DEFER;
> +   if (!panel) {
> +   DRM_ERROR("failed to find panel\n");
> +   return -EPROBE_DEFER;
> +   }
> }
>
> -   of_node_put(panel_node);
> -
> dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> if (!dp)
> return -ENOMEM;
> --
> 1.9.1
>
>

[PATCH v4 04/11] drm/rockchip: analogix_dp: add rk3399 eDP support

[Sean Paul]

On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang  wrote:
> RK3399 and RK3288 shared the same eDP IP controller, only some light
> difference with VOP configure and GRF configure.
>
> Signed-off-by: Yakir Yang 
> Acked-by: Mark Yao 
> Reviewed-by: Tomasz Figa 


Reviewed-by: Sean Paul 

> ---
> Changes in v4:
> - Improved the overly complicated .atomic_check function. (Sean)
> - Add reviewed flag from Tomasz
>
> Changes in v3:
> - Give the "rk3399-edp" a separate line for clarity in document (Tomasz, 
> reviewed at Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346314/10/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>  at 5]
> - Move 'output_type' setting before the return statement (Tomasz, reviewed at 
> Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346314/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 154]
> - Add the acked flag from Mark.
>
>  .../bindings/display/bridge/analogix_dp.txt|  1 +
>  .../display/rockchip/analogix_dp-rockchip.txt  |  3 ++-
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c| 23 
> ++
>  include/drm/bridge/analogix_dp.h   |  3 ++-
>  4 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt 
> b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> index 4f2ba8c..4a0f4f7 100644
> --- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> +++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> @@ -5,6 +5,7 @@ Required properties for dp-controller:
> platform specific such as:
>  * "samsung,exynos5-dp"
>  * "rockchip,rk3288-dp"
> +* "rockchip,rk3399-edp"
> -reg:
> physical base address of the controller and length
> of memory mapped region.
> diff --git 
> a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt 
> b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> index e832ff9..726c945 100644
> --- 
> a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> +++ 
> b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> @@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display 
> Port
>  
>
>  Required properties:
> -- compatible: "rockchip,rk3288-edp";
> +- compatible: "rockchip,rk3288-edp",
> + "rockchip,rk3399-edp";
>
>  - reg: physical base address of the controller and length
>
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index 0a30931..8557a08 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -36,6 +36,8 @@
>
>  #define RK3288_GRF_SOC_CON60x25c
>  #define RK3288_EDP_LCDC_SELBIT(5)
> +#define RK3399_GRF_SOC_CON20   0x6250
> +#define RK3399_EDP_LCDC_SELBIT(5)
>
>  #define HIWORD_UPDATE(val, mask)   (val | (mask) << 16)
>
> @@ -159,6 +161,8 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder 
> *encoder,
>   struct drm_connector_state *conn_state)
>  {
> struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
> +   struct rockchip_dp_device *dp = to_dp(encoder);
> +   int ret;
>
> /*
>  * FIXME(Yakir): driver should configure the CRTC output video
> @@ -173,8 +177,19 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder 
> *encoder,
>  * But if I configure CTRC to RGBaaa, and eDP driver still keep
>  * RGB666 input video mode, then screen would works prefect.
>  */
> +
> s->output_mode = ROCKCHIP_OUT_MODE_;
> s->output_type = DRM_MODE_CONNECTOR_eDP;
> +   if (dp->data->chip_type == RK3399_EDP) {
> +   /*
> +* For RK3399, VOP Lit must code the out mode to RGB888,
> +* VOP Big must code the out mode to RGB10.
> +*/
> +   ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
> +   encoder);
> +   if (ret > 0)
> +   s->output_mode = ROCKCHIP_OUT_MODE_P888;
> +   }
>
> return 0;
>  }
> @@ -378,6 +393,13 @@ static const struct dev_pm_ops rockchip_dp_pm_ops = {
>  #endif
>  };
>
> +static const struct rockchip_dp_chip_data rk3399_edp = {
> +   .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
> +   .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
> +   .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
> +   .chip_type = RK3399_EDP,
> +};
> +
>  static const struct rockchip_dp_chip_data rk3288_dp = {
> .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
> 

[PATCH v4 03/11] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting

[Sean Paul]

On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang  wrote:
> As vendor document indicate, when REF_CLK bit set 0, then DP
> phy's REF_CLK should switch to 24M source clock.
>
> But due to IC PHY layout mistaken, some chips need to flip this
> bit(like RK3288), and unfortunately they didn't indicate in the
> DP version register. That's why we have to make this little hack.
>
> Signed-off-by: Yakir Yang 
> Reviewed-by: Tomasz Figa 
> Tested-by: Javier Martinez Canillas 


Reviewed-by: Sean Paul 

> ---
> Changes in v4:
> - Remove subdev_type number, and add 'is_rockchip(type)' helper function 
> (Sean)
> - Add reviewed flag from Tomasz.
>
> Changes in v3:
> - Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
>   reg = ~reg & REF_CLK_MASK;  --->  reg ^= REF_CLK_MASK;
> 
> [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>  at 80]
> - Add tested flag from Javier
>
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 12 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h |  1 +
>  include/drm/bridge/analogix_dp.h  |  5 +
>  3 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c 
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 49205ef..48030f0 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -74,8 +74,12 @@ void analogix_dp_init_analog_param(struct 
> analogix_dp_device *dp)
> reg = SEL_24M | TX_DVDD_BIT_1_0625V;
> writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
>
> -   if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
> -   writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
> +   if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
> +   reg = REF_CLK_24M;
> +   if (dp->plat_data->dev_type == RK3288_DP)
> +   reg ^= REF_CLK_MASK;
> +
> +   writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
> writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
> writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
> writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
> @@ -244,7 +248,7 @@ void analogix_dp_set_analog_power_down(struct 
> analogix_dp_device *dp,
> u32 reg;
> u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
>
> -   if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
> +   if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
> phy_pd_addr = ANALOGIX_DP_PD;
>
> switch (block) {
> @@ -448,7 +452,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
> analogix_dp_reset_aux(dp);
>
> /* Disable AUX transaction H/W retry */
> -   if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
> +   if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
> reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
>   AUX_HW_RETRY_COUNT_SEL(3) |
>   AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h 
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> index 88d56ad..cdcc6c5 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> @@ -165,6 +165,7 @@
>  /* ANALOGIX_DP_PLL_REG_1 */
>  #define REF_CLK_24M(0x1 << 0)
>  #define REF_CLK_27M(0x0 << 0)
> +#define REF_CLK_MASK   (0x1 << 0)
>
>  /* ANALOGIX_DP_LANE_MAP */
>  #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
> diff --git a/include/drm/bridge/analogix_dp.h 
> b/include/drm/bridge/analogix_dp.h
> index 25afb31..790ab5d 100644
> --- a/include/drm/bridge/analogix_dp.h
> +++ b/include/drm/bridge/analogix_dp.h
> @@ -18,6 +18,11 @@ enum analogix_dp_devtype {
> RK3288_DP,
>  };
>
> +static inline bool is_rockchip(enum analogix_dp_devtype type)
> +{
> +   return type == RK3288_DP;
> +}
> +
>  struct analogix_dp_plat_data {
> enum analogix_dp_devtype dev_type;
> struct drm_panel *panel;
> --
> 1.9.1
>
>

[PATCH v4 01/11] drm/rockchip: analogix_dp: split the lcdc select setting into device data

[Sean Paul]

On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang  wrote:
> eDP controller need to declare which vop provide the video source,
> and it's defined in GRF registers.
>
> But different chips have different GRF register address, so we need to
> create a device data to declare the GRF messages for each chips.
>
> Signed-off-by: Yakir Yang 
> Acked-by: Mark Yao 
> Reviewed-by: Tomasz Figa 

Reviewed-by: Sean Paul 

> ---
> Changes in v4:
> - Assigned the GRF setting magic numbers to a #define that corresponds to
>   a TRM name. (Sean & Heiko)
> - Pass the chip type to device type directly. (Sean)
> - Add reviewed flag from Tomasz.
>
> Changes in v3:
> - Write a kerneldoc-style comment explaining the chips data fields (Tomasz, 
> reviewed at Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 39]
> - Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed at 
> Google Gerrit)
> 
> [https://chromium-review.googlesource.com/#/c/346313/10/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>  at 382]
> - Add acked flag from Mark.
>
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 49 
> -
>  1 file changed, 39 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index c120172..0a30931 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -14,6 +14,7 @@
>
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -33,13 +34,26 @@
>  #include "rockchip_drm_drv.h"
>  #include "rockchip_drm_vop.h"
>
> +#define RK3288_GRF_SOC_CON60x25c
> +#define RK3288_EDP_LCDC_SELBIT(5)
> +
> +#define HIWORD_UPDATE(val, mask)   (val | (mask) << 16)
> +
>  #define to_dp(nm)  container_of(nm, struct rockchip_dp_device, nm)
>
> -/* dp grf register offset */
> -#define GRF_SOC_CON60x025c
> -#define GRF_EDP_LCD_SEL_MASKBIT(5)
> -#define GRF_EDP_SEL_VOP_LIT BIT(5)
> -#define GRF_EDP_SEL_VOP_BIG 0
> +/**
> + * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
> + * @lcdsel_grf_reg: grf register offset of lcdc select
> + * @lcdsel_big: reg value of selecting vop big for eDP
> + * @lcdsel_lit: reg value of selecting vop little for eDP
> + * @chip_type: specific chip type
> + */
> +struct rockchip_dp_chip_data {
> +   u32 lcdsel_grf_reg;
> +   u32 lcdsel_big;
> +   u32 lcdsel_lit;
> +   u32 chip_type;
> +};
>
>  struct rockchip_dp_device {
> struct drm_device*drm_dev;
> @@ -51,6 +65,8 @@ struct rockchip_dp_device {
> struct regmap*grf;
> struct reset_control *rst;
>
> +   const struct rockchip_dp_chip_data *data;
> +
> struct analogix_dp_plat_data plat_data;
>  };
>
> @@ -119,13 +135,13 @@ static void rockchip_dp_drm_encoder_enable(struct 
> drm_encoder *encoder)
> return;
>
> if (ret)
> -   val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
> +   val = dp->data->lcdsel_lit;
> else
> -   val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
> +   val = dp->data->lcdsel_big;
>
> dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
>
> -   ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
> +   ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
> if (ret != 0) {
> dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
> return;
> @@ -246,6 +262,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
> device *master,
> void *data)
>  {
> struct rockchip_dp_device *dp = dev_get_drvdata(dev);
> +   const struct rockchip_dp_chip_data *dp_data;
> struct drm_device *drm_dev = data;
> int ret;
>
> @@ -256,10 +273,15 @@ static int rockchip_dp_bind(struct device *dev, struct 
> device *master,
>  */
> dev_set_drvdata(dev, NULL);
>
> +   dp_data = of_device_get_match_data(dev);
> +   if (!dp_data)
> +   return -ENODEV;
> +
> ret = rockchip_dp_init(dp);
> if (ret < 0)
> return ret;
>
> +   dp->data = dp_data;
> dp->drm_dev = drm_dev;
>
> ret = rockchip_dp_drm_create_encoder(dp);
> @@ -270,7 +292,7 @@ static int rockchip_dp_bind(struct device *dev, struct 
> device *master,
>
> dp->plat_data.encoder = >encoder;
>
> -   dp->plat_data.dev_type = RK3288_DP;
> +   dp->plat_data.dev_type = dp->data->chip_type;
> dp->plat_data.power_on = rockchip_dp_poweron;
> dp->plat_data.power_off = rockchip_dp_powerdown;
>
> @@ -356,8 +378,15 @@ static const struct dev_pm_ops rockchip_dp_pm_ops = {
>  

[PATCH] drm/vmwgfx: Fix corner case screen target surface management v2

[Thomas Hellstrom]

When the surface backing a framebuffer doesn't match the framebuffer's
dimensions, the screen target code would test the framebuffer dimensions
rather than the surface dimensions when deciding whether to bind the
surface as a screen target directly. This causes a screen target -
surface dimension mismatch and a subsequent device error.

Fix this by testing against the surface dimension.

v2: Remove an obsolete assignment

Signed-off-by: Thomas Hellstrom 
Reviewed-by: Sinclair Yeh 
Cc: 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index 9ca818f..41932a7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -399,8 +399,10 @@ static int vmw_stdu_bind_fb(struct vmw_private *dev_priv,

WARN_ON_ONCE(!stdu->defined);

-   if (!vfb->dmabuf && new_fb->width == mode->hdisplay &&
-   new_fb->height == mode->vdisplay)
+   new_vfbs = (vfb->dmabuf) ? NULL : vmw_framebuffer_to_vfbs(new_fb);
+
+   if (new_vfbs && new_vfbs->surface->base_size.width == mode->hdisplay &&
+   new_vfbs->surface->base_size.height == mode->vdisplay)
new_content_type = SAME_AS_DISPLAY;
else if (vfb->dmabuf)
new_content_type = SEPARATE_DMA;
@@ -444,7 +446,6 @@ static int vmw_stdu_bind_fb(struct vmw_private *dev_priv,
content_srf.mip_levels[0] = 1;
content_srf.multisample_count = 0;
} else {
-   new_vfbs = vmw_framebuffer_to_vfbs(new_fb);
content_srf = *new_vfbs->surface;
}

@@ -464,7 +465,6 @@ static int vmw_stdu_bind_fb(struct vmw_private *dev_priv,
return ret;
}
} else if (new_content_type == SAME_AS_DISPLAY) {
-   new_vfbs = vmw_framebuffer_to_vfbs(new_fb);
new_display_srf = vmw_surface_reference(new_vfbs->surface);
}

-- 
2.5.5

[PATCH 07/12] dt-bindings: i2c: Add support for 'i2c-bus' subnode

[Jon Hunter]

On 28/06/16 22:32, Wolfram Sang wrote:
> * PGP Signed by an unknown key
> 
>> For
>> example some Tegra devices have an I2C interface which may share its
>> pins with other devices and to share these pins subnodes for
>> representing these pins so they have be shared via the pinctrl framework
>> are needed.
> 
> I think the above sentence is hard to grasp. Can you split it into more
> sentences perhaps?

OK, yes does seem a bit of a mouthful.

>> +- i2c-bus
>> +For I2C adapters that have child nodes that are a mixture of both I2C
>> +devices and non-I2C devices (such as a pin controller), the 'i2c-bus'
> 
> I suggest to drop the phrase in the paranthesis. It is true for your
> case, but I don't think it's generic. So, it is not an obvious example
> like "Yes, sure, I see that a pin controller has I2C nodes and non-I2C
> nodes". At least for me, it was more like "It has what?"

OK, will drop that part.

Cheers
Jon

-- 
nvpublic

[PATCH 1/2] drm/fsl-dcu: update the panel dt binding document

[Meng Yi]

> >>  Optional properties:
> >>  - fsl,tcon:   The phandle to the timing controller node.
> >> @@ -24,6 +24,11 @@ dcu: dcu at 2ce {
> >>clocks = <_clk 0>, <_clk 0>;
> >>clock-names = "dcu", "pix";
> >>big-endian;
> >> -  fsl,panel = <>;
> >>fsl,tcon = <>;
> >> +
> >> +  port: port at 0 {
> >
> > Drop the unit address. With that,
> 
> I was going to say add a corresponding reg property and specify address-cells.
> 

For now, we only have one 'remote-endpoint', you mean maybe we should
use 'ports' that prepare for multiple connections?

> So is it ok to also create a port without address?
> 

It works fine, I think it is ok.

Best Regards,
Meng

[Bug 121021] drm/i915: kernel suspend during booting up

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=121021

--- Comment #5 from zhiquan.lee at gmail.com ---
Sorry for disturbing you, I was misled here, please ignore it.
I've filed the bug at:
https://bugs.freedesktop.org/show_bug.cgi?id=96692

-- 
You are receiving this mail because:
You are watching the assignee of the bug.

[PATCH 08/12] i2c: core: Add support for 'i2c-bus' subnode

[Wolfram Sang]

> Would you be okay if I take this patch along with the device tree
> binding change into a stable branch and provide a tag for you to pull
> into the I2C tree?

Yes, once my comments to the previous patch are addressed, we can do
that. For this patch already:

Acked-by: Wolfram Sang 

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[PATCH 07/12] dt-bindings: i2c: Add support for 'i2c-bus' subnode

[Wolfram Sang]

> For
> example some Tegra devices have an I2C interface which may share its
> pins with other devices and to share these pins subnodes for
> representing these pins so they have be shared via the pinctrl framework
> are needed.

I think the above sentence is hard to grasp. Can you split it into more
sentences perhaps?

> +- i2c-bus
> + For I2C adapters that have child nodes that are a mixture of both I2C
> + devices and non-I2C devices (such as a pin controller), the 'i2c-bus'

I suggest to drop the phrase in the paranthesis. It is true for your
case, but I don't think it's generic. So, it is not an obvious example
like "Yes, sure, I see that a pin controller has I2C nodes and non-I2C
nodes". At least for me, it was more like "It has what?"

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[PATCH] drm/exynos: Remove deprecated create_singlethread_workqueue

[Bhaktipriya Shridhar]

Please ignore this mail.
Thanks,
Bhaktipriya


On Tue, Jun 28, 2016 at 10:48 PM, Bhaktipriya Shridhar
 wrote:
> The workqueue g2d_workq has only a single workitem(>runqueue_work)
> and hence doesn't require ordering. Also, it is not being used on a
> memory reclaim path. Hence, the singlethreaded workqueue has been
> replaced with the use of system_wq.
>
> System workqueues have been able to handle high level of concurrency
> for a long time now and hence it's not required to have a singlethreaded
> workqueue just to gain concurrency. Unlike a dedicated per-cpu workqueue
> created with create_singlethread_workqueue(), system_wq allows multiple
> work items to overlap executions even on the same CPU; however, a
> per-cpu workqueue doesn't have any CPU locality or global ordering
> guarantee unless the target CPU is explicitly specified and thus the
> increase of local concurrency shouldn't make any difference.
>
> Occurences of the label err_destroy_workqueue have also been removed
> because with the usage of system_wq, calls to destroy_workqueue() have
> been dropped, which makes the label unnecessary.
>
> Work item has been flushed in g2d_remove() to ensure that nothing is
> pending when the driver disconnects.
>
> Signed-off-by: Bhaktipriya Shridhar 
> ---
>  drivers/gpu/drm/exynos/exynos_drm_g2d.c | 16 +++-
>  1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c 
> b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
> index 4935523..defb9d0 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
> @@ -224,7 +224,6 @@ struct g2d_data {
> struct clk  *gate_clk;
> void __iomem*regs;
> int irq;
> -   struct workqueue_struct *g2d_workq;
> struct work_struct  runqueue_work;
> struct exynos_drm_subdrvsubdrv;
> boolsuspended;
> @@ -921,7 +920,7 @@ static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
> }
>
> if (pending & G2D_INTP_ACMD_FIN)
> -   queue_work(g2d->g2d_workq, >runqueue_work);
> +   schedule_work(>runqueue_work);
>
> return IRQ_HANDLED;
>  }
> @@ -1380,13 +1379,6 @@ static int g2d_probe(struct platform_device *pdev)
>
> g2d->dev = dev;
>
> -   g2d->g2d_workq = create_singlethread_workqueue("g2d");
> -   if (!g2d->g2d_workq) {
> -   dev_err(dev, "failed to create workqueue\n");
> -   ret = -EINVAL;
> -   goto err_destroy_slab;
> -   }
> -
> INIT_WORK(>runqueue_work, g2d_runqueue_worker);
> INIT_LIST_HEAD(>free_cmdlist);
> INIT_LIST_HEAD(>runqueue);
> @@ -1398,7 +1390,7 @@ static int g2d_probe(struct platform_device *pdev)
> if (IS_ERR(g2d->gate_clk)) {
> dev_err(dev, "failed to get gate clock\n");
> ret = PTR_ERR(g2d->gate_clk);
> -   goto err_destroy_workqueue;
> +   goto err_destroy_slab;
> }
>
> pm_runtime_enable(dev);
> @@ -1449,8 +1441,6 @@ static int g2d_probe(struct platform_device *pdev)
>
>  err_put_clk:
> pm_runtime_disable(dev);
> -err_destroy_workqueue:
> -   destroy_workqueue(g2d->g2d_workq);
>  err_destroy_slab:
> kmem_cache_destroy(g2d->runqueue_slab);
> return ret;
> @@ -1471,7 +1461,7 @@ static int g2d_remove(struct platform_device *pdev)
> pm_runtime_disable(>dev);
>
> g2d_fini_cmdlist(g2d);
> -   destroy_workqueue(g2d->g2d_workq);
> +   flush_work(>runqueue_work);
> kmem_cache_destroy(g2d->runqueue_slab);
>
> return 0;
> --
> 2.1.4
>

[PATCH] drm/radeon: Remove deprecated create_singlethread_workqueue

[Bhaktipriya Shridhar]

Please ignore this mail.
Thanks,
Bhaktipriya


On Tue, Jun 28, 2016 at 10:56 PM, Bhaktipriya Shridhar
 wrote:
> alloc_workqueue replaces deprecated create_singlethread_workqueue().
>
> A dedicated workqueue has been used since work items need to be flushed
> as a group rather than individually.
>
> Since the flip_queue workqueue is involved in page-flipping and is not
> being used on a memory reclaim path, WQ_MEM_RECLAIM has not been set.
>
> Since there are only a fixed number of work items, explicit concurrency
> limit is unnecessary here.
>
> Signed-off-by: Bhaktipriya Shridhar 
> ---
>  drivers/gpu/drm/radeon/radeon_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_display.c 
> b/drivers/gpu/drm/radeon/radeon_display.c
> index 6a41b49..bbb29c7 100644
> --- a/drivers/gpu/drm/radeon/radeon_display.c
> +++ b/drivers/gpu/drm/radeon/radeon_display.c
> @@ -711,7 +711,7 @@ static void radeon_crtc_init(struct drm_device *dev, int 
> index)
>
> drm_mode_crtc_set_gamma_size(_crtc->base, 256);
> radeon_crtc->crtc_id = index;
> -   radeon_crtc->flip_queue = 
> create_singlethread_workqueue("radeon-crtc");
> +   radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", 0, 0);
> rdev->mode_info.crtcs[index] = radeon_crtc;
>
> if (rdev->family >= CHIP_BONAIRE) {
> --
> 2.1.4
>

[PATCH] drm/omap: panel-dsi-cm: Remove deprecated create_singlethread_workqueue

[Bhaktipriya Shridhar]

Please ignore this mail.
Thanks,
Bhaktipriya


On Tue, Jun 28, 2016 at 10:53 PM, Bhaktipriya Shridhar
 wrote:
> The workqueue "workqueue" has only a single workitem(>ulps_work) per
> panel_drv_data and hence doesn't require ordering.
> Also, it is not being used on a memory reclaim path. Hence, the
> singlethreaded workqueue has been replaced with the use of system_wq.
>
> System workqueues have been able to handle high level of concurrency
> for a long time now and hence it's not required to have a singlethreaded
> workqueue just to gain concurrency. Unlike a dedicated per-cpu workqueue
> created with create_singlethread_workqueue(), system_wq allows multiple
> work items to overlap executions even on the same CPU; however, a
> per-cpu workqueue doesn't have any CPU locality or global ordering
> guarantee unless the target CPU is explicitly specified and thus the
> increase of local concurrency shouldn't make any difference.
>
> Occurrences of the label err_bl have also been removed because with the
> usage of system_wq, calls to destroy_workqueue() have been dropped,
> which makes the label unnecessary.
>
> Workitem is sync cancelled in dsicm_cancel_ulps_work() which is called
> in dsicm_remove() to ensure that there are no workitems pending when the
> driver is disconnected.
>
> Signed-off-by: Bhaktipriya Shridhar 
> ---
>  drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c | 15 ++-
>  1 file changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c 
> b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
> index 2b11807..e614d5b 100644
> --- a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
> +++ b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
> @@ -76,8 +76,6 @@ struct panel_drv_data {
>
> bool intro_printed;
>
> -   struct workqueue_struct *workqueue;
> -
> bool ulps_enabled;
> unsigned ulps_timeout;
> struct delayed_work ulps_work;
> @@ -233,7 +231,7 @@ static int dsicm_set_update_window(struct panel_drv_data 
> *ddata,
>  static void dsicm_queue_ulps_work(struct panel_drv_data *ddata)
>  {
> if (ddata->ulps_timeout > 0)
> -   queue_delayed_work(ddata->workqueue, >ulps_work,
> +   schedule_delayed_work(>ulps_work,
> msecs_to_jiffies(ddata->ulps_timeout));
>  }
>
> @@ -1245,11 +1243,6 @@ static int dsicm_probe(struct platform_device *pdev)
> dev_dbg(dev, "Using GPIO TE\n");
> }
>
> -   ddata->workqueue = create_singlethread_workqueue("dsicm_wq");
> -   if (ddata->workqueue == NULL) {
> -   dev_err(dev, "can't create workqueue\n");
> -   return -ENOMEM;
> -   }
> INIT_DELAYED_WORK(>ulps_work, dsicm_ulps_work);
>
> dsicm_hw_reset(ddata);
> @@ -1263,7 +1256,7 @@ static int dsicm_probe(struct platform_device *pdev)
> dev, ddata, _bl_ops, );
> if (IS_ERR(bldev)) {
> r = PTR_ERR(bldev);
> -   goto err_bl;
> +   goto err_reg;
> }
>
> ddata->bldev = bldev;
> @@ -1286,8 +1279,6 @@ static int dsicm_probe(struct platform_device *pdev)
>  err_sysfs_create:
> if (bldev != NULL)
> backlight_device_unregister(bldev);
> -err_bl:
> -   destroy_workqueue(ddata->workqueue);
>  err_reg:
> return r;
>  }
> @@ -1317,8 +1308,6 @@ static int __exit dsicm_remove(struct platform_device 
> *pdev)
> omap_dss_put_device(ddata->in);
>
> dsicm_cancel_ulps_work(ddata);
> -   destroy_workqueue(ddata->workqueue);
> -
> /* reset, to be sure that the panel is in a valid state */
> dsicm_hw_reset(ddata);
>
> --
> 2.1.4
>

[PATCH] drm/exynos: Remove deprecated create_singlethread_workqueue

[Bhaktipriya Shridhar]

Please ignore this mail.



On Tue, Jun 28, 2016 at 10:48 PM, Bhaktipriya Shridhar
 wrote:
> The workqueue g2d_workq has only a single workitem(>runqueue_work)
> and hence doesn't require ordering. Also, it is not being used on a
> memory reclaim path. Hence, the singlethreaded workqueue has been
> replaced with the use of system_wq.
>
> System workqueues have been able to handle high level of concurrency
> for a long time now and hence it's not required to have a singlethreaded
> workqueue just to gain concurrency. Unlike a dedicated per-cpu workqueue
> created with create_singlethread_workqueue(), system_wq allows multiple
> work items to overlap executions even on the same CPU; however, a
> per-cpu workqueue doesn't have any CPU locality or global ordering
> guarantee unless the target CPU is explicitly specified and thus the
> increase of local concurrency shouldn't make any difference.
>
> Occurences of the label err_destroy_workqueue have also been removed
> because with the usage of system_wq, calls to destroy_workqueue() have
> been dropped, which makes the label unnecessary.
>
> Work item has been flushed in g2d_remove() to ensure that nothing is
> pending when the driver disconnects.
>
> Signed-off-by: Bhaktipriya Shridhar 
> ---
>  drivers/gpu/drm/exynos/exynos_drm_g2d.c | 16 +++-
>  1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c 
> b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
> index 4935523..defb9d0 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
> @@ -224,7 +224,6 @@ struct g2d_data {
> struct clk  *gate_clk;
> void __iomem*regs;
> int irq;
> -   struct workqueue_struct *g2d_workq;
> struct work_struct  runqueue_work;
> struct exynos_drm_subdrvsubdrv;
> boolsuspended;
> @@ -921,7 +920,7 @@ static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
> }
>
> if (pending & G2D_INTP_ACMD_FIN)
> -   queue_work(g2d->g2d_workq, >runqueue_work);
> +   schedule_work(>runqueue_work);
>
> return IRQ_HANDLED;
>  }
> @@ -1380,13 +1379,6 @@ static int g2d_probe(struct platform_device *pdev)
>
> g2d->dev = dev;
>
> -   g2d->g2d_workq = create_singlethread_workqueue("g2d");
> -   if (!g2d->g2d_workq) {
> -   dev_err(dev, "failed to create workqueue\n");
> -   ret = -EINVAL;
> -   goto err_destroy_slab;
> -   }
> -
> INIT_WORK(>runqueue_work, g2d_runqueue_worker);
> INIT_LIST_HEAD(>free_cmdlist);
> INIT_LIST_HEAD(>runqueue);
> @@ -1398,7 +1390,7 @@ static int g2d_probe(struct platform_device *pdev)
> if (IS_ERR(g2d->gate_clk)) {
> dev_err(dev, "failed to get gate clock\n");
> ret = PTR_ERR(g2d->gate_clk);
> -   goto err_destroy_workqueue;
> +   goto err_destroy_slab;
> }
>
> pm_runtime_enable(dev);
> @@ -1449,8 +1441,6 @@ static int g2d_probe(struct platform_device *pdev)
>
>  err_put_clk:
> pm_runtime_disable(dev);
> -err_destroy_workqueue:
> -   destroy_workqueue(g2d->g2d_workq);
>  err_destroy_slab:
> kmem_cache_destroy(g2d->runqueue_slab);
> return ret;
> @@ -1471,7 +1461,7 @@ static int g2d_remove(struct platform_device *pdev)
> pm_runtime_disable(>dev);
>
> g2d_fini_cmdlist(g2d);
> -   destroy_workqueue(g2d->g2d_workq);
> +   flush_work(>runqueue_work);
> kmem_cache_destroy(g2d->runqueue_slab);
>
> return 0;
> --
> 2.1.4
>

[PATCH 08/12] i2c: core: Add support for 'i2c-bus' subnode

[Thierry Reding]

On Thu, Jun 23, 2016 at 04:59:01PM +0100, Jon Hunter wrote:
> If the 'i2c-bus' device-tree node is present for an I2C adapter then
> parse this subnode for I2C slaves.
> 
> Signed-off-by: Jon Hunter 
> ---
>  drivers/i2c/i2c-core.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)

Hi Wolfram,

are you okay with this change? I'd like to take this through the Tegra
tree, with your Acked-by, to resolve the dependency of subsequent
patches.

Would you be okay if I take this patch along with the device tree
binding change into a stable branch and provide a tag for you to pull
into the I2C tree?

Thierry
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