[PATCH] drm/atomic_helper: correct kernel-doc function name warning
kernel-doc warns that a function name in a comment does not match the code's function name, so correct that. ../drivers/gpu/drm/drm_atomic_helper.c:802: warning: expecting prototype for drm_atomic_helper_check_wb_connector_state(). Prototype was for drm_atomic_helper_check_wb_encoder_state() instead Signed-off-by: Randy Dunlap Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel@lists.freedesktop.org Cc: airl...@gmail.com --- drivers/gpu/drm/drm_atomic_helper.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -786,7 +786,7 @@ drm_atomic_helper_check_modeset(struct d EXPORT_SYMBOL(drm_atomic_helper_check_modeset); /** - * drm_atomic_helper_check_wb_connector_state() - Check writeback encoder state + * drm_atomic_helper_check_wb_encoder_state() - Check writeback encoder state * @encoder: encoder state to check * @conn_state: connector state to check *
Re: [PATCH v6 0/4] Let userspace know when snd-hda-intel needs i915
Hi Luis, On Mon, 9 May 2022 13:38:28 -0700 Luis Chamberlain wrote: > On Mon, May 09, 2022 at 06:23:35PM +0200, Mauro Carvalho Chehab wrote: > > Currently, kernel/module annotates module dependencies when > > request_symbol is used, but it doesn't cover more complex inter-driver > > dependencies that are subsystem and/or driver-specific. > > > > At this pount v5.18-rc7 is out and so it is too late to soak this > in for the proper level of testing I'd like to see for modules-next. > So I can review this after the next merge window. I'd want to beat > the hell out of this and if possible I'd like to see if we can have > some test coverage for the intended goal and how to break it. Any news with regards to this patch series? Regards, Mauro
Re: [PATCH v2] drm: mediatek: Fix display vblank timeout when disable dsi
Hi CK,
We can use [1] in mt8186. Please ignore this PATCH.
Thanks,
Allen
[1]
http://lists.infradead.org/pipermail/linux-mediatek/2022-August/046713.html
On 9/19/22 11:01, Allen-KH Cheng wrote:
> Hi CK,
>
> We will test this fix on the mt8186/mt8183.
> Maybe our fix is not necessary.
>
> I appreciate your suggestion.
>
> BRs,
> Allen
>
> On 9/18/22 12:32, Chun-Kuang Hu wrote:
>> Hi, Allen:
>>
>> Allen-KH Cheng 於 2022年9月14日 週三 晚上10:00寫道：
>>>
>>> From: Xinlei Lee
>>>
>>> Dsi is turned off at bridge.disable, causing crtc to wait for vblank
>>> timeout. It is necessary to add count protection to turn off dsi and
>>> turn off at post_disable.
>>
>> If turn off dsi in post_disable(), you should turn on dsi in pre_enable().
>>
>> There is another patch fix this problem [1], do you have any comment
>> on that patch?
>>
>> [1]
>> http://lists.infradead.org/pipermail/linux-mediatek/2022-August/046713.html
>>
>> Regards,
>> Chun-Kuang.
>>
>>>
>>> Fixes: cde7e2e35c28 ("drm/mediatek: Separate poweron/poweroff from
>>> enable/disable and define new funcs")
>>> Signed-off-by: Xinlei Lee
>>> Co-developed-by: Allen-KH Cheng
>>> Signed-off-by: Allen-KH Cheng
>>> ---
>>> Change in v1:
>>> * Rebase to kernel/git/chunkuang.hu/linux.git, mediatek-drm-fixes
>>> [Allen-KH Cheng ]
>>> ---
>>> ---
>>> drivers/gpu/drm/mediatek/mtk_dsi.c | 15 ++-
>>> 1 file changed, 6 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> index 5b624e0f5b0a..e30f4244c001 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> @@ -768,14 +768,6 @@ static void mtk_dsi_bridge_mode_set(struct drm_bridge
>>> *bridge,
>>> drm_display_mode_to_videomode(adjusted, >vm);
>>> }
>>>
>>> -static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
>>> - struct drm_bridge_state
>>> *old_bridge_state)
>>> -{
>>> - struct mtk_dsi *dsi = bridge_to_dsi(bridge);
>>> -
>>> - mtk_output_dsi_disable(dsi);
>>> -}
>>> -
>>> static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
>>> struct drm_bridge_state
>>> *old_bridge_state)
>>> {
>>> @@ -803,13 +795,15 @@ static void mtk_dsi_bridge_atomic_post_disable(struct
>>> drm_bridge *bridge,
>>> {
>>> struct mtk_dsi *dsi = bridge_to_dsi(bridge);
>>>
>>> + if (dsi->refcount == 1)
>>> + mtk_output_dsi_disable(dsi);
>>> +
>>> mtk_dsi_poweroff(dsi);
>>> }
>>>
>>> static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
>>> .attach = mtk_dsi_bridge_attach,
>>> .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
>>> - .atomic_disable = mtk_dsi_bridge_atomic_disable,
>>> .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
>>> .atomic_enable = mtk_dsi_bridge_atomic_enable,
>>> .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
>>> @@ -829,6 +823,9 @@ void mtk_dsi_ddp_stop(struct device *dev)
>>> {
>>> struct mtk_dsi *dsi = dev_get_drvdata(dev);
>>>
>>> + if (dsi->refcount == 1)
>>> + mtk_output_dsi_disable(dsi);
>>> +
>>> mtk_dsi_poweroff(dsi);
>>> }
>>>
>>> --
>>> 2.18.0
>>>
Re: [PATCH 2/2] drm/i915/mtl: Add C6 residency support for MTL SAMedia
On Mon, 19 Sep 2022 05:13:18 -0700, Jani Nikula wrote:
>
> On Mon, 19 Sep 2022, Badal Nilawar wrote:
> > For MTL SAMedia updated relevant functions and places in the code to get
> > Media C6 residency.
> >
> > v2: Fixed review comments (Ashutosh)
> >
> > Cc: Vinay Belgaumkar
> > Cc: Ashutosh Dixit
> > Cc: Chris Wilson
> > Signed-off-by: Badal Nilawar
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 60 +++
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10
> > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
> > drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
> > drivers/gpu/drm/i915/gt/selftest_rc6.c| 9 ++-
> > drivers/gpu/drm/i915/i915_pmu.c | 8 ++-
> > 6 files changed, 97 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > index 68310881a793..053167b506a9 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > @@ -269,6 +269,64 @@ static int ilk_drpc(struct seq_file *m)
> > return 0;
> > }
> >
> > +static int mtl_drpc(struct seq_file *m)
> > +{
> > + struct intel_gt *gt = m->private;
> > + struct intel_uncore *uncore = gt->uncore;
> > + u32 gt_core_status, rcctl1, global_forcewake;
> > + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
> > + i915_reg_t reg;
> > +
> > + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> > +
> > + global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9);
> > +
> > + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> > + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
> > + mtl_powergate_status = intel_uncore_read(uncore,
> > +GEN9_PWRGT_DOMAIN_STATUS);
> > +
> > + seq_printf(m, "RC6 Enabled: %s\n",
> > + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> > + if (gt->type == GT_MEDIA) {
> > + seq_printf(m, "Media Well Gating Enabled: %s\n",
> > + str_yes_no(mtl_powergate_enable &
> > GEN9_MEDIA_PG_ENABLE));
> > + } else {
> > + seq_printf(m, "Render Well Gating Enabled: %s\n",
> > + str_yes_no(mtl_powergate_enable &
> > GEN9_RENDER_PG_ENABLE));
> > + }
> > +
> > + seq_puts(m, "Current RC state: ");
> > +
> > + switch ((gt_core_status & MTL_CC_MASK) >> MTL_CC_SHIFT) {
> > + case MTL_CC0:
> > + seq_puts(m, "on\n");
> > + break;
> > + case MTL_CC6:
> > + seq_puts(m, "RC6\n");
> > + break;
> > + default:
> > + seq_puts(m, "Unknown\n");
> > + break;
> > + }
> > +
> > + if (gt->type == GT_MEDIA)
> > + seq_printf(m, "Media Power Well: %s\n",
> > + (mtl_powergate_status &
> > + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
> > + else
> > + seq_printf(m, "Render Power Well: %s\n",
> > + (mtl_powergate_status &
> > + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> > +
> > + reg = (gt->type == GT_MEDIA) ? MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6;
> > + print_rc6_res(m, "RC6 residency since boot:", reg);
>
> Cc: Tvrtko, Joonas, Rodrigo
>
Hi Jani,
> IMO the register is not a good abstraction to build interfaces on. I see
> that this is not where the idea is introduced, but it'll probably get
> you in trouble later on.
By "this is not where the idea is introduced" are you referring to what we
did here:
https://patchwork.freedesktop.org/patch/502372/?series=108091=5
in intel_gt_perf_limit_reasons_reg()?
Or, should we follow the schema of centralizing the register selection
depending on gt type in a single function here too (since this register
selection is repeated throughout this patch)?
Thanks.
--
Ashutosh
>
> BR,
> Jani.
>
> > +
> > + seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake);
> > +
> > + return fw_domains_show(m, NULL);
> > +}
> > +
> > static int drpc_show(struct seq_file *m, void *unused)
> > {
> > struct intel_gt *gt = m->private;
> > @@ -279,6 +337,8 @@ static int drpc_show(struct seq_file *m, void *unused)
> > with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > err = vlv_drpc(m);
> > + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > + err = mtl_drpc(m);
> > else if (GRAPHICS_VER(i915) >= 6)
> > err = gen6_drpc(m);
> > else
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 7819d32db956..8a56fd873228 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1517,6 +1517,16 @@
> > */
> > #define MTL_MIRROR_TARGET_WP1
Re: [PATCH] drm/amdgpu: use dirty framebuffer helper
Thanks, the patch applied against 6.0-rc6 kernel worked and the amdgpu module
loaded and works on my Radeon R7 250 (Cape Verde) GPU.
Arthur Marsh.
On 20 September 2022 2:03:54 am ACST, Alex Deucher
wrote:
>On Sun, Sep 18, 2022 at 8:09 AM root wrote:
>>
>> Hi, I recently experienced lock-ups that only responded to magic sysreq
>> reboots when the amdgpu module was loading on my pc (Athlon II X4 640 CPU,
>> with Radeon R7 250 - Cape Verde).
>>
>> .config has:
>>
>> CONFIG_DRM_AMDGPU=m
>> CONFIG_DRM_AMDGPU_SI=y
>> # CONFIG_DRM_AMDGPU_CIK is not set
>> # CONFIG_DRM_AMDGPU_USERPTR is not set
>>
>> kernel command line has:
>>
>> amdgpu.audio=1 amdgpu.si_support=1 radeon.si_support=0 page_owner=on \
>> amdgpu.gpu_recovery=1
>>
>> Bisecting lead to:
>>
>> commit 66f99628eb24409cb8feb5061f78283c8b65f820
>> Author: Hamza Mahfooz
>> Date: Tue Sep 6 15:01:49 2022 -0400
>>
>> drm/amdgpu: use dirty framebuffer helper
>>
>> Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
>> drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
>> struct.
>>
>> Signed-off-by: Hamza Mahfooz
>> Acked-by: Alex Deucher
>> Signed-off-by: Alex Deucher
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> index c20922a5af9f..5b09c8f4fe95 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> @@ -38,6 +38,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -496,6 +497,7 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector
>> *amdgpu_connector,
>> static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
>> .destroy = drm_gem_fb_destroy,
>> .create_handle = drm_gem_fb_create_handle,
>> + .dirty = drm_atomic_helper_dirtyfb,
>> };
>>
>> uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>>
>> After doing a git bisect reset, git pull and reverting the patch above, I
>> rebuilt the kernel and am successfully running with the amdgpu module loaded
>> and using the Radeon R7 250 GPU.
>>
>> I am happy to supply any further configuration details.
>
>Does the attached patch help?
>
>Alex
>
>
>>
>> Arthur Marsh.
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
Re: [PATCH v3] drm/sched: Add FIFO sched policy to run queue v3
Please run this patch through checkpatch.pl, as it shows
12 warnings with it. Use these command line options:
"--strict --show-types".
Inlined:
On 2022-09-13 16:40, Andrey Grodzovsky wrote:
> Given many entities competing for same run queue on
> the same scheduler and unacceptably long wait time for some
> jobs waiting stuck in the run queue before being picked up are
> observed (seen using GPUVis).
Since the second part of this sentence is the result of the first,
I'd say something like "When many entities ... we see unacceptably long ...".
> The issue is due to the Round Robin policy used by schedulers
> to pick up the next entity's job queue for execution. Under stress
> of many entities and long job queus within entity some
Spelling: "queues".
> jobs could be stack for very long time in it's entity's
"stuck", not "stack".
> queue before being popped from the queue and executed
> while for other entities with smaller job queues a job
> might execute earlier even though that job arrived later
> then the job in the long queue.
"than".
>
> Fix:
> Add FIFO selection policy to entities in run queue, chose next entity
> on run queue in such order that if job on one entity arrived
> earlier then job on another entity the first job will start
> executing earlier regardless of the length of the entity's job
> queue.
>
> v2:
> Switch to rb tree structure for entities based on TS of
> oldest job waiting in the job queue of an entity. Improves next
> entity extraction to O(1). Entity TS update
> O(log N) where N is the number of entities in the run-queue
>
> Drop default option in module control parameter.
>
> v3:
> Various cosmetical fixes and minor refactoring of fifo update function.
> Signed-off-by: Andrey Grodzovsky
> Tested-by: Li Yunxiang (Teddy)
> ---
> drivers/gpu/drm/scheduler/sched_entity.c | 26 -
> drivers/gpu/drm/scheduler/sched_main.c | 132 ++-
> include/drm/gpu_scheduler.h | 35 ++
> 3 files changed, 187 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
> b/drivers/gpu/drm/scheduler/sched_entity.c
> index 6b25b2f4f5a3..f3ffce3c9304 100644
> --- a/drivers/gpu/drm/scheduler/sched_entity.c
> +++ b/drivers/gpu/drm/scheduler/sched_entity.c
> @@ -73,6 +73,7 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
> entity->priority = priority;
> entity->sched_list = num_sched_list > 1 ? sched_list : NULL;
> entity->last_scheduled = NULL;
> + RB_CLEAR_NODE(>rb_tree_node);
>
> if(num_sched_list)
> entity->rq = _list[0]->sched_rq[entity->priority];
> @@ -417,14 +418,16 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct
> drm_sched_entity *entity)
>
> sched_job = to_drm_sched_job(spsc_queue_peek(>job_queue));
> if (!sched_job)
> - return NULL;
> + goto skip;
>
> while ((entity->dependency =
> drm_sched_job_dependency(sched_job, entity))) {
> trace_drm_sched_job_wait_dep(sched_job, entity->dependency);
>
> - if (drm_sched_entity_add_dependency_cb(entity))
> - return NULL;
> + if (drm_sched_entity_add_dependency_cb(entity)) {
> + sched_job = NULL;
> + goto skip;
> + }
> }
>
> /* skip jobs from entity that marked guilty */
> @@ -443,6 +446,16 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct
> drm_sched_entity *entity)
> smp_wmb();
>
> spsc_queue_pop(>job_queue);
> +
> + /*
> + * It's when head job is extracted we can access the next job (or empty)
> + * queue and update the entity location in the min heap accordingly.
> + */
> +skip:
> + if (drm_sched_policy == DRM_SCHED_POLICY_FIFO)
> + drm_sched_rq_update_fifo(entity,
> + (sched_job ? sched_job->submit_ts :
> ktime_get()));
> +
> return sched_job;
> }
>
> @@ -502,11 +515,13 @@ void drm_sched_entity_push_job(struct drm_sched_job
> *sched_job)
> {
> struct drm_sched_entity *entity = sched_job->entity;
> bool first;
> + ktime_t ts = ktime_get();
>
> trace_drm_sched_job(sched_job, entity);
> atomic_inc(entity->rq->sched->score);
> WRITE_ONCE(entity->last_user, current->group_leader);
> first = spsc_queue_push(>job_queue, _job->queue_node);
> + sched_job->submit_ts = ts;
>
> /* first job wakes up scheduler */
> if (first) {
> @@ -518,8 +533,13 @@ void drm_sched_entity_push_job(struct drm_sched_job
> *sched_job)
> DRM_ERROR("Trying to push to a killed entity\n");
> return;
> }
> +
> drm_sched_rq_add_entity(entity->rq, entity);
> spin_unlock(>rq_lock);
> +
> + if (drm_sched_policy == DRM_SCHED_POLICY_FIFO)
> +
Re: [PATCH i-g-t v2 3/4] lib/igt_kmod: add compatibility for KUnit
On Mon, Sep 19, 2022 at 1:43 PM Isabella Basso wrote: > >> +* "(K)TAP version XX" should be the first line on all (sub)tests > >> as per > >> +* > >> https://www.kernel.org/doc/html/latest/dev-tools/ktap.html#version-lines > >> +* but actually isn't, as it currently depends on whoever writes > >> the > >> +* test to print this info > > > > FYI: we're really trying to fix cases of "missing version lines", > > largely by making the kunit_test_suites() macro work in more > > circumstances. > > > > So while it may be worth still handling the case where this is > > missing, I don't think there are any tests in the latest versions of > > the kernel which should have this missing. > > I’m not sure if I totally get how these work. Every time I run a KUnit test I > get something like this: https://pastebin.com/7Ff31PMC > > As you can see it has been loaded as a module, just like we intend to do it > from IGT, and I see no version lines whatsoever. Am I doing something wrong? You're doing everything right. The problem is we only print the version line for the *built-in* tests. It never gets printed for tests in loadable modules. Some more details below, if interested. Specifically, it happens in https://elixir.bootlin.com/linux/latest/C/ident/kunit_print_tap_header What David is referring to is we had tests that weren't in modules, but didn't use the normal built-in code path. Those were also missing TAP version lines. But KUnit needs to do better here in the case of modules. The goal was that you'd be able to parse the result of module based tests by something like $ cat /sys/kernel/debug/kunit/*/results | ./tools/testing/kunit/kunit.py parse but this doesn't work because of the lack of a version line. If we add it to each module's test results, then we'll need to update the parse to allow multiple verison lines, I think. Daniel
Re: [Intel-gfx] [PATCH] drm/i915/gt: Bump the reset-failure timeout to 60s
On Fri, Sep 16, 2022 at 01:48:23PM -0700, Ashutosh Dixit wrote:
> From: Chris Wilson
>
> If attempting to perform a GT reset takes long than 5 seconds (including
> resetting the display for gen3/4), then we declare all hope lost and
> discard all user work and wedge the device to prevent further
> misbehaviour. 5 seconds is too short a time for such drastic action, as
> we may be stuck on other timeouts and watchdogs. If we allow a little
> bit longer before hitting the big red button, we should at the very
> least capture other hung task indicators pointing towards the reason why
> the reset was hanging; and allow more marginal cases the extra headroom
> to complete the reset without further collateral damage.
>
> Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/6448
> Signed-off-by: Chris Wilson
Seems reasonable.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index b36674356986..3159df6cdd49 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1278,7 +1278,7 @@ static void intel_gt_reset_global(struct intel_gt *gt,
> kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
>
> /* Use a watchdog to ensure that our reset completes */
> - intel_wedge_on_timeout(, gt, 5 * HZ) {
> + intel_wedge_on_timeout(, gt, 60 * HZ) {
> intel_display_prepare_reset(gt->i915);
>
> intel_gt_reset(gt, engine_mask, reason);
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [BUG][5.20] refcount_t: underflow; use-after-free
Hi! Unfortunately the use-after-free issue still happens on the 6.0-rc5 kernel. The issue became hard to repeat. I spent the whole day at the computer when use-after-free again happened, I was playing the game Tiny Tina's Wonderlands. Therefore, forget about repeatability. It remains only to hope for logs and tracing. I didn't see anything new in the logs. It seems that we need to somehow expand the logging so that the next time this happens we have more information. Sep 18 20:52:16 primary-ws gnome-shell[2388]: meta_window_set_stack_position_no_sync: assertion 'window->stack_position >= 0' failed Sep 18 20:52:27 primary-ws gnome-shell[2388]: meta_window_set_stack_position_no_sync: assertion 'window->stack_position >= 0' failed Sep 18 20:53:44 primary-ws gnome-shell[2388]: Window manager warning: Window 0x4e3 sets an MWM hint indicating it isn't resizable, but sets min size 1 x 1 and max size 2147483647 x 2147483647; this doesn't make much sense. Sep 18 20:53:45 primary-ws kernel: umip_printk: 11 callbacks suppressed Sep 18 20:53:45 primary-ws kernel: umip: Wonderlands.exe[213853] ip:14ebb0d03 sp:4ee528: SGDT instruction cannot be used by applications. Sep 18 20:53:45 primary-ws kernel: umip: Wonderlands.exe[213853] ip:14ebb0d03 sp:4ee528: For now, expensive software emulation returns the result. Sep 18 20:53:53 primary-ws gnome-shell[2388]: meta_window_set_stack_position_no_sync: assertion 'window->stack_position >= 0' failed Sep 18 20:53:53 primary-ws kernel: umip: Wonderlands.exe[213853] ip:14ebb0d03 sp:4ee528: SGDT instruction cannot be used by applications. Sep 18 20:53:53 primary-ws kernel: umip: Wonderlands.exe[213853] ip:14ebb0d03 sp:4ee528: For now, expensive software emulation returns the result. Sep 18 20:54:15 primary-ws kernel: umip: Wonderlands.exe[214194] ip:15a270815 sp:6eaef490: SGDT instruction cannot be used by applications. Sep 18 20:56:01 primary-ws kernel: umip_printk: 15 callbacks suppressed Sep 18 20:56:01 primary-ws kernel: umip: Wonderlands.exe[213853] ip:15e3a82b0 sp:4ed178: SGDT instruction cannot be used by applications. Sep 18 20:56:01 primary-ws kernel: umip: Wonderlands.exe[213853] ip:15e3a82b0 sp:4ed178: For now, expensive software emulation returns the result. Sep 18 20:56:03 primary-ws kernel: umip: Wonderlands.exe[213853] ip:15e3a82b0 sp:4edbe8: SGDT instruction cannot be used by applications. Sep 18 20:56:03 primary-ws kernel: umip: Wonderlands.exe[213853] ip:15e3a82b0 sp:4edbe8: For now, expensive software emulation returns the result. Sep 18 20:56:03 primary-ws kernel: umip: Wonderlands.exe[213853] ip:15e3a82b0 sp:4ebf18: SGDT instruction cannot be used by applications. Sep 18 20:57:55 primary-ws kernel: [ cut here ] Sep 18 20:57:55 primary-ws kernel: refcount_t: underflow; use-after-free. Sep 18 20:57:55 primary-ws kernel: WARNING: CPU: 22 PID: 235114 at lib/refcount.c:28 refcount_warn_saturate+0xba/0x110 Sep 18 20:57:55 primary-ws kernel: Modules linked in: tls uinput rfcomm snd_seq_dummy snd_hrtimer nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4 nf_> Sep 18 20:57:55 primary-ws kernel: asus_wmi ledtrig_audio sparse_keymap platform_profile irqbypass rfkill mc rapl snd_timer video wmi_bmof pcspkr snd k10temp i2c_piix4 soundcore acpi_cpufreq zram amdgpu drm_ttm_helper ttm iommu_v2 crct1> Sep 18 20:57:55 primary-ws kernel: Unloaded tainted modules: amd64_edac():1 amd64_edac():1 amd64_edac():1 amd64_edac():1 amd64_edac():1 amd64_edac():1 amd64_edac():1 amd64_edac():1 amd64_edac():1 pcc_cpufreq():1 pcc_cpufreq():1 amd64_eda> Sep 18 20:57:55 primary-ws kernel: pcc_cpufreq():1 pcc_cpufreq():1 fjes():1 fjes():1 pcc_cpufreq():1 fjes():1 fjes():1 fjes():1 fjes():1 fjes():1 Sep 18 20:57:55 primary-ws kernel: CPU: 22 PID: 235114 Comm: kworker/22:0 Tainted: GWL--- --- 6.0.0-0.rc5.20220914git3245cb65fd91.39.fc38.x86_64 #1 Sep 18 20:57:55 primary-ws kernel: Hardware name: System manufacturer System Product Name/ROG STRIX X570-I GAMING, BIOS 4403 04/27/2022 Sep 18 20:57:55 primary-ws kernel: Workqueue: events drm_sched_entity_kill_jobs_work [gpu_sched] Sep 18 20:57:55 primary-ws kernel: RIP: 0010:refcount_warn_saturate+0xba/0x110 Sep 18 20:57:55 primary-ws kernel: Code: 01 01 e8 69 6b 6f 00 0f 0b e9 32 38 a5 00 80 3d 4d 7d be 01 00 75 85 48 c7 c7 80 b7 8e 95 c6 05 3d 7d be 01 01 e8 46 6b 6f 00 <0f> 0b e9 0f 38 a5 00 80 3d 28 7d be 01 00 0f 85 5e ff ff ff 48 c7 Sep 18 20:57:55 primary-ws kernel: RSP: 0018:a1a853ccbe60 EFLAGS: 00010286 Sep 18 20:57:55 primary-ws kernel: RAX: 0026 RBX: 8e0e60a96c28 RCX: Sep 18 20:57:55 primary-ws kernel: RDX: 0001 RSI: 958d255c RDI: Sep 18 20:57:55 primary-ws kernel: RBP: 8e19a83f5600 R08: R09: a1a853ccbd10 Sep 18 20:57:55 primary-ws kernel: R10: 0003 R11: 8e19ee2fffe8 R12: 8e19a83fc800 Sep 18
Re: [PATCH] drm/amd/display: remove redundant CalculateRemoteSurfaceFlipDelay's
Hi Tom
On 9/19/22 14:27, Tom Rix wrote:
> There are several copies of CalculateRemoteSurfaceFlipDelay.
> Reduce to one instance.
>
> Signed-off-by: Tom Rix
Reviewed-by: Maíra Canal
Just a minor comment below.
> ---
> .../dc/dml/dcn20/display_mode_vba_20.c| 4 +-
> .../dc/dml/dcn20/display_mode_vba_20v2.c | 40 +--
> .../dc/dml/dcn21/display_mode_vba_21.c| 40 +--
> 3 files changed, 4 insertions(+), 80 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index 4ca080950924..8e5d58336bc5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -158,7 +158,7 @@ double CalculateTWait(
> double DRAMClockChangeLatency,
> double UrgentLatency,
> double SREnterPlusExitTime);
> -static double CalculateRemoteSurfaceFlipDelay(
> +double CalculateRemoteSurfaceFlipDelay(
> struct display_mode_lib *mode_lib,
> double VRatio,
> double SwathWidth,
> @@ -2909,7 +2909,7 @@ double CalculateTWait(
> }
> }
>
> -static double CalculateRemoteSurfaceFlipDelay(
> +double CalculateRemoteSurfaceFlipDelay(
I guess it would be more clear if this function was placed on the
display_mode_vba20.h and named dml20_CalculateRemoteSurfaceFlipDelay.
Then, it would be clearer that this function is shared over the DCN20s.
Best Regards,
- Maíra Canal
> struct display_mode_lib *mode_lib,
> double VRatio,
> double SwathWidth,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index 2b4dcae4e432..e9ebc81adc71 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -182,7 +182,7 @@ double CalculateTWait(
> double DRAMClockChangeLatency,
> double UrgentLatency,
> double SREnterPlusExitTime);
> -static double CalculateRemoteSurfaceFlipDelay(
> +double CalculateRemoteSurfaceFlipDelay(
> struct display_mode_lib *mode_lib,
> double VRatio,
> double SwathWidth,
> @@ -2967,44 +2967,6 @@ static void dml20v2_DisplayPipeConfiguration(struct
> display_mode_lib *mode_lib)
> }
> }
>
> -static double CalculateRemoteSurfaceFlipDelay(
> - struct display_mode_lib *mode_lib,
> - double VRatio,
> - double SwathWidth,
> - double Bpp,
> - double LineTime,
> - double XFCTSlvVupdateOffset,
> - double XFCTSlvVupdateWidth,
> - double XFCTSlvVreadyOffset,
> - double XFCXBUFLatencyTolerance,
> - double XFCFillBWOverhead,
> - double XFCSlvChunkSize,
> - double XFCBusTransportTime,
> - double TCalc,
> - double TWait,
> - double *SrcActiveDrainRate,
> - double *TInitXFill,
> - double *TslvChk)
> -{
> - double TSlvSetup, AvgfillRate, result;
> -
> - *SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
> - TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth +
> XFCTSlvVreadyOffset;
> - *TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100);
> - AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100);
> - *TslvChk = XFCSlvChunkSize / AvgfillRate;
> - dml_print(
> - "DML::CalculateRemoteSurfaceFlipDelay:
> SrcActiveDrainRate: %f\n",
> - *SrcActiveDrainRate);
> - dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n",
> TSlvSetup);
> - dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n",
> *TInitXFill);
> - dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n",
> AvgfillRate);
> - dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n",
> *TslvChk);
> - result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk
> + *TInitXFill; // TODO: This doesn't seem to match programming guide
> - dml_print("DML::CalculateRemoteSurfaceFlipDelay:
> RemoteSurfaceFlipDelay: %f\n", result);
> - return result;
> -}
> -
> static void CalculateActiveRowBandwidth(
> bool GPUVMEnable,
> enum source_format_class SourcePixelFormat,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> index a3ef3638d979..d94aaf899f9b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> @@ -210,7 +210,7 @@ double
[linux-next:master] BUILD REGRESSION 4c9ca5b1597e3222177ba2a94658f78fa5ef4f58
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 4c9ca5b1597e3222177ba2a94658f78fa5ef4f58 Add linux-next specific files for 20220919 Error/Warning reports: https://lore.kernel.org/linux-doc/202209200314.tchs7q2y-...@intel.com https://lore.kernel.org/linux-doc/202209200341.be18yibm-...@intel.com https://lore.kernel.org/linux-mm/202209150141.wgbakqmx-...@intel.com https://lore.kernel.org/linux-mm/202209200603.hpvoa8ii-...@intel.com https://lore.kernel.org/llvm/202209192243.d80zuwvw-...@intel.com https://lore.kernel.org/llvm/202209200834.efwatsij-...@intel.com Error/Warning: (recently discovered and may have been fixed) ERROR: modpost: "devm_ioremap_resource" [drivers/dma/fsl-edma.ko] undefined! ERROR: modpost: "devm_memremap" [drivers/misc/open-dice.ko] undefined! ERROR: modpost: "devm_memunmap" [drivers/misc/open-dice.ko] undefined! ERROR: modpost: "devm_platform_ioremap_resource" [drivers/char/xillybus/xillybus_of.ko] undefined! ERROR: modpost: "devm_platform_ioremap_resource" [drivers/clk/xilinx/clk-xlnx-clock-wizard.ko] undefined! ERROR: modpost: "ioremap" [drivers/tty/ipwireless/ipwireless.ko] undefined! ERROR: modpost: "iounmap" [drivers/net/ethernet/8390/pcnet_cs.ko] undefined! ERROR: modpost: "iounmap" [drivers/tty/ipwireless/ipwireless.ko] undefined! arch/parisc/lib/iomap.c:363:5: warning: no previous prototype for 'ioread64_lo_hi' [-Wmissing-prototypes] arch/parisc/lib/iomap.c:373:5: warning: no previous prototype for 'ioread64_hi_lo' [-Wmissing-prototypes] arch/parisc/lib/iomap.c:448:6: warning: no previous prototype for 'iowrite64_lo_hi' [-Wmissing-prototypes] arch/parisc/lib/iomap.c:454:6: warning: no previous prototype for 'iowrite64_hi_lo' [-Wmissing-prototypes] drivers/gpu/drm/drm_atomic_helper.c:802: warning: expecting prototype for drm_atomic_helper_check_wb_connector_state(). Prototype was for drm_atomic_helper_check_wb_encoder_state() instead drivers/iommu/ipmmu-vmsa.c:946:34: warning: unused variable 'ipmmu_of_ids' [-Wunused-const-variable] drivers/scsi/qla2xxx/qla_os.c:2854:23: warning: assignment to 'struct trace_array *' from 'int' makes pointer from integer without a cast [-Wint-conversion] drivers/scsi/qla2xxx/qla_os.c:2854:25: error: implicit declaration of function 'trace_array_get_by_name'; did you mean 'trace_array_set_clr_event'? [-Werror=implicit-function-declaration] drivers/scsi/qla2xxx/qla_os.c:2869:9: error: implicit declaration of function 'trace_array_put' [-Werror=implicit-function-declaration] fs/btrfs/extent-io-tree.c:165: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst fs/btrfs/extent-io-tree.c:217: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst mm/hugetlb.c:5565:14: warning: variable 'reserve_alloc' set but not used [-Wunused-but-set-variable] Unverified Error/Warning (likely false positive, please contact us if interested): ERROR: modpost: "__tsan_memcpy" [arch/s390/crypto/chacha_s390.ko] undefined! ERROR: modpost: "__tsan_memcpy" [arch/s390/crypto/ghash_s390.ko] undefined! ERROR: modpost: "__tsan_memcpy" [arch/s390/crypto/prng.ko] undefined! ERROR: modpost: "__tsan_memcpy" [arch/s390/crypto/sha3_512_s390.ko] undefined! ERROR: modpost: "__tsan_memset" [arch/s390/crypto/chacha_s390.ko] undefined! ERROR: modpost: "__tsan_memset" [arch/s390/crypto/ghash_s390.ko] undefined! ERROR: modpost: "__tsan_memset" [arch/s390/crypto/prng.ko] undefined! ERROR: modpost: "__tsan_memset" [arch/s390/crypto/sha3_512_s390.ko] undefined! ERROR: modpost: "__tsan_memset" [kernel/rcu/refscale.ko] undefined! ERROR: modpost: "__tsan_memset" [kernel/scftorture.ko] undefined! Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-drm_atomic_helper.c:warning:expecting-prototype-for-drm_atomic_helper_check_wb_connector_state().-Prototype-was-for-drm_atomic_helper_check_wb_encoder_state()-instead | |-- drivers-scsi-qla2xxx-qla_os.c:error:implicit-declaration-of-function-trace_array_get_by_name | |-- drivers-scsi-qla2xxx-qla_os.c:error:implicit-declaration-of-function-trace_array_put | `-- drivers-scsi-qla2xxx-qla_os.c:warning:assignment-to-struct-trace_array-from-int-makes-pointer-from-integer-without-a-cast |-- alpha-randconfig-r026-20220919 | `-- fs-btrfs-extent-io-tree.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst |-- arc-allyesconfig | `-- drivers-gpu-drm-drm_atomic_helper.c:warning:expecting-prototype-for-drm_atomic_helper_check_wb_connector_state().-Prototype-was-for-drm_atomic_helper_check_wb_encoder_state()-instead |-- arc-randconfig-r043-20220919 | `-- dr
Re: [PATCH] drm/amd/display: remove redundant CalculateTWait's
Hi Tom,
On 9/18/22 23:37, Tom Rix wrote:
> There are several copies of CalculateTwait.
> Reduce to one instance and change local variable name to match common usage.
>
> Signed-off-by: Tom Rix
Reviewed-by: Maíra Canal
Although, it would be nice to put this function on the
display_mode_vba.h file, as all DCNs use this function.
Best Regards,
- Maíra Canal
> ---
> .../dc/dml/dcn20/display_mode_vba_20.c| 16 +++---
> .../dc/dml/dcn20/display_mode_vba_20v2.c | 21 ++-
> .../dc/dml/dcn21/display_mode_vba_21.c| 19 +
> .../dc/dml/dcn30/display_mode_vba_30.c| 18 +---
> .../dc/dml/dcn31/display_mode_vba_31.c| 13 +---
> .../dc/dml/dcn314/display_mode_vba_314.c | 13 +---
> 6 files changed, 14 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index 6e9d7e2b5243..4ca080950924 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -153,10 +153,10 @@ static unsigned int CalculateVMAndRowBytes(
> bool *PTEBufferSizeNotExceeded,
> unsigned int *dpte_row_height,
> unsigned int *meta_row_height);
> -static double CalculateTWait(
> +double CalculateTWait(
> unsigned int PrefetchMode,
> double DRAMClockChangeLatency,
> - double UrgentLatencyPixelDataOnly,
> + double UrgentLatency,
> double SREnterPlusExitTime);
> static double CalculateRemoteSurfaceFlipDelay(
> struct display_mode_lib *mode_lib,
> @@ -2892,20 +2892,20 @@ static void dml20_DisplayPipeConfiguration(struct
> display_mode_lib *mode_lib)
> }
> }
>
> -static double CalculateTWait(
> +double CalculateTWait(
> unsigned int PrefetchMode,
> double DRAMClockChangeLatency,
> - double UrgentLatencyPixelDataOnly,
> + double UrgentLatency,
> double SREnterPlusExitTime)
> {
> if (PrefetchMode == 0) {
> return dml_max(
> - DRAMClockChangeLatency +
> UrgentLatencyPixelDataOnly,
> - dml_max(SREnterPlusExitTime,
> UrgentLatencyPixelDataOnly));
> + DRAMClockChangeLatency + UrgentLatency,
> + dml_max(SREnterPlusExitTime, UrgentLatency));
> } else if (PrefetchMode == 1) {
> - return dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly);
> + return dml_max(SREnterPlusExitTime, UrgentLatency);
> } else {
> - return UrgentLatencyPixelDataOnly;
> + return UrgentLatency;
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index b02dda8ce70f..2b4dcae4e432 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -177,10 +177,10 @@ static unsigned int CalculateVMAndRowBytes(
> bool *PTEBufferSizeNotExceeded,
> unsigned int *dpte_row_height,
> unsigned int *meta_row_height);
> -static double CalculateTWait(
> +double CalculateTWait(
> unsigned int PrefetchMode,
> double DRAMClockChangeLatency,
> - double UrgentLatencyPixelDataOnly,
> + double UrgentLatency,
> double SREnterPlusExitTime);
> static double CalculateRemoteSurfaceFlipDelay(
> struct display_mode_lib *mode_lib,
> @@ -2967,23 +2967,6 @@ static void dml20v2_DisplayPipeConfiguration(struct
> display_mode_lib *mode_lib)
> }
> }
>
> -static double CalculateTWait(
> - unsigned int PrefetchMode,
> - double DRAMClockChangeLatency,
> - double UrgentLatencyPixelDataOnly,
> - double SREnterPlusExitTime)
> -{
> - if (PrefetchMode == 0) {
> - return dml_max(
> - DRAMClockChangeLatency +
> UrgentLatencyPixelDataOnly,
> - dml_max(SREnterPlusExitTime,
> UrgentLatencyPixelDataOnly));
> - } else if (PrefetchMode == 1) {
> - return dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly);
> - } else {
> - return UrgentLatencyPixelDataOnly;
> - }
> -}
> -
> static double CalculateRemoteSurfaceFlipDelay(
> struct display_mode_lib *mode_lib,
> double VRatio,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> index 6be14f55c78d..a3ef3638d979 100644
> ---
Re: [PATCH] drm/amd/display: refactor CalculateWriteBackDelay to use vba_vars_st ptr
Hi Tom
Nice to see this patch coming to the DML! Some small nits inline.
On 9/17/22 15:37, Tom Rix wrote:
> Mimimize the function signature by passing a pointer and an index instead
> of passing several elements of the pointer.
>
> The dml2x,dml3x families uses the same algorithm. Remove the duplicates.
> Use dml20_ and dml30_ prefix to distinguish the two variants.
>
> Signed-off-by: Tom Rix
> ---
> .../dc/dml/dcn20/display_mode_vba_20.c| 78 +++-
> .../dc/dml/dcn20/display_mode_vba_20v2.c | 115 ++
> .../dc/dml/dcn21/display_mode_vba_21.c| 114 +
> .../dc/dml/dcn30/display_mode_vba_30.c| 74 +++
> .../dc/dml/dcn31/display_mode_vba_31.c| 76 +---
> .../dc/dml/dcn314/display_mode_vba_314.c | 76 +---
> .../dc/dml/dcn32/display_mode_vba_32.c| 42 +--
> .../dc/dml/dcn32/display_mode_vba_util_32.c | 30 -
> .../dc/dml/dcn32/display_mode_vba_util_32.h | 10 +-
> 9 files changed, 63 insertions(+), 552 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index d3b5b6fedf04..6e9d7e2b5243 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -217,16 +217,8 @@ static void CalculateFlipSchedule(
> double *DestinationLinesToRequestRowInImmediateFlip,
> double *final_flip_bw,
> bool *ImmediateFlipSupportedForPipe);
> -static double CalculateWriteBackDelay(
> - enum source_format_class WritebackPixelFormat,
> - double WritebackHRatio,
> - double WritebackVRatio,
> - unsigned int WritebackLumaHTaps,
> - unsigned int WritebackLumaVTaps,
> - unsigned int WritebackChromaHTaps,
> - unsigned int WritebackChromaVTaps,
> - unsigned int WritebackDestinationWidth);
>
> +double dlm20_CalculateWriteBackDelay(struct vba_vars_st *vba, unsigned int
> i);
Small typo here: s/dlm/dml
> static void dml20_DisplayPipeConfiguration(struct display_mode_lib
> *mode_lib);
> static void
> dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
> struct display_mode_lib *mode_lib);
> @@ -1085,6 +1077,7 @@ static unsigned int CalculateVMAndRowBytes(
> static void
> dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
> struct display_mode_lib *mode_lib)
> {
> + struct vba_vars_st *v = _lib->vba;
> unsigned int j, k;
>
> mode_lib->vba.WritebackDISPCLK = 0.0;
> @@ -1980,36 +1973,15 @@ static void
> dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
> if (mode_lib->vba.BlendingAndTiming[k] == k) {
> if (mode_lib->vba.WritebackEnable[k] == true) {
>
> mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
> - mode_lib->vba.WritebackLatency
> - +
> CalculateWriteBackDelay(
> -
> mode_lib->vba.WritebackPixelFormat[k],
> -
> mode_lib->vba.WritebackHRatio[k],
> -
> mode_lib->vba.WritebackVRatio[k],
> -
> mode_lib->vba.WritebackLumaHTaps[k],
> -
> mode_lib->vba.WritebackLumaVTaps[k],
> -
> mode_lib->vba.WritebackChromaHTaps[k],
> -
> mode_lib->vba.WritebackChromaVTaps[k],
> -
> mode_lib->vba.WritebackDestinationWidth[k])
> -
> / mode_lib->vba.DISPCLK;
> + mode_lib->vba.WritebackLatency +
> dlm20_CalculateWriteBackDelay(v, k) / mode_lib->vba.DISPCLK;
> } else
>
> mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
> for (j = 0; j < mode_lib->vba.NumberOfActivePlanes;
> ++j) {
> if (mode_lib->vba.BlendingAndTiming[j] == k
> &&
> mode_lib->vba.WritebackEnable[j] == true) {
>
> mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
> -
Re: [PATCH 1/2] drm/i915/mtl: Modify CAGF functions for MTL
On Mon, Sep 19, 2022 at 03:46:47PM -0700, Matt Roper wrote:
> On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > Updated the CAGF functions to get actual resolved frequency of
> > 3D and SAMedia
> >
> > Bspec: 66300
> >
> > Cc: Vinay Belgaumkar
> > Cc: Ashutosh Dixit
> > Signed-off-by: Badal Nilawar
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
> > drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
> > 2 files changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 2275ee47da95..7819d32db956 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1510,6 +1510,14 @@
> > #define VLV_RENDER_C0_COUNT_MMIO(0x138118)
> > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
> >
> > +/*
> > + * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
> > + * 3D - 0x0C60 , SAMedia - 0x380C60
> > + * Intel uncore handler redirects transactions for SAMedia to
> > MTL_MEDIA_GSI_BASE
> > + */
Also, this comment is unnecessary. This is already how all GT registers
work so there's no reason to state this again on one one random
register.
> > +#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
> > +#define MTL_CAGF_MASKREG_GENMASK(8, 0)
> > +
>
> This register is at the wrong place in the file (and is misformatted).
> - Keep it sorted with respect to the other registers in the file.
> - Write it as "0xc60" for consistency with all the other registers
>(i.e., lower-case hex, no unnecessary 0 prefix).
> - The whitespace between the name and the REG_GENMASK should be tabs,
>not spaces, ensuring it's lined up with the other definitions.
>
> i915_reg.h turned into a huge mess over time because it wasn't
> consistently organized or formatted so nobody knew what to do when
> adding new registers. We're trying to do a better job of following
> consistent rules with the new register headers so that we don't wind up
> with the same confusion again.
>
> > #define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) *
> > 4))
> > #define GEN11_CSME (31)
> > #define GEN11_GUNIT (28)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> > b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index 17b40b625e31..c2349949ebae 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -2075,6 +2075,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32
> > rpstat)
> >
> > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > cagf = (rpstat >> 8) & 0xff;
> > + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > + cagf = rpstat & MTL_CAGF_MASK;
>
> Generally we try to put the newer platform at the top of if/else
> ladders. So this new MTL code should come before the VLV/CHV branch.
>
> > else if (GRAPHICS_VER(i915) >= 9)
> > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > @@ -2098,7 +2100,9 @@ static u32 read_cagf(struct intel_rps *rps)
> > vlv_punit_get(i915);
> > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> > vlv_punit_put(i915);
> > - } else if (GRAPHICS_VER(i915) >= 6) {
> > + } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > + freq = intel_uncore_read(rps_to_gt(rps)->uncore,
> > MTL_MIRROR_TARGET_WP1);
>
> Same here.
>
>
> Matt
>
> > + else if (GRAPHICS_VER(i915) >= 6) {
> > freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> > } else {
> > freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [PATCH 1/2] drm/i915/mtl: Modify CAGF functions for MTL
On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> Updated the CAGF functions to get actual resolved frequency of
> 3D and SAMedia
>
> Bspec: 66300
>
> Cc: Vinay Belgaumkar
> Cc: Ashutosh Dixit
> Signed-off-by: Badal Nilawar
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 2275ee47da95..7819d32db956 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1510,6 +1510,14 @@
> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
>
> +/*
> + * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
> + * 3D - 0x0C60 , SAMedia - 0x380C60
> + * Intel uncore handler redirects transactions for SAMedia to
> MTL_MEDIA_GSI_BASE
> + */
> +#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
> +#define MTL_CAGF_MASKREG_GENMASK(8, 0)
> +
This register is at the wrong place in the file (and is misformatted).
- Keep it sorted with respect to the other registers in the file.
- Write it as "0xc60" for consistency with all the other registers
(i.e., lower-case hex, no unnecessary 0 prefix).
- The whitespace between the name and the REG_GENMASK should be tabs,
not spaces, ensuring it's lined up with the other definitions.
i915_reg.h turned into a huge mess over time because it wasn't
consistently organized or formatted so nobody knew what to do when
adding new registers. We're trying to do a better job of following
consistent rules with the new register headers so that we don't wind up
with the same confusion again.
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> #define GEN11_GUNIT(28)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 17b40b625e31..c2349949ebae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2075,6 +2075,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32
> rpstat)
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> cagf = (rpstat >> 8) & 0xff;
> + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + cagf = rpstat & MTL_CAGF_MASK;
Generally we try to put the newer platform at the top of if/else
ladders. So this new MTL code should come before the VLV/CHV branch.
> else if (GRAPHICS_VER(i915) >= 9)
> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> @@ -2098,7 +2100,9 @@ static u32 read_cagf(struct intel_rps *rps)
> vlv_punit_get(i915);
> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> vlv_punit_put(i915);
> - } else if (GRAPHICS_VER(i915) >= 6) {
> + } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + freq = intel_uncore_read(rps_to_gt(rps)->uncore,
> MTL_MIRROR_TARGET_WP1);
Same here.
Matt
> + else if (GRAPHICS_VER(i915) >= 6) {
> freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> } else {
> freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
RE: [BUG] ls1046a: eDMA does not transfer data from I2C
> -Original Message- > From: Sean Anderson > Sent: Monday, September 19, 2022 5:24 PM > To: Oleksij Rempel ; Pengutronix Kernel Team > ; linux-...@vger.kernel.org; linux-arm-kernel > ; Vinod Koul ; > dmaeng...@vger.kernel.org > Cc: Sumit Semwal ; Christian König > ; Linux Kernel Mailing List ker...@vger.kernel.org>; linux-me...@vger.kernel.org; dri- > de...@lists.freedesktop.org; linaro-mm-...@lists.linaro.org; Joy Zou > ; Peng Ma ; Robin Gong > ; Shawn Guo ; Leo Li > > Subject: [BUG] ls1046a: eDMA does not transfer data from I2C > > Hi all, > > I discovered a bug in either imx_i2c or fsl-edma on the LS1046A where no > data is read in i2c_imx_dma_read except for the last two bytes (which are > not read using DMA). This is perhaps best illustrated with the following > example: What is the kernel tree/tag that you are testing with? Regards, Leo
[PATCH 11/12] drm/i915/mtl: Add multicast steering for render GT
MTL once again changes the multicast register types and steering
details. Key changes from past platforms:
* The number of instances of some MCR types (NODE, OAAL2, and GAM) vary
according to the MTL subplatform and cannot be read from fuse
registers.
* The MCR steering register (and its bitfields) has changed.
Unlike past platforms, we will be explicitly steering all types of MCR
accesses, including those for "SLICE" and "DSS" ranges; we no longer
rely on implicit steering. On previous platforms, various
hardware/firmware agents that needed to access registers typically had
their own steering control registers, allowing them to perform multicast
steering without clobbering the CPU/kernel steering. Starting with MTL,
more of these agents now share a single steering register (0xFD4) and it
is no longer safe for us to assume that the value will remain unchanged
from how we initialized it during startup. There is also a slight
chance of race conditions between the driver and a hardware/firmware
agent, so the hardware provides a semaphore register that can be used to
coordinate access to the steering register. Support for the semaphore
register will be introduced in a future patch.
Bspec: 67788, 67112
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 85 ++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h| 8 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 -
drivers/gpu/drm/i915/i915_pci.c | 1 +
5 files changed, 102 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 8f9009af3673..05f41f1cc88d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -40,6 +40,7 @@ static const char * const intel_steering_types[] = {
"L3BANK",
"MSLICE",
"LNCF",
+ "DSS",
"INSTANCE 0",
};
@@ -89,9 +90,40 @@ static const struct intel_mmio_range
pvc_instance0_steering_table[] = {
{},
};
+static const struct intel_mmio_range mtl3d_instance0_steering_table[] = {
+ { 0x000B00, 0x000BFF }, /* SQIDI */
+ { 0x001000, 0x001FFF }, /* SQIDI */
+ { 0x004000, 0x0048FF }, /* GAM */
+ { 0x008700, 0x0087FF }, /* SQIDI */
+ { 0x00B000, 0x00B0FF }, /* NODE */
+ { 0x00C800, 0x00CFFF }, /* GAM */
+ { 0x00D880, 0x00D8FF }, /* NODE */
+ { 0x00DD00, 0x00DDFF }, /* OAAL2 */
+ {},
+};
+
+static const struct intel_mmio_range mtl3d_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
+/* DSS steering is used for SLICE ranges as well */
+static const struct intel_mmio_range mtl3d_dss_steering_table[] = {
+ { 0x005200, 0x0052FF }, /* SLICE */
+ { 0x005500, 0x007FFF }, /* SLICE */
+ { 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS
(0x8150-0x815F) */
+ { 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS
(0x9520-0x955F) */
+ { 0x009680, 0x0096FF }, /* DSS */
+ { 0x00D800, 0x00D87F }, /* SLICE */
+ { 0x00DC00, 0x00DCFF }, /* SLICE */
+ { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
+};
+
void intel_gt_mcr_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned long fuse;
+ int i;
/*
* An mslice is unavailable only if both the meml3 for the slice is
@@ -109,7 +141,22 @@ void intel_gt_mcr_init(struct intel_gt *gt)
drm_warn(>drm, "mslice mask all zero!\n");
}
- if (IS_PONTEVECCHIO(i915)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
+ gt->type == GT_PRIMARY) {
+ fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
+intel_uncore_read(gt->uncore, XEHP_FUSE4));
+
+ /*
+* Despite the register field being named "exclude mask" the
+* bits actually represent enabled banks (two banks per bit).
+*/
+ for_each_set_bit(i, , 3)
+ gt->info.l3bank_mask |= (0x3 << 2*i);
+
+ gt->steering_table[INSTANCE0] = mtl3d_instance0_steering_table;
+ gt->steering_table[L3BANK] = mtl3d_l3bank_steering_table;
+ gt->steering_table[DSS] = mtl3d_dss_steering_table;
+ } else if (IS_PONTEVECCHIO(i915)) {
gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
} else if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
@@ -168,7 +215,12 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore
*uncore,
lockdep_assert_held(>lock);
- if (GRAPHICS_VER(uncore->i915) >= 11) {
+ if
[PATCH 05/12] drm/i915/xehp: Check for faults on primary GAM
On Xe_HP the fault registers are now in a multicast register range.
However as part of the GAM these registers follow special rules and we
need only read from the "primary" GAM's instance to get the information
we need. So a single intel_gt_mcr_read_any() (which will automatically
steer to the primary GAM) is sufficient; we don't need to loop over each
instance of the MCR register.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 40 -
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5ddae95d4886..1cb7dd40ec47 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -304,6 +304,42 @@ static void gen6_check_faults(struct intel_gt *gt)
}
}
+static void xehp_check_faults(struct intel_gt *gt)
+{
+ u32 fault;
+
+ /*
+* Although the fault register now lives in an MCR register range,
+* the GAM registers are special and we only truly need to read
+* the "primary" GAM instance rather than handling each instance
+* individually. intel_gt_mcr_read_any() will automatically steer
+* toward the primary instance.
+*/
+ fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
+ if (fault & RING_FAULT_VALID) {
+ u32 fault_data0, fault_data1;
+ u64 fault_addr;
+
+ fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
+ fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
+
+ fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+((u64)fault_data0 << 12);
+
+ drm_dbg(>i915->drm, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
+ }
+}
+
static void gen8_check_faults(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
@@ -350,7 +386,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
- if (GRAPHICS_VER(i915) >= 8)
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ xehp_check_faults(gt);
+ else if (GRAPHICS_VER(i915) >= 8)
gen8_check_faults(gt);
else if (GRAPHICS_VER(i915) >= 6)
gen6_check_faults(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index cf87a1b36a21..dff38b0c4430 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1024,11 +1024,14 @@
#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) *
4)
#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
+#define XEHP_FAULT_TLB_DATA0 _MMIO(0xceb8)
#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
+#define XEHP_FAULT_TLB_DATA1 _MMIO(0xcebc)
#define FAULT_VA_HIGH_BITS (0xf << 0)
#define FAULT_GTT_SEL(1 << 4)
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
+#define XEHP_RING_FAULT_REG_MMIO(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
--
2.37.3
[PATCH 10/12] drm/i915: Define multicast registers as a new type
Rather than treating multicast registers as 'i915_reg_t' let's define
them as a completely new type. This will allow the compiler to help us
make sure we're using multicast-aware functions to operate on multicast
registers.
This plan does break down a bit in places where we're just maintaining
heterogeneous lists of registers (e.g., various MMIO whitelists used by
perf, GVT, etc.) rather than performing reads/writes. We only really
care about the offset in those cases, so for now we can "cast" the
registers as non-MCR, leaving us with a list of i915_reg_t's, but we may
want to look for better ways to store mixed collections of i915_reg_t
and i915_mcr_reg_t in the future.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 49 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.h| 14 +++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 27 +++---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++--
.../gpu/drm/i915/gt/intel_workarounds_types.h | 5 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 4 +-
drivers/gpu/drm/i915/gvt/handlers.c | 17 ---
drivers/gpu/drm/i915/gvt/mmio_context.c | 14 +++---
drivers/gpu/drm/i915/i915_reg_defs.h | 22 +++--
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 ++--
12 files changed, 112 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index e79405a45312..8f9009af3673 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -134,6 +134,19 @@ void intel_gt_mcr_init(struct intel_gt *gt)
}
}
+/*
+ * Although the rest of the driver should use MCR-specific functions to
+ * read/write MCR registers, we still use the regular intel_uncore_* functions
+ * internally to implement those, so we need a way for the functions in this
+ * file to "cast" an i915_mcr_reg_t into an i915_reg_t.
+ */
+static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
+{
+ i915_reg_t r = { .reg = mcr.reg };
+
+ return r;
+}
+
/*
* rw_with_mcr_steering_fw - Access a register with specific MCR steering
* @uncore: pointer to struct intel_uncore
@@ -148,7 +161,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
* Caller needs to make sure the relevant forcewake wells are up.
*/
static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance, u32 value)
{
u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
@@ -185,9 +198,9 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore
*uncore,
intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
if (rw_flag == FW_REG_READ)
- val = intel_uncore_read_fw(uncore, reg);
+ val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
else
- intel_uncore_write_fw(uncore, reg, value);
+ intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
mcr &= ~mcr_mask;
mcr |= old_mcr & mcr_mask;
@@ -198,14 +211,14 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore
*uncore,
}
static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance,
u32 value)
{
enum forcewake_domains fw_domains;
u32 val;
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg),
rw_flag);
fw_domains |= intel_uncore_forcewake_for_reg(uncore,
GEN8_MCR_SELECTOR,
@@ -233,7 +246,7 @@ static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
* group/instance.
*/
u32 intel_gt_mcr_read(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
int group, int instance)
{
return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group,
instance, 0);
@@ -250,7 +263,7 @@ u32 intel_gt_mcr_read(struct intel_gt *gt,
* Write an MCR register in unicast mode after steering toward a specific
* group/instance.
*/
-void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value,
+void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32
value,
int group, int instance)
{
rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance,
value);
@@ -265,9 +278,9 @@ void
[PATCH 07/12] drm/i915/gt: Always use MCR functions on multicast registers
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 49 ---
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 12 --
drivers/gpu/drm/i915/intel_pm.c | 20 +
6 files changed, 55 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 30cf5c3369d9..e2620f41d8b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -986,7 +986,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
- setup_private_pat(ggtt->vm.gt->uncore);
+ setup_private_pat(ggtt->vm.gt);
return ggtt_probe_common(ggtt, size);
}
@@ -1302,7 +1302,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
wbinvd_on_all_cpus();
if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
- setup_private_pat(ggtt->vm.gt->uncore);
+ setup_private_pat(ggtt->vm.gt);
intel_ggtt_restore_fences(ggtt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 601d89b4feb1..6f61c8da0b61 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -15,6 +15,7 @@
#include "i915_trace.h"
#include "i915_utils.h"
#include "intel_gt.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_regs.h"
#include "intel_gtt.h"
@@ -477,27 +478,27 @@ void gtt_write_workarounds(struct intel_gt *gt)
}
}
-static void tgl_setup_private_ppat(struct intel_uncore *uncore)
+static void tgl_setup_private_ppat(struct intel_gt *gt)
{
- if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
- intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0),
GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1),
GEN8_PPAT_WC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2),
GEN8_PPAT_WT);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3),
GEN8_PPAT_UC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4),
GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(5),
GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(6),
GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(7),
GEN8_PPAT_WB);
} else {
/* TGL doesn't support LLC or AGE settings */
- intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(0),
GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(1),
GEN8_PPAT_WC);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(2),
GEN8_PPAT_WT);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(3),
GEN8_PPAT_UC);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(4),
GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(5),
GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(6),
GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(7),
GEN8_PPAT_WB);
}
}
@@ -593,20 +594,20 @@ static void chv_setup_private_ppat(struct intel_uncore
*uncore)
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
}
-void setup_private_pat(struct intel_uncore *uncore)
[PATCH 06/12] drm/i915: Define MCR registers explicitly
Rather than using the same _MMIO() macro to define MCR registers as singleton registers, let's use a new MCR_REG() macro to make it clear that these registers are special and should be handled accordingly. For now MCR_REG() will still generate an i915_reg_t with the given offset, but we'll change that in future patches. Bspec: 66673, 66696, 66534, 67609 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 124 1 file changed, 63 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index dff38b0c4430..f96cf08cd31e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -8,6 +8,8 @@ #include "i915_reg_defs.h" +#define MCR_REG(offset)_MMIO(offset) + /* RPM unit config (Gen8+) */ #define RPM_CONFIG0_MMIO(0xd00) #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT3 @@ -329,12 +331,12 @@ #define GEN7_TLB_RD_ADDR _MMIO(0x4700) #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) -#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) +#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4) -#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900) +#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) #define XEHP_TILE_LMEM_RANGE_SHIFT 8 -#define XEHP_FLAT_CCS_BASE_ADDR_MMIO(0x4910) +#define XEHP_FLAT_CCS_BASE_ADDRMCR_REG(0x4910) #define XEHP_CCS_BASE_SHIFT 8 #define GAMTARBMODE_MMIO(0x4a08) @@ -384,18 +386,18 @@ #define CHICKEN_RASTER_2 _MMIO(0x6208) #define TBIMR_FAST_CLIP REG_BIT(5) -#define VFLSKPD_MMIO(0x62a8) +#define VFLSKPDMCR_REG(0x62a8) #define DIS_OVER_FETCH_CACHE REG_BIT(1) #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) #define GEN12_FF_MODE2 _MMIO(0x6604) -#define XEHP_FF_MODE2 _MMIO(0x6604) +#define XEHP_FF_MODE2 MCR_REG(0x6604) #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) -#define XEHPG_INSTDONE_GEOM_SVG_MMIO(0x666c) +#define XEHPG_INSTDONE_GEOM_SVGMCR_REG(0x666c) #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ #define RC_OP_FLUSH_ENABLE (1 << 0) @@ -444,14 +446,14 @@ #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) #define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304) -#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) +#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLEREG_BIT(12) #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) -#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) +#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c) #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) @@ -482,7 +484,7 @@ #define GEN8_RC6_CTX_INFO _MMIO(0x8504) -#define XEHP_SQCM _MMIO(0x8724) +#define XEHP_SQCM MCR_REG(0x8724) #define EN_32B_ACCESSREG_BIT(30) #define HSW_IDICR _MMIO(0x9008) @@ -643,7 +645,7 @@ #define GEN7_MISCCPCTL _MMIO(0x9424) #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) -#define GEN8_MISCCPCTL _MMIO(0x9424) +#define GEN8_MISCCPCTL MCR_REG(0x9424) #define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0) #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) @@ -699,7 +701,7 @@ #define LTCDD_CLKGATE_DISREG_BIT(10) #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) -#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4) #define SARBUNIT_CLKGATE_DIS (1 << 5) #define RCCUNIT_CLKGATE_DIS (1 << 7) #define MSCUNIT_CLKGATE_DIS (1 << 10)
[PATCH 03/12] drm/i915/gt: Drop a few unused register definitions
Let's drop a few register definitions that are unused anywhere in the driver today. Since the referenced offsets are part of what is now considered a multicast register region, the current definitions would not be correct for use on any future platform. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 559e3473f14c..53bedbd5ba0c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -450,13 +450,6 @@ #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) -/* GEN9 chicken */ -#define SLICE_ECO_CHICKEN0 _MMIO(0x7308) -#define PIXEL_MASK_CAMMING_DISABLE (1 << 14) - -#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) -#define DISABLE_PIXEL_MASK_CAMMING (1 << 14) - #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) #define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) @@ -963,11 +956,6 @@ #define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4) #define GEN7_L3LOG_SIZE 0x80 -#define GEN10_SCRATCH_LNCF2_MMIO(0xb0a0) -#define PMFLUSHDONE_LNICRSDROP (1 << 20) -#define PMFLUSH_GAPL3UNBLOCK (1 << 21) -#define PMFLUSHDONE_LNEBLK (1 << 22) - #define XEHP_L3NODEARBCFG _MMIO(0xb0b4) #define XEHP_LNESPAREREG_BIT(19) @@ -982,9 +970,6 @@ #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) -#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xb114) -#define GEN11_I2M_WRITE_DISABLE (1 << 28) - #define GEN8_L3SQCREG4 _MMIO(0xb118) #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) #define GEN8_LQSC_RO_PERF_DIS(1 << 27) @@ -1179,8 +1164,6 @@ #define SARB_CHICKEN1 _MMIO(0xe90c) #define COMP_CKN_IN REG_GENMASK(30, 29) -#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) - #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) #define DOP_CLOCK_GATING_DISABLE (1 << 0) #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) -- 2.37.3
[PATCH 09/12] drm/i915/gt: Add MCR-specific workaround initializers
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 424 +++---
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 259 insertions(+), 169 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3d48189021ad..f98213b7c61d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -166,12 +166,33 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t
reg,
_wa_add(wal, );
}
+static void wa_mcr_add(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 clear, u32 set, u32 read_mask, bool masked_reg)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .clr = clear,
+ .set = set,
+ .read = read_mask,
+ .masked_reg = masked_reg,
+ .is_mcr = 1,
+ };
+
+ _wa_add(wal, );
+}
+
static void
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
{
wa_add(wal, reg, clear, set, clear, false);
}
+static void
+wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32
set)
+{
+ wa_mcr_add(wal, reg, clear, set, clear, false);
+}
+
static void
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
@@ -184,12 +205,24 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32
set)
wa_write_clr_set(wal, reg, set, set);
}
+static void
+wa_mcr_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
+{
+ wa_mcr_write_clr_set(wal, reg, set, set);
+}
+
static void
wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
{
wa_write_clr_set(wal, reg, clr, 0);
}
+static void
+wa_mcr_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
+{
+ wa_mcr_write_clr_set(wal, reg, clr, 0);
+}
+
/*
* WA operations on "masked register". A masked register has the upper 16 bits
* documented as "masked" in b-spec. Its purpose is to allow writing to just a
@@ -207,12 +240,24 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg,
u32 val)
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
}
+static void
+wa_mcr_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
+}
+
static void
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
}
+static void
+wa_mcr_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
+}
+
static void
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
u32 mask, u32 val)
@@ -220,6 +265,13 @@ wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t
reg,
wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
}
+static void
+wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 mask, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
+}
+
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
@@ -241,7 +293,7 @@ static void gen8_ctx_workarounds_init(struct
intel_engine_cs *engine,
wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE),
ASYNC_FLIP_PERF_DISABLE);
/* WaDisablePartialInstShootdown:bdw,chv */
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* Use Force Non-Coherent whenever executing a 3D context. This is a
@@ -288,18 +340,18 @@ static void bdw_ctx_workarounds_init(struct
intel_engine_cs *engine,
gen8_ctx_workarounds_init(engine, wal);
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
- wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* WaDisableDopClockGating:bdw
*
* Also see the related UCGTCL1 write in bdw_init_clock_gating()
* to disable EUTC clock gating.
*/
- wa_masked_en(wal, GEN8_ROW_CHICKEN2,
-DOP_CLOCK_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
+DOP_CLOCK_GATING_DISABLE);
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
-GEN8_SAMPLER_POWER_BYPASS_DIS);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
+GEN8_SAMPLER_POWER_BYPASS_DIS);
wa_masked_en(wal, HDC_CHICKEN0,
/* WaForceContextSaveRestoreNonCoherent:bdw */
@@ -314,7 +366,7 @@ static void chv_ctx_workarounds_init(struct
[PATCH 08/12] drm/i915/guc: Handle save/restore of MCR registers explicitly
MCR registers can be placed on the GuC's save/restore list, but at the
moment they are always handled in a multicast manner (i.e., the GuC
reads one instance to save the value and then does a multicast write to
restore that single value to all instances). In the future the GuC will
probably give us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 55 +-
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 7d9f4f57ca95..b5d3e3ef1787 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -277,24 +277,16 @@ __mmio_reg_add(struct temp_regset *regset, struct
guc_mmio_reg *reg)
return slot;
}
-#define GUC_REGSET_STEERING(group, instance) ( \
- FIELD_PREP(GUC_REGSET_STEERING_GROUP, (group)) | \
- FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, (instance)) | \
- GUC_REGSET_NEEDS_STEERING \
-)
-
static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
struct temp_regset *regset,
- i915_reg_t reg, u32 flags)
+ u32 offset, u32 flags)
{
u32 count = regset->storage_used - (regset->registers -
regset->storage);
- u32 offset = i915_mmio_reg_offset(reg);
struct guc_mmio_reg entry = {
.offset = offset,
.flags = flags,
};
struct guc_mmio_reg *slot;
- u8 group, inst;
/*
* The mmio list is built using separate lists within the driver.
@@ -306,17 +298,6 @@ static long __must_check guc_mmio_reg_add(struct intel_gt
*gt,
sizeof(entry), guc_mmio_reg_cmp))
return 0;
- /*
-* The GuC doesn't have a default steering, so we need to explicitly
-* steer all registers that need steering. However, we do not keep track
-* of all the steering ranges, only of those that have a chance of using
-* a non-default steering from the i915 pov. Instead of adding such
-* tracking, it is easier to just program the default steering for all
-* regs that don't need a non-default one.
-*/
- intel_gt_mcr_get_nonterminated_steering(gt, reg, , );
- entry.flags |= GUC_REGSET_STEERING(group, inst);
-
slot = __mmio_reg_add(regset, );
if (IS_ERR(slot))
return PTR_ERR(slot);
@@ -334,6 +315,38 @@ static long __must_check guc_mmio_reg_add(struct intel_gt
*gt,
#define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \
guc_mmio_reg_add(gt, \
+regset, \
+i915_mmio_reg_offset(reg), \
+(masked) ? GUC_REGSET_MASKED : 0)
+
+#define GUC_REGSET_STEERING(group, instance) ( \
+ FIELD_PREP(GUC_REGSET_STEERING_GROUP, (group)) | \
+ FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, (instance)) | \
+ GUC_REGSET_NEEDS_STEERING \
+)
+
+static long __must_check guc_mcr_reg_add(struct intel_gt *gt,
+struct temp_regset *regset,
+i915_reg_t reg, u32 flags)
+{
+ u8 group, inst;
+
+ /*
+* The GuC doesn't have a default steering, so we need to explicitly
+* steer all registers that need steering. However, we do not keep track
+* of all the steering ranges, only of those that have a chance of using
+* a non-default steering from the i915 pov. Instead of adding such
+* tracking, it is easier to just program the default steering for all
+* regs that don't need a non-default one.
+*/
+ intel_gt_mcr_get_nonterminated_steering(gt, reg, , );
+ flags |= GUC_REGSET_STEERING(group, inst);
+
+ return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags);
+}
+
+#define GUC_MCR_REG_ADD(gt, regset, reg, masked) \
+ guc_mcr_reg_add(gt, \
regset, \
(reg), \
(masked) ? GUC_REGSET_MASKED : 0)
@@ -374,7 +387,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
/* add in local MOCS registers */
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
- ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i),
false);
+ ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i),
false);
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i),
false);
--
2.37.3
[PATCH 12/12] drm/i915/mtl: Add multicast steering for media GT
MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1. We'll always steer to
media slice 0 unless it is fused off (which is the case when VD0, VE0,
and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 19 +--
drivers/gpu/drm/i915/gt/intel_gt_types.h| 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +-
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 05f41f1cc88d..04f75c1e0f4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -41,6 +41,7 @@ static const char * const intel_steering_types[] = {
"MSLICE",
"LNCF",
"DSS",
+ "OADDRM",
"INSTANCE 0",
};
@@ -119,6 +120,12 @@ static const struct intel_mmio_range
mtl3d_dss_steering_table[] = {
{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
};
+static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
+ { 0x393200, 0x39323F },
+ { 0x393400, 0x3934FF },
+};
+
+
void intel_gt_mcr_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -141,8 +148,9 @@ void intel_gt_mcr_init(struct intel_gt *gt)
drm_warn(>drm, "mslice mask all zero!\n");
}
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
- gt->type == GT_PRIMARY) {
+ if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
+ gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
intel_uncore_read(gt->uncore, XEHP_FUSE4));
@@ -435,6 +443,13 @@ static void get_nonterminated_steering(struct intel_gt *gt,
*group = 0;
*instance = 0;
break;
+ case OADDRM:
+ if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) &
BIT(0))
+ *group = 0;
+ else
+ *group = 1;
+ *instance = 0;
+ break;
default:
MISSING_CASE(type);
*group = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 2a0441410ec7..5fa59a66dba2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -60,6 +60,7 @@ enum intel_steering_type {
MSLICE,
LNCF,
DSS,
+ OADDRM,
/*
* On some platforms there are multiple types of MCR registers that
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2562ad83966b..9227391fc144 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1585,12 +1585,28 @@ mtl_3d_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
}
}
+static void
+mtl_media_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+ /*
+* Unlike older platforms, we no longer setup implicit steering here;
+* all MCR accesses are explicitly steered.
+*/
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ struct drm_printer p = drm_debug_printer("MCR Steering:");
+
+ intel_gt_mcr_report_steering(, gt, false);
+ }
+}
+
static void
gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
+ if (IS_METEORLAKE(i915) && gt->type == GT_MEDIA)
+ mtl_media_gt_workarounds_init(gt, wal);
+ else if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
mtl_3d_gt_workarounds_init(gt, wal);
else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
--
2.37.3
[PATCH 02/12] drm/i915/xehp: Create separate reg definitions for new MCR registers
Starting in Xe_HP, several registers our driver works with have been
converted from singleton registers into replicated registers with
multicast behavior. Although the registers are still located at the
same MMIO offsets as on previous platforms, let's duplicate the register
definitions in preparation for upcoming patches that will handle
multicast registers in a special manner.
The registers that are now replicated on Xe_HP are:
* PAT_INDEX (mslice replication)
* FF_MODE2 (gslice replication)
* COMMON_SLICE_CHICKEN3 (gslice replication)
* SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
* SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
* LNCFCMOCS (lncf replication)
Bspec: 66534
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 -
drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++---
drivers/gpu/drm/i915/gt/intel_mocs.c| 5 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 -
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++--
5 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index e5a1ea255640..559e3473f14c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -329,6 +329,7 @@
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
+#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
#define XEHP_TILE_LMEM_RANGE_SHIFT 8
@@ -387,7 +388,8 @@
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
-#define FF_MODE2 _MMIO(0x6604)
+#define GEN12_FF_MODE2 _MMIO(0x6604)
+#define XEHP_FF_MODE2 _MMIO(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224
REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
@@ -442,6 +444,7 @@
#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
#define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLEREG_BIT(12)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
@@ -455,10 +458,9 @@
#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
-#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
-
-#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
+#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice) * 0x4)
#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) *
0x34 + \
@@ -703,7 +705,8 @@
#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
#define LTCDD_CLKGATE_DISREG_BIT(10)
-#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
#define MSCUNIT_CLKGATE_DIS (1 << 10)
@@ -718,7 +721,7 @@
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
-#define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
+#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
@@ -943,7 +946,8 @@
/* MOCS (Memory Object Control State) registers */
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3
Cache Control */
-#define GEN9_LNCFCMOCS_REG_COUNT 32
+#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3
Cache Control */
+#define LNCFCMOCS_REG_COUNT32
#define GEN7_L3CNTLREG3_MMIO(0xb024)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index b67831833c9a..601d89b4feb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -479,15 +479,26 @@ void gtt_write_workarounds(struct intel_gt *gt)
static void tgl_setup_private_ppat(struct intel_uncore *uncore)
{
- /* TGL doesn't support LLC or AGE settings */
-
[PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers
Gen8 was the first time our hardware had multicast registers (or at
least the first time the multicast nature was exposed and MMIO accesses
could be steered). There are some registers that transitioned from
singleton behavior to multicast during the gen7 -> gen8 transition;
let's duplicate the register definitions for those registers in
preparation for upcoming patches that will handle MCR registers in a
special manner.
The registers adjusted are:
* MISCCPCTL
* SAMPLER_INSTDONE
* ROW_INSTDONE
* ROW_CHICKEN2
* HALF_SLICE_CHICKEN1
* HALF_SLICE_CHICKEN3
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 +--
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 10 -
9 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2ddcad497fa3..c408bac3c533 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1559,11 +1559,11 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
for_each_ss_steering(iter, engine->gt, slice, subslice) {
instdone->sampler[slice][subslice] =
intel_gt_mcr_read(engine->gt,
- GEN7_SAMPLER_INSTDONE,
+ GEN8_SAMPLER_INSTDONE,
slice, subslice);
instdone->row[slice][subslice] =
intel_gt_mcr_read(engine->gt,
- GEN7_ROW_INSTDONE,
+ GEN8_ROW_INSTDONE,
slice, subslice);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1cbb7226400b..e5a1ea255640 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -647,6 +647,9 @@
#define GEN7_MISCCPCTL _MMIO(0x9424)
#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
+
+#define GEN8_MISCCPCTL _MMIO(0x9424)
+#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
@@ -1068,18 +1071,22 @@
#define GEN12_GAM_DONE _MMIO(0xcf68)
#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV
*/
+#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
+#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
+#define GEN8_ROW_INSTDONE _MMIO(0xe164)
#define HALF_SLICE_CHICKEN2_MMIO(0xe180)
#define GEN8_ST_PO_DISABLE (1 << 13)
-#define HALF_SLICE_CHICKEN3_MMIO(0xe184)
+#define HSW_HALF_SLICE_CHICKEN3_MMIO(0xe184)
+#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
@@ -1132,6 +1139,8 @@
#define DISABLE_EARLY_EOTREG_BIT(1)
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
+
+#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6d2003d598e6..e382cb4c6971 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -295,10 +295,10 @@ static void bdw_ctx_workarounds_init(struct
intel_engine_cs *engine,
* Also see the related UCGTCL1 write in bdw_init_clock_gating()
* to disable EUTC clock gating.
[PATCH 04/12] drm/i915/gt: Correct prefix on a few registers
We have a few registers that have existed for several hardware
generations, but are only used by the driver on Xe_HP and beyond. In
cases where the Xe_HP version of the register is now replicated and uses
multicast behavior, but earlier generations were singleton, let's change
the register prefix to "XEHP_" to help clarify that we're using the
newer multicast form of the register.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 53bedbd5ba0c..cf87a1b36a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -482,7 +482,7 @@
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
-#define GEN12_SQCM _MMIO(0x8724)
+#define XEHP_SQCM _MMIO(0x8724)
#define EN_32B_ACCESSREG_BIT(30)
#define HSW_IDICR _MMIO(0x9008)
@@ -985,7 +985,7 @@
#define GEN11_SCRATCH2 _MMIO(0xb140)
#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE(1 << 19)
-#define GEN11_L3SQCREG5_MMIO(0xb158)
+#define XEHP_L3SQCREG5 _MMIO(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
#define MLTICTXCTL _MMIO(0xb170)
@@ -1041,7 +1041,7 @@
#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
-#define GEN12_MERT_MOD_CTRL_MMIO(0xcf28)
+#define XEHP_MERT_MOD_CTRL _MMIO(0xcf28)
#define RENDER_MOD_CTRL_MMIO(0xcf2c)
#define COMP_MOD_CTRL _MMIO(0xcf30)
#define VDBX_MOD_CTRL _MMIO(0xcf34)
@@ -1143,7 +1143,7 @@
#define EU_PERF_CNTL1 _MMIO(0xe558)
#define EU_PERF_CNTL5 _MMIO(0xe55c)
-#define GEN12_HDC_CHICKEN0 _MMIO(0xe5f0)
+#define XEHP_HDC_CHICKEN0 _MMIO(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13,
11)
#define ICL_HDC_MODE _MMIO(0xe5f4)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index eff5f4f85374..3d48189021ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,7 +569,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs
*engine,
struct i915_wa_list *wal)
{
wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
- wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+ wa_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
XEHP_FF_MODE2,
@@ -1504,7 +1504,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
* recommended tuning settings documented in the bspec's
* performance guide section.
*/
- wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
+ wa_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
/* Wa_14015795083 */
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
@@ -2163,7 +2163,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
* Wa_22010960976:dg2
* Wa_14013347512:dg2
*/
- wa_masked_dis(wal, GEN12_HDC_CHICKEN0,
+ wa_masked_dis(wal, XEHP_HDC_CHICKEN0,
LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
}
@@ -2216,7 +2216,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012362059:dg2 */
- wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
}
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
@@ -2757,7 +2757,7 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
}
/* Wa_14012362059:xehpsdv */
- wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
/* Wa_14014368820:xehpsdv */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
INVALIDATION_BROADCAST_MODE_DIS |
--
2.37.3
Re: [PATCH v5 00/11] drm: bridge: Add Samsung MIPI DSIM bridge
On Fri, Sep 16, 2022 at 11:18 AM Jagan Teki wrote: > > This series supports common bridge support for Samsung MIPI DSIM > which is used in Exynos and i.MX8MM SoC's. > > Previous v4 can be available here [1], repo on linux-next [2] and > Engicam i.Core MX8M Mini SoM boot log [3]. > > The final bridge supports both the Exynos and i.MX8MM DSI devices. > > Changes for v3: > * bridge changes to support multi-arch > * updated and clear commit messages > * add hw_type via plat data > * removed unneeded quirk > * rebased on linux-next > > Changes for v4: > * include Inki Dae in MAINTAINERS > * remove dsi_driver probe in exynos_drm_drv to support multi-arch build > * update init handling to ensure host init done on first cmd transfer > > Changes for v3: > * fix the mult-arch build > * fix dsi host init > * updated commit messages > > Changes for v2: > * fix bridge handling > * fix dsi host init > * correct the commit messages > > Patch 0001: Restore proper bridge chain in exynos_dsi > > Patch 0002: Samsung DSIM bridge > > Patch 0003: PHY optional > > Patch 0004: OF-graph or Child node lookup > > Patch 0005: DSI host initialization > > Patch 0006: atomic check > > Patch 0007: PMS_P offset via plat data > > Patch 0008: atomic_get_input_bus_fmts > > Patch 0009: input_bus_flags > > Patch 0010: document fsl,imx8mm-mipi-dsim > > Patch 0011: add i.MX8MM DSIM support > > [3] https://gist.github.com/openedev/22b2d63b30ade0ba55ab414a2f47aaf0 > [2] https://github.com/openedev/kernel/tree/imx8mm-dsi-v5 Jagan, I would like to try out this latest series a board I have here. It looks like perhaps you did not push this imx8mm-dsi-v5 branch? Best Regards, Tim > [1] > https://patchwork.kernel.org/project/dri-devel/cover/20220829184031.1863663-1-ja...@amarulasolutions.com/ >
Re: [PATCH v2 5/7] drm/msm/dp: Implement hpd_notify()
On Fri, Sep 16, 2022 at 02:17:30PM -0700, Jeff Johnson wrote: > On 9/16/2022 1:00 PM, Bjorn Andersson wrote: > > From: Bjorn Andersson > > > > The DisplayPort controller's hot-plug mechanism is based on pinmuxing a > > physical signal no a GPIO pin into the controller. This is not always > > nit: s/ no / on /? > Correct, thank you Jeff. > > possible, either because there aren't dedicated GPIOs available or > > because the hot-plug signal is a virtual notification, in cases such as > > USB Type-C. >
Re: [PATCH v2 1/7] dt-bindings: msm/dp: Add SDM845 and SC8280XP compatibles
On Sat, Sep 17, 2022 at 06:03:27PM +0100, Krzysztof Kozlowski wrote: > On 16/09/2022 21:00, Bjorn Andersson wrote: > > From: Bjorn Andersson > > > > Add compatibles for the DisplayPort and Embedded DisplayPort blocks in > > Qualcomm SDM845 and SC8280XP platforms. > > > > Signed-off-by: Bjorn Andersson > > Signed-off-by: Bjorn Andersson > > No need for quicinc SoB (unless you also take ownership). > It's my understanding that both needs to be there. Bjorn @ Linaro authored the patch and the author must certify its origin, but as the submitter I must certify its origin. I'm not entirely sure what you mean about taking ownership, I am going to pursue getting these patches landed. But it wouldn't be correct for new me to claim I authored them. Regards, Bjorn > Acked-by: Krzysztof Kozlowski \ > > > Best regards, > Krzysztof
Re: [PATCH v2] virtio-gpu: fix shift wrapping bug in virtio_gpu_fence_event_create()
On Sun, Sep 18, 2022 at 11:36 PM Dan Carpenter wrote:
>
> The ->ring_idx_mask variable is a u64 so static checkers, Smatch in
> this case, complain if the BIT() is not also a u64.
>
> drivers/gpu/drm/virtio/virtgpu_ioctl.c:50 virtio_gpu_fence_event_create()
> warn: should '(1 << ring_idx)' be a 64 bit type?
>
> Fixes: cd7f5ca33585 ("drm/virtio: implement context init: add
> virtio_gpu_fence_event")
> Signed-off-by: Dan Carpenter
> ---
> v2: Style change. Use BIT_ULL().
Reviewed-by: Chia-I Wu
>
> drivers/gpu/drm/virtio/virtgpu_ioctl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
> b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
> index 3b1701607aae..5d05093014ac 100644
> --- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
> +++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
> @@ -47,7 +47,7 @@ static int virtio_gpu_fence_event_create(struct drm_device
> *dev,
> struct virtio_gpu_fence_event *e = NULL;
> int ret;
>
> - if (!(vfpriv->ring_idx_mask & (1 << ring_idx)))
> + if (!(vfpriv->ring_idx_mask & BIT_ULL(ring_idx)))
> return 0;
>
> e = kzalloc(sizeof(*e), GFP_KERNEL);
> --
> 2.35.1
>
Re: [igt-dev] [PATCH i-g-t v2 3/4] lib/igt_kmod: add compatibility for KUnit
Hi, Janusz,
> Am 09/09/2022 um 12:18 PM schrieb Janusz Krzysztofik
> :
>
> Hi Isabella,
>
> On Monday, 29 August 2022 02:09:19 CEST Isabella Basso wrote:
>> This adds functions for both executing the tests as well as parsing (K)TAP
>> kmsg output, as per the KTAP spec [1].
>>
>> [1] https://www.kernel.org/doc/html/latest/dev-tools/ktap.html
>>
>> Signed-off-by: Isabella Basso
>> ---
>> lib/igt_kmod.c | 290 +
>> lib/igt_kmod.h | 2 +
>> 2 files changed, 292 insertions(+)
>>
>> diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
>> index 97cac7f5..93cdfcc5 100644
>> --- a/lib/igt_kmod.c
>> +++ b/lib/igt_kmod.c
>> @@ -25,6 +25,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #include "igt_aux.h"
>> #include "igt_core.h"
>> @@ -32,6 +33,8 @@
>> #include "igt_sysfs.h"
>> #include "igt_taints.h"
>>
>> +#define BUF_LEN 4096
>> +
>> /**
>> * SECTION:igt_kmod
>> * @short_description: Wrappers around libkmod for module loading/unloading
>> @@ -713,6 +716,293 @@ void igt_kselftest_get_tests(struct kmod_module *kmod,
>> kmod_module_info_free_list(pre);
>> }
>>
>> +/**
>> + * lookup_value:
>> + * @haystack: the string to search in
>> + * @needle: the string to search for
>> + *
>> + * Returns: the value of the needle in the haystack, or -1 if not found.
>> + */
>> +static long lookup_value(const char *haystack, const char *needle)
>> +{
>> +const char *needle_rptr;
>> +char *needle_end;
>> +long num;
>> +
>> +needle_rptr = strcasestr(haystack, needle);
>> +
>> +if (needle_rptr == NULL)
>> +return -1;
>> +
>> +/* skip search string and whitespaces after it */
>> +needle_rptr += strlen(needle);
>> +
>> +num = strtol(needle_rptr, _end, 10);
>> +
>> +if (needle_rptr == needle_end)
>> +return -1;
>> +
>> +if (num == LONG_MIN || num == LONG_MAX)
>> +return 0;
>> +
>> +return num > 0 ? num : 0;
>> +}
>> +
>> +static int find_next_tap_subtest(char *record, char *test_name,
>> + bool is_subtest)
>> +{
>> +const char *name_lookup_str,
>> + *lend, *version_rptr, *name_rptr;
>> +long test_count;
>> +
>> +name_lookup_str = "test: ";
>> +
>> +version_rptr = strcasestr(record, "TAP version ");
>> +name_rptr = strcasestr(record, name_lookup_str);
>> +
>> +/*
>> + * total test count will almost always appear as 0..N at the beginning
>> + * of a run, so we use it as indication of a run
>> + */
>> +test_count = lookup_value(record, "..");
>> +
>> +/* no count found, so this is probably not starting a (sub)test */
>> +if (test_count < 0) {
>> +if (name_rptr != NULL) {
>> +if (test_name[0] == '\0')
>> +strncpy(test_name,
>> +name_rptr + strlen(name_lookup_str),
>> +BUF_LEN);
>> +else if (strcmp(test_name, name_rptr +
>> strlen(name_lookup_str)) == 0)
>> +return 0;
>> +else
>> +test_name[0] = '\0';
>> +
>> +}
>> +return -1;
>> +}
>> +
>> +/*
>> + * "(K)TAP version XX" should be the first line on all (sub)tests as per
>> + *
>> https://www.kernel.org/doc/html/latest/dev-tools/ktap.html#version-lines
>> + * but actually isn't, as it currently depends on whoever writes the
>> + * test to print this info
>> + */
>> +if (version_rptr == NULL)
>> +igt_info("Missing test version string\n");
>> +
>> +if (name_rptr == NULL) {
>> +/* we have to keep track of the name string, as it might be
>> + * contained in a line read previously */
>> +if (test_name[0] == '\0') {
>> +igt_info("Missing test name string\n");
>> +
>> +if (is_subtest)
>> +igt_info("Running %ld subtests...\n",
>> test_count);
>> +else
>> +igt_info("Running %ld tests...\n", test_count);
>> +} else {
>> +lend = strchrnul(test_name, '\n');
>> +
>> +if (*lend == '\0') {
>> +if (is_subtest)
>> +igt_info("Executing %ld subtests in:
>> %s\n",
>> + test_count, test_name);
>> +else
>> +igt_info("Executing %ld tests in: %s\n",
>> + test_count, test_name);
>> +return test_count;
>> +}
>> +
>> +if (is_subtest)
>> +igt_info("Executing %ld subtests in: %.*s\n",
>> + test_count, (int)(lend - test_name),
>> +
Re: [PATCH i-g-t v2 3/4] lib/igt_kmod: add compatibility for KUnit
Hi, David
> Am 01/09/2022 um 3:37 AM schrieb 'David Gow' via KUnit Development
> :
>
> On Mon, Aug 29, 2022 at 8:10 AM Isabella Basso wrote:
>>
>> This adds functions for both executing the tests as well as parsing (K)TAP
>> kmsg output, as per the KTAP spec [1].
>>
>> [1] https://www.kernel.org/doc/html/latest/dev-tools/ktap.html
>>
>> Signed-off-by: Isabella Basso
>> ---
>
> Thanks very much for sending these patches out again.
>
> Alas, I don't have a particularly useful igt setup to test this
> properly, but I've left a couple of notes from trying it on my laptop
> here.
Thanks for the review, it’s much appreciated! If you have the time I’ve left a
note at the bottom with a very simple way to run the tests, but I can also
provide you with a pastebin of the results if you prefer.
>
>> lib/igt_kmod.c | 290 +
>> lib/igt_kmod.h | 2 +
>> 2 files changed, 292 insertions(+)
>>
>> diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
>> index 97cac7f5..93cdfcc5 100644
>> --- a/lib/igt_kmod.c
>> +++ b/lib/igt_kmod.c
>> @@ -25,6 +25,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #include "igt_aux.h"
>> #include "igt_core.h"
>> @@ -32,6 +33,8 @@
>> #include "igt_sysfs.h"
>> #include "igt_taints.h"
>>
>> +#define BUF_LEN 4096
>> +
>> /**
>> * SECTION:igt_kmod
>> * @short_description: Wrappers around libkmod for module loading/unloading
>> @@ -713,6 +716,293 @@ void igt_kselftest_get_tests(struct kmod_module *kmod,
>>kmod_module_info_free_list(pre);
>> }
>>
>> +/**
>> + * lookup_value:
>> + * @haystack: the string to search in
>> + * @needle: the string to search for
>> + *
>> + * Returns: the value of the needle in the haystack, or -1 if not found.
>> + */
>> +static long lookup_value(const char *haystack, const char *needle)
>> +{
>> + const char *needle_rptr;
>> + char *needle_end;
>> + long num;
>> +
>> + needle_rptr = strcasestr(haystack, needle);
>> +
>> + if (needle_rptr == NULL)
>> + return -1;
>> +
>> + /* skip search string and whitespaces after it */
>> + needle_rptr += strlen(needle);
>> +
>> + num = strtol(needle_rptr, _end, 10);
>> +
>> + if (needle_rptr == needle_end)
>> + return -1;
>> +
>> + if (num == LONG_MIN || num == LONG_MAX)
>> + return 0;
>> +
>> + return num > 0 ? num : 0;
>> +}
>> +
>> +static int find_next_tap_subtest(char *record, char *test_name,
>> +bool is_subtest)
>> +{
>> + const char *name_lookup_str,
>> + *lend, *version_rptr, *name_rptr;
>> + long test_count;
>> +
>> + name_lookup_str = "test: ";
>> +
>> + version_rptr = strcasestr(record, "TAP version ");
>> + name_rptr = strcasestr(record, name_lookup_str);
>> +
>> + /*
>> +* total test count will almost always appear as 0..N at the
>> beginning
>> +* of a run, so we use it as indication of a run
>> +*/
>> + test_count = lookup_value(record, "..");
>> +
>> + /* no count found, so this is probably not starting a (sub)test */
>> + if (test_count < 0) {
>> + if (name_rptr != NULL) {
>> + if (test_name[0] == '\0')
>> + strncpy(test_name,
>> + name_rptr + strlen(name_lookup_str),
>> + BUF_LEN);
>> + else if (strcmp(test_name, name_rptr +
>> strlen(name_lookup_str)) == 0)
>> + return 0;
>> + else
>> + test_name[0] = '\0';
>> +
>> + }
>> + return -1;
>> + }
>> +
>> + /*
>> +* "(K)TAP version XX" should be the first line on all (sub)tests as
>> per
>> +*
>> https://www.kernel.org/doc/html/latest/dev-tools/ktap.html#version-lines
>> +* but actually isn't, as it currently depends on whoever writes the
>> +* test to print this info
>
> FYI: we're really trying to fix cases of "missing version lines",
> largely by making the kunit_test_suites() macro work in more
> circumstances.
>
> So while it may be worth still handling the case where this is
> missing, I don't think there are any tests in the latest versions of
> the kernel which should have this missing.
I’m not sure if I totally get how these work. Every time I run a KUnit test I
get something like this: https://pastebin.com/7Ff31PMC
As you can see it has been loaded as a module, just like we intend to do it
from IGT, and I see no version lines whatsoever. Am I doing something wrong?
>
>> +*/
>> + if (version_rptr == NULL)
>> + igt_info("Missing test version string\n");
>> +
>> + if (name_rptr == NULL) {
>> + /* we have to keep track of the name string, as it might be
>> +* contained in a
Re: [PATCH] drm/bridge: ti-sn65dsi83: Add and use hs_rate and lp_rate
On 9/19/22 15:43, Maxime Ripard wrote:
Hi,
Hello Maxime,
On Sun, Sep 18, 2022 at 02:56:00PM +0200, Marek Vasut wrote:
On 8/1/22 15:11, Marek Vasut wrote:
Fill in hs_rate and lp_rate to struct mipi_dsi_device for this bridge and
adjust DSI input frequency calculations such that they expect the DSI host
to configure HS clock according to hs_rate.
This is an optimization for the DSI burst mode case. In case the DSI device
supports DSI burst mode, it is recommended to operate the DSI interface at
the highest possible HS clock frequency which the DSI device supports. This
permits the DSI host to send as short as possible bursts of data on the DSI
link and keep the DSI data lanes in LP mode otherwise, which reduces power
consumption.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Robert Foss
Cc: Sam Ravnborg
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
index 14e7aa77e7584..b161f25c3a2f5 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
@@ -286,8 +286,7 @@ static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
return (mode_clock - 12500) / 25000;
}
-static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
- const struct drm_display_mode *mode)
+static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx)
{
/*
* The encoding of the CHA_DSI_CLK_RANGE is as follows:
@@ -303,20 +302,20 @@ static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
* DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
* the 2 is there because the bus is DDR.
*/
- return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
- mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
- ctx->dsi->lanes / 2, 4U, 50U), 5000U);
+ return DIV_ROUND_UP(ctx->dsi->hs_rate, 500U);
}
-static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
+static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx,
+ const struct drm_display_mode *mode)
{
/* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
- unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
+ unsigned int dsi_div;
+ int mode_clock = mode->clock;
- dsi_div /= ctx->dsi->lanes;
+ if (ctx->lvds_dual_link)
+ mode_clock /= 2;
- if (!ctx->lvds_dual_link)
- dsi_div /= 2;
+ dsi_div = (ctx->dsi->hs_rate / mode_clock) / 1000;
return dsi_div - 1;
}
@@ -397,9 +396,9 @@ static void sn65dsi83_atomic_enable(struct drm_bridge
*bridge,
REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
regmap_write(ctx->regmap, REG_DSI_CLK,
-REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx,
mode)));
+
REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx)));
regmap_write(ctx->regmap, REG_RC_DSI_CLK,
-
REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
+REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx,
mode)));
/* Set number of DSI lanes and LVDS link config. */
regmap_write(ctx->regmap, REG_DSI_LANE,
@@ -643,6 +642,8 @@ static int sn65dsi83_host_attach(struct sn65dsi83 *ctx)
dsi->lanes = dsi_lanes;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
+ dsi->hs_rate = 5;
+ dsi->lp_rate = 1600;
Let's leave aside the comment from Dave that the host might choose a
lower HS rate, we can indeed assume it's true for now.
However.. Is there any guarantee that the host can even reach that
frequency in the first place? IIRC, the maximum rate a DSI host can
reach is implementation specific. So I'm not sure this solution flies.
It's not clear to me from that patch what problem / issue it's supposed
to solve in the first place, but it really looks similar to the
discussion we had some time ago about that bridge that could only
operate at a set of fixed frequencies.
The use of exact frequency on DSI HS clock for bridges which derive
their PLL clock frequency from DSI HS clock discussion is separate a
topic from this patch.
This patch is defining the maximum DSI HS clock frequency this bridge
supports per datasheet (500 MHz) AND then assumes the DSI host would use
that frequency on the DSI link (in burst mode, the highest frequency on
the link permits the link to be in LP mode for longest time and thus be
as power efficient as possible).
About the assumption -- currently the DSI HS clock frequency
[PATCH] drm/amd/display: remove redundant CalculateRemoteSurfaceFlipDelay's
There are several copies of CalculateRemoteSurfaceFlipDelay.
Reduce to one instance.
Signed-off-by: Tom Rix
---
.../dc/dml/dcn20/display_mode_vba_20.c| 4 +-
.../dc/dml/dcn20/display_mode_vba_20v2.c | 40 +--
.../dc/dml/dcn21/display_mode_vba_21.c| 40 +--
3 files changed, 4 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 4ca080950924..8e5d58336bc5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -158,7 +158,7 @@ double CalculateTWait(
double DRAMClockChangeLatency,
double UrgentLatency,
double SREnterPlusExitTime);
-static double CalculateRemoteSurfaceFlipDelay(
+double CalculateRemoteSurfaceFlipDelay(
struct display_mode_lib *mode_lib,
double VRatio,
double SwathWidth,
@@ -2909,7 +2909,7 @@ double CalculateTWait(
}
}
-static double CalculateRemoteSurfaceFlipDelay(
+double CalculateRemoteSurfaceFlipDelay(
struct display_mode_lib *mode_lib,
double VRatio,
double SwathWidth,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 2b4dcae4e432..e9ebc81adc71 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -182,7 +182,7 @@ double CalculateTWait(
double DRAMClockChangeLatency,
double UrgentLatency,
double SREnterPlusExitTime);
-static double CalculateRemoteSurfaceFlipDelay(
+double CalculateRemoteSurfaceFlipDelay(
struct display_mode_lib *mode_lib,
double VRatio,
double SwathWidth,
@@ -2967,44 +2967,6 @@ static void dml20v2_DisplayPipeConfiguration(struct
display_mode_lib *mode_lib)
}
}
-static double CalculateRemoteSurfaceFlipDelay(
- struct display_mode_lib *mode_lib,
- double VRatio,
- double SwathWidth,
- double Bpp,
- double LineTime,
- double XFCTSlvVupdateOffset,
- double XFCTSlvVupdateWidth,
- double XFCTSlvVreadyOffset,
- double XFCXBUFLatencyTolerance,
- double XFCFillBWOverhead,
- double XFCSlvChunkSize,
- double XFCBusTransportTime,
- double TCalc,
- double TWait,
- double *SrcActiveDrainRate,
- double *TInitXFill,
- double *TslvChk)
-{
- double TSlvSetup, AvgfillRate, result;
-
- *SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
- TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth +
XFCTSlvVreadyOffset;
- *TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100);
- AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100);
- *TslvChk = XFCSlvChunkSize / AvgfillRate;
- dml_print(
- "DML::CalculateRemoteSurfaceFlipDelay:
SrcActiveDrainRate: %f\n",
- *SrcActiveDrainRate);
- dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n",
TSlvSetup);
- dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n",
*TInitXFill);
- dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n",
AvgfillRate);
- dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n",
*TslvChk);
- result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk
+ *TInitXFill; // TODO: This doesn't seem to match programming guide
- dml_print("DML::CalculateRemoteSurfaceFlipDelay:
RemoteSurfaceFlipDelay: %f\n", result);
- return result;
-}
-
static void CalculateActiveRowBandwidth(
bool GPUVMEnable,
enum source_format_class SourcePixelFormat,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index a3ef3638d979..d94aaf899f9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -210,7 +210,7 @@ double CalculateTWait(
double DRAMClockChangeLatency,
double UrgentLatency,
double SREnterPlusExitTime);
-static double CalculateRemoteSurfaceFlipDelay(
+double CalculateRemoteSurfaceFlipDelay(
struct display_mode_lib *mode_lib,
double VRatio,
double SwathWidth,
@@ -2980,44 +2980,6 @@ static void DisplayPipeConfiguration(struct
display_mode_lib *mode_lib)
Re: [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Modify CAGF functions for MTL
On 19-09-2022 22:19, Andi Shyti wrote:
Hi Badal,
On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
Updated the CAGF functions to get actual resolved frequency of
3D and SAMedia
can you please use the imperative form? "Update" and not
"Updated".
Ok.
Besides I don't really understand what you did from the
commit, can you please bea bit more descriptive?
Sure I will describe more.
For MTL Current Actual GFX frequency (CAGF) can be obtained from regs
0xc60 (GT0) and 0x380c60 (GT1). So to support MTL I modified functions
read_cagf and intel_rps_get_cagf.
Bspec: 66300
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 2275ee47da95..7819d32db956 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1510,6 +1510,14 @@
#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT_MMIO(0x13811c)
+/*
+ * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
+ * 3D - 0x0C60 , SAMedia - 0x380C60
+ * Intel uncore handler redirects transactions for SAMedia to
MTL_MEDIA_GSI_BASE
+ */
This comment is not understandable... we don't have limits in
space, you can be a bit more explicit :)
Below I defined only 0x0C60, so I am trying to say that
intel_uncore_read/write functions takes care of adding GSI offset i.e.
0x38000 if the access is for Gt1 (SAMEDIA).
This patch gives more clarity about GSI offset
https://patchwork.freedesktop.org/patch/502004/?series=107908=5
Regards,
Badal
Andi
+#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
+#define MTL_CAGF_MASKREG_GENMASK(8, 0)
+
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN11_GUNIT (28)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 17b40b625e31..c2349949ebae 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2075,6 +2075,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ cagf = rpstat & MTL_CAGF_MASK;
else if (GRAPHICS_VER(i915) >= 9)
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -2098,7 +2100,9 @@ static u32 read_cagf(struct intel_rps *rps)
vlv_punit_get(i915);
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
- } else if (GRAPHICS_VER(i915) >= 6) {
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ freq = intel_uncore_read(rps_to_gt(rps)->uncore,
MTL_MIRROR_TARGET_WP1);
+ else if (GRAPHICS_VER(i915) >= 6) {
freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
} else {
freq = intel_uncore_read(uncore, MEMSTAT_ILK);
--
2.25.1
Re: [PATCH] drm: xlnx: Fix return type of zynqmp_dp_connector_mode_valid
Hi Nathan,
Thank you for the patch.
On Tue, Sep 13, 2022 at 01:56:00PM -0700, Nathan Huckleberry wrote:
> The mode_valid field in drm_connector_helper_funcs is expected to be of
> type
> enum drm_mode_status (* mode_valid) (struct drm_connector *connector,
> struct drm_display_mode *mode);
>
> The mismatched return type breaks forward edge kCFI since the underlying
> function definition does not match the function hook definition.
>
> The return type of zynqmp_dp_connector_mode_valid should be changed from
> int to enum drm_mode_status.
>
> Reported-by: Dan Carpenter
> Link: https://github.com/ClangBuiltLinux/linux/issues/1703
> Cc: l...@lists.linux.dev
> Signed-off-by: Nathan Huckleberry
I'm not sure what forward edge kCFI is, but the fix looks good, so
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/xlnx/zynqmp_dp.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> index d14612b34796..f571b08d23d3 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> @@ -1352,8 +1352,9 @@ zynqmp_dp_connector_best_encoder(struct drm_connector
> *connector)
> return >encoder;
> }
>
> -static int zynqmp_dp_connector_mode_valid(struct drm_connector *connector,
> - struct drm_display_mode *mode)
> +static enum drm_mode_status
> +zynqmp_dp_connector_mode_valid(struct drm_connector *connector,
> +struct drm_display_mode *mode)
> {
> struct zynqmp_dp *dp = connector_to_dp(connector);
> u8 max_lanes = dp->link_config.max_lanes;
--
Regards,
Laurent Pinchart
[PATCH v1 12/17] drm/mediatek: hdmi: mt8195: add audio support
Add HDMI audio support for mt8195
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
index 39e07a6dd490..bb7593ea4c86 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
@@ -215,6 +215,26 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi,
bool black)
mtk_hdmi_mask(hdmi, TOP_VMUTE_CFG1, 0, REG_VMUTE_EN);
}
+static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
+{
+ u32 val;
+
+ val = mtk_hdmi_read(hdmi, AIP_CTRL, );
+
+ if (val & DSD_EN)
+ mtk_hdmi_mask(hdmi, AIP_TXCTRL,
+ DSD_MUTE_DATA | AUD_MUTE_FIFO_EN,
+ DSD_MUTE_DATA | AUD_MUTE_FIFO_EN);
+ else
+ mtk_hdmi_mask(hdmi, AIP_TXCTRL, AUD_MUTE_FIFO_EN,
+ AUD_MUTE_FIFO_EN);
+}
+
+static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
+{
+ mtk_hdmi_mask(hdmi, AIP_TXCTRL, AUD_MUTE_DIS, AUD_MUTE_FIFO_EN);
+}
+
static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
{
mtk_hdmi_mask(hdmi, HDMITX_CONFIG, 0x0 << HDMITX_SW_RSTB_SHIFT,
@@ -899,6 +919,7 @@ static void mtk_hdmi_audio_reset(struct mtk_hdmi *hdmi,
bool rst)
static void mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
struct drm_display_mode *display_mode)
{
+ mtk_hdmi_hw_aud_mute(hdmi);
mtk_hdmi_aud_enable_packet(hdmi, false);
mtk_hdmi_audio_reset(hdmi, true);
mtk_hdmi_aip_ctrl_init(hdmi);
@@ -911,6 +932,7 @@ static void mtk_hdmi_aud_output_config(struct mtk_hdmi
*hdmi,
usleep_range(25, 50);
mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
mtk_hdmi_aud_enable_packet(hdmi, true);
+ mtk_hdmi_hw_aud_unmute(hdmi);
}
void mtk_hdmi_output_init_mt8195(struct mtk_hdmi *hdmi)
@@ -945,6 +967,28 @@ static void mtk_hdmi_reset_colorspace_setting(struct
mtk_hdmi *hdmi)
hdmi->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
}
+static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
+{
+ mtk_hdmi_aud_enable_packet(hdmi, true);
+ hdmi->audio_enable = true;
+}
+
+static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
+{
+ mtk_hdmi_aud_enable_packet(hdmi, false);
+ hdmi->audio_enable = false;
+}
+
+static void mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
+struct hdmi_audio_param *param)
+{
+ if (!hdmi->audio_enable)
+ return;
+
+ memcpy(>aud_param, param, sizeof(*param));
+ mtk_hdmi_aud_output_config(hdmi, >mode);
+}
+
static void mtk_hdmi_change_video_resolution(struct mtk_hdmi *hdmi)
{
bool is_over_340M = false;
@@ -965,6 +1009,7 @@ static void mtk_hdmi_change_video_resolution(struct
mtk_hdmi *hdmi)
usleep_range(5, 10);
mtk_hdmi_hw_vid_black(hdmi, true);
+ mtk_hdmi_hw_aud_mute(hdmi);
mtk_hdmi_hw_send_av_unmute(hdmi);
mtk_hdmi_mask(hdmi, TOP_CFG01, NULL_PKT_VSYNC_HIGH_EN,
@@ -1295,12 +1340,21 @@ static void mtk_hdmi_bridge_disable(struct drm_bridge
*bridge,
mtk_hdmi_hw_send_av_mute(hdmi);
usleep_range(5, 50050);
mtk_hdmi_hw_vid_black(hdmi, true);
+ mtk_hdmi_hw_aud_mute(hdmi);
mtk_hdmi_disable_hdcp_encrypt(hdmi);
usleep_range(5, 50050);
hdmi->enabled = false;
}
+static void mtk_hdmi_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugged)
+{
+ mutex_lock(>update_plugged_status_lock);
+ if (hdmi->plugged_cb && hdmi->codec_dev)
+ hdmi->plugged_cb(hdmi->codec_dev, plugged);
+ mutex_unlock(>update_plugged_status_lock);
+}
+
static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_state)
{
@@ -1314,6 +1368,9 @@ static void mtk_hdmi_bridge_post_disable(struct
drm_bridge *bridge,
hdmi->powered = false;
mtk_hdmi_reset_colorspace_setting(hdmi);
+
+ /* signal the disconnect event to audio codec */
+ mtk_hdmi_handle_plugged_change(hdmi, false);
}
static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge,
@@ -1346,6 +1403,10 @@ static void mtk_hdmi_bridge_enable(struct drm_bridge
*bridge,
mtk_hdmi_hw_avi_infoframe(hdmi, buffer_avi, sizeof(buffer_avi));
mtk_hdmi_hw_vid_black(hdmi, false);
+ mtk_hdmi_hw_aud_unmute(hdmi);
+
+ /* signal the connect event to audio codec */
+ mtk_hdmi_handle_plugged_change(hdmi, true);
hdmi->enabled = true;
}
@@ -1385,3 +1446,155 @@ const struct drm_bridge_funcs
mtk_mt8195_hdmi_bridge_funcs = {
.get_edid = mtk_hdmi_bridge_get_edid,
.detect = mtk_hdmi_bridge_detect,
};
+
+static void mtk_hdmi_set_plugged_cb(struct mtk_hdmi *hdmi,
+ hdmi_codec_plugged_cb fn,
+ struct
[PATCH v1 16/17] drm/mediatek: dpi: Add mt8195 hdmi to DPI driver
Add the DPI1 hdmi path support in mtk dpi driver
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 630a4e301ef6..91212b7610e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -15,7 +15,10 @@
#include
#include
#include
+#include
#include
+#include
+#include
#include
@@ -66,10 +69,14 @@ struct mtk_dpi {
struct drm_bridge *next_bridge;
struct drm_connector *connector;
void __iomem *regs;
+ struct reset_control *reset_ctl;
struct device *dev;
struct clk *engine_clk;
+ struct clk *dpi_ck_cg;
struct clk *pixel_clk;
+ struct clk *dpi_sel_clk;
struct clk *tvd_clk;
+ struct clk *hdmi_cg;
int irq;
struct drm_display_mode mode;
const struct mtk_dpi_conf *conf;
@@ -135,6 +142,7 @@ struct mtk_dpi_yc_limit {
* @yuv422_en_bit: Enable bit of yuv422.
* @csc_enable_bit: Enable bit of CSC.
* @pixels_per_iter: Quantity of transferred pixels per iteration.
+ * @is_internal_hdmi: True if this DPI block is directly connected to SoC
internal HDMI block
*/
struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
@@ -153,6 +161,7 @@ struct mtk_dpi_conf {
u32 yuv422_en_bit;
u32 csc_enable_bit;
u32 pixels_per_iter;
+ bool is_internal_hdmi;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -466,8 +475,15 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
mtk_dpi_disable(dpi);
+
+ reset_control_rearm(dpi->reset_ctl);
+
clk_disable_unprepare(dpi->pixel_clk);
clk_disable_unprepare(dpi->engine_clk);
+ clk_disable_unprepare(dpi->dpi_sel_clk);
+ clk_disable_unprepare(dpi->dpi_ck_cg);
+ clk_disable_unprepare(dpi->hdmi_cg);
+ clk_disable_unprepare(dpi->tvd_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi)
@@ -483,12 +499,44 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
goto err_refcount;
}
+ ret = clk_prepare_enable(dpi->dpi_sel_clk);
+ if (ret) {
+ dev_err(dpi->dev, "failed to enable dpi_sel clock: %d\n", ret);
+ goto err_refcount;
+ }
+
+ ret = clk_prepare_enable(dpi->tvd_clk);
+ if (ret) {
+ dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret);
+ goto err_tvd;
+ }
+
+ ret = clk_prepare_enable(dpi->engine_clk);
+ if (ret) {
+ dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
+ goto err_engine;
+ }
+
+ ret = clk_prepare_enable(dpi->hdmi_cg);
+ if (ret) {
+ dev_err(dpi->dev, "Failed to enable hdmi_cg clock: %d\n", ret);
+ goto err_hdmi_cg;
+ }
+
+ ret = clk_prepare_enable(dpi->dpi_ck_cg);
+ if (ret) {
+ dev_err(dpi->dev, "Failed to enable dpi_ck_cg clock: %d\n",
ret);
+ goto err_ck_cg;
+ }
+
ret = clk_prepare_enable(dpi->pixel_clk);
if (ret) {
dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
goto err_pixel;
}
+ reset_control_reset(dpi->reset_ctl);
+
if (dpi->pinctrl && dpi->pins_dpi)
pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
@@ -496,6 +544,15 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel:
clk_disable_unprepare(dpi->engine_clk);
+ clk_disable_unprepare(dpi->dpi_ck_cg);
+err_ck_cg:
+ clk_disable_unprepare(dpi->hdmi_cg);
+err_hdmi_cg:
+ clk_disable_unprepare(dpi->engine_clk);
+err_engine:
+ clk_disable_unprepare(dpi->tvd_clk);
+err_tvd:
+ clk_disable_unprepare(dpi->dpi_sel_clk);
err_refcount:
dpi->refcount--;
return ret;
@@ -539,7 +596,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
else
clk_set_rate(dpi->pixel_clk, vm.pixelclock);
-
vm.pixelclock = clk_get_rate(dpi->pixel_clk);
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
@@ -606,7 +662,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
if (dpi->conf->support_direct_pin) {
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
mtk_dpi_config_2n_h_fre(dpi);
- mtk_dpi_dual_edge(dpi);
+ // DPI could be connecting to external bridge
+ // or internal HDMI encoder.
+ if (dpi->conf->is_internal_hdmi) {
+ mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN,
+DPI_OUTPUT_1T1P_EN);
+ mtk_dpi_mask(dpi, DPI_CON, DPI_INPUT_2P_EN,
+DPI_INPUT_2P_EN);
+ } else {
+ mtk_dpi_dual_edge(dpi);
[PATCH v1 10/17] drm/mediatek: hdmi: add frame_colorimetry flag
Add a flag to indicate support for frame colorimetry.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 30407603d693..9fe086e2cd7c 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -120,6 +120,17 @@ int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, u8
*buffer, size_t bufsz
return err;
}
+ if (hdmi->conf->has_frame_colorimetry) {
+ frame.colorimetry = hdmi->colorimtery;
+ if (frame.colorimetry == HDMI_COLORIMETRY_EXTENDED)
+ frame.extended_colorimetry = hdmi->extended_colorimetry;
+
+ /* quantiation range:limited or full */
+ if (frame.colorspace == HDMI_COLORSPACE_RGB)
+ frame.quantization_range = hdmi->quantization_range;
+ else
+ frame.ycc_quantization_range =
hdmi->ycc_quantization_range;
+ }
err = hdmi_avi_infoframe_pack(, buffer, bufsz);
if (err < 0) {
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
index 62a14435be69..75a9b62dccee 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -33,6 +33,7 @@ struct mtk_hdmi_conf {
bool cea_modes_only;
bool has_cec;
bool has_connector;
+ bool has_frame_colorimetry;
unsigned long max_mode_clock;
const struct drm_bridge_funcs *bridge_funcs;
void (*mtk_hdmi_output_init)(struct mtk_hdmi *hdmi);
--
b4 0.10.0-dev
[PATCH v1 13/17] phy: phy-mtk-hdmi: Add generic phy configure callback
Some phys, such as mt8195, needs to have a configure callback defined.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c
b/drivers/phy/mediatek/phy-mtk-hdmi.c
index d4bd419abc3c..af46472237e0 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
@@ -8,10 +8,12 @@
static int mtk_hdmi_phy_power_on(struct phy *phy);
static int mtk_hdmi_phy_power_off(struct phy *phy);
+static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts
*opts);
static const struct phy_ops mtk_hdmi_phy_dev_ops = {
.power_on = mtk_hdmi_phy_power_on,
.power_off = mtk_hdmi_phy_power_off,
+ .configure = mtk_hdmi_phy_configure,
.owner = THIS_MODULE,
};
@@ -76,6 +78,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
return 0;
}
+static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts
*opts)
+{
+ struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
+
+ if (hdmi_phy->conf->hdmi_phy_configure)
+ return hdmi_phy->conf->hdmi_phy_configure(phy, opts);
+
+ return 0;
+}
+
static const struct phy_ops *
mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
{
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h
b/drivers/phy/mediatek/phy-mtk-hdmi.h
index dcf9bb13699b..05de93f63a61 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.h
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.h
@@ -25,6 +25,7 @@ struct mtk_hdmi_phy_conf {
const struct clk_ops *hdmi_phy_clk_ops;
void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
+ int (*hdmi_phy_configure)(struct phy *phy, union phy_configure_opts
*opts);
};
struct mtk_hdmi_phy {
--
b4 0.10.0-dev
[PATCH v1 17/17] drm/mediatek: Add mt8195-dpi support to drm_drv
Add dpi support to enable the HDMI path.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 72049a530ae1..27f029ca760b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -820,6 +820,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8192-dpi",
.data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8195-dpi",
+ .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8195-dp-intf",
.data = (void *)MTK_DP_INTF },
{ .compatible = "mediatek,mt2701-dsi",
--
b4 0.10.0-dev
[PATCH v1 06/17] dt-bindings: mediatek: set the hdmi to be compatible with syscon
In order to share register with a dedicated ddc driver, set the hdmi
compatible to syscon.
Signed-off-by: Guillaume Ranquet
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
index abb231a0694b..86297b7eb7f7 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
@@ -16,12 +16,14 @@ description: |
properties:
compatible:
-enum:
- - mediatek,mt2701-hdmi
- - mediatek,mt7623-hdmi
- - mediatek,mt8167-hdmi
- - mediatek,mt8173-hdmi
- - mediatek,mt8195-hdmi
+items:
+ - enum:
+ - mediatek,mt2701-hdmi
+ - mediatek,mt7623-hdmi
+ - mediatek,mt8167-hdmi
+ - mediatek,mt8173-hdmi
+ - const: syscon
+
clocks: true
clock-names: true
@@ -142,7 +144,7 @@ examples:
#include
#include
hdmi0: hdmi@14025000 {
-compatible = "mediatek,mt8173-hdmi";
+compatible = "mediatek,mt8173-hdmi", "syscon";
reg = <0x14025000 0x400>;
interrupts = ;
clocks = < CLK_MM_HDMI_PIXEL>,
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 7640b5158ff9..3e7a0f406631 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1306,7 +1306,7 @@ od@14023000 {
};
hdmi0: hdmi@14025000 {
- compatible = "mediatek,mt8173-hdmi";
+ compatible = "mediatek,mt8173-hdmi", "syscon";
reg = <0 0x14025000 0 0x400>;
interrupts = ;
clocks = < CLK_MM_HDMI_PIXEL>,
--
b4 0.10.0-dev
[PATCH v1 08/17] drm/mediatek: hdmi: add cec flag
Add a flag to indicate support for cec.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index bfcca6f8b839..86653ebaacfd 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -154,35 +154,38 @@ int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct
platform_device *pdev,
return ret;
}
- /* The CEC module handles HDMI hotplug detection */
- cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
- if (!cec_np) {
- dev_err(dev, "Failed to find CEC node\n");
- return -EINVAL;
- }
+ if (hdmi->conf->has_cec) {
+ /* The CEC module handles HDMI hotplug detection */
+ cec_np = of_get_compatible_child(np->parent,
"mediatek,mt8173-cec");
+ if (!cec_np) {
+ dev_err(dev, "Failed to find CEC node\n");
+ return -EINVAL;
+ }
- cec_pdev = of_find_device_by_node(cec_np);
- if (!cec_pdev) {
- dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", cec_np);
+ cec_pdev = of_find_device_by_node(cec_np);
+ if (!cec_pdev) {
+ dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
cec_np);
+ of_node_put(cec_np);
+ return -EPROBE_DEFER;
+ }
of_node_put(cec_np);
- return -EPROBE_DEFER;
- }
- of_node_put(cec_np);
- hdmi->cec_dev = _pdev->dev;
- /*
-* The mediatek,syscon-hdmi property contains a phandle link to the
-* MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
-* registers it contains.
-*/
- regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
- ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
>sys_offset);
- if (IS_ERR(regmap))
- ret = PTR_ERR(regmap);
- if (ret) {
- dev_err(dev, "Failed to get system configuration registers:
%d\n", ret);
- goto put_device;
+ hdmi->cec_dev = _pdev->dev;
+ /*
+* The mediatek,syscon-hdmi property contains a phandle link to
the
+* MMSYS_CONFIG device and the register offset of the
HDMI_SYS_CFG
+* registers it contains.
+*/
+ regmap = syscon_regmap_lookup_by_phandle(np,
"mediatek,syscon-hdmi");
+ ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
>sys_offset);
+ if (IS_ERR(regmap))
+ ret = PTR_ERR(regmap);
+ if (ret) {
+ dev_err(dev,
+ "Failed to get system configuration registers:
%d\n", ret);
+ goto put_device;
+ }
+ hdmi->sys_regmap = regmap;
}
- hdmi->sys_regmap = regmap;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem) {
@@ -230,7 +233,8 @@ int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct
platform_device *pdev,
return 0;
put_device:
- put_device(hdmi->cec_dev);
+ if (hdmi->conf->has_cec)
+ put_device(hdmi->cec_dev);
return ret;
}
@@ -320,6 +324,7 @@ int mtk_drm_hdmi_remove(struct platform_device *pdev)
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
.tz_disabled = true,
+ .has_cec = true,
.bridge_funcs = _mt8183_hdmi_bridge_funcs,
.mtk_hdmi_output_init = mtk_hdmi_output_init_mt8183,
.mtk_hdmi_clk_disable = mtk_hdmi_clk_disable_audio_mt8183,
@@ -332,6 +337,7 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
.max_mode_clock = 148500,
.cea_modes_only = true,
+ .has_cec = true,
.bridge_funcs = _mt8183_hdmi_bridge_funcs,
.mtk_hdmi_output_init = mtk_hdmi_output_init_mt8183,
.mtk_hdmi_clk_disable = mtk_hdmi_clk_disable_audio_mt8183,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
index 7452bea91f9e..921bde150e11 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -31,6 +31,7 @@
struct mtk_hdmi_conf {
bool tz_disabled;
bool cea_modes_only;
+ bool has_cec;
unsigned long max_mode_clock;
const struct drm_bridge_funcs *bridge_funcs;
void (*mtk_hdmi_output_init)(struct mtk_hdmi *hdmi);
--
b4 0.10.0-dev
[PATCH v1 11/17] drm/mediatek: hdmi: add mt8195 support
Adds hdmi and hdmi-ddc support for mt8195.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 008ec69da67b..f1ef6c8ae2b8 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -24,6 +24,8 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
mtk_hdmi.o \
mtk_hdmi_ddc.o \
mtk_hdmi_common.o \
+ mtk_mt8195_hdmi.o \
+ mtk_mt8195_hdmi_ddc.o \
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 9fe086e2cd7c..f6bfe6c1c0be 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -226,14 +226,22 @@ int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct
platform_device *pdev,
goto put_device;
}
}
- }
- i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
- if (!i2c_np) {
- of_node_put(pdev->dev.of_node);
- dev_err(dev, "Failed to find ddc-i2c-bus");
- ret = -EINVAL;
- goto put_device;
+ i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
+ if (!i2c_np) {
+ of_node_put(pdev->dev.of_node);
+ dev_err(dev, "Failed to find ddc-i2c-bus");
+ ret = -EINVAL;
+ goto put_device;
+ }
+ } else {
+ i2c_np = of_parse_phandle(pdev->dev.of_node, "ddc-i2c-bus", 0);
+ if (!i2c_np) {
+ of_node_put(pdev->dev.of_node);
+ dev_err(dev, "Failed to find ddc-i2c-bus");
+ ret = -EINVAL;
+ goto put_device;
+ }
}
hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
@@ -372,6 +380,17 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8173 = {
.num_clocks = MTK_MT8183_HDMI_CLK_COUNT,
};
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8195 = {
+ .has_frame_colorimetry = true,
+ .bridge_funcs = _mt8195_hdmi_bridge_funcs,
+ .mtk_hdmi_output_init = mtk_hdmi_output_init_mt8195,
+ .mtk_hdmi_clk_disable = mtk_hdmi_clk_disable_mt8195,
+ .mtk_hdmi_clk_enable = mtk_hdmi_clk_enable_mt8195,
+ .set_hdmi_codec_pdata = set_hdmi_codec_pdata_mt8195,
+ .mtk_hdmi_clock_names = mtk_hdmi_clk_names_mt8195,
+ .num_clocks = MTK_MT8195_HDMI_CLK_COUNT,
+};
+
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt2701-hdmi",
.data = _hdmi_conf_mt2701,
@@ -382,6 +401,9 @@ static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt8173-hdmi",
.data = _hdmi_conf_mt8173,
},
+ { .compatible = "mediatek,mt8195-hdmi",
+ .data = _hdmi_conf_mt8195,
+ },
{}
};
MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
@@ -430,6 +452,7 @@ static struct platform_driver mtk_hdmi_driver = {
static struct platform_driver * const mtk_hdmi_drivers[] = {
_hdmi_ddc_driver,
_cec_driver,
+ _hdmi_mt8195_ddc_driver,
_hdmi_driver,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
index 75a9b62dccee..737306611fb9 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -27,6 +27,7 @@
#include "mtk_cec.h"
#include "mtk_hdmi.h"
+#include "mtk_mt8195_hdmi.h"
struct mtk_hdmi_conf {
bool tz_disabled;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
new file mode 100644
index ..39e07a6dd490
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
@@ -0,0 +1,1387 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Copyright (c) 2022 BayLibre, SAS
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_drm_crtc.h"
+#include "mtk_hdmi_common.h"
+#include "mtk_mt8195_hdmi.h"
+#include "mtk_mt8195_hdmi_regs.h"
+
+#define RGB444_8bit BIT(0)
+#define RGB444_10bit BIT(1)
+#define RGB444_12bit BIT(2)
+#define RGB444_16bit BIT(3)
+
+#define YCBCR444_8bit BIT(4)
+#define YCBCR444_10bit BIT(5)
+#define YCBCR444_12bit BIT(6)
+#define YCBCR444_16bit BIT(7)
+
+#define YCBCR422_8bit_NO_SUPPORT BIT(8)
+#define YCBCR422_10bit_NO_SUPPORT BIT(9)
+#define YCBCR422_12bit BIT(10)
+#define YCBCR422_16bit_NO_SUPPORT BIT(11)
+
+#define YCBCR420_8bit BIT(12)
+#define YCBCR420_10bit BIT(13)
[PATCH v1 14/17] phy: mediatek: add support for phy-mtk-hdmi-mt8195
Add basic support for the mediatek hdmi phy on MT8195 SoC
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
index bb7593ea4c86..0157acdce56c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
@@ -1344,6 +1344,8 @@ static void mtk_hdmi_bridge_disable(struct drm_bridge
*bridge,
mtk_hdmi_disable_hdcp_encrypt(hdmi);
usleep_range(5, 50050);
+ phy_power_off(hdmi->phy);
+
hdmi->enabled = false;
}
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index fb1f8edaffa7..c9a50395533e 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
+phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8195.o
obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi-drv.o
phy-mtk-mipi-dsi-drv-y := phy-mtk-mipi-dsi.o
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
new file mode 100644
index ..149015b64c02
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2021 BayLibre, SAS
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-mtk-hdmi.h"
+#include "phy-mtk-hdmi-mt8195.h"
+
+static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy)
+{
+ /* make data fifo writable for hdmi2.0 */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN,
+ REG_ANA_HDMI20_FIFO_EN);
+}
+
+static void
+mtk_mt8195_phy_tmds_high_bit_clk_ratio(struct mtk_hdmi_phy *hdmi_phy,
+ bool enable)
+{
+ mtk_hdmi_ana_fifo_en(hdmi_phy);
+
+ /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G,
+* clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10
+*/
+ if (enable)
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI20_CLK_CFG,
+ 0x2 << REG_TXC_DIV_SHIFT, REG_TXC_DIV);
+ else
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI20_CLK_CFG, 0, REG_TXC_DIV);
+}
+
+static void mtk_hdmi_pll_select_source(struct clk_hw *hw)
+{
+ struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CTL_3, 0x0, REG_HDMITX_REF_XTAL_SEL);
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CTL_3, 0x0, REG_HDMITX_REF_RESPLL_SEL);
+
+ /* DA_HDMITX21_REF_CK for TXPLL input source */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_CFG_10, 0x0,
+ RG_HDMITXPLL_REF_CK_SEL);
+}
+
+static int mtk_hdmi_pll_performance_setting(struct clk_hw *hw)
+{
+ struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+
+ /* BP2 */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_0,
+ 0x1 << RG_HDMITXPLL_BP2_SHIFT, RG_HDMITXPLL_BP2);
+
+ /* BC */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_2,
+ 0x3 << RG_HDMITXPLL_BC_SHIFT, RG_HDMITXPLL_BC);
+
+ /* IC */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_2,
+ 0x1 << RG_HDMITXPLL_IC_SHIFT, RG_HDMITXPLL_IC);
+
+ /* BR */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_2,
+ 0x2 << RG_HDMITXPLL_BR_SHIFT, RG_HDMITXPLL_BR);
+
+ /* IR */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_2,
+ 0x2 << RG_HDMITXPLL_IR_SHIFT, RG_HDMITXPLL_IR);
+
+ /* BP */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_2,
+ 0xf << RG_HDMITXPLL_BP_SHIFT, RG_HDMITXPLL_BP);
+
+ /* IBAND_FIX_EN, RESERVE[14] */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_0,
+ 0x0 << RG_HDMITXPLL_IBAND_FIX_EN_SHIFT,
+ RG_HDMITXPLL_IBAND_FIX_EN);
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_1,
+ 0x0 << RG_HDMITXPLL_RESERVE_BIT14_SHIFT,
+ RG_HDMITXPLL_RESERVE_BIT14);
+
+ /* HIKVCO */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_2,
+ 0x0 << RG_HDMITXPLL_HIKVCO_SHIFT,
+ RG_HDMITXPLL_HIKVCO);
+
+ /* HREN */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_0,
+ 0x1 << RG_HDMITXPLL_HREN_SHIFT, RG_HDMITXPLL_HREN);
+
+ /* LVR_SEL */
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_1_PLL_CFG_0,
+ 0x1 << RG_HDMITXPLL_LVR_SEL_SHIFT,
+ RG_HDMITXPLL_LVR_SEL);
+
+ /* RG_HDMITXPLL_RESERVE[12:11] */
+
[PATCH v1 07/17] drm/mediatek: extract common functions from the mtk hdmi driver
Create a common "framework" that can be used to add support for
different hdmi IPs within the mediatek range of products.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..008ec69da67b 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -22,7 +22,8 @@ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
mediatek-drm-hdmi-objs := mtk_cec.o \
mtk_hdmi.o \
- mtk_hdmi_ddc.o
+ mtk_hdmi_ddc.o \
+ mtk_hdmi_common.o \
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 5cd05d4fe1a9..837d36ec4d64 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -32,187 +32,18 @@
#include
#include "mtk_cec.h"
-#include "mtk_hdmi.h"
#include "mtk_hdmi_regs.h"
+#include "mtk_hdmi_common.h"
#define NCTS_BYTES 7
-enum mtk_hdmi_clk_id {
- MTK_HDMI_CLK_HDMI_PIXEL,
- MTK_HDMI_CLK_HDMI_PLL,
- MTK_HDMI_CLK_AUD_BCLK,
- MTK_HDMI_CLK_AUD_SPDIF,
- MTK_HDMI_CLK_COUNT
+const char * const mtk_hdmi_clk_names_mt8183[MTK_MT8183_HDMI_CLK_COUNT] = {
+ [MTK_MT8183_HDMI_CLK_HDMI_PIXEL] = "pixel",
+ [MTK_MT8183_HDMI_CLK_HDMI_PLL] = "pll",
+ [MTK_MT8183_HDMI_CLK_AUD_BCLK] = "bclk",
+ [MTK_MT8183_HDMI_CLK_AUD_SPDIF] = "spdif",
};
-enum hdmi_aud_input_type {
- HDMI_AUD_INPUT_I2S = 0,
- HDMI_AUD_INPUT_SPDIF,
-};
-
-enum hdmi_aud_i2s_fmt {
- HDMI_I2S_MODE_RJT_24BIT = 0,
- HDMI_I2S_MODE_RJT_16BIT,
- HDMI_I2S_MODE_LJT_24BIT,
- HDMI_I2S_MODE_LJT_16BIT,
- HDMI_I2S_MODE_I2S_24BIT,
- HDMI_I2S_MODE_I2S_16BIT
-};
-
-enum hdmi_aud_mclk {
- HDMI_AUD_MCLK_128FS,
- HDMI_AUD_MCLK_192FS,
- HDMI_AUD_MCLK_256FS,
- HDMI_AUD_MCLK_384FS,
- HDMI_AUD_MCLK_512FS,
- HDMI_AUD_MCLK_768FS,
- HDMI_AUD_MCLK_1152FS,
-};
-
-enum hdmi_aud_channel_type {
- HDMI_AUD_CHAN_TYPE_1_0 = 0,
- HDMI_AUD_CHAN_TYPE_1_1,
- HDMI_AUD_CHAN_TYPE_2_0,
- HDMI_AUD_CHAN_TYPE_2_1,
- HDMI_AUD_CHAN_TYPE_3_0,
- HDMI_AUD_CHAN_TYPE_3_1,
- HDMI_AUD_CHAN_TYPE_4_0,
- HDMI_AUD_CHAN_TYPE_4_1,
- HDMI_AUD_CHAN_TYPE_5_0,
- HDMI_AUD_CHAN_TYPE_5_1,
- HDMI_AUD_CHAN_TYPE_6_0,
- HDMI_AUD_CHAN_TYPE_6_1,
- HDMI_AUD_CHAN_TYPE_7_0,
- HDMI_AUD_CHAN_TYPE_7_1,
- HDMI_AUD_CHAN_TYPE_3_0_LRS,
- HDMI_AUD_CHAN_TYPE_3_1_LRS,
- HDMI_AUD_CHAN_TYPE_4_0_CLRS,
- HDMI_AUD_CHAN_TYPE_4_1_CLRS,
- HDMI_AUD_CHAN_TYPE_6_1_CS,
- HDMI_AUD_CHAN_TYPE_6_1_CH,
- HDMI_AUD_CHAN_TYPE_6_1_OH,
- HDMI_AUD_CHAN_TYPE_6_1_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
- HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
- HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
- HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
- HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
- HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
- HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
- HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
- HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
- HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_6_0_CS,
- HDMI_AUD_CHAN_TYPE_6_0_CH,
- HDMI_AUD_CHAN_TYPE_6_0_OH,
- HDMI_AUD_CHAN_TYPE_6_0_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
- HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
- HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
- HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
- HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
- HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
- HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
- HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
- HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
- HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
- HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
-};
-
-enum hdmi_aud_channel_swap_type {
- HDMI_AUD_SWAP_LR,
- HDMI_AUD_SWAP_LFE_CC,
- HDMI_AUD_SWAP_LSRS,
- HDMI_AUD_SWAP_RLS_RRS,
- HDMI_AUD_SWAP_LR_STATUS,
-};
-
-struct hdmi_audio_param {
- enum hdmi_audio_coding_type aud_codec;
- enum hdmi_audio_sample_size aud_sampe_size;
- enum hdmi_aud_input_type aud_input_type;
- enum hdmi_aud_i2s_fmt aud_i2s_fmt;
- enum hdmi_aud_mclk aud_mclk;
- enum hdmi_aud_channel_type aud_input_chan_type;
- struct hdmi_codec_params codec_params;
-};
-
-struct mtk_hdmi_conf {
- bool tz_disabled;
- bool cea_modes_only;
- unsigned long max_mode_clock;
-};
-
-struct mtk_hdmi {
- struct drm_bridge bridge;
- struct drm_bridge *next_bridge;
- struct drm_connector
[PATCH v1 15/17] dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT8195
Add dt-binding documentation of dpi for MediaTek MT8195 SoC. Signed-off-by: Guillaume Ranquet diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 5bb23e97cf33..2c7ecef54986 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dpi - mediatek,mt8195-dp-intf reg: -- b4 0.10.0-dev
[PATCH v1 05/17] drm/mediatek: hdmi: use a syscon/regmap instead of iomem
To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, move to a syscon.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 3196189429bc..5cd05d4fe1a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -172,7 +172,7 @@ struct mtk_hdmi {
u32 ibias_up;
struct regmap *sys_regmap;
unsigned int sys_offset;
- void __iomem *regs;
+ struct regmap *regs;
enum hdmi_colorspace csp;
struct hdmi_audio_param aud_param;
bool audio_enable;
@@ -188,44 +188,29 @@ static inline struct mtk_hdmi
*hdmi_ctx_from_bridge(struct drm_bridge *b)
return container_of(b, struct mtk_hdmi, bridge);
}
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
{
- return readl(hdmi->regs + offset);
+ return regmap_read(hdmi->regs, offset, val);
}
static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
{
- writel(val, hdmi->regs + offset);
+ regmap_write(hdmi->regs, offset, val);
}
static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~bits;
- writel(tmp, reg);
+ regmap_clear_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp |= bits;
- writel(tmp, reg);
+ regmap_set_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, reg);
+ regmap_update_bits(hdmi->regs, offset, mask, val);
}
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -474,7 +459,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi
*hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG0);
+ mtk_hdmi_read(hdmi, GRL_CFG0, );
val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
switch (i2s_fmt) {
@@ -566,7 +551,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi
*hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG1);
+ mtk_hdmi_read(hdmi, GRL_CFG1, );
if (input_type == HDMI_AUD_INPUT_I2S &&
(val & CFG1_SPDIF) == CFG1_SPDIF) {
val &= ~CFG1_SPDIF;
@@ -597,7 +582,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi
*hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, );
if (val & MIX_CTRL_SRC_EN) {
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -611,7 +596,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi
*hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, );
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -622,7 +607,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG5);
+ mtk_hdmi_read(hdmi, GRL_CFG5, );
val &= CFG5_CD_RATIO_MASK;
switch (mclk) {
@@ -1428,7 +1413,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
struct device_node *cec_np, *remote, *i2c_np;
struct platform_device *cec_pdev;
struct regmap *regmap;
- struct resource *mem;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1474,8 +1458,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
hdmi->sys_regmap = regmap;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hdmi->regs = devm_ioremap_resource(dev, mem);
+ hdmi->regs = syscon_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs)) {
ret = PTR_ERR(hdmi->regs);
goto put_device;
--
b4 0.10.0-dev
[PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings
Add mt8195 SoC bindings for hdmi and hdmi-ddc
Make port1 optional for mt8195 as it only supports HDMI tx for now.
Requires a ddc-i2c-bus phandle.
Requires a power-domains phandle.
Signed-off-by: Guillaume Ranquet
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
index bdaf0b51e68c..abb231a0694b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
@@ -21,6 +21,10 @@ properties:
- mediatek,mt7623-hdmi
- mediatek,mt8167-hdmi
- mediatek,mt8173-hdmi
+ - mediatek,mt8195-hdmi
+
+ clocks: true
+ clock-names: true
reg:
maxItems: 1
@@ -28,20 +32,6 @@ properties:
interrupts:
maxItems: 1
- clocks:
-items:
- - description: Pixel Clock
- - description: HDMI PLL
- - description: Bit Clock
- - description: S/PDIF Clock
-
- clock-names:
-items:
- - const: pixel
- - const: pll
- - const: bclk
- - const: spdif
-
phys:
maxItems: 1
@@ -58,6 +48,16 @@ properties:
description: |
phandle link and register offset to the system configuration registers.
+ ddc-i2c-bus:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: Phandle to the ddc-i2c device
+
+ power-domains:
+description:
+ A phandle and PM domain specifier as defined by bindings
+ of the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -76,7 +76,6 @@ properties:
required:
- port@0
- - port@1
required:
- compatible
@@ -86,9 +85,55 @@ required:
- clock-names
- phys
- phy-names
- - mediatek,syscon-hdmi
- ports
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8195-hdmi
+then:
+ properties:
+clocks:
+ items:
+- description: APB
+- description: HDCP
+- description: HDCP 24M
+- description: Split HDMI
+clock-names:
+ items:
+- const: hdmi_apb_sel
+- const: hdcp_sel
+- const: hdcp24_sel
+- const: split_hdmi
+
+ required:
+- power-domains
+- ddc-i2c-bus
+else:
+ properties:
+clocks:
+ items:
+- description: Pixel Clock
+- description: HDMI PLL
+- description: Bit Clock
+- description: S/PDIF Clock
+
+clock-names:
+ items:
+- const: pixel
+- const: pll
+- const: bclk
+- const: spdif
+
+ports:
+ required:
+- port@1
+
+ required:
+- mediatek,syscon-hdmi
+
additionalProperties: false
examples:
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
new file mode 100644
index ..3c80bcebe6d3
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI DDC Device Tree Bindings for mt8195
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+
+description: |
+ The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt8195-hdmi-ddc
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+items:
+ - const: ddc-i2c
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+hdmiddc0: ddc_i2c {
+ compatible = "mediatek,mt8195-hdmi-ddc";
+ clocks = <>;
+ clock-names = "ddc-i2c";
+};
+
+...
--
b4 0.10.0-dev
[PATCH v1 03/17] dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible
Add a compatible for the HDMI PHY on MT8195 Signed-off-by: Guillaume Ranquet diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml index 0d94950b84ca..71c75a11e189 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml @@ -28,6 +28,7 @@ properties: - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt8173-hdmi-phy + - const: mediatek,mt8195-hdmi-phy reg: maxItems: 1 -- b4 0.10.0-dev
[PATCH v1 09/17] drm/mediatek: hdmi: add connector flag
Add a flag to indicate support for an external connector
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 86653ebaacfd..30407603d693 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -199,20 +199,22 @@ int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct
platform_device *pdev,
goto put_device;
}
- remote = of_graph_get_remote_node(np, 1, 0);
- if (!remote) {
- ret = -EINVAL;
- goto put_device;
- }
-
- if (!of_device_is_compatible(remote, "hdmi-connector")) {
- hdmi->next_bridge = of_drm_find_bridge(remote);
- if (!hdmi->next_bridge) {
- dev_err(dev, "Waiting for external bridge\n");
- of_node_put(remote);
- ret = -EPROBE_DEFER;
+ if (hdmi->conf->has_connector) {
+ remote = of_graph_get_remote_node(np, 1, 0);
+ if (!remote) {
+ ret = -EINVAL;
goto put_device;
}
+
+ if (!of_device_is_compatible(remote, "hdmi-connector")) {
+ hdmi->next_bridge = of_drm_find_bridge(remote);
+ if (!hdmi->next_bridge) {
+ dev_err(dev, "Waiting for external bridge\n");
+ of_node_put(remote);
+ ret = -EPROBE_DEFER;
+ goto put_device;
+ }
+ }
}
i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
@@ -325,6 +327,7 @@ int mtk_drm_hdmi_remove(struct platform_device *pdev)
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
.tz_disabled = true,
.has_cec = true,
+ .has_connector = true,
.bridge_funcs = _mt8183_hdmi_bridge_funcs,
.mtk_hdmi_output_init = mtk_hdmi_output_init_mt8183,
.mtk_hdmi_clk_disable = mtk_hdmi_clk_disable_audio_mt8183,
@@ -338,6 +341,7 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
.max_mode_clock = 148500,
.cea_modes_only = true,
.has_cec = true,
+ .has_connector = true,
.bridge_funcs = _mt8183_hdmi_bridge_funcs,
.mtk_hdmi_output_init = mtk_hdmi_output_init_mt8183,
.mtk_hdmi_clk_disable = mtk_hdmi_clk_disable_audio_mt8183,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
index 921bde150e11..62a14435be69 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -32,6 +32,7 @@ struct mtk_hdmi_conf {
bool tz_disabled;
bool cea_modes_only;
bool has_cec;
+ bool has_connector;
unsigned long max_mode_clock;
const struct drm_bridge_funcs *bridge_funcs;
void (*mtk_hdmi_output_init)(struct mtk_hdmi *hdmi);
--
b4 0.10.0-dev
[PATCH v1 02/17] clk: mediatek: add VDOSYS1 clock
From: Pablo Sun
Add the clock gate definition for the DPI1 hardware
in VDOSYS1.
The parent clock "hdmi_txpll" is already defined in
`mt8195.dtsi`.
Signed-off-by: Pablo Sun
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c
b/drivers/clk/mediatek/clk-mt8195-vdo1.c
index d54d7726d186..835335b9d87b 100644
--- a/drivers/clk/mediatek/clk-mt8195-vdo1.c
+++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c
@@ -34,6 +34,12 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = {
.sta_ofs = 0x140,
};
+static const struct mtk_gate_regs vdo1_4_cg_regs = {
+ .set_ofs = 0x400,
+ .clr_ofs = 0x400,
+ .sta_ofs = 0x400,
+};
+
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, _0_cg_regs, _shift,
_clk_gate_ops_setclr)
@@ -50,6 +56,9 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = {
#define GATE_VDO1_3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, _3_cg_regs, _shift,
_clk_gate_ops_setclr)
+#define GATE_VDO1_4(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, _4_cg_regs, _shift,
_clk_gate_ops_no_setclr_inv)
+
static const struct mtk_gate vdo1_clks[] = {
/* VDO1_0 */
GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
@@ -107,6 +116,8 @@ static const struct mtk_gate vdo1_clks[] = {
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf",
"top_vpp", 17),
/* VDO1_3 */
GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
+ /* VDO1_4 */
+ GATE_VDO1_4(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0),
};
static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
--
b4 0.10.0-dev
[PATCH v1 01/17] dt-bindings: clk: mediatek: Add MT8195 DPI clocks
From: Pablo Sun Expand dt-bindings slot for VDOSYS1 of MT8195. This clock is required by the DPI1 hardware and is a downstream of the HDMI pixel clock. Signed-off-by: Pablo Sun Signed-off-by: Guillaume Ranquet Reviewed-by: Mattijs Korpershoek diff --git a/include/dt-bindings/clock/mt8195-clk.h b/include/dt-bindings/clock/mt8195-clk.h index 95cf812a0b37..d70d017ad69c 100644 --- a/include/dt-bindings/clock/mt8195-clk.h +++ b/include/dt-bindings/clock/mt8195-clk.h @@ -859,6 +859,8 @@ #define CLK_VDO1_DPINTF47 #define CLK_VDO1_DISP_MONITOR_DPINTF 48 #define CLK_VDO1_26M_SLOW 49 -#define CLK_VDO1_NR_CLK50 +#define CLK_VDO1_DPI1_HDMI 50 +#define CLK_VDO1_NR_CLK51 + #endif /* _DT_BINDINGS_CLK_MT8195_H */ -- b4 0.10.0-dev
[PATCH v1 00/17] Add MT8195 HDMI support
Add support for HDMI Tx on MT8195. This includes a split of the current "legacy" hdmi driver into a common library of functions and a two dedicated compilation units with specific code for mt8167 and another for the "new" mt8195 SoC. Support for the new mt8195 hdmi phy and the dpi/drm_drv adjustements to support hdmi. Based on next-20220919 Signed-off-by: Guillaume Ranquet --- Guillaume Ranquet (15): dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible dt-bindings: display: mediatek: add MT8195 hdmi bindings drm/mediatek: hdmi: use a syscon/regmap instead of iomem dt-bindings: mediatek: set the hdmi to be compatible with syscon drm/mediatek: extract common functions from the mtk hdmi driver drm/mediatek: hdmi: add cec flag drm/mediatek: hdmi: add connector flag drm/mediatek: hdmi: add frame_colorimetry flag drm/mediatek: hdmi: add mt8195 support drm/mediatek: hdmi: mt8195: add audio support phy: phy-mtk-hdmi: Add generic phy configure callback phy: mediatek: add support for phy-mtk-hdmi-mt8195 dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT8195 drm/mediatek: dpi: Add mt8195 hdmi to DPI driver drm/mediatek: Add mt8195-dpi support to drm_drv Pablo Sun (2): dt-bindings: clk: mediatek: Add MT8195 DPI clocks clk: mediatek: add VDOSYS1 clock .../bindings/display/mediatek/mediatek,dpi.yaml|1 + .../bindings/display/mediatek/mediatek,hdmi.yaml | 91 +- .../display/mediatek/mediatek,mt8195-hdmi-ddc.yaml | 45 + .../devicetree/bindings/phy/mediatek,hdmi-phy.yaml |1 + arch/arm64/boot/dts/mediatek/mt8173.dtsi |2 +- drivers/clk/mediatek/clk-mt8195-vdo1.c | 11 + drivers/gpu/drm/mediatek/Makefile |5 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 143 +- drivers/gpu/drm/mediatek/mtk_dpi_regs.h|5 + drivers/gpu/drm/mediatek/mtk_drm_drv.c |2 + drivers/gpu/drm/mediatek/mtk_hdmi.c| 647 +--- drivers/gpu/drm/mediatek/mtk_hdmi.h| 16 + drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 477 ++ drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 225 +++ drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c | 1602 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.h | 31 + drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.c | 539 +++ drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_regs.h| 329 drivers/phy/mediatek/Makefile |1 + drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 673 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h | 204 +++ drivers/phy/mediatek/phy-mtk-hdmi.c| 15 + drivers/phy/mediatek/phy-mtk-hdmi.h|2 + include/dt-bindings/clock/mt8195-clk.h |4 +- 24 files changed, 4429 insertions(+), 642 deletions(-) --- base-commit: ec65813678c97a05766d29f1ec40bdf1b30bc3d6 change-id: 20220919-hdmi_mtk Best regards, -- Guillaume Ranquet
Re: [PATCH v7 2/2] drm: rcar-du: Add RZ/G2L DSI driver
Hi Biju,
Thank you for the patch.
On Fri, Sep 16, 2022 at 09:48:07AM +0100, Biju Das wrote:
> This driver supports the MIPI DSI encoder found in the RZ/G2L
> SoC. It currently supports DSI video mode only.
>
> Signed-off-by: Biju Das
> Acked-by: Sam Ravnborg
> ---
> v6->v7:
> * Added rzg2l_mipi_dsi_stop_video() counterpart of
> rzg2l_mipi_dsi_start_video().
> * Error labels are named according to the cleanup operation they perform.
> * Restored Max lane capability read after dphy timing initialization
>as per the guide lines from SoC design team.
> * Added recommended lut values for the Global Operation Timing
>parameters for MIPI DPHY.
> v5->v6:
> * Updated commit description
> * Moved handling of arst and prst from rzg2l_mipi_dsi_startup->runtime
>PM suspend/resume handlers.
> * Max lane capability read at probe(), and enforced in
>rzg2l_mipi_dsi_host_attach()
> * Simplified vich1ppsetr setting.
> * Renamed hsclk_running_mode,hsclk_mode->is_clk_cont.
> * Fixed typo in probe error message(arst->rst).
> * Reordered DRM bridge initaization in probe()
> * Updated typo in e-mail address.
> v4->v5:
> * Added Ack from Sam.
> * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
>with drm_of_get_data_lanes_count_ep() in probe.
> v3->v4:
> * Updated error handling in rzg2l_mipi_dsi_startup() and
> rzg2l_mipi_dsi_atomic_enable()
> v2->v3:
> * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
>of the memory pointer
> * Fixed the comment in rzg2l_mipi_dsi_startup()
> * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
> * DRM bridge parameter initialization moved to probe
> * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
> * Inserted the missing blank lane after return in probe()
> * Added missing MODULE_DEVICE_TABLE
> * Added include linux/bits.h in header file
> * Fixed various macros in header file.
> * Reorder the make file for DSI, so that it is no more dependent
>on RZ/G2L DU patch series.
> v1->v2:
> * Rework based on dt-binding change (DSI + D-PHY) as single block
> * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
> * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
>and rzg2l_mipi_dsi_link_write
> * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> RFC->v1:
> * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
>and dropped DRM as it is implied by DRM_BRIDGE
> * Used devm_reset_control_get_exclusive() for reset handle
> * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> * Added error check for pm, using pm_runtime_resume_and_get() instead of
>pm_runtime_get_sync()
> * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
> * Avoided read-modify-write stopping hsclock
> * Used devm_platform_ioremap_resource for resource allocation
> * Removed unnecessary assert call from probe and remove.
> * wrap the line after the PTR_ERR() in probe()
> * Updated reset failure messages in probe
> * Fixed the typo arstc->prstc
> * Made hex constants to lower case.
> RFC:
> *
> https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/
> ---
> drivers/gpu/drm/rcar-du/Kconfig | 8 +
> drivers/gpu/drm/rcar-du/Makefile | 2 +
> drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c | 782 ++
> drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151
> 4 files changed, 943 insertions(+)
> create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
>
> diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
> index c959e8c6be7d..58ffb8c2443b 100644
> --- a/drivers/gpu/drm/rcar-du/Kconfig
> +++ b/drivers/gpu/drm/rcar-du/Kconfig
> @@ -51,6 +51,14 @@ config DRM_RCAR_MIPI_DSI
> help
> Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
>
> +config DRM_RZG2L_MIPI_DSI
> + tristate "RZ/G2L MIPI DSI Encoder Support"
> + depends on DRM_BRIDGE && OF
> + depends on ARCH_RENESAS || COMPILE_TEST
> + select DRM_MIPI_DSI
> + help
> + Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders.
> +
> config DRM_RCAR_VSP
> bool "R-Car DU VSP Compositor Support" if ARM
> default y if ARM64
> diff --git a/drivers/gpu/drm/rcar-du/Makefile
> b/drivers/gpu/drm/rcar-du/Makefile
> index 6f132325c8b7..b8f2c82651d9 100644
> --- a/drivers/gpu/drm/rcar-du/Makefile
> +++ b/drivers/gpu/drm/rcar-du/Makefile
> @@ -14,3 +14,5 @@ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o
> obj-$(CONFIG_DRM_RCAR_DW_HDMI) += rcar_dw_hdmi.o
> obj-$(CONFIG_DRM_RCAR_LVDS) += rcar_lvds.o
> obj-$(CONFIG_DRM_RCAR_MIPI_DSI) += rcar_mipi_dsi.o
> +
> +obj-$(CONFIG_DRM_RZG2L_MIPI_DSI) += rzg2l_mipi_dsi.o
> diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
>
Re: [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Modify CAGF functions for MTL
Hi Badal,
On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> Updated the CAGF functions to get actual resolved frequency of
> 3D and SAMedia
can you please use the imperative form? "Update" and not
"Updated".
Besides I don't really understand what you did from the
commit, can you please bea bit more descriptive?
> Bspec: 66300
>
> Cc: Vinay Belgaumkar
> Cc: Ashutosh Dixit
> Signed-off-by: Badal Nilawar
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 2275ee47da95..7819d32db956 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1510,6 +1510,14 @@
> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
>
> +/*
> + * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
> + * 3D - 0x0C60 , SAMedia - 0x380C60
> + * Intel uncore handler redirects transactions for SAMedia to
> MTL_MEDIA_GSI_BASE
> + */
This comment is not understandable... we don't have limits in
space, you can be a bit more explicit :)
Andi
> +#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
> +#define MTL_CAGF_MASKREG_GENMASK(8, 0)
> +
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> #define GEN11_GUNIT(28)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 17b40b625e31..c2349949ebae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2075,6 +2075,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32
> rpstat)
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> cagf = (rpstat >> 8) & 0xff;
> + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + cagf = rpstat & MTL_CAGF_MASK;
> else if (GRAPHICS_VER(i915) >= 9)
> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> @@ -2098,7 +2100,9 @@ static u32 read_cagf(struct intel_rps *rps)
> vlv_punit_get(i915);
> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> vlv_punit_put(i915);
> - } else if (GRAPHICS_VER(i915) >= 6) {
> + } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + freq = intel_uncore_read(rps_to_gt(rps)->uncore,
> MTL_MIRROR_TARGET_WP1);
> + else if (GRAPHICS_VER(i915) >= 6) {
> freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> } else {
> freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> --
> 2.25.1
Re: [PATCH] drm/amdgpu: use dirty framebuffer helper
On Sun, Sep 18, 2022 at 8:09 AM root wrote:
>
> Hi, I recently experienced lock-ups that only responded to magic sysreq
> reboots when the amdgpu module was loading on my pc (Athlon II X4 640 CPU,
> with Radeon R7 250 - Cape Verde).
>
> .config has:
>
> CONFIG_DRM_AMDGPU=m
> CONFIG_DRM_AMDGPU_SI=y
> # CONFIG_DRM_AMDGPU_CIK is not set
> # CONFIG_DRM_AMDGPU_USERPTR is not set
>
> kernel command line has:
>
> amdgpu.audio=1 amdgpu.si_support=1 radeon.si_support=0 page_owner=on \
> amdgpu.gpu_recovery=1
>
> Bisecting lead to:
>
> commit 66f99628eb24409cb8feb5061f78283c8b65f820
> Author: Hamza Mahfooz
> Date: Tue Sep 6 15:01:49 2022 -0400
>
> drm/amdgpu: use dirty framebuffer helper
>
> Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
> drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
> struct.
>
> Signed-off-by: Hamza Mahfooz
> Acked-by: Alex Deucher
> Signed-off-by: Alex Deucher
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index c20922a5af9f..5b09c8f4fe95 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -38,6 +38,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -496,6 +497,7 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector
> *amdgpu_connector,
> static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
> .destroy = drm_gem_fb_destroy,
> .create_handle = drm_gem_fb_create_handle,
> + .dirty = drm_atomic_helper_dirtyfb,
> };
>
> uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>
> After doing a git bisect reset, git pull and reverting the patch above, I
> rebuilt the kernel and am successfully running with the amdgpu module loaded
> and using the Radeon R7 250 GPU.
>
> I am happy to supply any further configuration details.
Does the attached patch help?
Alex
>
> Arthur Marsh.
From 5e49c68c1ac1fbb98b1c84407485abfb7d309783 Mon Sep 17 00:00:00 2001
From: Alex Deucher
Date: Mon, 19 Sep 2022 12:26:20 -0400
Subject: [PATCH] drm/amdgpu: don't register a dirty callback for non-atomic
Some asics still support non-atomic code paths.
Fixes: 66f99628eb2440 ("drm/amdgpu: use dirty framebuffer helper")
Reported-by: Arthur Marsh
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 5b09c8f4fe95..23998f727c7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -39,6 +39,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -497,6 +498,11 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
.destroy = drm_gem_fb_destroy,
.create_handle = drm_gem_fb_create_handle,
+};
+
+static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
+ .destroy = drm_gem_fb_destroy,
+ .create_handle = drm_gem_fb_create_handle,
.dirty = drm_atomic_helper_dirtyfb,
};
@@ -1102,7 +1108,10 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
if (ret)
goto err;
- ret = drm_framebuffer_init(dev, >base, _fb_funcs);
+ if (drm_drv_uses_atomic_modeset(dev))
+ ret = drm_framebuffer_init(dev, >base, _fb_funcs_atomic);
+ else
+ ret = drm_framebuffer_init(dev, >base, _fb_funcs);
if (ret)
goto err;
--
2.37.3
RE: [PATCH] gpu: color: eliminate implicit conversion about enum type
[AMD Official Use Only - General]
> I think the proper fix is to set it to:
> build_coefficients(, TRANSFER_FUNCTION_SRGB);
I agree, default arg should be TRANSFER_FUNCTION_SRGB.
Even though it's a change in behaviour, previous behaviour was wrong.
Ideally it would be based on input TF, but afaik on both Linux and Win there's
no current case where this is not sRGB.
Thanks,
Kruno
-Original Message-
From: Alex Deucher
Sent: Monday, September 19, 2022 12:07 PM
To: Zeng Heng ; Chung, Jaehyun ;
Kovac, Krunoslav
Cc: Wentland, Harry ; Li, Sun peng (Leo)
; Siqueira, Rodrigo ; Deucher,
Alexander ; Koenig, Christian
; Pan, Xinhui ; airl...@linux.ie;
dan...@ffwll.ch; Kotarac, Pavle ; Liu, HaoPing (Alan)
; Wang, Sherry ;
weiyongj...@huawei.com; liwei...@huawei.com; dri-devel@lists.freedesktop.org;
amd-...@lists.freedesktop.org
Subject: Re: [PATCH] gpu: color: eliminate implicit conversion about enum type
Add the relevant AMD developers to comment.
On Mon, Sep 19, 2022 at 12:05 PM Alex Deucher wrote:
>
> On Mon, Sep 19, 2022 at 3:19 AM Zeng Heng wrote:
> >
> > Fix below compile warning when open enum-conversion option check:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:
> > In function ‘apply_degamma_for_user_regamma’:
> > drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:1695:29:
> > error: implicit conversion from ‘enum ’ to ‘enum
> > dc_transfer_func_predefined’ [-Werror=enum-conversion]
> > 1695 | build_coefficients(, true);
> > | ^~~~
> >
> > As 'build_coefficients' definition, it needs enum
> > 'dc_transfer_func_predefined' type acts as the second argument,
> > instead of bool-type one.
> >
> > The numerical values of TRANSFER_FUNCTION_BT709 & true happen to be
> > the same, so there is no change in behavior.
>
> This looks like a regression from:
>
> commit 9b3d76527f6ea50270f7f7ac749493b41783e8bd
> Author: Jaehyun Chung
> Date: Mon Aug 30 16:46:42 2021 -0400
>
> drm/amd/display: Revert adding degamma coefficients
>
> [Why]
> Degamma coefficients are calculated in our degamma formula using
> the regamma coefficients. We do not need to add separate degamma
> coefficients.
>
> [How]
> Remove the change to add separate degamma coefficients.
>
> Reviewed-by: Krunoslav Kovac
> Acked-by: Mikita Lipski
> Signed-off-by: Jaehyun Chung
> Tested-by: Daniel Wheeler
> Signed-off-by: Alex Deucher
>
> Which seems to improperly revert:
> commit d020970959169627d59a711769f8c4b87bf5f90c
> Author: Jaehyun Chung
> Date: Tue Aug 24 14:05:48 2021 -0400
>
> drm/amd/display: Add regamma/degamma coefficients and set sRGB
> when TF is BT709
>
> [Why]
> In YUV case, need to set the input TF to sRGB instead of BT709,
> even though the input TF type is distributed. SRGB was not
> being used because pixel format was not being set in the
> surface update sequence.
> Also, we were using the same coefficients for degamma and
> regamma formula, causing the cutoff point of the linear
> section of the curve to be incorrect.
>
> [How]
> Set pixel format in the surface update sequence. Add separate
> coefficient arrays for regamma and degamma.
>
> Reviewed-by: Krunoslav Kovac
> Acked-by: Mikita Lipski
> Signed-off-by: Jaehyun Chung
> Tested-by: Daniel Wheeler
> Signed-off-by: Alex Deucher
>
> I think the proper fix is to set it to:
> build_coefficients(, TRANSFER_FUNCTION_SRGB);
>
> Alex
>
> >
> > Signed-off-by: Zeng Heng
> > ---
> > drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > index 04f7656906ca..2f807d787c77 100644
> > --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > @@ -1692,7 +1692,7 @@ static void apply_degamma_for_user_regamma(struct
> > pwl_float_data_ex *rgb_regamma
> > struct pwl_float_data_ex *rgb = rgb_regamma;
> > const struct hw_x_point *coord_x = coordinates_x;
> >
> > - build_coefficients(, true);
> > + build_coefficients(, TRANSFER_FUNCTION_BT709);
> >
> > i = 0;
> > while (i != hw_points_num + 1) {
> > --
> > 2.25.1
> >
Re: [PATCH] drm/amdgpu: use dirty framebuffer helper
On Mon, Sep 19, 2022 at 2:44 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 06.09.22 um 21:57 schrieb Hamza Mahfooz:
> > Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
> > drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
> > struct.
>
> drm_atomic_helper_dirtyfb() creates a new atomic commit for the
> frambuffer's planes. Drivers can then updates these planes' output
> (e.g., writeback to video memory). I thought that amdgpu simply scans
> out from the framebuffer's memory regions in VRAM. So I'm curious why
> this patch is necessary.
I think in this particular case, the problem is that there are still
some asic which default to non-atomic code which is what is causing
the problem here. Something like this would fix that:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 5b09c8f4fe95..f5e9dd454c54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -497,6 +497,11 @@ bool amdgpu_display_ddc_probe(struct
amdgpu_connector *amdgpu_connector,
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
.destroy = drm_gem_fb_destroy,
.create_handle = drm_gem_fb_create_handle,
+};
+
+static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
+ .destroy = drm_gem_fb_destroy,
+ .create_handle = drm_gem_fb_create_handle,
.dirty = drm_atomic_helper_dirtyfb,
};
@@ -1102,7 +1107,10 @@ static int
amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
if (ret)
goto err;
- ret = drm_framebuffer_init(dev, >base, _fb_funcs);
+ if (drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
+ ret = drm_framebuffer_init(dev, >base,
_fb_funcs_atomic);
+ else
+ ret = drm_framebuffer_init(dev, >base, _fb_funcs);
if (ret)
goto err;
As for why we need the dirty callback, I think it's used for PSR.
Alex
>
> Best regards
> Thomas
>
> >
> > Signed-off-by: Hamza Mahfooz
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index c20922a5af9f..5b09c8f4fe95 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -38,6 +38,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -496,6 +497,7 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector
> > *amdgpu_connector,
> > static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
> > .destroy = drm_gem_fb_destroy,
> > .create_handle = drm_gem_fb_create_handle,
> > + .dirty = drm_atomic_helper_dirtyfb,
> > };
> >
> > uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>
> --
> Thomas Zimmermann
> Graphics Driver Developer
> SUSE Software Solutions Germany GmbH
> Maxfeldstr. 5, 90409 Nürnberg, Germany
> (HRB 36809, AG Nürnberg)
> Geschäftsführer: Ivo Totev
[PATCH] drm/i915: Perf_limit_reasons are only available for Gen11+
Register GT0_PERF_LIMIT_REASONS (0x1381a8) is available only for
Gen11+. Therefore ensure perf_limit_reasons sysfs/debugfs files are created
only for Gen11+. Otherwise on Gen < 5 accessing these files results in the
following oops:
<1> [88.829420] BUG: unable to handle page fault for address: c9bb81a8
<1> [88.829438] #PF: supervisor read access in kernel mode
<1> [88.829447] #PF: error_code(0x) - not-present page
Bspec: 20008
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/6863
Fixes: fe5979665f64 ("drm/i915/debugfs: Add perf_limit_reasons in debugfs")
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt.c| 4
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 10 +-
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 15 +++
3 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5ddae95d4886..b367cfff48d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -233,6 +233,10 @@ static void gen6_clear_engine_error_register(struct
intel_engine_cs *engine)
i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
{
+ /* GT0_PERF_LIMIT_REASONS is available only for Gen11+ */
+ if (GRAPHICS_VER(gt->i915) < 11)
+ return INVALID_MMIO_REG;
+
return gt->type == GT_MEDIA ?
MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 68310881a793..10f680dbd7b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -682,6 +682,14 @@ static int perf_limit_reasons_clear(void *data, u64 val)
return 0;
}
+
+static bool perf_limit_reasons_eval(void *data)
+{
+ struct intel_gt *gt = data;
+
+ return i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt));
+}
+
DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
perf_limit_reasons_clear, "%llu\n");
@@ -694,7 +702,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt,
struct dentry *root)
{ "forcewake_user", _user_fops, NULL},
{ "llc", _fops, llc_eval },
{ "rps_boost", _boost_fops, rps_eval },
- { "perf_limit_reasons", _limit_reasons_fops, NULL },
+ { "perf_limit_reasons", _limit_reasons_fops,
perf_limit_reasons_eval },
};
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 54deae45d81f..904160952369 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -545,8 +545,7 @@ static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl,
RATL_MASK);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert,
VR_THERMALERT_MASK);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
-static const struct attribute *freq_attrs[] = {
- _attr_punit_req_freq_mhz.attr,
+static const struct attribute *throttle_reason_attrs[] = {
_throttle_reason_status.attr,
_throttle_reason_pl1.attr,
_throttle_reason_pl2.attr,
@@ -791,12 +790,20 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct
kobject *kobj)
if (!is_object_gt(kobj))
return;
- ret = sysfs_create_files(kobj, freq_attrs);
+ ret = sysfs_create_file(kobj, _attr_punit_req_freq_mhz.attr);
if (ret)
drm_warn(>i915->drm,
-"failed to create gt%u throttle sysfs files (%pe)",
+"failed to create gt%u punit_req_freq_mhz sysfs (%pe)",
gt->info.id, ERR_PTR(ret));
+ if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
+ ret = sysfs_create_files(kobj, throttle_reason_attrs);
+ if (ret)
+ drm_warn(>i915->drm,
+"failed to create gt%u throttle sysfs files
(%pe)",
+gt->info.id, ERR_PTR(ret));
+ }
+
if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(>uc)) {
ret = sysfs_create_files(kobj, media_perf_power_attrs);
if (ret)
--
2.34.1
Re: [PATCH v3 0/2] drm/i915/gem: Really move i915_gem_context.link under ref protection
Pushed, Thanks! Andi On Fri, Sep 16, 2022 at 11:24:01AM +0200, Janusz Krzysztofik wrote: > i915_perf assumes that it can use the i915_gem_context reference to > protect its i915->gem.contexts.list iteration. However, this requires > that we do not remove the context from the list until after we drop the > final reference and release the struct. If, as currently, we remove the > context from the list during context_close(), the link.next pointer may > be poisoned while we are holding the context reference and cause a GPF: > > [ 4070.573157] i915 :00:02.0: [drm:i915_perf_open_ioctl [i915]] filtering > on ctx_id=0x > 1f ctx_id_mask=0x1f > [ 4070.574881] general protection fault, probably for non-canonical address > 0xdead > 0100: [#1] PREEMPT SMP > [ 4070.574897] CPU: 1 PID: 284392 Comm: amd_performance Tainted: G > E 5.17.9 > #180 > [ 4070.574903] Hardware name: Intel Corporation NUC7i5BNK/NUC7i5BNB, BIOS > BNKBL357.86A.0052.2017.0918.1346 09/18/2017 > [ 4070.574907] RIP: 0010:oa_configure_all_contexts.isra.0+0x222/0x350 [i915] > [ 4070.574982] Code: 08 e8 32 6e 10 e1 4d 8b 6d 50 b8 ff ff ff ff 49 83 ed 50 > f0 41 0f c1 04 24 83 f8 01 0f 84 e3 00 00 00 85 c0 0f 8e fa 00 00 00 <49> 8b > 45 50 48 8d 70 b0 49 8d 45 50 48 39 44 24 10 0f 85 34 fe ff > [ 4070.574990] RSP: 0018:c90002077b78 EFLAGS: 00010202 > [ 4070.574995] RAX: 0002 RBX: 0002 RCX: > > [ 4070.575000] RDX: 0001 RSI: c90002077b20 RDI: > 88810ddc7c68 > [ 4070.575004] RBP: 0001 R08: 888103242648 R09: > fffc > [ 4070.575008] R10: 82c50bc0 R11: 00025c80 R12: > 888101bf1860 > [ 4070.575012] R13: dead00b0 R14: c90002077c04 R15: > 88810be5cabc > [ 4070.575016] FS: 7f1ed50c0780() GS:5ec8() > knlGS: > [ 4070.575021] CS: 0010 DS: ES: CR0: 80050033 > [ 4070.575025] CR2: 7f1ed5590280 CR3: 00010ef6f005 CR4: > 003706e0 > [ 4070.575029] Call Trace: > [ 4070.575033] > [ 4070.575037] lrc_configure_all_contexts+0x13e/0x150 [i915] > [ 4070.575103] gen8_enable_metric_set+0x4d/0x90 [i915] > [ 4070.575164] i915_perf_open_ioctl+0xbc0/0x1500 [i915] > [ 4070.575224] ? asm_common_interrupt+0x1e/0x40 > [ 4070.575232] ? i915_oa_init_reg_state+0x110/0x110 [i915] > [ 4070.575290] drm_ioctl_kernel+0x85/0x110 > [ 4070.575296] ? update_load_avg+0x5f/0x5e0 > [ 4070.575302] drm_ioctl+0x1d3/0x370 > [ 4070.575307] ? i915_oa_init_reg_state+0x110/0x110 [i915] > [ 4070.575382] ? gen8_gt_irq_handler+0x46/0x130 [i915] > [ 4070.575445] __x64_sys_ioctl+0x3c4/0x8d0 > [ 4070.575451] ? __do_softirq+0xaa/0x1d2 > [ 4070.575456] do_syscall_64+0x35/0x80 > [ 4070.575461] entry_SYSCALL_64_after_hwframe+0x44/0xae > [ 4070.575467] RIP: 0033:0x7f1ed5c10397 > [ 4070.575471] Code: 3c 1c e8 1c ff ff ff 85 c0 79 87 49 c7 c4 ff ff ff ff 5b > 5d 4c 89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d > 01 f0 ff ff 73 01 c3 48 8b 0d a9 da 0d 00 f7 d8 64 89 01 48 > [ 4070.575478] RSP: 002b:7ffd65c8d7a8 EFLAGS: 0246 ORIG_RAX: > 0010 > [ 4070.575484] RAX: ffda RBX: 0006 RCX: > 7f1ed5c10397 > [ 4070.575488] RDX: 7ffd65c8d7c0 RSI: 40106476 RDI: > 0006 > [ 4070.575492] RBP: 5620972f9c60 R08: 000a R09: > 0005 > [ 4070.575496] R10: 000d R11: 0246 R12: > 000a > [ 4070.575500] R13: 000d R14: R15: > 7ffd65c8d7c0 > [ 4070.575505] > [ 4070.575507] Modules linked in: nls_ascii(E) nls_cp437(E) vfat(E) fat(E) > i915(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) crct10dif_pclmul(E) > crc32_pclmul(E) crc32c_intel(E) aesni_intel(E) crypto_simd(E) intel_gtt(E) > cryptd(E) ttm(E) rapl(E) intel_cstate(E) drm_kms_helper(E) cfbfillrect(E) > syscopyarea(E) cfbimgblt(E) intel_uncore(E) sysfillrect(E) mei_me(E) > sysimgblt(E) i2c_i801(E) fb_sys_fops(E) mei(E) intel_pch_thermal(E) > i2c_smbus(E) cfbcopyarea(E) video(E) button(E) efivarfs(E) autofs4(E) > [ 4070.575549] ---[ end trace ]--- > > However, there is a risk of triggering kernel warning on contexts list not > empty at driver release time if we deleagate that task to a worker for > i915_gem_context_release_work(), unless that work is flushed first. > Unfortunately, it is not flushed on driver release. Fix it. > > Chris Wilson (1): > drm/i915/gem: Really move i915_gem_context.link under ref protection > > Janusz Krzysztofik (1): > drm/i915/gem: Flush contexts on driver release > > drivers/gpu/drm/i915/gem/i915_gem_context.c | 8 > drivers/gpu/drm/i915/i915_gem.c | 3 ++- > 2 files changed, 6 insertions(+), 5 deletions(-) > > -- > 2.25.1
Re: [PATCH] gpu: color: eliminate implicit conversion about enum type
Add the relevant AMD developers to comment.
On Mon, Sep 19, 2022 at 12:05 PM Alex Deucher wrote:
>
> On Mon, Sep 19, 2022 at 3:19 AM Zeng Heng wrote:
> >
> > Fix below compile warning when open enum-conversion
> > option check:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:
> > In function ‘apply_degamma_for_user_regamma’:
> > drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:1695:29:
> > error: implicit conversion from ‘enum ’ to ‘enum
> > dc_transfer_func_predefined’ [-Werror=enum-conversion]
> > 1695 | build_coefficients(, true);
> > | ^~~~
> >
> > As 'build_coefficients' definition, it needs enum
> > 'dc_transfer_func_predefined' type acts as the
> > second argument, instead of bool-type one.
> >
> > The numerical values of TRANSFER_FUNCTION_BT709 & true
> > happen to be the same, so there is no change in
> > behavior.
>
> This looks like a regression from:
>
> commit 9b3d76527f6ea50270f7f7ac749493b41783e8bd
> Author: Jaehyun Chung
> Date: Mon Aug 30 16:46:42 2021 -0400
>
> drm/amd/display: Revert adding degamma coefficients
>
> [Why]
> Degamma coefficients are calculated in our degamma formula using
> the regamma coefficients. We do not need to add separate degamma
> coefficients.
>
> [How]
> Remove the change to add separate degamma coefficients.
>
> Reviewed-by: Krunoslav Kovac
> Acked-by: Mikita Lipski
> Signed-off-by: Jaehyun Chung
> Tested-by: Daniel Wheeler
> Signed-off-by: Alex Deucher
>
> Which seems to improperly revert:
> commit d020970959169627d59a711769f8c4b87bf5f90c
> Author: Jaehyun Chung
> Date: Tue Aug 24 14:05:48 2021 -0400
>
> drm/amd/display: Add regamma/degamma coefficients and set sRGB
> when TF is BT709
>
> [Why]
> In YUV case, need to set the input TF to sRGB instead of BT709,
> even though the input TF type is distributed. SRGB was not
> being used because pixel format was not being set in the
> surface update sequence.
> Also, we were using the same coefficients for degamma and
> regamma formula, causing the cutoff point of the linear
> section of the curve to be incorrect.
>
> [How]
> Set pixel format in the surface update sequence. Add separate
> coefficient arrays for regamma and degamma.
>
> Reviewed-by: Krunoslav Kovac
> Acked-by: Mikita Lipski
> Signed-off-by: Jaehyun Chung
> Tested-by: Daniel Wheeler
> Signed-off-by: Alex Deucher
>
> I think the proper fix is to set it to:
> build_coefficients(, TRANSFER_FUNCTION_SRGB);
>
> Alex
>
> >
> > Signed-off-by: Zeng Heng
> > ---
> > drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > index 04f7656906ca..2f807d787c77 100644
> > --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> > @@ -1692,7 +1692,7 @@ static void apply_degamma_for_user_regamma(struct
> > pwl_float_data_ex *rgb_regamma
> > struct pwl_float_data_ex *rgb = rgb_regamma;
> > const struct hw_x_point *coord_x = coordinates_x;
> >
> > - build_coefficients(, true);
> > + build_coefficients(, TRANSFER_FUNCTION_BT709);
> >
> > i = 0;
> > while (i != hw_points_num + 1) {
> > --
> > 2.25.1
> >
Re: [PATCH] gpu: color: eliminate implicit conversion about enum type
On Mon, Sep 19, 2022 at 3:19 AM Zeng Heng wrote:
>
> Fix below compile warning when open enum-conversion
> option check:
>
> drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:
> In function ‘apply_degamma_for_user_regamma’:
> drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:1695:29:
> error: implicit conversion from ‘enum ’ to ‘enum
> dc_transfer_func_predefined’ [-Werror=enum-conversion]
> 1695 | build_coefficients(, true);
> | ^~~~
>
> As 'build_coefficients' definition, it needs enum
> 'dc_transfer_func_predefined' type acts as the
> second argument, instead of bool-type one.
>
> The numerical values of TRANSFER_FUNCTION_BT709 & true
> happen to be the same, so there is no change in
> behavior.
This looks like a regression from:
commit 9b3d76527f6ea50270f7f7ac749493b41783e8bd
Author: Jaehyun Chung
Date: Mon Aug 30 16:46:42 2021 -0400
drm/amd/display: Revert adding degamma coefficients
[Why]
Degamma coefficients are calculated in our degamma formula using
the regamma coefficients. We do not need to add separate degamma
coefficients.
[How]
Remove the change to add separate degamma coefficients.
Reviewed-by: Krunoslav Kovac
Acked-by: Mikita Lipski
Signed-off-by: Jaehyun Chung
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Which seems to improperly revert:
commit d020970959169627d59a711769f8c4b87bf5f90c
Author: Jaehyun Chung
Date: Tue Aug 24 14:05:48 2021 -0400
drm/amd/display: Add regamma/degamma coefficients and set sRGB
when TF is BT709
[Why]
In YUV case, need to set the input TF to sRGB instead of BT709,
even though the input TF type is distributed. SRGB was not
being used because pixel format was not being set in the
surface update sequence.
Also, we were using the same coefficients for degamma and
regamma formula, causing the cutoff point of the linear
section of the curve to be incorrect.
[How]
Set pixel format in the surface update sequence. Add separate
coefficient arrays for regamma and degamma.
Reviewed-by: Krunoslav Kovac
Acked-by: Mikita Lipski
Signed-off-by: Jaehyun Chung
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
I think the proper fix is to set it to:
build_coefficients(, TRANSFER_FUNCTION_SRGB);
Alex
>
> Signed-off-by: Zeng Heng
> ---
> drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> index 04f7656906ca..2f807d787c77 100644
> --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> @@ -1692,7 +1692,7 @@ static void apply_degamma_for_user_regamma(struct
> pwl_float_data_ex *rgb_regamma
> struct pwl_float_data_ex *rgb = rgb_regamma;
> const struct hw_x_point *coord_x = coordinates_x;
>
> - build_coefficients(, true);
> + build_coefficients(, TRANSFER_FUNCTION_BT709);
>
> i = 0;
> while (i != hw_points_num + 1) {
> --
> 2.25.1
>
Re: [PATCH v1 07/12] drm/bridge: tc358767: Use drm_bridge_funcs.atomic_check
On Mon, Sep 19, 2022 at 06:29:41PM +0300, Laurent Pinchart wrote:
> On Sun, Jul 17, 2022 at 07:44:49PM +0200, Sam Ravnborg wrote:
> > When atomic_check() is defined, then mode_fixup() is ignored,
> > so it had no effect that drm_bridge_funcs.mode_fixup was assigned.
> > Embed the original implementation in the caller and drop the function.
> >
> > Signed-off-by: Sam Ravnborg
> > Cc: Andrzej Hajda
> > Cc: Neil Armstrong
> > Cc: Robert Foss
> > Cc: Laurent Pinchart
> > Cc: Jonas Karlman
> > Cc: Jernej Skrabec
>
> Reviewed-by: Laurent Pinchart
But this doesn't apply anymore, as the mode_fixup operation has been
removed from the driver already. You can just drop this patch.
> > ---
> > drivers/gpu/drm/bridge/tc358767.c | 21 ++---
> > 1 file changed, 6 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/tc358767.c
> > b/drivers/gpu/drm/bridge/tc358767.c
> > index 02bd757a8987..b2ab967504af 100644
> > --- a/drivers/gpu/drm/bridge/tc358767.c
> > +++ b/drivers/gpu/drm/bridge/tc358767.c
> > @@ -1496,26 +1496,18 @@ tc_edp_bridge_atomic_disable(struct drm_bridge
> > *bridge,
> > dev_err(tc->dev, "main link disable error: %d\n", ret);
> > }
> >
> > -static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
> > -const struct drm_display_mode *mode,
> > -struct drm_display_mode *adj)
> > -{
> > - /* Fixup sync polarities, both hsync and vsync are active low */
> > - adj->flags = mode->flags;
> > - adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> > - adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> > -
> > - return true;
> > -}
> > -
> > static int tc_common_atomic_check(struct drm_bridge *bridge,
> > struct drm_bridge_state *bridge_state,
> > struct drm_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state,
> > const unsigned int max_khz)
> > {
> > - tc_bridge_mode_fixup(bridge, _state->mode,
> > -_state->adjusted_mode);
> > + struct drm_display_mode *adj = _state->adjusted_mode;
> > +
> > + /* Fixup sync polarities, both hsync and vsync are active low */
> > + adj->flags = crtc_state->mode.flags;
> > + adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> > + adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> >
> > if (crtc_state->adjusted_mode.clock > max_khz)
> > return -EINVAL;
> > @@ -1783,7 +1775,6 @@ static const struct drm_bridge_funcs
> > tc_edp_bridge_funcs = {
> > .atomic_check = tc_edp_atomic_check,
> > .atomic_enable = tc_edp_bridge_atomic_enable,
> > .atomic_disable = tc_edp_bridge_atomic_disable,
> > - .mode_fixup = tc_bridge_mode_fixup,
> > .detect = tc_bridge_detect,
> > .get_edid = tc_get_edid,
> > .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
--
Regards,
Laurent Pinchart
Re: [PATCH v1 11/12] drm/bridge: Drop drm_bridge_funcs.mode_fixup
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:58:00PM +0200, Sam Ravnborg wrote:
> All users are converted over to drm_bridge_funcs.atomic_check()
> so it is safe to drop the mode_fixup support.
>
> Update the comment for atomic_check with relevant parts from mode_fixup.
>
> Signed-off-by: Sam Ravnborg
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Thomas Zimmermann
> Cc: David Airlie
> Cc: Daniel Vetter
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/drm_bridge.c | 7 +
> include/drm/drm_bridge.h | 60 ++--
> 2 files changed, 17 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
> index b6f56d8f3547..3f5acb19957c 100644
> --- a/drivers/gpu/drm/drm_bridge.c
> +++ b/drivers/gpu/drm/drm_bridge.c
> @@ -685,10 +685,6 @@ static int drm_atomic_bridge_check(struct drm_bridge
> *bridge,
> crtc_state, conn_state);
> if (ret)
> return ret;
> - } else if (bridge->funcs->mode_fixup) {
> - if (!bridge->funcs->mode_fixup(bridge, _state->mode,
> -_state->adjusted_mode))
> - return -EINVAL;
> }
>
> return 0;
> @@ -934,8 +930,7 @@ drm_atomic_bridge_propagate_bus_flags(struct drm_bridge
> *bridge,
> * @conn_state: new connector state
> *
> * First trigger a bus format negotiation before calling
> - * _bridge_funcs.atomic_check() (falls back on
> - * _bridge_funcs.mode_fixup()) op for all the bridges in the encoder
> chain,
> + * _bridge_funcs.atomic_check() op for all the bridges in the encoder
> chain,
> * starting from the last bridge to the first. These are called before
> calling
> * _encoder_helper_funcs.atomic_check()
> *
> diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
> index 7496f41535b1..8c93369bcc74 100644
> --- a/include/drm/drm_bridge.h
> +++ b/include/drm/drm_bridge.h
> @@ -106,7 +106,7 @@ struct drm_bridge_funcs {
>* to look at anything else but the passed-in mode, and validate it
>* against configuration-invariant hardward constraints. Any further
>* limits which depend upon the configuration can only be checked in
> - * @mode_fixup.
> + * @atomic_check.
>*
>* RETURNS:
>*
> @@ -116,46 +116,6 @@ struct drm_bridge_funcs {
> const struct drm_display_info *info,
> const struct drm_display_mode *mode);
>
> - /**
> - * @mode_fixup:
> - *
> - * This callback is used to validate and adjust a mode. The parameter
> - * mode is the display mode that should be fed to the next element in
> - * the display chain, either the final _connector or the next
> - * _bridge. The parameter adjusted_mode is the input mode the bridge
> - * requires. It can be modified by this callback and does not need to
> - * match mode. See also _crtc_state.adjusted_mode for more details.
> - *
> - * This is the only hook that allows a bridge to reject a modeset. If
> - * this function passes all other callbacks must succeed for this
> - * configuration.
> - *
> - * The mode_fixup callback is optional. _bridge_funcs.mode_fixup()
> - * is not called when _bridge_funcs.atomic_check() is implemented,
> - * so only one of them should be provided.
> - *
> - * NOTE:
> - *
> - * This function is called in the check phase of atomic modesets, which
> - * can be aborted for any reason (including on userspace's request to
> - * just check whether a configuration would be possible). Drivers MUST
> - * NOT touch any persistent state (hardware or software) or data
> - * structures except the passed in @state parameter.
> - *
> - * Also beware that userspace can request its own custom modes, neither
> - * core nor helpers filter modes to the list of probe modes reported by
> - * the GETCONNECTOR IOCTL and stored in _connector.modes. To ensure
> - * that modes are filtered consistently put any bridge constraints and
> - * limits checks into @mode_valid.
> - *
> - * RETURNS:
> - *
> - * True if an acceptable configuration is possible, false if the modeset
> - * operation should be rejected.
> - */
> - bool (*mode_fixup)(struct drm_bridge *bridge,
> -const struct drm_display_mode *mode,
> -struct drm_display_mode *adjusted_mode);
> /**
>* @disable:
>*
> @@ -466,9 +426,7 @@ struct drm_bridge_funcs {
>* _bridge_funcs.atomic_check() hooks are called in reverse
>* order (from the last to the first bridge).
>*
> - * This method is optional. _bridge_funcs.mode_fixup() is not
> - * called when
Re: [PATCH v1 10/12] drm/omapdrm: Use drm_bridge_funcs.atomic_check
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:57:59PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
>
> drm_bridge_funcs.atomic_check() requires the atomic state operations,
> update these to the default implementations.
> Likewise update enable/disable to their atomic variants.
>
> With these changes omapdrm now implement the full bridge atomic API.
>
> Signed-off-by: Sam Ravnborg
> Cc: Sam Ravnborg
> Cc: Tomi Valkeinen
> Cc: Cai Huoqing
> Cc: Arnd Bergmann
> Cc: Laurent Pinchart
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/omapdrm/dss/dpi.c | 31 ++
> drivers/gpu/drm/omapdrm/dss/sdi.c | 31 ++
> drivers/gpu/drm/omapdrm/dss/venc.c | 28 +--
> 3 files changed, 56 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c
> b/drivers/gpu/drm/omapdrm/dss/dpi.c
> index 030f997eccd0..0a0b49750eca 100644
> --- a/drivers/gpu/drm/omapdrm/dss/dpi.c
> +++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
> @@ -21,6 +21,7 @@
> #include
> #include
>
> +#include
> #include
>
> #include "dss.h"
> @@ -454,21 +455,22 @@ dpi_bridge_mode_valid(struct drm_bridge *bridge,
> return MODE_OK;
> }
>
> -static bool dpi_bridge_mode_fixup(struct drm_bridge *bridge,
> -const struct drm_display_mode *mode,
> -struct drm_display_mode *adjusted_mode)
> +static int dpi_bridge_atomic_check(struct drm_bridge *bridge,
> +struct drm_bridge_state *bridge_state,
> +struct drm_crtc_state *crtc_state,
> +struct drm_connector_state *conn_state)
> {
> struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
> - unsigned long clock = mode->clock * 1000;
> + unsigned long clock = crtc_state->mode.clock * 1000;
> int ret;
>
> ret = dpi_clock_update(dpi, );
> if (ret < 0)
> - return false;
> + return ret;
>
> - adjusted_mode->clock = clock / 1000;
> + crtc_state->adjusted_mode.clock = clock / 1000;
>
> - return true;
> + return 0;
> }
>
> static void dpi_bridge_mode_set(struct drm_bridge *bridge,
> @@ -480,7 +482,8 @@ static void dpi_bridge_mode_set(struct drm_bridge *bridge,
> dpi->pixelclock = adjusted_mode->clock * 1000;
> }
>
> -static void dpi_bridge_enable(struct drm_bridge *bridge)
> +static void dpi_bridge_atomic_enable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> {
> struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
> int r;
> @@ -531,7 +534,8 @@ static void dpi_bridge_enable(struct drm_bridge *bridge)
> regulator_disable(dpi->vdds_dsi_reg);
> }
>
> -static void dpi_bridge_disable(struct drm_bridge *bridge)
> +static void dpi_bridge_atomic_disable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> {
> struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
>
> @@ -552,10 +556,13 @@ static void dpi_bridge_disable(struct drm_bridge
> *bridge)
> static const struct drm_bridge_funcs dpi_bridge_funcs = {
> .attach = dpi_bridge_attach,
> .mode_valid = dpi_bridge_mode_valid,
> - .mode_fixup = dpi_bridge_mode_fixup,
> + .atomic_check = dpi_bridge_atomic_check,
> .mode_set = dpi_bridge_mode_set,
> - .enable = dpi_bridge_enable,
> - .disable = dpi_bridge_disable,
> + .atomic_enable = dpi_bridge_atomic_enable,
> + .atomic_disable = dpi_bridge_atomic_disable,
> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> + .atomic_reset = drm_atomic_helper_bridge_reset,
> };
>
> static void dpi_bridge_init(struct dpi_data *dpi)
> diff --git a/drivers/gpu/drm/omapdrm/dss/sdi.c
> b/drivers/gpu/drm/omapdrm/dss/sdi.c
> index 91eaae3b9481..73b728722c2f 100644
> --- a/drivers/gpu/drm/omapdrm/dss/sdi.c
> +++ b/drivers/gpu/drm/omapdrm/dss/sdi.c
> @@ -15,6 +15,7 @@
> #include
> #include
>
> +#include
> #include
>
> #include "dss.h"
> @@ -159,12 +160,13 @@ sdi_bridge_mode_valid(struct drm_bridge *bridge,
> return MODE_OK;
> }
>
> -static bool sdi_bridge_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> +static int sdi_bridge_atomic_check(struct drm_bridge *bridge,
> +struct drm_bridge_state *bridge_state,
> +struct drm_crtc_state *crtc_state,
> +struct drm_connector_state *conn_state)
> {
> struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
> -
Re: [PATCH v1 09/12] drm/rcar-du: lvds: Use drm_bridge_funcs.atomic_check
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:57:58PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
> The driver implements the state operations, so no other changes
> are required for the replacement.
>
> Signed-off-by: Sam Ravnborg
> Cc: Laurent Pinchart
> Cc: Kieran Bingham
> Cc: linux-renesas-...@vger.kernel.org
Reviewed-by: Laurent Pinchart
I assume you'll merge this through drm-misc with the rest of the series,
so I won't take it in my tree unless you ask me so.
> ---
> drivers/gpu/drm/rcar-du/rcar_lvds.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c
> b/drivers/gpu/drm/rcar-du/rcar_lvds.c
> index 830aac0a2cb4..c4adbcede090 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
> @@ -554,10 +554,12 @@ static void rcar_lvds_atomic_disable(struct drm_bridge
> *bridge,
> clk_disable_unprepare(lvds->clocks.mod);
> }
>
> -static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> +static int rcar_lvds_atomic_check(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> {
> + struct drm_display_mode *adjusted_mode = _state->adjusted_mode;
> struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
> int min_freq;
>
> @@ -569,7 +571,7 @@ static bool rcar_lvds_mode_fixup(struct drm_bridge
> *bridge,
> min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
> adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
>
> - return true;
> + return 0;
> }
>
> static int rcar_lvds_attach(struct drm_bridge *bridge,
> @@ -591,7 +593,7 @@ static const struct drm_bridge_funcs rcar_lvds_bridge_ops
> = {
> .atomic_reset = drm_atomic_helper_bridge_reset,
> .atomic_enable = rcar_lvds_atomic_enable,
> .atomic_disable = rcar_lvds_atomic_disable,
> - .mode_fixup = rcar_lvds_mode_fixup,
> + .atomic_check = rcar_lvds_atomic_check,
> };
>
> bool rcar_lvds_dual_link(struct drm_bridge *bridge)
--
Regards,
Laurent Pinchart
Re: [PATCH v1 08/12] drm/mediatek: Drop mtk_hdmi_bridge_mode_fixup
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:57:57PM +0200, Sam Ravnborg wrote:
> The implementation of drm_bridge_funcs.mode_fixup is optional
> so there is no need to provide an empty implementation.
> Drop mtk_hdmi_bridge_mode_fixup() so the driver no longer uses the
> deprecated drm_bridge_funcs.mode_fixup() operation.
>
> Signed-off-by: Sam Ravnborg
> Cc: Chun-Kuang Hu
> Cc: Philipp Zabel
> Cc: Matthias Brugger
> Cc: linux-media...@lists.infradead.org
> Cc: linux-arm-ker...@lists.infradead.org
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index a63b76055f81..7321aa1ee6f0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1293,13 +1293,6 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge
> *bridge,
> return 0;
> }
>
> -static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
> -const struct drm_display_mode *mode,
> -struct drm_display_mode *adjusted_mode)
> -{
> - return true;
> -}
> -
> static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
> struct drm_bridge_state
> *old_bridge_state)
> {
> @@ -1399,7 +1392,6 @@ static const struct drm_bridge_funcs
> mtk_hdmi_bridge_funcs = {
> .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> .atomic_reset = drm_atomic_helper_bridge_reset,
> .attach = mtk_hdmi_bridge_attach,
> - .mode_fixup = mtk_hdmi_bridge_mode_fixup,
> .atomic_disable = mtk_hdmi_bridge_atomic_disable,
> .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
> .mode_set = mtk_hdmi_bridge_mode_set,
--
Regards,
Laurent Pinchart
Re: [PATCH v1 07/12] drm/bridge: tc358767: Use drm_bridge_funcs.atomic_check
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:49PM +0200, Sam Ravnborg wrote:
> When atomic_check() is defined, then mode_fixup() is ignored,
> so it had no effect that drm_bridge_funcs.mode_fixup was assigned.
> Embed the original implementation in the caller and drop the function.
>
> Signed-off-by: Sam Ravnborg
> Cc: Andrzej Hajda
> Cc: Neil Armstrong
> Cc: Robert Foss
> Cc: Laurent Pinchart
> Cc: Jonas Karlman
> Cc: Jernej Skrabec
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/bridge/tc358767.c | 21 ++---
> 1 file changed, 6 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c
> b/drivers/gpu/drm/bridge/tc358767.c
> index 02bd757a8987..b2ab967504af 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1496,26 +1496,18 @@ tc_edp_bridge_atomic_disable(struct drm_bridge
> *bridge,
> dev_err(tc->dev, "main link disable error: %d\n", ret);
> }
>
> -static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adj)
> -{
> - /* Fixup sync polarities, both hsync and vsync are active low */
> - adj->flags = mode->flags;
> - adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> - adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> -
> - return true;
> -}
> -
> static int tc_common_atomic_check(struct drm_bridge *bridge,
> struct drm_bridge_state *bridge_state,
> struct drm_crtc_state *crtc_state,
> struct drm_connector_state *conn_state,
> const unsigned int max_khz)
> {
> - tc_bridge_mode_fixup(bridge, _state->mode,
> - _state->adjusted_mode);
> + struct drm_display_mode *adj = _state->adjusted_mode;
> +
> + /* Fixup sync polarities, both hsync and vsync are active low */
> + adj->flags = crtc_state->mode.flags;
> + adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> + adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>
> if (crtc_state->adjusted_mode.clock > max_khz)
> return -EINVAL;
> @@ -1783,7 +1775,6 @@ static const struct drm_bridge_funcs
> tc_edp_bridge_funcs = {
> .atomic_check = tc_edp_atomic_check,
> .atomic_enable = tc_edp_bridge_atomic_enable,
> .atomic_disable = tc_edp_bridge_atomic_disable,
> - .mode_fixup = tc_bridge_mode_fixup,
> .detect = tc_bridge_detect,
> .get_edid = tc_get_edid,
> .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
--
Regards,
Laurent Pinchart
RE: [PATCH] drm/i915: Do not dereference NULL bo->resource
> -Original Message-
> From: Das, Nirmoy
> Sent: Monday, September 19, 2022 8:33 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Auld, Matthew
> ; Gupta, Anshuman
> Subject: [PATCH] drm/i915: Do not dereference NULL bo->resource
>
> bo->resource could be NULL hence add a NULL check for resource before
> bo->dereferencing it.
Will bo->resource will be NULL only in case of object is smem or it can be NULL
even in lmem case as well ?
Thanks,
Anshuman Gupta.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/6850
> Fixes: ad74457a6b5a96 ("drm/i915/dgfx: Release mmap on rpm suspend")
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> index 0544b0a4a43a..8608801cd9ab 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> @@ -513,7 +513,7 @@ static void i915_ttm_delete_mem_notify(struct
> ttm_buffer_object *bo)
>
> if (likely(obj)) {
> /* ttm_bo_release() already has dma_resv_lock */
> - if (i915_ttm_cpu_maps_iomem(bo->resource))
> + if (bo->resource && i915_ttm_cpu_maps_iomem(bo-
> >resource))
> wakeref = intel_runtime_pm_get(_i915(obj-
> >base.dev)->runtime_pm);
>
> __i915_gem_object_pages_fini(obj);
> --
> 2.37.3
Re: [PATCH v1 06/12] drm/bridge: cros-ec-anx7688: Use drm_bridge_funcs.atomic_check
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:48PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
>
> drm_bridge_funcs.atomic_check() requires the atomic state operations,
> update these to the default implementations.
>
> Signed-off-by: Sam Ravnborg
> Cc: Andrzej Hajda
> Cc: Neil Armstrong
> Cc: Robert Foss
> Cc: Laurent Pinchart
> Cc: Jonas Karlman
> Cc: Jernej Skrabec
> Cc: Benson Leung
> Cc: Guenter Roeck
> Cc: chrome-platf...@lists.linux.dev
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/bridge/cros-ec-anx7688.c | 28 +++-
> 1 file changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> index 0f6d907432e3..fc19ea87926f 100644
> --- a/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> +++ b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> @@ -5,6 +5,7 @@
> * Copyright 2020 Google LLC
> */
>
> +#include
> #include
> #include
> #include
> @@ -45,9 +46,10 @@ bridge_to_cros_ec_anx7688(struct drm_bridge *bridge)
> return container_of(bridge, struct cros_ec_anx7688, bridge);
> }
>
> -static bool cros_ec_anx7688_bridge_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode
> *mode,
> - struct drm_display_mode
> *adjusted_mode)
> +static int cros_ec_anx7688_bridge_atomic_check(struct drm_bridge *bridge,
> +struct drm_bridge_state
> *bridge_state,
> +struct drm_crtc_state
> *crtc_state,
> +struct drm_connector_state
> *conn_state)
> {
> struct cros_ec_anx7688 *anx = bridge_to_cros_ec_anx7688(bridge);
> int totalbw, requiredbw;
> @@ -56,13 +58,13 @@ static bool cros_ec_anx7688_bridge_mode_fixup(struct
> drm_bridge *bridge,
> int ret;
>
> if (!anx->filter)
> - return true;
> + return 0;
>
> /* Read both regs 0x85 (bandwidth) and 0x86 (lane count). */
> ret = regmap_bulk_read(anx->regmap, ANX7688_DP_BANDWIDTH_REG, regs, 2);
> if (ret < 0) {
> DRM_ERROR("Failed to read bandwidth/lane count\n");
> - return false;
> + return ret;
> }
> dpbw = regs[0];
> lanecount = regs[1];
> @@ -71,28 +73,34 @@ static bool cros_ec_anx7688_bridge_mode_fixup(struct
> drm_bridge *bridge,
> if (dpbw > 0x19 || lanecount > 2) {
> DRM_ERROR("Invalid bandwidth/lane count (%02x/%d)\n", dpbw,
> lanecount);
> - return false;
> + return -EINVAL;
> }
>
> /* Compute available bandwidth (kHz) */
> totalbw = dpbw * lanecount * 27 * 8 / 10;
>
> /* Required bandwidth (8 bpc, kHz) */
> - requiredbw = mode->clock * 8 * 3;
> + requiredbw = crtc_state->mode.clock * 8 * 3;
>
> DRM_DEBUG_KMS("DP bandwidth: %d kHz (%02x/%d); mode requires %d Khz\n",
> totalbw, dpbw, lanecount, requiredbw);
>
> if (totalbw == 0) {
> DRM_ERROR("Bandwidth/lane count are 0, not rejecting modes\n");
> - return true;
> + return 0;
> }
>
> - return totalbw >= requiredbw;
> + if (totalbw < requiredbw)
> + return -EINVAL;
> +
> + return 0;
> }
>
> static const struct drm_bridge_funcs cros_ec_anx7688_bridge_funcs = {
> - .mode_fixup = cros_ec_anx7688_bridge_mode_fixup,
> + .atomic_check = cros_ec_anx7688_bridge_atomic_check,
> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> + .atomic_reset = drm_atomic_helper_bridge_reset,
> };
>
> static int cros_ec_anx7688_bridge_probe(struct i2c_client *client)
--
Regards,
Laurent Pinchart
Re: [PATCH v1 05/12] drm/bridge: sii8620: Use drm_bridge_funcs.atomic_check
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:47PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
>
> drm_bridge_funcs.atomic_check() requires the atomic state operations,
> update these to the default implementations.
>
> Signed-off-by: Sam Ravnborg
> Cc: Andrzej Hajda
> Cc: Neil Armstrong
> Cc: Robert Foss
> Cc: Laurent Pinchart
> Cc: Jonas Karlman
> Cc: Jernej Skrabec
> ---
> drivers/gpu/drm/bridge/sil-sii8620.c | 17 +++--
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c
> b/drivers/gpu/drm/bridge/sil-sii8620.c
> index ab0bce4a988c..b6e5c285c8ea 100644
> --- a/drivers/gpu/drm/bridge/sil-sii8620.c
> +++ b/drivers/gpu/drm/bridge/sil-sii8620.c
> @@ -8,6 +8,7 @@
>
> #include
>
> +#include
I'd move this one line down, in alphabetical order.
> #include
> #include
> #include
> @@ -2262,26 +2263,30 @@ static enum drm_mode_status sii8620_mode_valid(struct
> drm_bridge *bridge,
> }
> }
>
> -static bool sii8620_mode_fixup(struct drm_bridge *bridge,
> -const struct drm_display_mode *mode,
> -struct drm_display_mode *adjusted_mode)
> +static int sii8620_atomic_check(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> {
> struct sii8620 *ctx = bridge_to_sii8620(bridge);
>
> mutex_lock(>lock);
>
> - ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode);
> + ctx->use_packed_pixel = sii8620_is_packing_required(ctx,
> _state->adjusted_mode);
Shouldn't this be moved to atomic_enable ? A test commit should change
the device state.
As this code was initially in mode_fixup I suppose this patch could be
merged as-is, with the problem fixed on top, so
Reviewed-by: Laurent Pinchart
>
> mutex_unlock(>lock);
>
> - return true;
> + return 0;
> }
>
> static const struct drm_bridge_funcs sii8620_bridge_funcs = {
> .attach = sii8620_attach,
> .detach = sii8620_detach,
> - .mode_fixup = sii8620_mode_fixup,
> + .atomic_check = sii8620_atomic_check,
> .mode_valid = sii8620_mode_valid,
> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> + .atomic_reset = drm_atomic_helper_bridge_reset,
> };
>
> static int sii8620_probe(struct i2c_client *client,
--
Regards,
Laurent Pinchart
Re: [PATCH] drm/mgag200: Force 32 bpp on the console
On 15/09/2022 17:03, Thomas Zimmermann wrote:
G200ER does not seem to support 24 bpp, so force the console to
use 32 bpp. The problem was introduced, when commit 73f54d5d9682
("drm/mgag200: Remove special case for G200SE with <2 MiB") changed
the preferred color depth from 32 bit to 24 bit.
A setting of 24 is the correct color depth, but G200ER doesn't seem
to be able to use the respective RGB888 color format. Using 24-bit
color with forced 32 bpp works around the problem.
Thanks for the patch.
At least on my G200EW, 24 bpp is working well. So maybe only the G200ER
is affected.
I think it may have a performance penalty, I will try to measure it.
Reviewed-by: Jocelyn Falempe
--
Jocelyn
Reported-by: Wang Yugui
Signed-off-by: Thomas Zimmermann
Tested-by: Wang Yugui
Fixes: 73f54d5d9682 ("drm/mgag200: Remove special case for G200SE with <2 MiB")
Cc: Thomas Zimmermann
Cc: Jocelyn Falempe
Cc: Dave Airlie
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/mgag200/mgag200_drv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c
b/drivers/gpu/drm/mgag200/mgag200_drv.c
index 251a1bb648cc..a222bf76804f 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.c
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
@@ -262,7 +262,11 @@ mgag200_pci_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
return ret;
- drm_fbdev_generic_setup(dev, 0);
+ /*
+* FIXME: A 24-bit color depth does not work with 24 bpp on
+* G200ER. Force 32 bpp.
+*/
+ drm_fbdev_generic_setup(dev, 32);
return 0;
}
Re: [Intel-gfx] [PATCH] drm/i915: Document and future-proof preemption control policy
On 9/7/22 2:24 PM, Matt Roper wrote:
Intel hardware allows some preemption settings to be controlled either
by the kernel-mode driver exclusively, or placed under control of the
user-mode drivers; on Linux we always select the userspace control
option. The various registers involved in this are not documented very
clearly; let's add some clarifying comments to help explain how this all
works and provide some history on why our Linux drivers take the
approach they do (which I believe differs from the path taken by certain
other operating systems' drivers).
While we're at it, let's also remove the graphics version 12 upper bound
on this programming. As described, we don't have any plans to move away
from UMD control of preemption settings on future platforms, and there's
currently no reason to believe that the hardware will fundamentally
change how these registers and settings work after version 12.
Bspec: 45921, 45858, 45863
Cc: Joonas Lahtinen
Cc: Jordan Justen
Cc: Lionel Landwerlin
Suggested-by: Joonas Lahtinen
Signed-off-by: Matt Roper
Reviewed-by: Wayne Boyer
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 58 +++--
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6d2003d598e6..3e5a41378e81 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2389,12 +2389,64 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (IS_GRAPHICS_VER(i915, 9, 12)) {
- /*
FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
+ /*
+* Intel platforms that support fine-grained preemption (i.e., gen9 and
+* beyond) allow the kernel-mode driver to choose between two different
+* options for controlling preemption granularity and behavior.
+*
+* Option 1 (hardware default):
+* Preemption settings are controlled in a global manner via
+* kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity
+* and settings chosen by the kernel-mode driver will apply to all
+* userspace clients.
+*
+* Option 2:
+* Preemption settings are controlled on a per-context basis via
+* register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on
+* context switch and is writable by userspace (e.g., via
+* MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer)
+* which allows different userspace drivers/clients to select
+* different settings, or to change those settings on the fly in
+* response to runtime needs. This option was known by name
+* "FtrPerCtxtPreemptionGranularityControl" at one time, although
+* that name is somewhat misleading as other non-granularity
+* preemption settings are also impacted by this decision.
+*
+* On Linux, our policy has always been to let userspace drivers
+* control preemption granularity/settings (Option 2). This was
+* originally mandatory on gen9 to prevent ABI breakage (old gen9
+* userspace developed before object-level preemption was enabled would
+* not behave well if i915 were to go with Option 1 and enable that
+* preemption in a global manner). On gen9 each context would have
+* object-level preemption disabled by default (see
+* WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but
+* userspace drivers could opt-in to object-level preemption as they
+* saw fit. For post-gen9 platforms, we continue to utilize Option 2;
+* even though it is no longer necessary for ABI compatibility when
+* enabling a new platform, it does ensure that userspace will be able
+* to implement any workarounds that show up requiring temporary
+* adjustments to preemption behavior at runtime.
+*
+* Notes/Workarounds:
+* - Wa_14015141709: On DG2 and early steppings of MTL,
+* CS_CHICKEN1[0] does not disable object-level preemption as
+* it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been
+* using Option 1). Effectively this means userspace is unable
+* to disable object-level preemption on these platforms/steppings
+* despite the setting here.
+*
+* - Wa_16013994831: May require that userspace program
+* CS_CHICKEN1[10] when certain runtime conditions are true.
+* Userspace requires Option 2 to be in effect for their update of
+* CS_CHICKEN1[10] to be effective.
+*
+* Other workarounds may appear in the future that will also require
+* Option 2 behavior to allow proper
Re: [PATCH v1 04/12] drm/bridge: Drop drm_bridge_chain_mode_fixup
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:46PM +0200, Sam Ravnborg wrote:
> There are no users left of drm_bridge_chain_mode_fixup() and we
> do not want to have this function available, so drop it.
>
> Signed-off-by: Sam Ravnborg
> Reviewed-by: Maxime Ripard
> Cc: Laurent Pinchart
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Thomas Zimmermann
> Cc: David Airlie
> Cc: Daniel Vetter
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/drm_bridge.c | 37
> include/drm/drm_bridge.h | 3 ---
> 2 files changed, 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
> index bb7fc09267af..b6f56d8f3547 100644
> --- a/drivers/gpu/drm/drm_bridge.c
> +++ b/drivers/gpu/drm/drm_bridge.c
> @@ -430,43 +430,6 @@ void drm_bridge_detach(struct drm_bridge *bridge)
> * needed, in order to gradually transition to the new model.
> */
>
> -/**
> - * drm_bridge_chain_mode_fixup - fixup proposed mode for all bridges in the
> - *encoder chain
> - * @bridge: bridge control structure
> - * @mode: desired mode to be set for the bridge
> - * @adjusted_mode: updated mode that works for this bridge
> - *
> - * Calls _bridge_funcs.mode_fixup for all the bridges in the
> - * encoder chain, starting from the first bridge to the last.
> - *
> - * Note: the bridge passed should be the one closest to the encoder
> - *
> - * RETURNS:
> - * true on success, false on failure
> - */
> -bool drm_bridge_chain_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> -{
> - struct drm_encoder *encoder;
> -
> - if (!bridge)
> - return true;
> -
> - encoder = bridge->encoder;
> - list_for_each_entry_from(bridge, >bridge_chain, chain_node) {
> - if (!bridge->funcs->mode_fixup)
> - continue;
> -
> - if (!bridge->funcs->mode_fixup(bridge, mode, adjusted_mode))
> - return false;
> - }
> -
> - return true;
> -}
> -EXPORT_SYMBOL(drm_bridge_chain_mode_fixup);
> -
> /**
> * drm_bridge_chain_mode_valid - validate the mode against all bridges in the
> *encoder chain.
> diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
> index 1eca9c4c3346..7496f41535b1 100644
> --- a/include/drm/drm_bridge.h
> +++ b/include/drm/drm_bridge.h
> @@ -845,9 +845,6 @@ drm_bridge_chain_get_first_bridge(struct drm_encoder
> *encoder)
> #define drm_for_each_bridge_in_chain(encoder, bridge)
> \
> list_for_each_entry(bridge, &(encoder)->bridge_chain, chain_node)
>
> -bool drm_bridge_chain_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode);
> enum drm_mode_status
> drm_bridge_chain_mode_valid(struct drm_bridge *bridge,
> const struct drm_display_info *info,
--
Regards,
Laurent Pinchart
Re: [PATCH] A simple doc fix
On 2022-09-14 15:26, Anup K Parikh wrote:
On Wed, Sep 14, 2022 at 10:24:36AM -0400, Andrey Grodzovsky wrote:
On 2022-09-14 06:36, Anup K Parikh wrote:
Fix two warnings during doc build which also results in corresponding
additions in generated docs
Warnings Fixed:
1. include/drm/gpu_scheduler.h:462: warning: Function parameter or member
'dev' not described in 'drm_gpu_scheduler'
2. drivers/gpu/drm/scheduler/sched_main.c:1005: warning: Function
parameter or member 'dev' not described in 'drm_sched_init'
Signed-off-by: Anup K Parikh
---
drivers/gpu/drm/scheduler/sched_main.c | 1 +
include/drm/gpu_scheduler.h| 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 68317d3a7a27..875d00213849 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -994,6 +994,7 @@ static int drm_sched_main(void *param)
* used
* @score: optional score atomic shared with other schedulers
* @name: name used for debugging
+ * @dev: A device pointer for use in error reporting in a multiple GPU
scenario.
Why multiple GPUs scenario ? It's also used in single GPU scenario.
Andrey
Hello Mr. Andrey Grodzovsky,
Thanks for the quick review and response.
My documentation string (same for both files) is based on commit id
8ab62eda177bc350f34fea4fcea23603b8184bfd. It seemed that both warnings
might've been introduced by the addition of that device pointer.
Also, the commit message specifically mentions this addition for use with
DRM_DEV_ERROR() to make life easier under a multiple GPU scenario. So, I
used cscope to look for DRM_DEV_ERROR() and then for drm_dev_printk(). I
also checked previous versions of both files and noticed DRM_ERROR() in
drivers/gpu/drm/scheduler/sched_main.c changed to DRM_DEV_ERROR().
Perhaps, I wrongly correlated my cscope/history findings with the commit
message and used absolute wording. I guess that this might be (I usually
avoid absolute wording) useful not only in a single GPU scenario (to print
better standardized messages with dev when available) but also in non-error
printing such as with KERN_NOTICE, KERN_INFO, etc. I'm still not sure if
the added device pointer could be used for something else besides printing.
Please let me know if my understanding is correct and whether I should
change the wording to:
A device pointer - primarily useful for printing standardized messages with
DRM_DEV_ERROR().
It could be used for many other things but in this case in deed used
only for the print.
So yep - looks good.
Andrey
*
* Return 0 on success, otherwise error code.
*/
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index addb135eeea6..920b91fd1719 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -435,6 +435,7 @@ struct drm_sched_backend_ops {
* @_score: score used when the driver doesn't provide one
* @ready: marks if the underlying HW is ready to work
* @free_guilty: A hit to time out handler to free the guilty job.
+ * @dev: A device pointer for use in error reporting in a multiple GPU
scenario.
*
* One scheduler is implemented for each hardware ring.
*/
Re: [PATCH v1 03/12] drm/mediatek: Drop chain_mode_fixup call in mode_valid()
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:45PM +0200, Sam Ravnborg wrote:
> The mode_valid implementation had a call to
> drm_bridge_chain_mode_fixup() which would be wrong as the mode_valid is
> not allowed to change anything - only to validate the mode.
>
> As the next bridge is often/always a connector the call had no effect
> anyway. So drop it.
>
> From the git history I could see this call was included in the original
> version of the driver so there was no help there to find out why it was
> added in the first place. But a lot has changed since the initial driver
> were added and is seems safe to remove the call now.
>
> Signed-off-by: Sam Ravnborg
> Reviewed-by: Maxime Ripard
> Cc: Chun-Kuang Hu
> Cc: Philipp Zabel
> Cc: Matthias Brugger
> Cc: Dafna Hirschfeld
> Cc: linux-media...@lists.infradead.org
> Cc: linux-arm-ker...@lists.infradead.org
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 11 ---
> 1 file changed, 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 3196189429bc..a63b76055f81 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1208,22 +1208,11 @@ static int mtk_hdmi_bridge_mode_valid(struct
> drm_bridge *bridge,
> const struct drm_display_mode *mode)
> {
> struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> - struct drm_bridge *next_bridge;
>
> dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
> mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
> !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
>
> - next_bridge = drm_bridge_get_next_bridge(>bridge);
> - if (next_bridge) {
> - struct drm_display_mode adjusted_mode;
> -
> - drm_mode_copy(_mode, mode);
> - if (!drm_bridge_chain_mode_fixup(next_bridge, mode,
> - _mode))
> - return MODE_BAD;
> - }
> -
> if (hdmi->conf) {
> if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
> return MODE_BAD;
--
Regards,
Laurent Pinchart
Re: [PATCH v1 01/12] drm/bridge: ps8640: Use atomic variants of drm_bridge_funcs
Hi Sam,
Thank you for the patch, and sorry for the review delay. The series only
recently jumped to the top of my inbox.
On Sun, Jul 17, 2022 at 07:44:43PM +0200, Sam Ravnborg wrote:
> The atomic variants of enable/disable in drm_bridge_funcs are the
> preferred operations - introduce these.
>
> The ps8640 driver used the non-atomic variants of the
> drm_bridge_chain_pre_enable/
> drm_bridge_chain_post_disable - convert these to the atomic variants.
>
> v2:
> - Init state operations in drm_bridge_funcs (Laurent)
>
> Signed-off-by: Sam Ravnborg
> Reviewed-by: Maxime Ripard
> Cc: Jitao Shi
> Cc: Enric Balletbo i Serra
> Cc: Philip Chen
> Cc: Andrzej Hajda
> Cc: Neil Armstrong
> Cc: Robert Foss
> Cc: Laurent Pinchart
> Cc: Jonas Karlman
> Cc: Jernej Skrabec
Reviewed-by: Laurent Pinchart
> ---
> drivers/gpu/drm/bridge/parade-ps8640.c | 18 --
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
> b/drivers/gpu/drm/bridge/parade-ps8640.c
> index 31e88cb39f8a..bb8076fb8625 100644
> --- a/drivers/gpu/drm/bridge/parade-ps8640.c
> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> @@ -15,6 +15,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -409,7 +410,8 @@ static const struct dev_pm_ops ps8640_pm_ops = {
> pm_runtime_force_resume)
> };
>
> -static void ps8640_pre_enable(struct drm_bridge *bridge)
> +static void ps8640_atomic_pre_enable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> {
> struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
> @@ -443,7 +445,8 @@ static void ps8640_pre_enable(struct drm_bridge *bridge)
> ps_bridge->pre_enabled = true;
> }
>
> -static void ps8640_post_disable(struct drm_bridge *bridge)
> +static void ps8640_atomic_post_disable(struct drm_bridge *bridge,
> +struct drm_bridge_state
> *old_bridge_state)
> {
> struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
>
> @@ -521,7 +524,7 @@ static struct edid *ps8640_bridge_get_edid(struct
> drm_bridge *bridge,
>* EDID, for this chip, we need to do a full poweron, otherwise it will
>* fail.
>*/
> - drm_bridge_chain_pre_enable(bridge);
> + drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state);
>
> edid = drm_get_edid(connector,
> ps_bridge->page[PAGE0_DP_CNTL]->adapter);
> @@ -531,7 +534,7 @@ static struct edid *ps8640_bridge_get_edid(struct
> drm_bridge *bridge,
>* before, return the chip to its original power state.
>*/
> if (poweroff)
> - drm_bridge_chain_post_disable(bridge);
> + drm_atomic_bridge_chain_post_disable(bridge,
> connector->state->state);
>
> return edid;
> }
> @@ -546,8 +549,11 @@ static const struct drm_bridge_funcs ps8640_bridge_funcs
> = {
> .attach = ps8640_bridge_attach,
> .detach = ps8640_bridge_detach,
> .get_edid = ps8640_bridge_get_edid,
> - .post_disable = ps8640_post_disable,
> - .pre_enable = ps8640_pre_enable,
> + .atomic_post_disable = ps8640_atomic_post_disable,
> + .atomic_pre_enable = ps8640_atomic_pre_enable,
> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> + .atomic_reset = drm_atomic_helper_bridge_reset,
> };
>
> static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640
> *ps_bridge)
--
Regards,
Laurent Pinchart
[PATCH] drm/i915: Do not dereference NULL bo->resource
bo->resource could be NULL hence add a NULL check for
bo->resource before dereferencing it.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6850
Fixes: ad74457a6b5a96 ("drm/i915/dgfx: Release mmap on rpm suspend")
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 0544b0a4a43a..8608801cd9ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -513,7 +513,7 @@ static void i915_ttm_delete_mem_notify(struct
ttm_buffer_object *bo)
if (likely(obj)) {
/* ttm_bo_release() already has dma_resv_lock */
- if (i915_ttm_cpu_maps_iomem(bo->resource))
+ if (bo->resource && i915_ttm_cpu_maps_iomem(bo->resource))
wakeref =
intel_runtime_pm_get(_i915(obj->base.dev)->runtime_pm);
__i915_gem_object_pages_fini(obj);
--
2.37.3
Re: [PATCH 2/4] drm/plane: Allocate planes with drm_universal_plane_alloc()
Hi Thomas,
On Fri, Sep 16, 2022 at 01:31:25PM +0200, Thomas Zimmermann wrote:
> Am 16.09.22 um 13:06 schrieb Laurent Pinchart:
> > On Fri, Sep 09, 2022 at 12:59:45PM +0200, Thomas Zimmermann wrote:
> >> Provide drm_univeral_plane_alloc(), which allocated an initializes a
> >> plane. Code for non-atomic drivers uses this pattern. Convert it to
> >> the new function. The modeset helpers contain a quirk for handling their
> >> color formats differently. Set the flag outside plane allocation.
> >>
> >> The new function is already deprecated to some extend. Drivers should
> >> rather use drmm_univeral_plane_alloc() or drm_universal_plane_init().
> >
> > If this is already deprecated and used by a single driver, what is the
> > point ?
>
> It's used by nouveau and drm_modeset_helper.c. Since the code is
> duplicated, it seems generally better to have it located and documented
> in a central place.
>
> Although it may look somewhat pointless now, the helper will get useful
> in the future. The affected code in drm_modeset_helper is in
> drm_crtc_init(), which is also a deprecated interface; only used by
> non-atomic drivers. The function is a good candidate to be inlined into
> calling drivers. Getting drm_crtc_init() removed will allow us to
> correct these drivers' color-format handling. Once that happened,
> several more drivers will call drm_univeral_plane_alloc().
OK, works for me.
> >> Signed-off-by: Thomas Zimmermann
> >> ---
> >> drivers/gpu/drm/drm_modeset_helper.c| 61 +++--
> >> drivers/gpu/drm/drm_plane.c | 38 +++
> >> drivers/gpu/drm/nouveau/dispnv04/crtc.c | 41 ++---
> >> include/drm/drm_plane.h | 44 ++
> >> 4 files changed, 121 insertions(+), 63 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_modeset_helper.c
> >> b/drivers/gpu/drm/drm_modeset_helper.c
> >> index 611dd01fb604..38040eebfa16 100644
> >> --- a/drivers/gpu/drm/drm_modeset_helper.c
> >> +++ b/drivers/gpu/drm/drm_modeset_helper.c
> >> @@ -113,38 +113,6 @@ static const struct drm_plane_funcs
> >> primary_plane_funcs = {
> >>.destroy = drm_plane_helper_destroy,
> >> };
> >>
> >> -static struct drm_plane *create_primary_plane(struct drm_device *dev)
> >> -{
> >> - struct drm_plane *primary;
> >> - int ret;
> >> -
> >> - primary = kzalloc(sizeof(*primary), GFP_KERNEL);
> >> - if (primary == NULL) {
> >> - DRM_DEBUG_KMS("Failed to allocate primary plane\n");
> >> - return NULL;
> >> - }
> >> -
> >> - /*
> >> - * Remove the format_default field from drm_plane when dropping
> >> - * this helper.
> >> - */
> >> - primary->format_default = true;
> >> -
> >> - /* possible_crtc's will be filled in later by crtc_init */
> >> - ret = drm_universal_plane_init(dev, primary, 0,
> >> - _plane_funcs,
> >> - safe_modeset_formats,
> >> - ARRAY_SIZE(safe_modeset_formats),
> >> - NULL,
> >> - DRM_PLANE_TYPE_PRIMARY, NULL);
> >> - if (ret) {
> >> - kfree(primary);
> >> - primary = NULL;
> >> - }
> >> -
> >> - return primary;
> >> -}
> >> -
> >> /**
> >>* drm_crtc_init - Legacy CRTC initialization function
> >>* @dev: DRM device
> >> @@ -176,10 +144,33 @@ int drm_crtc_init(struct drm_device *dev, struct
> >> drm_crtc *crtc,
> >> const struct drm_crtc_funcs *funcs)
> >> {
> >>struct drm_plane *primary;
> >> + int ret;
> >> +
> >> + /* possible_crtc's will be filled in later by crtc_init */
> >> + primary = __drm_universal_plane_alloc(dev, sizeof(*primary), 0, 0,
> >> +_plane_funcs,
> >> +safe_modeset_formats,
> >> +ARRAY_SIZE(safe_modeset_formats),
> >> +NULL, DRM_PLANE_TYPE_PRIMARY,
> >> NULL);
> >> + if (IS_ERR(primary))
> >> + return PTR_ERR(primary);
> >>
> >> - primary = create_primary_plane(dev);
> >> - return drm_crtc_init_with_planes(dev, crtc, primary, NULL, funcs,
> >> - NULL);
> >> + /*
> >> + * Remove the format_default field from drm_plane when dropping
> >> + * this helper.
> >> + */
> >> + primary->format_default = true;
> >> +
> >> + ret = drm_crtc_init_with_planes(dev, crtc, primary, NULL, funcs, NULL);
> >> + if (ret)
> >> + goto err_drm_plane_cleanup;
> >> +
> >> + return 0;
> >> +
> >> +err_drm_plane_cleanup:
> >> + drm_plane_cleanup(primary);
> >> + kfree(primary);
> >> + return ret;
> >> }
> >> EXPORT_SYMBOL(drm_crtc_init);
> >>
> >> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> >> index 0f14b4d3bb10..33357629a7f5 100644
> >> --- a/drivers/gpu/drm/drm_plane.c
> >> +++ b/drivers/gpu/drm/drm_plane.c
> >>
Re: linux-next: manual merge of the drm tree with Linus' tree
Hi Geert,
On Mon, Sep 19, 2022 at 09:58:01AM +0200, Geert Uytterhoeven wrote:
> Hi Stephen,
>
> On Mon, Sep 19, 2022 at 3:07 AM Stephen Rothwell
> wrote:
> > Today's linux-next merge of the drm tree got a conflict in:
> >
> > drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> >
> > between commit:
> >
> > 41012d715d5d ("drm/amd/display: Mark dml30's UseMinimumDCFCLK() as
> > noinline for stack usage")
> >
> > from Linus' tree and commit:
> >
> > a0f7e7f759cf ("drm/amd/display: fix i386 frame size warning")
> >
> > from the drm tree.
> >
> > I fixed it up (see below) and can carry the fix as necessary. This
> > is now fixed as far as linux-next is concerned, but any non trivial
> > conflicts should be mentioned to your upstream maintainer when your tree
> > is submitted for merging. You may also want to consider cooperating
> > with the maintainer of the conflicting tree to minimise any particularly
> > complex conflicts.
> >
> > --
> > Cheers,
> > Stephen Rothwell
> >
> > diff --cc drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> > index 1cb858dd6ea0,b7fa003ffe06..
> > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> > @@@ -6610,66 -6497,11 +6497,11 @@@ static double CalculateUrgentLatency
> > return ret;
> > }
> >
> > -static void UseMinimumDCFCLK(
> > +static noinline_for_stack void UseMinimumDCFCLK(
>
> While this looks like the correct merge resolution, it does mean that
> both stack size mitigations are now applied, and probably one of them
> can be dropped?
Thanks for taking a look! As I note in the commit message of
41012d715d5d:
"Commit a0f7e7f759cf ("drm/amd/display: fix i386 frame size warning")
aimed to address this for i386 but it did not help x86_64.
... The aforementioned change does help reduce UseMinimumDCFCLK()'s
stack usage so it should not be reverted in favor of this change."
While it is possible that 41012d715d5d fixes the warning for both 32-bit
and 64-bit x86 (I did not check), a0f7e7f759cf is still a good change in
my opinion so neither should be reverted.
Cheers,
Nathan
> > struct display_mode_lib *mode_lib,
> > - int MaxInterDCNTileRepeaters,
> > + struct vba_vars_st *v,
> > int MaxPrefetchMode,
> > - double FinalDRAMClockChangeLatency,
> > - double SREnterPlusExitTime,
> > - int ReturnBusWidth,
> > - int RoundTripPingLatencyCycles,
> > - int ReorderingBytes,
> > - int PixelChunkSizeInKByte,
> > - int MetaChunkSize,
> > - bool GPUVMEnable,
> > - int GPUVMMaxPageTableLevels,
> > - bool HostVMEnable,
> > - int NumberOfActivePlanes,
> > - double HostVMMinPageSize,
> > - int HostVMMaxNonCachedPageTableLevels,
> > - bool DynamicMetadataVMEnabled,
> > - enum immediate_flip_requirement ImmediateFlipRequirement,
> > - bool ProgressiveToInterlaceUnitInOPP,
> > - double
> > MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
> > - double
> > PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
> > - double
> > PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
> > - double
> > PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly,
> > - int VTotal[],
> > - int VActive[],
> > - int DynamicMetadataTransmittedBytes[],
> > - int DynamicMetadataLinesBeforeActiveRequired[],
> > - bool Interlace[],
> > - double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
> > - double RequiredDISPCLK[][2],
> > - double UrgLatency[],
> > - unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
> > - double ProjectedDCFCLKDeepSleep[][2],
> > - double MaximumVStartup[][2][DC__NUM_DPP__MAX],
> > - double TotalVActivePixelBandwidth[][2],
> > - double TotalVActiveCursorBandwidth[][2],
> > - double TotalMetaRowBandwidth[][2],
> > - double TotalDPTERowBandwidth[][2],
> > - unsigned int TotalNumberOfActiveDPP[][2],
> > - unsigned int TotalNumberOfDCCActiveDPP[][2],
> > - int dpte_group_bytes[],
> > - double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
> > - double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
> > - unsigned int
> > swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
> > - unsigned int
> > swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
> > - int BytePerPixelY[],
> > - int BytePerPixelC[],
> > -
Re: [PATCH] drm/bridge: ti-sn65dsi83: Add and use hs_rate and lp_rate
Hi,
On Sun, Sep 18, 2022 at 02:56:00PM +0200, Marek Vasut wrote:
> On 8/1/22 15:11, Marek Vasut wrote:
> > Fill in hs_rate and lp_rate to struct mipi_dsi_device for this bridge and
> > adjust DSI input frequency calculations such that they expect the DSI host
> > to configure HS clock according to hs_rate.
> >
> > This is an optimization for the DSI burst mode case. In case the DSI device
> > supports DSI burst mode, it is recommended to operate the DSI interface at
> > the highest possible HS clock frequency which the DSI device supports. This
> > permits the DSI host to send as short as possible bursts of data on the DSI
> > link and keep the DSI data lanes in LP mode otherwise, which reduces power
> > consumption.
>
> > Signed-off-by: Marek Vasut
> > Cc: Jagan Teki
> > Cc: Laurent Pinchart
> > Cc: Linus Walleij
> > Cc: Robert Foss
> > Cc: Sam Ravnborg
> > Cc: dri-devel@lists.freedesktop.org
> > ---
> > drivers/gpu/drm/bridge/ti-sn65dsi83.c | 25 +
> > 1 file changed, 13 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> > b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> > index 14e7aa77e7584..b161f25c3a2f5 100644
> > --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> > @@ -286,8 +286,7 @@ static u8 sn65dsi83_get_lvds_range(struct sn65dsi83
> > *ctx,
> > return (mode_clock - 12500) / 25000;
> > }
> > -static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
> > - const struct drm_display_mode *mode)
> > +static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx)
> > {
> > /*
> > * The encoding of the CHA_DSI_CLK_RANGE is as follows:
> > @@ -303,20 +302,20 @@ static u8 sn65dsi83_get_dsi_range(struct sn65dsi83
> > *ctx,
> > * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
> > * the 2 is there because the bus is DDR.
> > */
> > - return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
> > - mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
> > - ctx->dsi->lanes / 2, 4U, 50U), 5000U);
> > + return DIV_ROUND_UP(ctx->dsi->hs_rate, 500U);
> > }
> > -static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
> > +static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx,
> > + const struct drm_display_mode *mode)
> > {
> > /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
> > - unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
> > + unsigned int dsi_div;
> > + int mode_clock = mode->clock;
> > - dsi_div /= ctx->dsi->lanes;
> > + if (ctx->lvds_dual_link)
> > + mode_clock /= 2;
> > - if (!ctx->lvds_dual_link)
> > - dsi_div /= 2;
> > + dsi_div = (ctx->dsi->hs_rate / mode_clock) / 1000;
> > return dsi_div - 1;
> > }
> > @@ -397,9 +396,9 @@ static void sn65dsi83_atomic_enable(struct drm_bridge
> > *bridge,
> >
> > REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
> > REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
> > regmap_write(ctx->regmap, REG_DSI_CLK,
> > -REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx,
> > mode)));
> > +
> > REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx)));
> > regmap_write(ctx->regmap, REG_RC_DSI_CLK,
> > -
> > REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
> > +REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx,
> > mode)));
> > /* Set number of DSI lanes and LVDS link config. */
> > regmap_write(ctx->regmap, REG_DSI_LANE,
> > @@ -643,6 +642,8 @@ static int sn65dsi83_host_attach(struct sn65dsi83 *ctx)
> > dsi->lanes = dsi_lanes;
> > dsi->format = MIPI_DSI_FMT_RGB888;
> > dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
> > + dsi->hs_rate = 5;
> > + dsi->lp_rate = 1600;
Let's leave aside the comment from Dave that the host might choose a
lower HS rate, we can indeed assume it's true for now.
However.. Is there any guarantee that the host can even reach that
frequency in the first place? IIRC, the maximum rate a DSI host can
reach is implementation specific. So I'm not sure this solution flies.
It's not clear to me from that patch what problem / issue it's supposed
to solve in the first place, but it really looks similar to the
discussion we had some time ago about that bridge that could only
operate at a set of fixed frequencies.
You basically want to propagate the clock constraints along the bridge
chain, and make sure every body is fine with that. The most reasonable
would be to make it part of the bridge state, and possibly add a bunch
of extra functions to query the upstream bridge clock output for a given
state.
Maxime
signature.asc
Description: PGP signature
[PATCH] drm: panel-orientation-quirks: Add quirk for Nanote UMPC-01
The Nanote UMPC-01 is a mini laptop with a 1200x1920 portrait screen
mounted in a landscape oriented clamshell case. Add a quirk for this.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
b/drivers/gpu/drm/drm_panel_orientation_quirks.c
index 8a0c0e0bb5bd..f0f6fa306521 100644
--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
+++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
@@ -319,6 +319,12 @@ static const struct dmi_system_id orientation_data[] = {
DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
},
.driver_data = (void *)_rightside_up,
+ }, {/* Nanote UMPC-01 */
+ .matches = {
+DMI_MATCH(DMI_SYS_VENDOR, "RWC CO.,LTD"),
+DMI_MATCH(DMI_PRODUCT_NAME, "UMPC-01"),
+ },
+ .driver_data = (void *)_rightside_up,
}, {/* OneGX1 Pro */
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "SYSTEM_MANUFACTURER"),
--
2.37.3
Re: [PATCH] drm/mediatek: dsi: Move mtk_dsi_stop() call back to mtk_dsi_poweroff()
Il 19/09/22 10:40, Hsin-Yi Wang ha scritto:
On Mon, Sep 19, 2022 at 4:39 PM Nícolas F. R. A. Prado
wrote:
As the comment right before the mtk_dsi_stop() call advises,
mtk_dsi_stop() should only be called after
mtk_drm_crtc_atomic_disable(). That's because that function calls
drm_crtc_wait_one_vblank(), which requires the vblank irq to be enabled.
Previously mtk_dsi_stop(), being in mtk_dsi_poweroff() and guarded by a
refcount, would only be called at the end of
mtk_drm_crtc_atomic_disable(), through the call to mtk_crtc_ddp_hw_fini().
Commit cde7e2e35c28 ("drm/mediatek: Separate poweron/poweroff from
enable/disable and define new funcs") moved the mtk_dsi_stop() call to
mtk_output_dsi_disable(), causing it to be called before
mtk_drm_crtc_atomic_disable(), and consequently generating vblank
timeout warnings during suspend.
Move the mtk_dsi_stop() call back to mtk_dsi_poweroff() so that we have
a working vblank irq during mtk_drm_crtc_atomic_disable() and stop
getting vblank timeout warnings.
Fixes: cde7e2e35c28 ("drm/mediatek: Separate poweron/poweroff from enable/disable
and define new funcs")
Signed-off-by: Nícolas F. R. A. Prado
Tested-by: Hsin-Yi Wang
Reviewed-by: AngeloGioacchino Del Regno
Re: [PATCH v2 2/2] Revert "drm/bridge: chrontel-ch7033: Add byteswap order setting"
On Mon, 19 Sept 2022 at 12:48, Laurent Pinchart
wrote:
>
> Hi Rob,
>
> Thank you for the patch.
>
> On Mon, Sep 19, 2022 at 12:20:09PM +0200, Robert Foss wrote:
> > Revert this patch since it depends on devicetree functionality that
> > previously has been reverted in the below commit.
> >
> > commit e798ba3374a1 ("Revert "dt-bindings: Add byteswap order to chrontel
> > ch7033"")
> >
> > This reverts commit ce9564cfc9aea65e68eb343c599317633bc2321a.
> >
> > Fixes: 8c9c40ec8344 ("Revert "drm/bridge: ti-sn65dsi86: Implement bridge
> > connector operations for DP"")
>
> I'm not sure this Fixes tag is meaningful here. Apart from that,
Ack.
>
> Reviewed-by: Laurent Pinchart
>
> > Signed-off-by: Robert Foss
> > ---
> > drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 ++-
> > 1 file changed, 2 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
> > b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> > index c5719908ce2d..ba060277c3fd 100644
> > --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
> > +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> > @@ -68,7 +68,6 @@ enum {
> > BYTE_SWAP_GBR = 3,
> > BYTE_SWAP_BRG = 4,
> > BYTE_SWAP_BGR = 5,
> > - BYTE_SWAP_MAX = 6,
> > };
> >
> > /* Page 0, Register 0x19 */
> > @@ -356,8 +355,6 @@ static void ch7033_bridge_mode_set(struct drm_bridge
> > *bridge,
> > int hsynclen = mode->hsync_end - mode->hsync_start;
> > int vbporch = mode->vsync_start - mode->vdisplay;
> > int vsynclen = mode->vsync_end - mode->vsync_start;
> > - u8 byte_swap;
> > - int ret;
> >
> > /*
> >* Page 4
> > @@ -401,16 +398,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge
> > *bridge,
> > regmap_write(priv->regmap, 0x15, vbporch);
> > regmap_write(priv->regmap, 0x16, vsynclen);
> >
> > - /* Input color swap. Byte order is optional and will default to
> > - * BYTE_SWAP_BGR to preserve backwards compatibility with existing
> > - * driver.
> > - */
> > - ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
> > - _swap);
> > - if (!ret && byte_swap < BYTE_SWAP_MAX)
> > - regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
> > - else
> > - regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
> > + /* Input color swap. */
> > + regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
> >
> > /* Input clock and sync polarity. */
> > regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
>
> --
> Regards,
>
> Laurent Pinchart
Re: [PATCH] dma-buf: fix dma_fence_default_wait() signaling check
On Mon, Sep 19, 2022 at 8:06 AM Christian König
wrote:
>
> That check must now come after grabing the spinlock, not before.
>
> Signed-off-by: Christian König
> Fixes: b96fb1e724ae ("dma-buf: dma_fence_wait must enable signaling")
Acked-by: Alex Deucher
> ---
> drivers/dma-buf/dma-fence.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
> index a5fbf1c1e0ea..406b4e26f538 100644
> --- a/drivers/dma-buf/dma-fence.c
> +++ b/drivers/dma-buf/dma-fence.c
> @@ -763,11 +763,11 @@ dma_fence_default_wait(struct dma_fence *fence, bool
> intr, signed long timeout)
> unsigned long flags;
> signed long ret = timeout ? timeout : 1;
>
> - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
> - return ret;
> -
> spin_lock_irqsave(fence->lock, flags);
>
> + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
> + goto out;
> +
> if (intr && signal_pending(current)) {
> ret = -ERESTARTSYS;
> goto out;
> --
> 2.25.1
>
[PATCH 15/16] drm/udl: Add register constants for framebuffer scanout addresses
Add register constants for the framebuffer scanout addresses and
update the related helper functions. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 28
drivers/gpu/drm/udl/udl_proto.h | 8
2 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index b6aebfaae03d..df0b70f3ddf1 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -59,23 +59,35 @@ static char *udl_set_color_depth(char *buf, u8 selection)
return udl_set_register(buf, UDL_REG_COLORDEPTH, selection);
}
-static char *udl_set_base16bpp(char *wrptr, u32 base)
+static char *udl_set_base16bpp(char *buf, u32 base)
{
/* the base pointer is 16 bits wide, 0x20 is hi byte. */
- wrptr = udl_set_register(wrptr, 0x20, base >> 16);
- wrptr = udl_set_register(wrptr, 0x21, base >> 8);
- return udl_set_register(wrptr, 0x22, base);
+ u8 reg20 = (base & 0xff) >> 16;
+ u8 reg21 = (base & 0x00ff00) >> 8;
+ u8 reg22 = (base & 0xff);
+
+ buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR2, reg20);
+ buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR1, reg21);
+ buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR0, reg22);
+
+ return buf;
}
/*
* DisplayLink HW has separate 16bpp and 8bpp framebuffers.
* In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
*/
-static char *udl_set_base8bpp(char *wrptr, u32 base)
+static char *udl_set_base8bpp(char *buf, u32 base)
{
- wrptr = udl_set_register(wrptr, 0x26, base >> 16);
- wrptr = udl_set_register(wrptr, 0x27, base >> 8);
- return udl_set_register(wrptr, 0x28, base);
+ u8 reg26 = (base & 0xff) >> 16;
+ u8 reg27 = (base & 0x00ff00) >> 8;
+ u8 reg28 = (base & 0xff);
+
+ buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR2, reg26);
+ buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR1, reg27);
+ buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR0, reg28);
+
+ return buf;
}
static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
diff --git a/drivers/gpu/drm/udl/udl_proto.h b/drivers/gpu/drm/udl/udl_proto.h
index 8e7d1a090644..3e7fcb43cb04 100644
--- a/drivers/gpu/drm/udl/udl_proto.h
+++ b/drivers/gpu/drm/udl/udl_proto.h
@@ -31,6 +31,14 @@
#define UDL_BLANKMODE_HSYNC_OFF0x05 /* hsync off, blanked */
#define UDL_BLANKMODE_POWERDOWN0x07 /* powered off; requires
modeset */
+/* Framebuffer address */
+#define UDL_REG_BASE16BPP_ADDR20x20
+#define UDL_REG_BASE16BPP_ADDR10x21
+#define UDL_REG_BASE16BPP_ADDR00x22
+#define UDL_REG_BASE8BPP_ADDR2 0x26
+#define UDL_REG_BASE8BPP_ADDR1 0x27
+#define UDL_REG_BASE8BPP_ADDR0 0x28
+
/* Lock/unlock video registers */
#define UDL_REG_VIDREG 0xff
#define UDL_VIDREG_LOCK0x00
--
2.37.3
[PATCH 16/16] drm/udl: Add constants for commands
Add constants for the various commands that the driver can send to
the device and update the respective helper functions. No functional
changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_drv.h | 10 --
drivers/gpu/drm/udl/udl_modeset.c | 16 +---
drivers/gpu/drm/udl/udl_proto.h| 15 +++
drivers/gpu/drm/udl/udl_transfer.c | 7 ---
4 files changed, 28 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_drv.h b/drivers/gpu/drm/udl/udl_drv.h
index 580989087c54..282ebd6c02fd 100644
--- a/drivers/gpu/drm/udl/udl_drv.h
+++ b/drivers/gpu/drm/udl/udl_drv.h
@@ -102,14 +102,4 @@ int udl_render_hline(struct drm_device *dev, int log_bpp,
struct urb **urb_ptr,
int udl_drop_usb(struct drm_device *dev);
int udl_select_std_channel(struct udl_device *udl);
-#define CMD_WRITE_RAW8 "\xAF\x60" /**< 8 bit raw write command. */
-#define CMD_WRITE_RL8"\xAF\x61" /**< 8 bit run length command. */
-#define CMD_WRITE_COPY8 "\xAF\x62" /**< 8 bit copy command. */
-#define CMD_WRITE_RLX8 "\xAF\x63" /**< 8 bit extended run length command. */
-
-#define CMD_WRITE_RAW16 "\xAF\x68" /**< 16 bit raw write command. */
-#define CMD_WRITE_RL16 "\xAF\x69" /**< 16 bit run length command. */
-#define CMD_WRITE_COPY16 "\xAF\x6A" /**< 16 bit copy command. */
-#define CMD_WRITE_RLX16 "\xAF\x6B" /**< 16 bit extended run length command. */
-
#endif
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index df0b70f3ddf1..1814bc84effe 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -27,15 +27,17 @@
#include "udl_proto.h"
/*
- * All DisplayLink bulk operations start with 0xAF, followed by specific code
- * All operations are written to buffers which then later get sent to device
+ * All DisplayLink bulk operations start with 0xaf (UDL_MSG_BULK), followed by
+ * a specific command code. All operations are written to a command buffer,
which
+ * the driver sends to the device.
*/
static char *udl_set_register(char *buf, u8 reg, u8 val)
{
- *buf++ = 0xAF;
- *buf++ = 0x20;
+ *buf++ = UDL_MSG_BULK;
+ *buf++ = UDL_CMD_WRITEREG;
*buf++ = reg;
*buf++ = val;
+
return buf;
}
@@ -176,8 +178,8 @@ static char *udl_set_display_mode(char *buf, struct
drm_display_mode *mode)
static char *udl_dummy_render(char *wrptr)
{
- *wrptr++ = 0xAF;
- *wrptr++ = 0x6A; /* copy */
+ *wrptr++ = UDL_MSG_BULK;
+ *wrptr++ = UDL_CMD_WRITECOPY16;
*wrptr++ = 0x00; /* from addr */
*wrptr++ = 0x00;
*wrptr++ = 0x00;
@@ -232,7 +234,7 @@ static int udl_handle_damage(struct drm_framebuffer *fb,
/* Send partial buffer remaining before exiting */
int len;
if (cmd < (char *)urb->transfer_buffer +
urb->transfer_buffer_length)
- *cmd++ = 0xAF;
+ *cmd++ = UDL_MSG_BULK;
len = cmd - (char *)urb->transfer_buffer;
ret = udl_submit_urb(dev, urb, len);
} else {
diff --git a/drivers/gpu/drm/udl/udl_proto.h b/drivers/gpu/drm/udl/udl_proto.h
index 3e7fcb43cb04..b3b199ffc616 100644
--- a/drivers/gpu/drm/udl/udl_proto.h
+++ b/drivers/gpu/drm/udl/udl_proto.h
@@ -3,6 +3,21 @@
#ifndef UDL_PROTO_H
#define UDL_PROTO_H
+#define UDL_MSG_BULK 0xaf
+
+/* Register access */
+#define UDL_CMD_WRITEREG 0x20 /* See register constants below */
+
+/* Framebuffer access */
+#define UDL_CMD_WRITERAW8 0x60 /* 8 bit raw write command. */
+#define UDL_CMD_WRITERL8 0x61 /* 8 bit run length command. */
+#define UDL_CMD_WRITECOPY8 0x62 /* 8 bit copy command. */
+#define UDL_CMD_WRITERLX8 0x63 /* 8 bit extended run length command. */
+#define UDL_CMD_WRITERAW16 0x68 /* 16 bit raw write command. */
+#define UDL_CMD_WRITERL16 0x69 /* 16 bit run length command. */
+#define UDL_CMD_WRITECOPY160x6a /* 16 bit copy command. */
+#define UDL_CMD_WRITERLX16 0x6b /* 16 bit extended run length command. */
+
/* Color depth */
#define UDL_REG_COLORDEPTH 0x00
#define UDL_COLORDEPTH_16BPP 0
diff --git a/drivers/gpu/drm/udl/udl_transfer.c
b/drivers/gpu/drm/udl/udl_transfer.c
index b57844632dbd..5ff1037a3453 100644
--- a/drivers/gpu/drm/udl/udl_transfer.c
+++ b/drivers/gpu/drm/udl/udl_transfer.c
@@ -10,6 +10,7 @@
#include
#include "udl_drv.h"
+#include "udl_proto.h"
#define MAX_CMD_PIXELS 255
@@ -89,8 +90,8 @@ static void udl_compress_hline16(
const u8 *cmd_pixel_start, *cmd_pixel_end = NULL;
uint16_t pixel_val16;
- *cmd++ = 0xaf;
- *cmd++ = 0x6b;
+ *cmd++ = UDL_MSG_BULK;
+ *cmd++ = UDL_CMD_WRITERLX16;
*cmd++ = (uint8_t) ((dev_addr >> 16) & 0xFF);
*cmd++ = (uint8_t) ((dev_addr >> 8) & 0xFF);
*cmd++ =
[PATCH 12/16] drm/udl: Add constants for display-mode registers
Add constants for the registers the contain various display-mode
parameters and update the mode-setting function. No functional
changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 102 ++
drivers/gpu/drm/udl/udl_proto.h | 15 +
2 files changed, 47 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index e80ed218563e..04135ebd41d3 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -126,78 +126,40 @@ static char *udl_set_register_lfsr16(char *wrptr, u8 reg,
u16 value)
}
/*
- * This takes a standard fbdev screeninfo struct and all of its monitor mode
- * details and converts them into the DisplayLink equivalent register commands.
- ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1));
- ERR(vreg_lfsr16(dev,0x01, xDisplayStart));
- ERR(vreg_lfsr16(dev,0x03, xDisplayEnd));
- ERR(vreg_lfsr16(dev,0x05, yDisplayStart));
- ERR(vreg_lfsr16(dev,0x07, yDisplayEnd));
- ERR(vreg_lfsr16(dev,0x09, xEndCount));
- ERR(vreg_lfsr16(dev,0x0B, hSyncStart));
- ERR(vreg_lfsr16(dev,0x0D, hSyncEnd));
- ERR(vreg_big_endian(dev,0x0F, hPixels));
- ERR(vreg_lfsr16(dev,0x11, yEndCount));
- ERR(vreg_lfsr16(dev,0x13, vSyncStart));
- ERR(vreg_lfsr16(dev,0x15, vSyncEnd));
- ERR(vreg_big_endian(dev,0x17, vPixels));
- ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
-
- ERR(vreg(dev, 0x1F, 0));
-
- ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
+ * Takes a DRM display mode and converts it into the DisplayLink
+ * equivalent register commands.
*/
-static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
+static char *udl_set_display_mode(char *buf, struct drm_display_mode *mode)
{
- u16 xds, yds;
- u16 xde, yde;
- u16 yec;
+ u16 reg01 = mode->crtc_htotal - mode->crtc_hsync_start;
+ u16 reg03 = reg01 + mode->crtc_hdisplay;
+ u16 reg05 = mode->crtc_vtotal - mode->crtc_vsync_start;
+ u16 reg07 = reg05 + mode->crtc_vdisplay;
+ u16 reg09 = mode->crtc_htotal - 1;
+ u16 reg0b = 1; /* libdlo hardcodes hsync start to 1 */
+ u16 reg0d = mode->crtc_hsync_end - mode->crtc_hsync_start + 1;
+ u16 reg0f = mode->hdisplay;
+ u16 reg11 = mode->crtc_vtotal;
+ u16 reg13 = 0; /* libdlo hardcodes vsync start to 0 */
+ u16 reg15 = mode->crtc_vsync_end - mode->crtc_vsync_start;
+ u16 reg17 = mode->crtc_vdisplay;
+ u16 reg1b = mode->clock / 5;
+
+ buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYSTART, reg01);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYEND, reg03);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYSTART, reg05);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYEND, reg07);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_XENDCOUNT, reg09);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCSTART, reg0b);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCEND, reg0d);
+ buf = udl_set_register_16(buf, UDL_REG_HPIXELS, reg0f);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_YENDCOUNT, reg11);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCSTART, reg13);
+ buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCEND, reg15);
+ buf = udl_set_register_16(buf, UDL_REG_VPIXELS, reg17);
+ buf = udl_set_register_16be(buf, UDL_REG_PIXELCLOCK5KHZ, reg1b);
- /* x display start */
- xds = mode->crtc_htotal - mode->crtc_hsync_start;
- wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
- /* x display end */
- xde = xds + mode->crtc_hdisplay;
- wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
-
- /* y display start */
- yds = mode->crtc_vtotal - mode->crtc_vsync_start;
- wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
- /* y display end */
- yde = yds + mode->crtc_vdisplay;
- wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
-
- /* x end count is active + blanking - 1 */
- wrptr = udl_set_register_lfsr16(wrptr, 0x09,
- mode->crtc_htotal - 1);
-
- /* libdlo hardcodes hsync start to 1 */
- wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
-
- /* hsync end is width of sync pulse + 1 */
- wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
- mode->crtc_hsync_end -
mode->crtc_hsync_start + 1);
-
- /* hpixels is active pixels */
- wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
-
- /* yendcount is vertical active + vertical blanking */
- yec = mode->crtc_vtotal;
- wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
-
- /* libdlo hardcodes vsync start to 0 */
- wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
-
- /*
[PATCH 09/16] drm/udl: Support DRM hot-unplugging
Add drm_dev_enter() and drm_dev_exit() to the various modesetting
functions that interact with the device. After hot-unplugging the
device, these functions will return early. So far, the udl driver
relied on USB interfaces to handle unplugging of the device.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 43 ++-
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index 97d68cf88bd8..aaa828034a04 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -295,14 +296,21 @@ static const uint64_t udl_primary_plane_fmtmods[] = {
static void udl_primary_plane_helper_atomic_update(struct drm_plane *plane,
struct drm_atomic_state
*state)
{
+ struct drm_device *dev = plane->dev;
struct drm_plane_state *plane_state =
drm_atomic_get_new_plane_state(state, plane);
struct drm_shadow_plane_state *shadow_plane_state =
to_drm_shadow_plane_state(plane_state);
struct drm_framebuffer *fb = plane_state->fb;
struct drm_plane_state *old_plane_state =
drm_atomic_get_old_plane_state(state, plane);
struct drm_rect rect;
+ int idx;
+
+ if (!drm_dev_enter(dev, ))
+ return;
if (drm_atomic_helper_damage_merged(old_plane_state, plane_state,
))
udl_handle_damage(fb, _plane_state->data[0], );
+
+ drm_dev_exit(idx);
}
static void udl_primary_plane_helper_atomic_disable(struct drm_plane *plane,
@@ -348,10 +356,14 @@ static void udl_crtc_helper_atomic_enable(struct drm_crtc
*crtc, struct drm_atom
struct drm_display_mode *mode = _state->mode;
struct urb *urb;
char *buf;
+ int idx;
+
+ if (!drm_dev_enter(dev, ))
+ return;
urb = udl_get_urb(dev);
if (!urb)
- return;
+ goto out;
buf = (char *)urb->transfer_buffer;
buf = udl_vidreg_lock(buf);
@@ -366,6 +378,9 @@ static void udl_crtc_helper_atomic_enable(struct drm_crtc
*crtc, struct drm_atom
buf = udl_dummy_render(buf);
udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
+
+out:
+ drm_dev_exit(idx);
}
static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct
drm_atomic_state *state)
@@ -373,10 +388,14 @@ static void udl_crtc_helper_atomic_disable(struct
drm_crtc *crtc, struct drm_ato
struct drm_device *dev = crtc->dev;
struct urb *urb;
char *buf;
+ int idx;
+
+ if (!drm_dev_enter(dev, ))
+ return;
urb = udl_get_urb(dev);
if (!urb)
- return;
+ goto out;
buf = (char *)urb->transfer_buffer;
buf = udl_vidreg_lock(buf);
@@ -385,6 +404,9 @@ static void udl_crtc_helper_atomic_disable(struct drm_crtc
*crtc, struct drm_ato
buf = udl_dummy_render(buf);
udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
+
+out:
+ drm_dev_exit(idx);
}
static const struct drm_crtc_helper_funcs udl_crtc_helper_funcs = {
@@ -471,17 +493,26 @@ static int udl_get_edid_block(void *data, u8 *buf,
unsigned int block, size_t le
static enum drm_connector_status udl_connector_detect(struct drm_connector
*connector, bool force)
{
- struct udl_device *udl = to_udl(connector->dev);
+ struct drm_device *dev = connector->dev;
+ struct udl_device *udl = to_udl(dev);
struct udl_connector *udl_connector = to_udl_connector(connector);
+ enum drm_connector_status status = connector_status_disconnected;
+ int idx;
/* cleanup previous EDID */
kfree(udl_connector->edid);
+ udl_connector->edid = NULL;
- udl_connector->edid = drm_do_get_edid(connector, udl_get_edid_block,
udl);
- if (!udl_connector->edid)
+ if (!drm_dev_enter(dev, ))
return connector_status_disconnected;
- return connector_status_connected;
+ udl_connector->edid = drm_do_get_edid(connector, udl_get_edid_block,
udl);
+ if (udl_connector->edid)
+ status = connector_status_connected;
+
+ drm_dev_exit(idx);
+
+ return status;
}
static void udl_connector_destroy(struct drm_connector *connector)
--
2.37.3
[PATCH 07/16] drm/udl: Convert to atomic-modesetting helpers
Replace simple-KMS helpers with regular atomic-modesetting helpers.
The simple-KMS helpers introduce a mid-layer abstraction without
added functionality. Using regular atomic helpers makes the driver's
implementation more discoverable and simplifies code sharing.
The conversion effectively open-codes the simple-KMS functions and
data structure within udl. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_drv.h | 9 +-
drivers/gpu/drm/udl/udl_modeset.c | 166 --
2 files changed, 121 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_drv.h b/drivers/gpu/drm/udl/udl_drv.h
index d7a3d495f2e7..e96166ce2919 100644
--- a/drivers/gpu/drm/udl/udl_drv.h
+++ b/drivers/gpu/drm/udl/udl_drv.h
@@ -14,10 +14,13 @@
#include
#include
+#include
+#include
#include
+#include
#include
#include
-#include
+#include
struct drm_mode_create_dumb;
@@ -62,7 +65,9 @@ struct udl_device {
struct device *dev;
struct device *dmadev;
- struct drm_simple_display_pipe display_pipe;
+ struct drm_plane primary_plane;
+ struct drm_crtc crtc;
+ struct drm_encoder encoder;
struct mutex gem_lock;
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index 7f8bde89396d..f83d0feff434 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -8,6 +8,7 @@
* Copyright (C) 2009 Bernie Thompson
*/
+#include
#include
#include
#include
@@ -17,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -302,61 +304,105 @@ static int udl_handle_damage(struct drm_framebuffer *fb,
}
/*
- * Simple display pipeline
+ * Primary plane
*/
-static const uint32_t udl_simple_display_pipe_formats[] = {
+static const uint32_t udl_primary_plane_formats[] = {
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB,
};
-static void
-udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
- struct drm_crtc_state *crtc_state,
- struct drm_plane_state *plane_state)
+static const uint64_t udl_primary_plane_fmtmods[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static void udl_primary_plane_helper_atomic_update(struct drm_plane *plane,
+ struct drm_atomic_state
*state)
{
- struct drm_crtc *crtc = >crtc;
- struct drm_device *dev = crtc->dev;
+ struct drm_plane_state *plane_state =
drm_atomic_get_new_plane_state(state, plane);
+ struct drm_shadow_plane_state *shadow_plane_state =
to_drm_shadow_plane_state(plane_state);
struct drm_framebuffer *fb = plane_state->fb;
+ struct drm_plane_state *old_plane_state =
drm_atomic_get_old_plane_state(state, plane);
+ struct drm_rect rect;
+
+ if (drm_atomic_helper_damage_merged(old_plane_state, plane_state,
))
+ udl_handle_damage(fb, _plane_state->data[0], );
+}
+
+static void udl_primary_plane_helper_atomic_disable(struct drm_plane *plane,
+ struct drm_atomic_state
*state)
+{
+ /*
+* Keep this function here to avoid calling atomic_update when
+* the plane is being disabled.
+*
+* TODO: Maybe clear the adapter's display buffer from here.
+*/
+}
+
+static const struct drm_plane_helper_funcs udl_primary_plane_helper_funcs = {
+ DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
+ .atomic_check = drm_plane_helper_atomic_check,
+ .atomic_update = udl_primary_plane_helper_atomic_update,
+ .atomic_disable = udl_primary_plane_helper_atomic_disable,
+};
+
+static const struct drm_plane_funcs udl_primary_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = drm_plane_cleanup,
+ DRM_GEM_SHADOW_PLANE_FUNCS,
+};
+
+/*
+ * CRTC
+ */
+
+static int udl_crtc_helper_atomic_check(struct drm_crtc *crtc, struct
drm_atomic_state *state)
+{
+ struct drm_crtc_state *new_crtc_state =
drm_atomic_get_new_crtc_state(state, crtc);
+
+ return drm_atomic_helper_check_crtc_state(new_crtc_state, false);
+}
+
+static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct
drm_atomic_state *state)
+{
+ struct drm_device *dev = crtc->dev;
struct udl_device *udl = to_udl(dev);
+ struct drm_crtc_state *crtc_state =
drm_atomic_get_new_crtc_state(state, crtc);
struct drm_display_mode *mode = _state->mode;
- struct drm_shadow_plane_state *shadow_plane_state =
to_drm_shadow_plane_state(plane_state);
- struct drm_rect clip = DRM_RECT_INIT(0, 0, fb->width, fb->height);
char *buf;
char *wrptr;
int color_depth = UDL_COLOR_DEPTH_16BPP;
buf = (char *)udl->mode_buf;
- /* This first section has to do
[PATCH 00/16] drm/udl: Better modesetting, hot-unplug, protocol
This patchset reworks the udl driver's modesetting code. Patches #1 to #5 improve the connector code with various updates. Patches #6 to #10 improve the modesetting code. Patch #7 replaces the simple-KMS helpers with the regular atomic helpers. Patch #9 adds DRM hot-unplugging. The driver had some unplugging support via USB functions, the DRM side was probably not prepared yet. Patch #10 changes damage updates to the damage iterator. This minimizes the amount of data to send over USB. Patches #11 to #16 add protocol constants for the various UDL display operations. Tested with X11, console and Weston. Thomas Zimmermann (16): drm/udl: Rename struct udl_drm_connector to struct udl_connector drm/udl: Test pixel limit in mode-config's mode-valid function drm/udl: Use USB timeout constant when reading EDID drm/udl: Various improvements to the connector drm/udl: Move connector to modesetting code drm/udl: Remove udl_simple_display_pipe_mode_valid() drm/udl: Convert to atomic-modesetting helpers drm/udl: Simplify modesetting in CRTC's enable function drm/udl: Support DRM hot-unplugging drm/udl: Use damage iterator drm/udl: Move register constants to udl_proto.h drm/udl: Add constants for display-mode registers drm/udl: Add register constants for color depth drm/udl: Add register constants for video locks drm/udl: Add register constants for framebuffer scanout addresses drm/udl: Add constants for commands drivers/gpu/drm/udl/Makefile| 2 +- drivers/gpu/drm/udl/udl_connector.c | 139 --- drivers/gpu/drm/udl/udl_connector.h | 15 - drivers/gpu/drm/udl/udl_drv.h | 42 +-- drivers/gpu/drm/udl/udl_modeset.c | 567 ++-- drivers/gpu/drm/udl/udl_proto.h | 62 +++ drivers/gpu/drm/udl/udl_transfer.c | 7 +- 7 files changed, 450 insertions(+), 384 deletions(-) delete mode 100644 drivers/gpu/drm/udl/udl_connector.c delete mode 100644 drivers/gpu/drm/udl/udl_connector.h create mode 100644 drivers/gpu/drm/udl/udl_proto.h base-commit: d8deedaa0fcd8192715a052a0239bee3f74a8fb1 -- 2.37.3
[PATCH 03/16] drm/udl: Use USB timeout constant when reading EDID
Set the USB control-message timeout to the USB default of 5 seconds.
Done for consistency with other uses of usb_control_msg() in udl and
other drivers.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_connector.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/udl/udl_connector.c
b/drivers/gpu/drm/udl/udl_connector.c
index e9539829032c..cb3d6820eaf9 100644
--- a/drivers/gpu/drm/udl/udl_connector.c
+++ b/drivers/gpu/drm/udl/udl_connector.c
@@ -31,7 +31,7 @@ static int udl_get_edid_block(void *data, u8 *buf, unsigned
int block,
int bval = (i + block * EDID_LENGTH) << 8;
ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
0x02, (0x80 | (0x02 << 5)), bval,
- 0xA1, read_buff, 2, 1000);
+ 0xA1, read_buff, 2, USB_CTRL_GET_TIMEOUT);
if (ret < 1) {
DRM_ERROR("Read EDID byte %d failed err %x\n", i, ret);
kfree(read_buff);
--
2.37.3
[PATCH 13/16] drm/udl: Add register constants for color depth
Add the register constants for setting the color depth. The driver
only uses 16bpp. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 2 +-
drivers/gpu/drm/udl/udl_proto.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index 04135ebd41d3..1e28eb1e295f 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -56,7 +56,7 @@ static char *udl_set_blank_mode(char *buf, u8 mode)
static char *udl_set_color_depth(char *buf, u8 selection)
{
- return udl_set_register(buf, 0x00, selection);
+ return udl_set_register(buf, UDL_REG_COLORDEPTH, selection);
}
static char *udl_set_base16bpp(char *wrptr, u32 base)
diff --git a/drivers/gpu/drm/udl/udl_proto.h b/drivers/gpu/drm/udl/udl_proto.h
index 5a6c960bd10d..22bc1ae8420c 100644
--- a/drivers/gpu/drm/udl/udl_proto.h
+++ b/drivers/gpu/drm/udl/udl_proto.h
@@ -3,7 +3,10 @@
#ifndef UDL_PROTO_H
#define UDL_PROTO_H
+/* Color depth */
+#define UDL_REG_COLORDEPTH 0x00
#define UDL_COLORDEPTH_16BPP 0
+#define UDL_COLORDEPTH_24BPP 1
/* Display-mode settings */
#define UDL_REG_XDISPLAYSTART 0x01
--
2.37.3
[PATCH 11/16] drm/udl: Move register constants to udl_proto.h
Move the existing register constants to a new file in preparation of
adding more of them. Renaming is intentional. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_drv.h | 9 -
drivers/gpu/drm/udl/udl_modeset.c | 11 +--
drivers/gpu/drm/udl/udl_proto.h | 16
3 files changed, 21 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/udl/udl_proto.h
diff --git a/drivers/gpu/drm/udl/udl_drv.h b/drivers/gpu/drm/udl/udl_drv.h
index b090b6cebdc4..580989087c54 100644
--- a/drivers/gpu/drm/udl/udl_drv.h
+++ b/drivers/gpu/drm/udl/udl_drv.h
@@ -112,13 +112,4 @@ int udl_select_std_channel(struct udl_device *udl);
#define CMD_WRITE_COPY16 "\xAF\x6A" /**< 16 bit copy command. */
#define CMD_WRITE_RLX16 "\xAF\x6B" /**< 16 bit extended run length command. */
-/* On/Off for driving the DisplayLink framebuffer to the display */
-#define UDL_REG_BLANK_MODE 0x1f
-
-#define UDL_BLANK_MODE_ON 0x00 /* hsync and vsync on, visible */
-#define UDL_BLANK_MODE_BLANKED 0x01 /* hsync and vsync on, blanked */
-#define UDL_BLANK_MODE_VSYNC_OFF 0x03 /* vsync off, blanked */
-#define UDL_BLANK_MODE_HSYNC_OFF 0x05 /* hsync off, blanked */
-#define UDL_BLANK_MODE_POWERDOWN 0x07 /* powered off; requires modeset */
-
#endif
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index 6fa4c8b5c2c6..e80ed218563e 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -24,8 +24,7 @@
#include
#include "udl_drv.h"
-
-#define UDL_COLOR_DEPTH_16BPP 0
+#include "udl_proto.h"
/*
* All DisplayLink bulk operations start with 0xAF, followed by specific code
@@ -52,7 +51,7 @@ static char *udl_vidreg_unlock(char *buf)
static char *udl_set_blank_mode(char *buf, u8 mode)
{
- return udl_set_register(buf, UDL_REG_BLANK_MODE, mode);
+ return udl_set_register(buf, UDL_REG_BLANKMODE, mode);
}
static char *udl_set_color_depth(char *buf, u8 selection)
@@ -367,13 +366,13 @@ static void udl_crtc_helper_atomic_enable(struct drm_crtc
*crtc, struct drm_atom
buf = (char *)urb->transfer_buffer;
buf = udl_vidreg_lock(buf);
- buf = udl_set_color_depth(buf, UDL_COLOR_DEPTH_16BPP);
+ buf = udl_set_color_depth(buf, UDL_COLORDEPTH_16BPP);
/* set base for 16bpp segment to 0 */
buf = udl_set_base16bpp(buf, 0);
/* set base for 8bpp segment to end of fb */
buf = udl_set_base8bpp(buf, 2 * mode->vdisplay * mode->hdisplay);
buf = udl_set_vid_cmds(buf, mode);
- buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_ON);
+ buf = udl_set_blank_mode(buf, UDL_BLANKMODE_ON);
buf = udl_vidreg_unlock(buf);
buf = udl_dummy_render(buf);
@@ -399,7 +398,7 @@ static void udl_crtc_helper_atomic_disable(struct drm_crtc
*crtc, struct drm_ato
buf = (char *)urb->transfer_buffer;
buf = udl_vidreg_lock(buf);
- buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN);
+ buf = udl_set_blank_mode(buf, UDL_BLANKMODE_POWERDOWN);
buf = udl_vidreg_unlock(buf);
buf = udl_dummy_render(buf);
diff --git a/drivers/gpu/drm/udl/udl_proto.h b/drivers/gpu/drm/udl/udl_proto.h
new file mode 100644
index ..3f5b8e832b99
--- /dev/null
+++ b/drivers/gpu/drm/udl/udl_proto.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef UDL_PROTO_H
+#define UDL_PROTO_H
+
+#define UDL_COLORDEPTH_16BPP 0
+
+/* On/Off for driving the DisplayLink framebuffer to the display */
+#define UDL_REG_BLANKMODE 0x1f
+#define UDL_BLANKMODE_ON 0x00 /* hsync and vsync on, visible */
+#define UDL_BLANKMODE_BLANKED 0x01 /* hsync and vsync on, blanked */
+#define UDL_BLANKMODE_VSYNC_OFF0x03 /* vsync off, blanked */
+#define UDL_BLANKMODE_HSYNC_OFF0x05 /* hsync off, blanked */
+#define UDL_BLANKMODE_POWERDOWN0x07 /* powered off; requires
modeset */
+
+#endif
--
2.37.3
[PATCH 08/16] drm/udl: Simplify modesetting in CRTC's enable function
Inline a modesetting helper in the CRTC's enable function. Build the
command set directly in the USB URB's buffer and drop an intermediate
buffer. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_drv.h | 3 --
drivers/gpu/drm/udl/udl_modeset.c | 61 +++
2 files changed, 14 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_drv.h b/drivers/gpu/drm/udl/udl_drv.h
index e96166ce2919..b090b6cebdc4 100644
--- a/drivers/gpu/drm/udl/udl_drv.h
+++ b/drivers/gpu/drm/udl/udl_drv.h
@@ -74,9 +74,6 @@ struct udl_device {
int sku_pixel_limit;
struct urb_list urbs;
-
- char mode_buf[1024];
- uint32_t mode_buf_len;
};
#define to_udl(x) container_of(x, struct udl_device, drm)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index f83d0feff434..97d68cf88bd8 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -214,31 +214,6 @@ static char *udl_dummy_render(char *wrptr)
return wrptr;
}
-static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
-{
- struct drm_device *dev = crtc->dev;
- struct udl_device *udl = to_udl(dev);
- struct urb *urb;
- char *buf;
- int retval;
-
- if (udl->mode_buf_len == 0) {
- DRM_ERROR("No mode set\n");
- return -EINVAL;
- }
-
- urb = udl_get_urb(dev);
- if (!urb)
- return -ENOMEM;
-
- buf = (char *)urb->transfer_buffer;
-
- memcpy(buf, udl->mode_buf, udl->mode_buf_len);
- retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
- DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
- return retval;
-}
-
static long udl_log_cpp(unsigned int cpp)
{
if (WARN_ON(!is_power_of_2(cpp)))
@@ -369,36 +344,28 @@ static int udl_crtc_helper_atomic_check(struct drm_crtc
*crtc, struct drm_atomic
static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct
drm_atomic_state *state)
{
struct drm_device *dev = crtc->dev;
- struct udl_device *udl = to_udl(dev);
struct drm_crtc_state *crtc_state =
drm_atomic_get_new_crtc_state(state, crtc);
struct drm_display_mode *mode = _state->mode;
+ struct urb *urb;
char *buf;
- char *wrptr;
- int color_depth = UDL_COLOR_DEPTH_16BPP;
-
- buf = (char *)udl->mode_buf;
- /*
-* This first section has to do with setting the base address on
-* the controller associated with the display. There are 2 base
-* pointers. Currently, we only use the 16 bpp segment.
-*/
+ urb = udl_get_urb(dev);
+ if (!urb)
+ return;
- wrptr = udl_vidreg_lock(buf);
- wrptr = udl_set_color_depth(wrptr, color_depth);
+ buf = (char *)urb->transfer_buffer;
+ buf = udl_vidreg_lock(buf);
+ buf = udl_set_color_depth(buf, UDL_COLOR_DEPTH_16BPP);
/* set base for 16bpp segment to 0 */
- wrptr = udl_set_base16bpp(wrptr, 0);
+ buf = udl_set_base16bpp(buf, 0);
/* set base for 8bpp segment to end of fb */
- wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
- wrptr = udl_set_vid_cmds(wrptr, mode);
- wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON);
- wrptr = udl_vidreg_unlock(wrptr);
- wrptr = udl_dummy_render(wrptr);
-
- udl->mode_buf_len = wrptr - buf;
+ buf = udl_set_base8bpp(buf, 2 * mode->vdisplay * mode->hdisplay);
+ buf = udl_set_vid_cmds(buf, mode);
+ buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_ON);
+ buf = udl_vidreg_unlock(buf);
+ buf = udl_dummy_render(buf);
- /* enable display */
- udl_crtc_write_mode_to_hw(crtc);
+ udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
}
static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct
drm_atomic_state *state)
--
2.37.3
[PATCH 14/16] drm/udl: Add register constants for video locks
Add register constants for the video lock. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 4 ++--
drivers/gpu/drm/udl/udl_proto.h | 5 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index 1e28eb1e295f..b6aebfaae03d 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -41,12 +41,12 @@ static char *udl_set_register(char *buf, u8 reg, u8 val)
static char *udl_vidreg_lock(char *buf)
{
- return udl_set_register(buf, 0xFF, 0x00);
+ return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_LOCK);
}
static char *udl_vidreg_unlock(char *buf)
{
- return udl_set_register(buf, 0xFF, 0xFF);
+ return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_UNLOCK);
}
static char *udl_set_blank_mode(char *buf, u8 mode)
diff --git a/drivers/gpu/drm/udl/udl_proto.h b/drivers/gpu/drm/udl/udl_proto.h
index 22bc1ae8420c..8e7d1a090644 100644
--- a/drivers/gpu/drm/udl/udl_proto.h
+++ b/drivers/gpu/drm/udl/udl_proto.h
@@ -31,4 +31,9 @@
#define UDL_BLANKMODE_HSYNC_OFF0x05 /* hsync off, blanked */
#define UDL_BLANKMODE_POWERDOWN0x07 /* powered off; requires
modeset */
+/* Lock/unlock video registers */
+#define UDL_REG_VIDREG 0xff
+#define UDL_VIDREG_LOCK0x00
+#define UDL_VIDREG_UNLOCK 0xff
+
#endif
--
2.37.3
[PATCH 10/16] drm/udl: Use damage iterator
Use a damage iterator to process damage areas individually. Merging
damage areas can resul tin large updates of unchanged framebuffer
regions. As USB is rather slow, it's better to process damage areas
individually and hence minimize USB-transfered data.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 38 +++
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index aaa828034a04..6fa4c8b5c2c6 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -238,15 +238,9 @@ static int udl_handle_damage(struct drm_framebuffer *fb,
return ret;
log_bpp = ret;
- ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
- if (ret)
- return ret;
-
urb = udl_get_urb(dev);
- if (!urb) {
- ret = -ENOMEM;
- goto out_drm_gem_fb_end_cpu_access;
- }
+ if (!urb)
+ return -ENOMEM;
cmd = urb->transfer_buffer;
for (i = clip->y1; i < clip->y2; i++) {
@@ -258,7 +252,7 @@ static int udl_handle_damage(struct drm_framebuffer *fb,
, byte_offset, dev_byte_offset,
byte_width);
if (ret)
- goto out_drm_gem_fb_end_cpu_access;
+ return ret;
}
if (cmd > (char *)urb->transfer_buffer) {
@@ -272,11 +266,7 @@ static int udl_handle_damage(struct drm_framebuffer *fb,
udl_urb_completion(urb);
}
- ret = 0;
-
-out_drm_gem_fb_end_cpu_access:
- drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
- return ret;
+ return 0;
}
/*
@@ -301,16 +291,26 @@ static void udl_primary_plane_helper_atomic_update(struct
drm_plane *plane,
struct drm_shadow_plane_state *shadow_plane_state =
to_drm_shadow_plane_state(plane_state);
struct drm_framebuffer *fb = plane_state->fb;
struct drm_plane_state *old_plane_state =
drm_atomic_get_old_plane_state(state, plane);
- struct drm_rect rect;
- int idx;
+ struct drm_atomic_helper_damage_iter iter;
+ struct drm_rect damage;
+ int ret, idx;
- if (!drm_dev_enter(dev, ))
+ ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
+ if (ret)
return;
- if (drm_atomic_helper_damage_merged(old_plane_state, plane_state,
))
- udl_handle_damage(fb, _plane_state->data[0], );
+ if (!drm_dev_enter(dev, ))
+ goto out_drm_gem_fb_end_cpu_access;
+
+ drm_atomic_helper_damage_iter_init(, old_plane_state, plane_state);
+ drm_atomic_for_each_plane_damage(, ) {
+ udl_handle_damage(fb, _plane_state->data[0], );
+ }
drm_dev_exit(idx);
+
+out_drm_gem_fb_end_cpu_access:
+ drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
}
static void udl_primary_plane_helper_atomic_disable(struct drm_plane *plane,
--
2.37.3
