[PATCH] drm/bridge: analogix_dp: Use devm_platform_get_and_ioremap_resource() in analogix_dp_probe()
From: Markus Elfring
Date: Mon, 5 Feb 2024 08:30:57 +0100
A wrapper function is available since the commit
890cc39a879906b63912482dfc41944579df2dc6
("drivers: provide devm_platform_get_and_ioremap_resource()").
Thus reuse existing functionality instead of keeping duplicate source code.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index df9370e0ff23..1c7dbf1ced77 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1739,10 +1739,7 @@ analogix_dp_probe(struct device *dev, struct
analogix_dp_plat_data *plat_data)
}
clk_prepare_enable(dp->clock);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
- dp->reg_base = devm_ioremap_resource(>dev, res);
+ dp->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, );
if (IS_ERR(dp->reg_base)) {
ret = PTR_ERR(dp->reg_base);
goto err_disable_clk;
--
2.43.0
Re: [PATCH v3 4/5] drm: xlnx: zynqmp_dpsub: Filter interrupts against mask
Hi Anatoliy, Thank you for the patch. On Tue, Jan 23, 2024 at 06:54:01PM -0800, Anatoliy Klymenko wrote: > Filter out status register against the interrupts' mask. > > Some events are being reported via DP status register, even if > corresponding interrupts have been disabled. One instance of such event > leads to generation of VBLANK when the driver is in DRM bridge mode, > which in turn results in NULL pointer dereferencing. We should avoid > processing such events in an interrupt handler context. > > This problem is less noticeable when the driver operates in DMA mode, as > in this case we have DRM CRTC object instantiated and DRM framework > simply discards unwanted VBLANKs in drm_handle_vblank(). > > Signed-off-by: Anatoliy Klymenko Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 9 - > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c > b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 5a3335e1fffa..9f48e5bbcdec 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -1627,7 +1627,14 @@ static irqreturn_t zynqmp_dp_irq_handler(int irq, void > *data) > /* clear status register as soon as we read it */ > zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); > mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK); > - if (!(status & ~mask)) > + > + /* > + * Status register may report some events, which corresponding > interrupts > + * have been disabled. Filter out those events against interrupts' mask. > + */ > + status &= ~mask; > + > + if (!status) > return IRQ_NONE; > > /* dbg for diagnostic, but not much that the driver can do */ -- Regards, Laurent Pinchart
Re: [PATCH v3 3/5] drm: xlnx: zynqmp_dpsub: Clear status register ASAP
Hi Anatoliy, Thank you for the patch. On Tue, Jan 23, 2024 at 06:54:00PM -0800, Anatoliy Klymenko wrote: > Clear status register as soon as we read it. > > Addressing comments from > https://lore.kernel.org/dri-devel/beb551c7-bb7e-4cd0-b166-e9aad90c4...@ideasonboard.com/ > > Signed-off-by: Anatoliy Klymenko > --- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c > b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index d60b7431603f..5a3335e1fffa 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -1624,6 +1624,8 @@ static irqreturn_t zynqmp_dp_irq_handler(int irq, void > *data) > u32 status, mask; > > status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS); > + /* clear status register as soon as we read it */ I don't think a comment is strictly required, but I don't mind it. Reviewed-by: Laurent Pinchart > + zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); > mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK); > if (!(status & ~mask)) > return IRQ_NONE; > @@ -1634,8 +1636,6 @@ static irqreturn_t zynqmp_dp_irq_handler(int irq, void > *data) > if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) > dev_dbg_ratelimited(dp->dev, "overflow interrupt\n"); > > - zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); > - > if (status & ZYNQMP_DP_INT_VBLANK_START) > zynqmp_dpsub_drm_handle_vblank(dp->dpsub); > -- Regards, Laurent Pinchart
Re: [PATCH V8 11/12] arm64: dts: imx8mp: add HDMI display pipeline
Hi Adam,
thanks for working on this.
Am Samstag, 3. Februar 2024, 17:52:51 CET schrieb Adam Ford:
> From: Lucas Stach
>
> This adds the DT nodes for all the peripherals that make up the
> HDMI display pipeline.
>
> Signed-off-by: Lucas Stach
> Signed-off-by: Adam Ford
>
> ---
> V2: I took this from Lucas' original submission with the following:
> Removed extra clock from HDMI-TX since it is now part of the
> power domain
> Added interrupt-parent to PVI
> Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx
> Added ports to HDMI-tx
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 94 +++
> 1 file changed, 94 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 5e51a766f3d9..e84b4f40e570 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1412,6 +1412,100 @@ irqsteer_hdmi: interrupt-controller@32fc2000 {
> clock-names = "ipg";
> power-domains = <_blk_ctrl
IMX8MP_HDMIBLK_PD_IRQSTEER>;
> };
> +
> + hdmi_pvi: display-bridge@32fc4000 {
> + compatible = "fsl,imx8mp-hdmi-pvi";
> + reg = <0x32fc4000 0x40>;
> + interrupt-parent = <_hdmi>;
> + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
irqsteer_hdmi has #interrupt-cells = <1>, so IRQ flags should be removed.
dtbs_check also warns about this.
> + power-domains = <_blk_ctrl
IMX8MP_HDMIBLK_PD_PVI>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + pvi_from_lcdif3:
endpoint {
> + remote-
endpoint = <_to_pvi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + pvi_to_hdmi_tx:
endpoint {
> + remote-
endpoint = <_tx_from_pvi>;
> + };
> + };
> + };
> + };
> +
> + lcdif3: display-controller@32fc6000 {
> + compatible = "fsl,imx8mp-lcdif";
> + reg = <0x32fc6000 0x238>;
> + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
irqsteer_hdmi has #interrupt-cells = <1>, so IRQ flags should be removed.
dtbs_check also warns about this.
> + interrupt-parent = <_hdmi>;
> + clocks = <_tx_phy>,
> + < IMX8MP_CLK_HDMI_APB>,
> + <
IMX8MP_CLK_HDMI_ROOT>;
> + clock-names = "pix", "axi",
"disp_axi";
> + power-domains = <_blk_ctrl
IMX8MP_HDMIBLK_PD_LCDIF>;
> +
> + port {
> + lcdif3_to_pvi: endpoint {
> + remote-endpoint =
<_from_lcdif3>;
> + };
> + };
> + };
> +
> + hdmi_tx: hdmi@32fd8000 {
> + compatible = "fsl,imx8mp-hdmi-tx";
> + reg = <0x32fd8000 0x7eff>;
> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
irqsteer_hdmi has #interrupt-cells = <1>, so IRQ flags should be removed.
dtbs_check also warns about this.
> + interrupt-parent = <_hdmi>;
> + clocks = < IMX8MP_CLK_HDMI_APB>,
> + <
IMX8MP_CLK_HDMI_REF_266M>,
> + < IMX8MP_CLK_32K>,
> + <_tx_phy>;
> + clock-names = "iahb", "isfr", "cec",
"pix";
> + assigned-clocks = <
IMX8MP_CLK_HDMI_REF_266M>;
> + assigned-clock-parents = <
IMX8MP_SYS_PLL1_266M>;
> + power-domains = <_blk_ctrl
IMX8MP_HDMIBLK_PD_HDMI_TX>;
> + reg-io-width = <1>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells
Re: [PATCH v3 0/5] Fixing live video input in ZynqMP DPSUB
Hello, This series looks good. Tomi, could you get it merged through drm-misc ? On Tue, Jan 23, 2024 at 06:53:57PM -0800, Anatoliy Klymenko wrote: > Add few missing pieces to support ZynqMP DPSUB live video in mode. > > ZynqMP DPSUB supports 2 modes of operations in regard to video data > input. > > In the first mode, DPSUB uses DMA engine to pull video data from memory > buffers. To support this the driver implements CRTC and DRM bridge > representing DP encoder. > > In the second mode, DPSUB acquires video data pushed from FPGA and > passes it downstream to DP output. This mode of operation is modeled in > the driver as a DRM bridge that should be attached to some external > CRTC. > > Patches 1/5,2/5,3/5,4/5 are minor fixes. > > DPSUB requires input live video format to be configured. > Patch 5/5: The DP Subsystem requires the input live video format to be > configured. In this patch, we are assuming that the CRTC's bus format is > fixed (typical for FPGA CRTC) and comes from the device tree. This is a > proposed solution, as there is no API to query CRTC output bus format > or negotiate it in any other way. > > Changes in v2: > - Address reviewers' comments: > - More elaborate and consistent comments / commit messages > - Fix includes' order > - Replace of_property_read_u32_index() with of_property_read_u32() > > Changes in v3: > - Split patch #3 into 3) moving status register clear immediately after > read; 4) masking status against interrupts' mask > > Link to v1: > https://lore.kernel.org/all/20240112234222.913138-1-anatoliy.klyme...@amd.com/ > Link to v2: > https://lore.kernel.org/all/20240119055437.2549149-1-anatoliy.klyme...@amd.com/ > > Anatoliy Klymenko (5): > drm: xlnx: zynqmp_dpsub: Make drm bridge discoverable > drm: xlnx: zynqmp_dpsub: Fix timing for live mode > drm: xlnx: zynqmp_dpsub: Clear status register ASAP > drm: xlnx: zynqmp_dpsub: Filter interrupts against mask > drm: xlnx: zynqmp_dpsub: Set live video in format > > drivers/gpu/drm/xlnx/zynqmp_disp.c | 111 +--- > drivers/gpu/drm/xlnx/zynqmp_disp.h | 3 +- > drivers/gpu/drm/xlnx/zynqmp_disp_regs.h | 8 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c| 16 +++- > drivers/gpu/drm/xlnx/zynqmp_kms.c | 2 +- > 5 files changed, 119 insertions(+), 21 deletions(-) -- Regards, Laurent Pinchart
Re: [PATCH V8 06/12] arm64: dts: imx8mp: add HDMI irqsteer
Hi Adam,
thanks for working on this.
Am Samstag, 3. Februar 2024, 17:52:46 CET schrieb Adam Ford:
> From: Lucas Stach
>
> The HDMI irqsteer is a secondary interrupt controller within the HDMI
> subsystem that maps all HDMI peripheral IRQs into a single upstream
> IRQ line.
>
> Signed-off-by: Lucas Stach
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 5c54073de615..5e51a766f3d9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1399,6 +1399,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc {
>"hdcp",
"hrv";
> #power-domain-cells = <1>;
> };
> +
> + irqsteer_hdmi: interrupt-controller@32fc2000 {
> + compatible = "fsl,imx-irqsteer";
> + reg = <0x32fc2000 0x44>;
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + fsl,channel = <1>;
> + fsl,num-irqs = <64>;
> + clocks = < IMX8MP_CLK_HDMI_APB>;
> + clock-names = "ipg";
> + power-domains = <_blk_ctrl
IMX8MP_HDMIBLK_PD_IRQSTEER>;
> + };
According to RM this block is part of HDMI_TX which is part of AIPS4, so it
should be below hsio_blk_ctrl.
Best regards,
Alexander
> };
>
> aips5: bus@30c0 {
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
Re: [PATCH V8 05/12] arm64: dts: imx8mp: add HDMI power-domains
Hi Adam,
thanks for working on this.
Am Samstag, 3. Februar 2024, 17:52:45 CET schrieb Adam Ford:
> From: Lucas Stach
>
> This adds the PGC and HDMI blk-ctrl nodes providing power control for
> HDMI subsystem peripherals.
>
> Signed-off-by: Adam Ford
> Signed-off-by: Lucas Stach
> ---
> V2: Add missing power-domains hdcp and hrv
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 76c73daf546b..5c54073de615 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -836,6 +836,23 @@ pgc_mediamix: power-domain@10 {
><
IMX8MP_CLK_MEDIA_APB_ROOT>;
> };
>
> + pgc_hdmimix: power-
domains@14 {
As per Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml the node
should be called power-domain@.
> + #power-domain-
cells = <0>;
> + reg =
;
> + clocks = <
IMX8MP_CLK_HDMI_ROOT>,
> + <
IMX8MP_CLK_HDMI_APB>;
> + assigned-clocks =
< IMX8MP_CLK_HDMI_AXI>,
> +
< IMX8MP_CLK_HDMI_APB>;
> + assigned-clock-
parents = < IMX8MP_SYS_PLL2_500M>,
> +
< IMX8MP_SYS_PLL1_133M>;
> + assigned-clock-
rates = <5>, <13300>;
> + };
> +
> + pgc_hdmi_phy: power-
domains@15 {
As per Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml the node
should be called power-domain@.
> + #power-domain-
cells = <0>;
> + reg =
;
> + };
> +
> pgc_mipi_phy2: power-
domain@16 {
> #power-domain-
cells = <0>;
> reg =
;
> @@ -1361,6 +1378,27 @@ eqos: ethernet@30bf {
> intf_mode = < 0x4>;
> status = "disabled";
> };
> +
> + hdmi_blk_ctrl: blk-ctrl@32fc {
> + compatible = "fsl,imx8mp-hdmi-blk-
ctrl", "syscon";
> + reg = <0x32fc 0x23c>;
> + clocks = < IMX8MP_CLK_HDMI_APB>,
> + <
IMX8MP_CLK_HDMI_ROOT>,
> + <
IMX8MP_CLK_HDMI_REF_266M>,
> + < IMX8MP_CLK_HDMI_24M>,
> + <
IMX8MP_CLK_HDMI_FDCC_TST>;
> + clock-names = "apb", "axi",
"ref_266m", "ref_24m", "fdcc";
> + power-domains = <_hdmimix>,
<_hdmimix>,
> + <_hdmimix>,
<_hdmimix>,
> + <_hdmimix>,
<_hdmimix>,
> + <_hdmimix>,
<_hdmi_phy>,
> + <_hdmimix>,
<_hdmimix>;
> + power-domain-names = "bus",
"irqsteer", "lcdif",
> + "pai", "pvi",
"trng",
> + "hdmi-tx",
"hdmi-tx-phy",
> + "hdcp",
"hrv";
> + #power-domain-cells = <1>;
> + };
> };
>
According to RM this block is part of AIPS4, so it should be below
hsio_blk_ctrl.
Best regards,
Alexander
> aips5: bus@30c0 {
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
Re: [PATCH] drm/mgag200: Flush the cache to improve latency
On Mon, 6 Nov 2023 at 20:47, Jocelyn Falempe wrote:
>
> On 23/10/2023 10:30, Jocelyn Falempe wrote:
> > On 20/10/2023 14:06, Thomas Zimmermann wrote:
> >> (cc'ing lkml for feedback)
> >>
> >> Hi Jocelyn
> >>
> >> Am 19.10.23 um 15:55 schrieb Jocelyn Falempe:
> >>> We found a regression in v5.10 on real-time server, using the
> >>> rt-kernel and the mgag200 driver. It's some really specialized
> >>> workload, with <10us latency expectation on isolated core.
> >>> After the v5.10, the real time tasks missed their <10us latency
> >>> when something prints on the screen (fbcon or printk)
> >>
> >> I'd like to hear the opinion of the RT-devs on this patch. Because
> >> AFAIK we never did such a workaround in other drivers. And AFAIK
> >> printk is a PITA anyway.
> >
> > Most other drivers uses DMA, which means this workaround can't apply to
> > them.
> >
> >>
> >> IMHO if that RT system cannot handle differences in framebuffer
> >> caching, it's under-powered. It's just a matter of time until
> >> something else changes and the problem returns. And (honest question)
> >> as it's an x86-64, how do they handle System Management Mode?
> >
> > I think it's not a big news, that the Matrox G200 from 1999 is
> > under-powered.
> > I was also a bit surprised that flushing the cache would have such
> > effect on latency. The tests we are doing can run 24h with the
> > workaround, without any interrupt taking more than 10us. Without the
> > workaround, every ~30s the interrupt failed its 10us target.
> >
> >>
> >>>
> >>> The regression has been bisected to 2 commits:
> >>> 0b34d58b6c32 ("drm/mgag200: Enable caching for SHMEM pages")
> >>> 4862ffaec523 ("drm/mgag200: Move vmap out of commit tail")
> >>>
> >>> The first one changed the system memory framebuffer from Write-Combine
> >>> to the default caching.
> >>> Before the second commit, the mgag200 driver used to unmap the
> >>> framebuffer after each frame, which implicitly does a cache flush.
> >>> Both regressions are fixed by the following patch, which forces a
> >>> cache flush after each frame, reverting to almost v5.9 behavior.
> >>
> >> With that second commit, we essentially never unmap an active
> >> framebuffer console. But with commit
> >>
> >> 359c6649cd9a ("drm/gem: Implement shadow-plane {begin, end}_fb_access
> >> with vmap")
> >>
> >> we now again unmap the console framebuffer after the pageflip happened.
> >>
> >> So how does the latest kernel behave wrt to the problem?
> >
> > The regression was found when upgrading the server from v5.4 to v5.14,
> > so we didn't test with later kernels.
> > We will test with v6.3 (which should have 359c6649cd9a ) and see what it
> > gives.
>
> I don't have a clear explanation, but testing with v6.3, and forcing the
> Write Combine, doesn't fix the latency issue. So forcing the cache flush
> is still needed.
>
> Also, on some systems, they use "isolated cpu" to handle RT task, but
> with a standard kernel (so without the CONFIG_PREEMPT_RT).
> So I'm wondering if we can use a kernel module parameter for this,
> so that users that wants to achieve low latency, can opt-in ?
>
> something like mgag200.force_cache_flush=1 or mgag200.low_latency=1 ?
I think we should either add a config option or command line parameter here.
I'd don't think adding nopat to the kernel command line is a good
suggestion in the long run, servers often have other cards plugged
into them like nvidia gpus or rdma etc, you don't want to cripple them
because you want reduced latency on the crappy on-board.
I'd rather we put the default back to what it used to be, which was
flush the cache though, I'm not sure why we have any objection to
doing that, it used to work, it was clearly fine in operation, why
undo it?
Dave.
[PATCH v2] drm/panel: re-alphabetize the menu list
A few of the DRM_PANEL entries have become out of alphabetical order, so move them around a bit to restore alpha order. Signed-off-by: Randy Dunlap Cc: Neil Armstrong Cc: Jessica Zhang Cc: Sam Ravnborg Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel@lists.freedesktop.org Cc: Aradhya Bhatia --- v2: rebase, move more driver entries around Aradhya Bhatia had responded with Reviewed-by: for v1, but I mode quite a few additions in v2 so I didn't include that R-B: here. drivers/gpu/drm/panel/Kconfig | 202 1 file changed, 101 insertions(+), 101 deletions(-) diff -- a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -76,53 +76,6 @@ config DRM_PANEL_BOE_TV101WUM_NL6 Say Y here if you want to support for BOE TV101WUM and AUO KD101N80 45NA WUXGA PANEL DSI Video Mode panel -config DRM_PANEL_DSI_CM - tristate "Generic DSI command mode panels" - depends on OF - depends on DRM_MIPI_DSI - depends on BACKLIGHT_CLASS_DEVICE - help - DRM panel driver for DSI command mode panels with support for - embedded and external backlights. - -config DRM_PANEL_LVDS - tristate "Generic LVDS panel driver" - depends on OF - depends on BACKLIGHT_CLASS_DEVICE - select VIDEOMODE_HELPERS - help - This driver supports LVDS panels that don't require device-specific - handling of power supplies or control signals. It implements automatic - backlight handling if the panel is attached to a backlight controller. - -config DRM_PANEL_SIMPLE - tristate "support for simple panels (other than eDP ones)" - depends on OF - depends on BACKLIGHT_CLASS_DEVICE - depends on PM - select VIDEOMODE_HELPERS - help - DRM panel driver for dumb non-eDP panels that need at most a regulator - and a GPIO to be powered up. Optionally a backlight can be attached so - that it can be automatically turned off when the panel goes into a - low power state. - -config DRM_PANEL_EDP - tristate "support for simple Embedded DisplayPort panels" - depends on OF - depends on BACKLIGHT_CLASS_DEVICE - depends on PM - select VIDEOMODE_HELPERS - select DRM_DISPLAY_DP_HELPER - select DRM_DISPLAY_HELPER - select DRM_DP_AUX_BUS - select DRM_KMS_HELPER - help - DRM panel driver for dumb eDP panels that need at most a regulator and - a GPIO to be powered up. Optionally a backlight can be attached so - that it can be automatically turned off when the panel goes into a - low power state. - config DRM_PANEL_EBBG_FT8719 tristate "EBBG FT8719 panel driver" depends on OF @@ -162,6 +115,25 @@ config DRM_PANEL_FEIYANG_FY07024DI26A30D Say Y if you want to enable support for panels based on the Feiyang FY07024DI26A30-D MIPI-DSI interface. +config DRM_PANEL_DSI_CM + tristate "Generic DSI command mode panels" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + DRM panel driver for DSI command mode panels with support for + embedded and external backlights. + +config DRM_PANEL_LVDS + tristate "Generic LVDS panel driver" + depends on OF + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + This driver supports LVDS panels that don't require device-specific + handling of power supplies or control signals. It implements automatic + backlight handling if the panel is attached to a backlight controller. + config DRM_PANEL_HIMAX_HX8394 tristate "HIMAX HX8394 MIPI-DSI LCD panels" depends on OF @@ -251,17 +223,6 @@ config DRM_PANEL_JADARD_JD9365DA_H3 WXGA MIPI DSI panel. The panel support TFT dot matrix LCD with 800RGBx1280 dots at maximum. -config DRM_PANEL_JDI_LT070ME05000 - tristate "JDI LT070ME05000 WUXGA DSI panel" - depends on OF - depends on DRM_MIPI_DSI - depends on BACKLIGHT_CLASS_DEVICE - help - Say Y here if you want to enable support for JDI DSI video mode - panel as found in Google Nexus 7 (2013) devices. - The panel has a 1200(RGB)×1920 (WUXGA) resolution and uses - 24 bit per pixel. - config DRM_PANEL_JDI_LPM102A188A tristate "JDI LPM102A188A DSI panel" depends on OF && GPIOLIB @@ -273,6 +234,17 @@ config DRM_PANEL_JDI_LPM102A188A The panel has a 2560×1800 resolution. It provides a MIPI DSI interface to the host. +config DRM_PANEL_JDI_LT070ME05000 + tristate "JDI LT070ME05000 WUXGA DSI panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE +
[PATCH v2 2/3] Subject: [PATCH] drm/mediatek/dp: Add HDCP2.x feature for DisplayPort
Add HDCP2.x feature for DisplayPort.
When userspace request the kernel protect future content communicated
over the link with Content_Protection property, the feature will do
HDCP2.x authentication if the sink support HDCP2.X.
Changes in v2:
- remove switch case, and refine code to make more clear
- remove some definitions, and use the definitions in
include/drm/drm_hdcp.h
- use the struct which defined in include/drm/drm_hdcp.h
- do HDCP2.x authentication when userspace request the
kernel protect future content communicated
per suggestion from the previous thread:
https://lore.kernel.org/all/8fff59b5567449d8201dd1138c8fa
9218a545c46.ca...@mediatek.com/
Signed-off-by: mac.shen
---
drivers/gpu/drm/mediatek/Makefile |1 +
drivers/gpu/drm/mediatek/mtk_dp.c | 297 +--
drivers/gpu/drm/mediatek/mtk_dp.h | 99 +++
drivers/gpu/drm/mediatek/mtk_dp_hdcp2.c | 1021 +++
drivers/gpu/drm/mediatek/mtk_dp_hdcp2.h | 52 ++
drivers/gpu/drm/mediatek/mtk_dp_reg.h |4 +-
drivers/gpu/drm/mediatek/mtk_dpi.c |3 +
7 files changed, 1392 insertions(+), 85 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp2.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp2.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index c80e6c2f9336..50ea069b047e 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -27,6 +27,7 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
mtk-dp-objs := tlc_dp_hdcp.o \
+ mtk_dp_hdcp2.o \
mtk_dp.o
obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk-dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
b/drivers/gpu/drm/mediatek/mtk_dp.c
index e4c16ba9902d..7ff72f15528b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2019-2022 MediaTek Inc.
+ * Copyright (c) 2019-2024 MediaTek Inc.
* Copyright (c) 2022 BayLibre
*/
@@ -8,13 +8,13 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -30,10 +30,10 @@
#include
#include
#include
-#include
-#include
+#include "mtk_dp.h"
#include "mtk_dp_reg.h"
+#include "mtk_dp_hdcp2.h"
#define MTK_DP_SIP_CONTROL_AARCH32 MTK_SIP_SMC_CMD(0x523)
#define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE(BIT(0) | BIT(5))
@@ -52,43 +52,6 @@
#define MTK_DP_VERSION 0x11
#define MTK_DP_SDP_AUI 0x4
-enum {
- MTK_DP_CAL_GLB_BIAS_TRIM = 0,
- MTK_DP_CAL_CLKTX_IMPSE,
- MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0,
- MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1,
- MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2,
- MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3,
- MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0,
- MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1,
- MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2,
- MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3,
- MTK_DP_CAL_MAX,
-};
-
-struct mtk_dp_train_info {
- bool sink_ssc;
- bool cable_plugged_in;
- /* link_rate is in multiple of 0.27Gbps */
- int link_rate;
- int lane_count;
- unsigned int channel_eq_pattern;
-};
-
-struct mtk_dp_audio_cfg {
- bool detect_monitor;
- int sad_count;
- int sample_rate;
- int word_length_bits;
- int channels;
-};
-
-struct mtk_dp_info {
- enum dp_pixelformat format;
- struct videomode vm;
- struct mtk_dp_audio_cfg audio_cur_cfg;
-};
-
struct mtk_dp_efuse_fmt {
unsigned short idx;
unsigned short shift;
@@ -98,44 +61,6 @@ struct mtk_dp_efuse_fmt {
unsigned short default_val;
};
-struct mtk_dp {
- bool enabled;
- bool need_debounce;
- int irq;
- u8 max_lanes;
- u8 max_linkrate;
- u8 rx_cap[DP_RECEIVER_CAP_SIZE];
- u32 cal_data[MTK_DP_CAL_MAX];
- u32 irq_thread_handle;
- /* irq_thread_lock is used to protect irq_thread_handle */
- spinlock_t irq_thread_lock;
-
- struct device *dev;
- struct drm_bridge bridge;
- struct drm_bridge *next_bridge;
- struct drm_connector *conn;
- struct drm_device *drm_dev;
- struct drm_dp_aux aux;
-
- const struct mtk_dp_data *data;
- struct mtk_dp_info info;
- struct mtk_dp_train_info train_info;
-
- struct platform_device *phy_dev;
- struct phy *phy;
- struct regmap *regs;
- struct timer_list debounce_timer;
-
- /* For audio */
- bool audio_enable;
- hdmi_codec_plugged_cb plugged_cb;
- struct platform_device *audio_pdev;
-
- struct device *codec_dev;
- /* protect the plugged_cb as it's used in both bridge ops and audio */
- struct mutex update_plugged_status_lock;
-};
-
struct mtk_dp_data {
int bridge_type;
unsigned int
[PATCH v2 0/3] Add HDCP feature for DisplayPort
Add tee client application, HDCP 1.x and 2.x authentication for DisplayPort to support the HDCP feature. mac.shen (3): Subject: [PATCH] drm/mediatek/dp: Add tee client application for HDCP feature Subject: [PATCH] drm/mediatek/dp: Add HDCP2.x feature for DisplayPort Subject: [PATCH] drm/mediatek/dp: Add HDCP1.x feature for DisplayPort drivers/gpu/drm/mediatek/Makefile|7 +- drivers/gpu/drm/mediatek/mtk_dp.c| 324 +-- drivers/gpu/drm/mediatek/mtk_dp.h| 99 +++ drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.c | 589 + drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.h | 46 + drivers/gpu/drm/mediatek/mtk_dp_hdcp2.c | 1021 ++ drivers/gpu/drm/mediatek/mtk_dp_hdcp2.h | 52 ++ drivers/gpu/drm/mediatek/mtk_dp_reg.h|7 +- drivers/gpu/drm/mediatek/mtk_dpi.c |3 + drivers/gpu/drm/mediatek/tci.h | 156 drivers/gpu/drm/mediatek/tlc_dp_hdcp.c | 598 + drivers/gpu/drm/mediatek/tlc_dp_hdcp.h | 414 + 12 files changed, 3230 insertions(+), 86 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.h create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp2.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp2.h create mode 100644 drivers/gpu/drm/mediatek/tci.h create mode 100644 drivers/gpu/drm/mediatek/tlc_dp_hdcp.c create mode 100644 drivers/gpu/drm/mediatek/tlc_dp_hdcp.h -- 2.43.0
[PATCH v2 1/3] Subject: [PATCH] drm/mediatek/dp: Add tee client application for HDCP feature
Add tee client application which will be used for
HDCP 1.x and 2.x authentication in DisplayPort.
Changes in v2:
- remove ca folder, and change file name with lower case
- refine the tci_t structure to make the data to tee can
through this structure
- remove aux and regs from mtk_hdcp_info structure
- remove some definitions, and use the definitions in
include/drm/drm_hdcp.h
- remove useless code
per suggestion from the previous thread:
https://lore.kernel.org/all/8fff59b5567449d8201dd1138c8fa
9218a545c46.ca...@mediatek.com/
Signed-off-by: mac.shen
---
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/tci.h | 156 +++
drivers/gpu/drm/mediatek/tlc_dp_hdcp.c | 598 +
drivers/gpu/drm/mediatek/tlc_dp_hdcp.h | 414 +
4 files changed, 1172 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/tci.h
create mode 100644 drivers/gpu/drm/mediatek/tlc_dp_hdcp.c
create mode 100644 drivers/gpu/drm/mediatek/tlc_dp_hdcp.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..c80e6c2f9336 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -26,4 +26,7 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
-obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
+mtk-dp-objs := tlc_dp_hdcp.o \
+ mtk_dp.o
+
+obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk-dp.o
diff --git a/drivers/gpu/drm/mediatek/tci.h b/drivers/gpu/drm/mediatek/tci.h
new file mode 100644
index ..f2239ea3ffbf
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/tci.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019-2024 MediaTek Inc.
+ */
+
+#ifndef _TCI_H_
+#define _TCI_H_
+
+#include
+
+#define CMD_DEVICE_ADDED1
+#define CMD_DEVICE_REMOVE 2
+#define CMD_WRITE_VAL 3
+#define CMD_DEVICE_CLEAN4
+#define CMD_ENABLE_ENCRYPT 5
+
+/* V1.3 */
+#define CMD_CALCULATE_LM11
+#define CMD_COMPARE_R0 12
+#define CMD_COMPARE_V1 13
+#define CMD_GET_AKSV14
+
+/* V2.2 */
+#define CMD_AKE_CERTIFICATE 20
+#define CMD_ENC_KM 21
+#define CMD_AKE_H_PRIME 22
+#define CMD_AKE_PARING 23
+#define CMD_LC_L_PRIME 24
+#define CMD_COMPARE_L 25
+#define CMD_SKE_CAL_EKS 26
+
+#define CMD_COMPARE_V2 27
+#define CMD_COMPARE_M 28
+
+/* Need remove in furture */
+#define CMD_LOAD_KEY50
+
+#define RET_COMPARE_PASS 0
+#define RET_COMPARE_FAIL 1
+#define RET_NEW_DEVICE 2
+#define RET_STORED_DEVICE 3
+
+#define TYPE_HDCP_PARAM_AN 10
+#define TYPE_HDCP_PARAM_RST_1 11
+#define TYPE_HDCP_PARAM_RST_2 12
+#define TYPE_HDCP_ENABLE_ENCRYPT 13
+#define TYPE_HDCP_DISABLE_ENCRYPT 14
+
+#define TYPE_HDCP13_KEY 20
+#define TYPE_HDCP22_KEY 21
+
+// reserved:2
+#define HDCP2_CERTRX_LEN (HDCP_2_2_RECEIVER_ID_LEN + HDCP_2_2_K_PUB_RX_LEN + \
+ 2 + HDCP_2_2_DCP_LLC_SIG_LEN)
+// version:1
+#define HDCP_2_2_TXCAPS_LEN (HDCP_2_2_TXCAP_MASK_LEN + 1)
+#define PARAM_LEN 1024
+
+#define TCI_LENGTH sizeof(struct tci_t)
+
+struct cmd_hdcp_init_for_verion_t {
+ u32 version;
+ bool need_load_key;
+};
+
+struct cmd_hdcp_write_val_t {
+ u8 type;
+ u8 len;
+ u8 val[DRM_HDCP_AN_LEN];
+};
+
+struct cmd_hdcp_calculate_lm_t {
+ u8 bksv[DRM_HDCP_KSV_LEN];
+};
+
+struct cmd_hdcp_get_aksv_t {
+ u8 aksv[DRM_HDCP_KSV_LEN];
+};
+
+struct cmd_hdcp_ake_certificate_t {
+ u8 certification[HDCP2_CERTRX_LEN];
+ bool stored;
+ u8 m[HDCP_2_2_E_KH_KM_M_LEN - HDCP_2_2_E_KH_KM_LEN];
+ u8 ekm[HDCP_2_2_E_KH_KM_LEN];
+};
+
+struct cmd_hdcp_ake_paring_t {
+ u8 ekm[HDCP_2_2_E_KH_KM_LEN];
+};
+
+struct cmd_hdcp_enc_km_t {
+ u8 enc_km[HDCP_2_2_E_KPUB_KM_LEN];
+};
+
+struct cmd_hdcp_ake_h_prime_t {
+ u8 rtx[HDCP_2_2_RTX_LEN];
+ u8 rrx[HDCP_2_2_RRX_LEN];
+ u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
+ u8 tx_caps[HDCP_2_2_TXCAPS_LEN];
+ u32 rx_h_len;
+ u8 rx_h[HDCP_2_2_H_PRIME_LEN];
+};
+
+struct cmd_hdcp_lc_l_prime_t {
+ u8 rn[HDCP_2_2_RN_LEN];
+ u32 rx_l_len;
+ u8 rx_l[HDCP_2_2_L_PRIME_LEN];
+};
+
+struct cmd_hdcp_ske_eks_t {
+ u8 riv[HDCP_2_2_RIV_LEN];
+ u32 eks_len;
+ u32 eks;
+};
+
+struct cmd_hdcp_compare_t {
+ u32 rx_val_len;
+ u8 rx_val[HDCP_2_2_MPRIME_LEN];
+ u32 param_len;
+ u8 param[PARAM_LEN];
+ u32 out_len;
+ u32 out;
+};
+
+union tci_cmd_body_t {
+ /* Init with special HDCP version */
+ struct cmd_hdcp_init_for_verion_t cmd_hdcp_init_for_verion;
+ /* Write uint32 data to hw */
+ struct cmd_hdcp_write_val_t cmd_hdcp_write_val;
+ /* Get aksv */
+ struct cmd_hdcp_get_aksv_t cmd_hdcp_get_aksv;
+ /* Calculate r0 */
+ struct cmd_hdcp_calculate_lm_t cmd_hdcp_calculate_lm;
+ /* Generate
[PATCH v2 3/3] Subject: [PATCH] drm/mediatek/dp: Add HDCP1.x feature for DisplayPort
Add HDCP1.x feature for DisplayPort.
If the sink support HDCP1.X only, the feature will do HDCP1.x
authentication when userspace request the kernel protect with
HDCP_Content_Type property as DRM_MODE_HDCP_CONTENT_TYPE0.
Changes in v2:
- remove useless code
- remove the prefix 'mdrv'
- do HDCP1.x authentication when userspace request the
kernel protect future content communicated
per suggestion from the previous thread:
https://lore.kernel.org/all/8fff59b5567449d8201dd1138c8
fa9218a545c46.ca...@mediatek.com/
Signed-off-by: mac.shen
---
drivers/gpu/drm/mediatek/Makefile| 1 +
drivers/gpu/drm/mediatek/mtk_dp.c| 33 +-
drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.c | 589 +++
drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.h | 46 ++
drivers/gpu/drm/mediatek/mtk_dp_reg.h| 3 +
5 files changed, 669 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_hdcp1x.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 50ea069b047e..9738235f76b8 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -27,6 +27,7 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
mtk-dp-objs := tlc_dp_hdcp.o \
+ mtk_dp_hdcp1x.o \
mtk_dp_hdcp2.o \
mtk_dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
b/drivers/gpu/drm/mediatek/mtk_dp.c
index 7ff72f15528b..8cd7562dab7a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -33,6 +33,7 @@
#include "mtk_dp.h"
#include "mtk_dp_reg.h"
+#include "mtk_dp_hdcp1x.h"
#include "mtk_dp_hdcp2.h"
#define MTK_DP_SIP_CONTROL_AARCH32 MTK_SIP_SMC_CMD(0x523)
@@ -1811,6 +1812,9 @@ void mtk_dp_check_hdcp_version(struct mtk_dp *mtk_dp,
bool only_hdcp1x)
if (!only_hdcp1x && dp_tx_hdcp2_support(_dp->hdcp_info))
return;
+ if (dp_tx_hdcp1x_support(_dp->hdcp_info))
+ return;
+
if (tee_add_device(_dp->hdcp_info, HDCP_NONE) != RET_SUCCESS)
mtk_dp->hdcp_info.auth_status = AUTH_FAIL;
}
@@ -1860,15 +1864,34 @@ static void mtk_dp_hdcp_handle(struct work_struct *data)
mtk_dp_check_hdcp_version(mtk_dp, false);
if (mtk_dp->hdcp_info.hdcp2_info.enable)
dp_tx_hdcp2_set_start_auth(_dp->hdcp_info, true);
+ else if (mtk_dp->hdcp_info.hdcp1x_info.enable &&
+mtk_dp->hdcp_info.hdcp_content_type !=
DRM_MODE_HDCP_CONTENT_TYPE1)
+ dp_tx_hdcp1x_set_start_auth(_dp->hdcp_info, true);
else
mtk_dp->hdcp_info.auth_status = AUTH_ZERO;
}
- while (mtk_dp->hdcp_info.hdcp2_info.enable &&
- mtk_dp->hdcp_info.auth_status != AUTH_FAIL &&
+ while ((mtk_dp->hdcp_info.hdcp1x_info.enable ||
+ mtk_dp->hdcp_info.hdcp2_info.enable) &&
+ mtk_dp->hdcp_info.auth_status != AUTH_FAIL &&
mtk_dp->hdcp_info.auth_status != AUTH_PASS) {
- if (mtk_dp->hdcp_info.hdcp2_info.enable)
+ if (mtk_dp->hdcp_info.hdcp2_info.enable) {
dp_tx_hdcp2_fsm(_dp->hdcp_info);
+ if (mtk_dp->hdcp_info.auth_status == AUTH_FAIL) {
+ tee_remove_device(_dp->hdcp_info);
+ mtk_dp_check_hdcp_version(mtk_dp, true);
+ if (mtk_dp->hdcp_info.hdcp1x_info.enable &&
+ mtk_dp->hdcp_info.hdcp_content_type !=
+ DRM_MODE_HDCP_CONTENT_TYPE1) {
+ mtk_dp->hdcp_info.hdcp2_info.enable =
false;
+
dp_tx_hdcp1x_set_start_auth(_dp->hdcp_info, true);
+ }
+ }
+ }
+
+ if (mtk_dp->hdcp_info.hdcp1x_info.enable &&
+ mtk_dp->hdcp_info.hdcp_content_type !=
DRM_MODE_HDCP_CONTENT_TYPE1)
+ dp_tx_hdcp1x_fsm(_dp->hdcp_info);
}
}
@@ -1924,6 +1947,8 @@ static void mtk_dp_hdcp_atomic_check(struct mtk_dp
*mtk_dp, struct drm_connector
dev_dbg(mtk_dp->dev, "disable HDCP\n");
if (mtk_dp->hdcp_info.hdcp2_info.enable)
dp_tx_hdcp2_set_start_auth(_dp->hdcp_info, false);
+ else if (mtk_dp->hdcp_info.hdcp1x_info.enable)
+ dp_tx_hdcp1x_set_start_auth(_dp->hdcp_info, false);
drm_hdcp_update_content_protection(mtk_dp->conn,
mtk_dp->hdcp_info.content_protection);
@@ -2394,6 +2419,8 @@ static void mtk_dp_bridge_atomic_disable(struct
drm_bridge *bridge,
if
[PATCH v2] drm/rect: fix kernel-doc typos
Correct typos of "translated". Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel@lists.freedesktop.org Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Reviewed-by: Simon Ser Signed-off-by: Randy Dunlap --- v2: add Reviewed-by, rebase include/drm/drm_rect.h |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff -- a/include/drm/drm_rect.h b/include/drm/drm_rect.h --- a/include/drm/drm_rect.h +++ b/include/drm/drm_rect.h @@ -129,7 +129,7 @@ static inline void drm_rect_adjust_size( /** * drm_rect_translate - translate the rectangle - * @r: rectangle to be tranlated + * @r: rectangle to be translated * @dx: horizontal translation * @dy: vertical translation * @@ -146,7 +146,7 @@ static inline void drm_rect_translate(st /** * drm_rect_translate_to - translate the rectangle to an absolute position - * @r: rectangle to be tranlated + * @r: rectangle to be translated * @x: horizontal position * @y: vertical position *
Re: [PATCH] drm/msm/dpu: Only enable DSC_MODE_MULTIPLEX if dsc_merge is enabled
On Sun, 4 Feb 2024 at 18:45, Marijn Suijten
wrote:
>
> When the topology calls for two interfaces on the current fixed topology
> of 2 DSC blocks, or uses 1 DSC block for a single interface (e.g. SC7280
> with only one DSC block), there should be no merging of DSC output.
>
> This is already represented by the return value of
> dpu_encoder_use_dsc_merge(), but not yet used to correctly configure
> this flag.
>
> Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
> Signed-off-by: Marijn Suijten
> ---
> Note that more changes are needed to properly support the proposed 2:2:2
> and 1:1:1 topology (in contrast to the already-supported 2:2:1 topology),
> but this could be a trivial patch to get going separately before all that
> extra work is done.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH 00/27] sparc32: sunset sun4m and sun4d
Hi Sam, On Sun, 2024-02-04 at 20:21 +0100, Sam Ravnborg wrote: > Assuming you agree with the patchset how do you want me to move forward? > I can rebase on top of the latest -rc and collect acks if that helps. > > Arnd promised to pick up the patches until you got a git tree up, > but I do not expect Arnd to pick up anything unless you have acked or > reviewed said patch(es). > > If I rebase the patch-set I will likely include a few bug-fix patches that > was prepared in the meantime. > I can also send them as a separate series, no worries. I met with Andreas this weekend and he got GPG signatures from at least me and Geert which he needs for his kernel.org account. Please give him a few more days, maybe be even 2-3 weeks to get everything up and comfortable with the whole process. The more patches Andreas can review and merge himself, the better. And since your patches have been laying around for some time already, I don't think that waiting a little longer will be a problem. Thanks, Adrian -- .''`. John Paul Adrian Glaubitz : :' : Debian Developer `. `' Physicist `-GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
Re: [PATCH 00/27] sparc32: sunset sun4m and sun4d
Hi Andreas. Congratulation being the new sparc co-maintainer! On Tue, Dec 19, 2023 at 11:03:05PM +0100, Sam Ravnborg via B4 Relay wrote: > This is the second attempt to sunset sun4m and sun4d. > See [1] for the inital attempt. I have now verified that the kernel can boot with qemu. There was a bug in the uart driver that is fixed and upstream, and then using the instructions you provided I could use buildroot with an external kernel tree to get a booting kernel. Assuming you agree with the patchset how do you want me to move forward? I can rebase on top of the latest -rc and collect acks if that helps. Arnd promised to pick up the patches until you got a git tree up, but I do not expect Arnd to pick up anything unless you have acked or reviewed said patch(es). If I rebase the patch-set I will likely include a few bug-fix patches that was prepared in the meantime. I can also send them as a separate series, no worries. Sam
[PATCH] drm/msm/dpu: Only enable DSC_MODE_MULTIPLEX if dsc_merge is enabled
When the topology calls for two interfaces on the current fixed topology
of 2 DSC blocks, or uses 1 DSC block for a single interface (e.g. SC7280
with only one DSC block), there should be no merging of DSC output.
This is already represented by the return value of
dpu_encoder_use_dsc_merge(), but not yet used to correctly configure
this flag.
Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
Signed-off-by: Marijn Suijten
---
Note that more changes are needed to properly support the proposed 2:2:2
and 1:1:1 topology (in contrast to the already-supported 2:2:1 topology),
but this could be a trivial patch to get going separately before all that
extra work is done.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 83380bc92a00..6d3ed4d870d7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1857,7 +1857,9 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt
*dpu_enc,
dsc_common_mode = 0;
pic_width = dsc->pic_width;
- dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
+ dsc_common_mode = DSC_MODE_SPLIT_PANEL;
+ if (dpu_encoder_use_dsc_merge(enc_master->parent))
+ dsc_common_mode |= DSC_MODE_MULTIPLEX;
if (enc_master->intf_mode == INTF_MODE_VIDEO)
dsc_common_mode |= DSC_MODE_VIDEO;
---
base-commit: 01af33cc9894b4489fb68fa35c40e9fe85df63dc
change-id: 20240204-dpu-dsc-multiplex-49c14b73f3e0
Best regards,
--
Marijn Suijten
Re: [PATCH] drm/msm/dsi: Replace dsi_get_bpp() with mipi_dsi header function
On Sun, 4 Feb 2024 at 18:04, Marijn Suijten wrote: > > drm_mipi_dsi.h already provides a conversion function from MIPI_DSI_FMT_ > to bpp, named mipi_dsi_pixel_format_to_bpp(). > > Signed-off-by: Marijn Suijten > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 18 -- > 1 file changed, 4 insertions(+), 14 deletions(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
[PATCH] drm/msm/dsi: Replace dsi_get_bpp() with mipi_dsi header function
drm_mipi_dsi.h already provides a conversion function from MIPI_DSI_FMT_
to bpp, named mipi_dsi_pixel_format_to_bpp().
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index deeecdfd6c4e..9fa0053fac74 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -183,16 +183,6 @@ struct msm_dsi_host {
int irq;
};
-static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
-{
- switch (fmt) {
- case MIPI_DSI_FMT_RGB565: return 16;
- case MIPI_DSI_FMT_RGB666_PACKED:return 18;
- case MIPI_DSI_FMT_RGB666:
- case MIPI_DSI_FMT_RGB888:
- default:return 24;
- }
-}
static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
{
@@ -567,7 +557,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host
*host, bool is_bonded_d
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
u8 lanes = msm_host->lanes;
- u32 bpp = dsi_get_bpp(msm_host->format);
+ u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format);
unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc,
is_bonded_dsi);
unsigned long pclk_bpp;
@@ -610,7 +600,7 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
- u32 bpp = dsi_get_bpp(msm_host->format);
+ u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format);
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
@@ -993,7 +983,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
/* image data and 1 byte write_memory_start cmd */
if (!msm_host->dsc)
- wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+ wc = hdisplay *
mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1;
else
/*
* When DSC is enabled, WC = slice_chunk_size *
slice_per_pkt + 1.
@@ -1413,7 +1403,7 @@ static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
{
int len, ret;
int bllp_len = msm_host->mode->hdisplay *
- dsi_get_bpp(msm_host->format) / 8;
+ mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8;
len = dsi_cmd_dma_add(msm_host, msg);
if (len < 0) {
---
base-commit: 01af33cc9894b4489fb68fa35c40e9fe85df63dc
change-id: 20231019-drm-msm-dsi-remove-open-coded-get-bpp-e7864b0b11dd
Best regards,
--
Marijn Suijten
Re: [PATCH V8 06/12] arm64: dts: imx8mp: add HDMI irqsteer
On Sun, Feb 4, 2024 at 6:00 AM Francesco Dolcini wrote: > > On Sat, Feb 03, 2024 at 10:52:46AM -0600, Adam Ford wrote: > > From: Lucas Stach > > > > The HDMI irqsteer is a secondary interrupt controller within the HDMI > > subsystem that maps all HDMI peripheral IRQs into a single upstream > > IRQ line. > > > > Signed-off-by: Lucas Stach > > This is missing your signed-off-by, and in other patches of this series Opps. I thought I caught all those. > your signed-off-by is not the last, as it should be. > > Please have a look and fix this and the other instances. > OK. I have some work to do on some other portions, so I'll clean up that too. adam > Thanks for this work! Thanks for the feedback. adam > > Francesco >
RE: [EXT] Re: [PATCH v12 4/7] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver
Hi Alexander,
Thanks your comments,
>
>
> Hi Sandor,
>
> thanks for the update.
>
> Am Mittwoch, 10. Januar 2024, 02:08:45 CET schrieb Sandor Yu:
> > Add a new DRM DisplayPort and HDMI bridge driver for Candence
> MHDP8501
> > used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
> > standards according embedded Firmware running in the uCPU.
> >
> > For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
> > SOC's ROM code. Bootload binary included respective specific firmware
> > is required.
> >
> > Driver will check display connector type and then load the
> > corresponding driver.
> >
> > Signed-off-by: Sandor Yu
> > Tested-by: Alexander Stein
> > ---
> > v11->v12:
> > - Replace DRM_INFO with dev_info or dev_warn.
> > - Replace DRM_ERROR with dev_err.
> > - Return ret when cdns_mhdp_dpcd_read failed in function
> > cdns_dp_aux_transferi(). - Remove unused parmeter in function
> > cdns_dp_get_msa_misc
> > and use two separate variables for color space and bpc.
> > - Add year 2024 to copyright.
> >
> > drivers/gpu/drm/bridge/cadence/Kconfig| 16 +
> > drivers/gpu/drm/bridge/cadence/Makefile | 2 +
> > .../drm/bridge/cadence/cdns-mhdp8501-core.c | 315
> > .../drm/bridge/cadence/cdns-mhdp8501-core.h | 365 +
> > .../gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 699
> ++
> > .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 678
> +
> > 6 files changed, 2075 insertions(+)
> > create mode 100644
> > drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
> > create mode 100644
> > drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h
> > create mode 100644
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
> > create mode 100644
> > drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c
> >
> > diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
> > b/drivers/gpu/drm/bridge/cadence/Kconfig index
> > e0973339e9e33..45848e741f5f4
> > 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> > +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> > @@ -51,3 +51,19 @@ config DRM_CDNS_MHDP8546_J721E
> > initializes the J721E Display Port and sets up the
> > clock and data muxes.
> > endif
> > +
> > +config DRM_CDNS_MHDP8501
> > + tristate "Cadence MHDP8501 DP/HDMI bridge"
> > + select DRM_KMS_HELPER
> > + select DRM_PANEL_BRIDGE
> > + select DRM_DISPLAY_DP_HELPER
> > + select DRM_DISPLAY_HELPER
> > + select CDNS_MHDP_HELPER
> > + select DRM_CDNS_AUDIO
> > + depends on OF
> > + help
> > + Support Cadence MHDP8501 DisplayPort/HDMI bridge.
> > + Cadence MHDP8501 support one or more protocols,
> > + including DisplayPort and HDMI.
> > + To use the DP and HDMI drivers, their respective
> > + specific firmware is required.
> > diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
> > b/drivers/gpu/drm/bridge/cadence/Makefile index
> > 087dc074820d7..02c1a9f3cf6fc 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Makefile
> > +++ b/drivers/gpu/drm/bridge/cadence/Makefile
> > @@ -6,3 +6,5 @@ obj-$(CONFIG_CDNS_MHDP_HELPER) +=
> cdns-mhdp-helper.o
> > obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
> cdns-mhdp8546-y
> > := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
> > cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) +=
> > cdns-mhdp8546-j721e.o
> > +obj-$(CONFIG_DRM_CDNS_MHDP8501) += cdns-mhdp8501.o
> cdns-mhdp8501-y :=
> > +cdns-mhdp8501-core.o cdns-mhdp8501-dp.o
> > cdns-mhdp8501-hdmi.o diff --git
> > a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c new file mode
> > 100644 index 0..3080c7507a012
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
> > @@ -0,0 +1,315 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Cadence Display Port Interface (DP) driver
> > + *
> > + * Copyright (C) 2023, 2024 NXP Semiconductor, Inc.
> > + *
> > + */
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> Since commit d57d584ef69de ("of: Stop circularly including of_device.h and
> of_platform.h") you to explicitly include linux/platform_device.h here. Please
> compile against next tree.
OK, I will check it on next tree.
>
> > +#include
> > +
> > +#include "cdns-mhdp8501-core.h"
> > +
> > [snip]
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file mode
> > 100644 index 0..6963c7143a3b0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
> > @@ -0,0 +1,699 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Cadence MHDP8501 DisplayPort(DP) bridge driver
> > + *
> > + * Copyright (C) 2019-2024 NXP Semiconductor, Inc.
> > + *
> > + */
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "cdns-mhdp8501-core.h"
> > +
> > +#define
RE: [EXT] Re: [PATCH v12 7/7] phy: freescale: Add HDMI PHY driver for i.MX8MQ
Hi Alexander,
Thanks your comments,
> -Original Message-
> From: Alexander Stein
> Sent: 2024年1月17日 17:47
> To: dmitry.barysh...@linaro.org; andrzej.ha...@intel.com;
> neil.armstr...@linaro.org; Laurent Pinchart
> ; jo...@kwiboo.se;
> jernej.skra...@gmail.com; airl...@gmail.com; dan...@ffwll.ch;
> robh...@kernel.org; krzysztof.kozlowski...@linaro.org;
> shawn...@kernel.org; s.ha...@pengutronix.de; feste...@gmail.com;
> vk...@kernel.org; dri-devel@lists.freedesktop.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; linux-...@lists.infradead.org; Sandor Yu
>
> Cc: ker...@pengutronix.de; dl-linux-imx ; Sandor Yu
> ; Oliver Brown ;
> s...@ravnborg.org
> Subject: [EXT] Re: [PATCH v12 7/7] phy: freescale: Add HDMI PHY driver for
> i.MX8MQ
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> Hi Sandor,
>
> thanks for the update.
>
> Am Mittwoch, 10. Januar 2024, 02:08:48 CET schrieb Sandor Yu:
> > Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
> >
> > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base
> on
> > the configuration chosen.
> > HDMI PHY mode is configurated in the driver.
> >
> > Signed-off-by: Sandor Yu
> > Tested-by: Alexander Stein
> > ---
> > v11->v12:
> > - Adjust clk disable order.
> > - Return error code to replace -1 for function wait_for_ack().
> > - Use bool for variable pclk_in.
> > - Add year 2024 to copyright.
> >
> > drivers/phy/freescale/Kconfig | 10 +
> > drivers/phy/freescale/Makefile | 1 +
> > drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c | 959
> >
> > 3 files changed, 970 insertions(+)
> > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c
> >
> > diff --git a/drivers/phy/freescale/Kconfig
> > b/drivers/phy/freescale/Kconfig index c39709fd700ac..14f47b7cc77ab
> > 100644
> > --- a/drivers/phy/freescale/Kconfig
> > +++ b/drivers/phy/freescale/Kconfig
> > @@ -45,6 +45,16 @@ config PHY_FSL_IMX8MQ_DP
> > Enable this to support the Cadence HDPTX DP PHY driver
> > on i.MX8MQ SOC.
> >
> > +config PHY_FSL_IMX8MQ_HDMI
> > + tristate "Freescale i.MX8MQ HDMI PHY support"
> > + depends on OF && HAS_IOMEM
> > + depends on COMMON_CLK
> > + select GENERIC_PHY
> > + select CDNS_MHDP_HELPER
> > + help
> > + Enable this to support the Cadence HDPTX HDMI PHY driver
> > + on i.MX8MQ SOC.
> > +
> > endif
> >
> > config PHY_FSL_LYNX_28G
> > diff --git a/drivers/phy/freescale/Makefile
> > b/drivers/phy/freescale/Makefile index 47e5285209fa8..1380ac31c2ead
> > 100644
> > --- a/drivers/phy/freescale/Makefile
> > +++ b/drivers/phy/freescale/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > obj-$(CONFIG_PHY_FSL_IMX8MQ_DP) +=
> phy-fsl-imx8mq-dp.o
> > +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDMI)+= phy-fsl-imx8mq-hdmi.o
> > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)+= phy-fsl-imx8-mipi-dphy.o
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c
> > b/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c new file mode 100644
> > index 0..9e03c726f290c
> > --- /dev/null
> > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c
> > @@ -0,0 +1,959 @@
> > [snip]
> > +int cdns_hdptx_hdmi_phy_valid(struct phy *phy, enum phy_mode mode,
> > +int
> > submode, + union phy_configure_opts
> *opts)
>
> This function can be made static.
>
OK, thanks!
B.R
Sandor
> Thanks and best regards,
> Alexander
>
> > +{
> > + u32 rate = opts->hdmi.pixel_clk_rate;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++)
> > + if (rate ==
> pixel_clk_output_ctrl_table[i].pixel_clk_freq_min)
> > + return 0;
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int cdns_hdptx_hdmi_phy_init(struct phy *phy) {
> > + return 0;
> > +}
> > +
> > +static int cdns_hdptx_hdmi_configure(struct phy *phy,
> > + union phy_configure_opts *opts)
> {
> > + struct cdns_hdptx_hdmi_phy *cdns_phy = phy_get_drvdata(phy);
> > + int ret;
> > +
> > + cdns_phy->pixel_clk_rate = opts->hdmi.pixel_clk_rate;
> > + cdns_phy->color_space = opts->hdmi.color_space;
> > + cdns_phy->bpc = opts->hdmi.bpc;
> > +
> > + /* Check HDMI FW alive before HDMI PHY init */
> > + ret = hdptx_phy_check_alive(cdns_phy);
> > + if (!ret) {
> > + dev_err(cdns_phy->dev, "NO HDMI FW running\n");
> > + return -ENXIO;
> > + }
> > +
> > + /* Configure PHY */
> > + if (hdptx_hdmi_phy_cfg(cdns_phy, cdns_phy->pixel_clk_rate) < 0) {
> > + dev_err(cdns_phy->dev, "failed to set phy
Re: [PATCH V8 06/12] arm64: dts: imx8mp: add HDMI irqsteer
On Sat, Feb 03, 2024 at 10:52:46AM -0600, Adam Ford wrote: > From: Lucas Stach > > The HDMI irqsteer is a secondary interrupt controller within the HDMI > subsystem that maps all HDMI peripheral IRQs into a single upstream > IRQ line. > > Signed-off-by: Lucas Stach This is missing your signed-off-by, and in other patches of this series your signed-off-by is not the last, as it should be. Please have a look and fix this and the other instances. Thanks for this work! Francesco
Re: [PATCH v4 4/4] arm64: dts: rockchip: Add devicetree for Pine64 PineTab2
Tested-by: Dang Huynh On Saturday, January 27, 2024 9:48:45 AM UTC Manuel Traut wrote: > This includes support for both the v0.1 units that were sent to developers > and the v2.0 units from production.
Re: (subset) [PATCH v4 0/4] arm64: rockchip: Pine64 PineTab2 support
On Sat, 27 Jan 2024 10:48:41 +0100, Manuel Traut wrote: > This adds support for the BOE TH101MB31IG002 LCD Panel used in PineTab2 [1] > and > PineTab-V [2] as well as the devictrees for the PineTab2 v0.1 and v2.0. > > The BOE LCD Panel patch was retrieved from [3]. The function-name prefix has > been adapted and the LCD init section was simplified. > > The PineTab2 devicetree patch was retrieved from [4]. Some renaming was needed > to pass the dtb-checks, the brightness-levels are specified as range and steps > instead of a list of values. > > [...] Applied, thanks! [3/4] dt-bindings: arm64: rockchip: Add Pine64 PineTab2 commit: 6a0a5a2a71b3e3c4ae1ee0b34a496cbf2d980832 [4/4] arm64: dts: rockchip: Add devicetree for Pine64 PineTab2 commit: 1b7e19448f8fbeee23111795f67a003431c40b27 Best regards, -- Heiko Stuebner
Re:Re: [PATCH v4 00/14] drm: Add a driver for CSF-based Mali GPUs
Hi Boris:
在 2024-02-04 18:07:56，"Boris Brezillon" 写道：
>On Sun, 4 Feb 2024 09:14:44 +0800 (CST)
>"Andy Yan" wrote:
>
>> Hi Boris：
>> I saw this warning sometimes（Run on a armbain based bookworm），not sure is a
>> know issue or something else。
>
>No it's not, and I didn't manage to reproduce locally. Looks like
>you're using a 6.8 kernel, but my panthor-v4/next branches are still
>based on drm-misc-next from 2 weeks ago, which was based on a 6.7
>kernel. Can you share the kernel branch you're using?
>
Here is my kernel branch:
https://github.com/andyshrk/linux/commits/linux-6.8-rc1-rk3588_panthor_v4/
>> [15368.293031] systemd-journald[715]: Received client request to relinquish
>> /var/log/journal/1bc4a340506142af9bd31a6a3d2170ba access.
>> [37743.040737] [ cut here ]
>> [37743.040764] panthor fb00.gpu: drm_WARN_ON(shmem->pages_use_count)
>> [37743.040890] WARNING: CPU: 2 PID: 5702 at
>> drivers/gpu/drm/drm_gem_shmem_helper.c:158 drm_gem_shmem_free+0x144/0x14c
>> [drm_shmem_helper]
>> [37743.040929] Modules linked in: joydev rfkill sunrpc lz4hc lz4 zram
>> binfmt_misc hantro_vpu crct10dif_ce v4l2_vp9 v4l2_h264
>> snd_soc_simple_amplifier v4l2_mem2mem videobuf2_dma_contig
>> snd_soc_es8328_i2c videobuf2_memops rk_crypto2 snd_soc_es8328 videobuf2_v4l2
>> sm3_generic videodev crypto_engine sm3 rockchip_rng videobuf2_common
>> nvmem_rockchip_otp snd_soc_rockchip_i2s_tdm snd_soc_hdmi_codec
>> snd_soc_simple_card mc snd_soc_simple_card_utils snd_soc_core snd_compress
>> ac97_bus snd_pcm_dmaengine snd_pcm snd_timer snd soundcore dm_mod ip_tables
>> x_tables autofs4 dw_hdmi_qp_i2s_audio dw_hdmi_qp_cec rk808_regulator
>> rockchipdrm dw_mipi_dsi dw_hdmi_qp dw_hdmi analogix_dp drm_dma_helper
>> fusb302 display_connector rk8xx_spi drm_display_helper
>> phy_rockchip_snps_pcie3 phy_rockchip_samsung_hdptx_hdmi panthor tcpm
>> rk8xx_core cec drm_gpuvm gpu_sched drm_kms_helper drm_shmem_helper drm_exec
>> r8169 drm pwm_bl adc_keys
>> [37743.041108] CPU: 2 PID: 5702 Comm: kworker/u16:8 Not tainted
>> 6.8.0-rc1-edge-rockchip-rk3588 #2
>> [37743.041115] Hardware name: Rockchip RK3588 EVB1 V10 Board (DT)
>> [37743.041120] Workqueue: panthor-cleanup
>> panthor_vm_bind_job_cleanup_op_ctx_work [panthor]
>> [37743.041151] pstate: 6049 (nZCv daif +PAN -UAO -TCO -DIT -SSBS
>> BTYPE=--)
>> [37743.041157] pc : drm_gem_shmem_free+0x144/0x14c [drm_shmem_helper]
>> [37743.041169] lr : drm_gem_shmem_free+0x144/0x14c [drm_shmem_helper]
>> [37743.041181] sp : 80008d37bcc0
>> [37743.041184] x29: 80008d37bcc0 x28: 800081d379c0 x27:
>> 800081d37000
>> [37743.041196] x26: 00019909a280 x25: 00019909a2c0 x24:
>> 0001017a4c05
>> [37743.041206] x23: dead0100 x22: dead0122 x21:
>> 0001627ac1a0
>> [37743.041217] x20: x19: 0001627ac000 x18:
>>
>> [37743.041227] x17: 00040044 x16: 005000f2b5503510 x15:
>> fff91b77
>> [37743.041238] x14: 0001 x13: 03c5 x12:
>> ffea
>> [37743.041248] x11: dfff x10: dfff x9 :
>> 800081e0e818
>> [37743.041259] x8 : 0002ffe8 x7 : c000dfff x6 :
>> 000affa8
>> [37743.041269] x5 : 1fff x4 : x3 :
>> 8000819a6008
>> [37743.041279] x2 : x1 : x0 :
>> 00018465e900
>> [37743.041290] Call trace:
>> [37743.041293] drm_gem_shmem_free+0x144/0x14c [drm_shmem_helper]
>> [37743.041306] panthor_gem_free_object+0x24/0xa0 [panthor]
>> [37743.041321] drm_gem_object_free+0x1c/0x30 [drm]
>> [37743.041452] panthor_vm_bo_put+0xc4/0x12c [panthor]
>
>I checked the _pin/_unpin calls in panthor, and they seem to be
>balanced (we take a ref when we allocate a gpuvm_bo and release it
>when the gpuvm_bo is gone). I wonder if something else is calling
>_pin_pages() or _get_pages() without holding a GEM ref...
>
>While investigating I found a double-cleanup in the code (see below)
>which explains why those memset(0) were required in
>panthor_vm_cleanup_op_ctx()), but I doubt it fixes your issue.
>
>--->8---
>diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c
>b/drivers/gpu/drm/panthor/panthor_mmu.c
>index d3ce29cd0662..5606ab4d6289 100644
>--- a/drivers/gpu/drm/panthor/panthor_mmu.c
>+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
>@@ -1085,17 +1085,12 @@ static void panthor_vm_cleanup_op_ctx(struct
>panthor_vm_op_ctx *op_ctx,
>}
>
>kfree(op_ctx->rsvd_page_tables.pages);
>- memset(_ctx->rsvd_page_tables, 0, sizeof(op_ctx->rsvd_page_tables));
>
>if (op_ctx->map.vm_bo)
>panthor_vm_bo_put(op_ctx->map.vm_bo);
>
>- memset(_ctx->map, 0, sizeof(op_ctx->map));
>-
>- for (u32 i = 0; i < ARRAY_SIZE(op_ctx->preallocated_vmas); i++) {
>+ for (u32 i = 0; i < ARRAY_SIZE(op_ctx->preallocated_vmas); i++)
>kfree(op_ctx->preallocated_vmas[i]);
>-
[PATCH v13 7/7] phy: freescale: Add HDMI PHY driver for i.MX8MQ
Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ. Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. HDMI PHY mode is configurated in the driver. Signed-off-by: Sandor Yu Tested-by: Alexander Stein --- v12->v13: - Fix build warning v11->v12: - Adjust clk disable order. - Return error code to replace -1 for function wait_for_ack(). - Use bool for variable pclk_in. - Add year 2024 to copyright. drivers/phy/freescale/Kconfig | 10 + drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c | 960 3 files changed, 971 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index c39709fd700ac..14f47b7cc77ab 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -45,6 +45,16 @@ config PHY_FSL_IMX8MQ_DP Enable this to support the Cadence HDPTX DP PHY driver on i.MX8MQ SOC. +config PHY_FSL_IMX8MQ_HDMI + tristate "Freescale i.MX8MQ HDMI PHY support" + depends on OF && HAS_IOMEM + depends on COMMON_CLK + select GENERIC_PHY + select CDNS_MHDP_HELPER + help + Enable this to support the Cadence HDPTX HDMI PHY driver + on i.MX8MQ SOC. + endif config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index 47e5285209fa8..1380ac31c2ead 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_FSL_IMX8MQ_DP)+= phy-fsl-imx8mq-dp.o +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDMI) += phy-fsl-imx8mq-hdmi.o obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c b/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c new file mode 100644 index 0..537b1f45c91cc --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c @@ -0,0 +1,960 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence High-Definition Multimedia Interface (HDMI) PHY driver + * + * Copyright (C) 2022-2024 NXP Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +#define ADDR_PHY_AFE 0x8 + +/* PHY registers */ +#define CMN_SSM_BIAS_TMR 0x0022 +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f +#define CMN_PSM_CLK_CTRL 0x0061 +#define CMN_CDIAG_REFCLK_CTRL 0x0062 +#define CMN_PLL0_VCOCAL_START 0x0081 +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084 +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085 +#define CMN_TXPUCAL_CTRL 0x00e0 +#define CMN_TXPDCAL_CTRL 0x00f0 +#define CMN_TXPU_ADJ_CTRL 0x0108 +#define CMN_TXPD_ADJ_CTRL 0x010c +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0 +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1 +#define CMN_DIAG_PLL0_OVRD 0x01c2 +#define CMN_DIAG_PLL0_TEST_MODE0x01c4 +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5 +#define CMN_DIAG_PLL0_CP_TUNE 0x01c6 +#define CMN_DIAG_PLL0_LF_PROG 0x01c7 +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01c8 +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01c9 +#define CMN_DIAG_PLL0_INCLK_CTRL 0x01ca +#define CMN_DIAG_PLL0_PXL_DIVH 0x01cb +#define CMN_DIAG_PLL0_PXL_DIVL 0x01cc +#define CMN_DIAG_HSCLK_SEL 0x01e0 +#define XCVR_PSM_RCTRL 0x4001 +#define TX_TXCC_CAL_SCLR_MULT_00x4047 +#define TX_TXCC_CPOST_MULT_00_00x404c +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0 +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0 +#define XCVR_DIAG_HSCLK_SEL0x40e1 +#define XCVR_DIAG_BIDI_CTRL0x40e8 +#define TX_PSC_A0 0x4100 +#define TX_PSC_A1 0x4101 +#define TX_PSC_A2 0x4102 +#define TX_PSC_A3 0x4103 +#define TX_DIAG_TX_CTRL0x41e0 +#define TX_DIAG_TX_DRV 0x41e1 +#define TX_DIAG_BGREF_PREDRV_DELAY 0x41e7 +#define TX_DIAG_ACYA_0 0x41ff +#define TX_DIAG_ACYA_1 0x43ff +#define TX_DIAG_ACYA_2 0x45ff +#define TX_DIAG_ACYA_3 0x47ff +#define TX_ANA_CTRL_REG_1 0x5020 +#define TX_ANA_CTRL_REG_2 0x5021 +#define
[PATCH v13 6/7] phy: freescale: Add DisplayPort PHY driver for i.MX8MQ
Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort PHY mode is configurated in the driver. Signed-off-by: Sandor Yu --- v12->v13: *No change. v11->v12: - Return error code to replace -1 for function wait_for_ack(). - Set cdns_phy->power_up = false in phy_power_down function. - Remove "RATE_8_1 = 81", it is not used in driver. - Add year 2024 to copyright. drivers/phy/freescale/Kconfig | 10 + drivers/phy/freescale/Makefile| 1 + drivers/phy/freescale/phy-fsl-imx8mq-dp.c | 726 ++ 3 files changed, 737 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-dp.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 853958fb2c063..c39709fd700ac 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE Enable this to add support for the PCIE PHY as found on i.MX8M family of SOCs. +config PHY_FSL_IMX8MQ_DP + tristate "Freescale i.MX8MQ DP PHY support" + depends on OF && HAS_IOMEM + depends on COMMON_CLK + select GENERIC_PHY + select CDNS_MHDP_HELPER + help + Enable this to support the Cadence HDPTX DP PHY driver + on i.MX8MQ SOC. + endif config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index cedb328bc4d28..47e5285209fa8 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_FSL_IMX8MQ_DP)+= phy-fsl-imx8mq-dp.o obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-dp.c b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c new file mode 100644 index 0..2e24ca04c5980 --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence HDP-TX Display Port Interface (DP) PHY driver + * + * Copyright (C) 2022-2024 NXP Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADDR_PHY_AFE 0x8 + +/* PHY registers */ +#define CMN_SSM_BIAS_TMR 0x0022 +#define CMN_PLLSM0_PLLEN_TMR 0x0029 +#define CMN_PLLSM0_PLLPRE_TMR 0x002a +#define CMN_PLLSM0_PLLVREF_TMR 0x002b +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f +#define CMN_PSM_CLK_CTRL 0x0061 +#define CMN_PLL0_VCOCAL_START 0x0081 +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084 +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085 +#define CMN_PLL0_INTDIV0x0094 +#define CMN_PLL0_FRACDIV 0x0095 +#define CMN_PLL0_HIGH_THR 0x0096 +#define CMN_PLL0_DSM_DIAG 0x0097 +#define CMN_PLL0_SS_CTRL2 0x0099 +#define CMN_ICAL_INIT_TMR 0x00c4 +#define CMN_ICAL_ITER_TMR 0x00c5 +#define CMN_RXCAL_INIT_TMR 0x00d4 +#define CMN_RXCAL_ITER_TMR 0x00d5 +#define CMN_TXPUCAL_INIT_TMR 0x00e4 +#define CMN_TXPUCAL_ITER_TMR 0x00e5 +#define CMN_TXPDCAL_INIT_TMR 0x00f4 +#define CMN_TXPDCAL_ITER_TMR 0x00f5 +#define CMN_ICAL_ADJ_INIT_TMR 0x0102 +#define CMN_ICAL_ADJ_ITER_TMR 0x0103 +#define CMN_RX_ADJ_INIT_TMR0x0106 +#define CMN_RX_ADJ_ITER_TMR0x0107 +#define CMN_TXPU_ADJ_INIT_TMR 0x010a +#define CMN_TXPU_ADJ_ITER_TMR 0x010b +#define CMN_TXPD_ADJ_INIT_TMR 0x010e +#define CMN_TXPD_ADJ_ITER_TMR 0x010f +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0 +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1 +#define CMN_DIAG_PLL0_OVRD 0x01c2 +#define CMN_DIAG_PLL0_TEST_MODE0x01c4 +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5 +#define CMN_DIAG_PLL0_CP_TUNE 0x01c6 +#define CMN_DIAG_PLL0_LF_PROG 0x01c7 +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01c8 +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01c9 +#define CMN_DIAG_HSCLK_SEL 0x01e0 +#define CMN_DIAG_PER_CAL_ADJ 0x01ec +#define CMN_DIAG_CAL_CTRL 0x01ed +#define CMN_DIAG_ACYA 0x01ff +#define XCVR_PSM_RCTRL 0x4001 +#define
[PATCH v13 5/7] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY
Add bindings for Freescale iMX8MQ DP and HDMI PHY.
Signed-off-by: Sandor Yu
Reviewed-by: Rob Herring
---
v9->v13:
*No change.
.../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
new file mode 100644
index 0..917f113503dca
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8mq-dp-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX DP/HDMI PHY for Freescale i.MX8MQ SoC
+
+maintainers:
+ - Sandor Yu
+
+properties:
+ compatible:
+enum:
+ - fsl,imx8mq-dp-phy
+ - fsl,imx8mq-hdmi-phy
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: PHY reference clock.
+ - description: APB clock.
+
+ clock-names:
+items:
+ - const: ref
+ - const: apb
+
+ "#phy-cells":
+const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+dp_phy: phy@32c0 {
+compatible = "fsl,imx8mq-dp-phy";
+reg = <0x32c0 0x10>;
+#phy-cells = <0>;
+clocks = <_phy_27m>, < IMX8MQ_CLK_DISP_APB_ROOT>;
+clock-names = "ref", "apb";
+};
--
2.34.1
[PATCH v13 4/7] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver
Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
SOC's ROM code. Bootload binary included respective specific firmware
is required.
Driver will check display connector type and
then load the corresponding driver.
Signed-off-by: Sandor Yu
Tested-by: Alexander Stein
---
v12->v13:
- Explicitly include linux/platform_device.h for cdns-mhdp8501-core.c
- Fix build warning
- Order bit bpc and color_space in descending shit.
v11->v12:
- Replace DRM_INFO with dev_info or dev_warn.
- Replace DRM_ERROR with dev_err.
- Return ret when cdns_mhdp_dpcd_read failed in function
cdns_dp_aux_transferi().
- Remove unused parmeter in function cdns_dp_get_msa_misc
and use two separate variables for color space and bpc.
- Add year 2024 to copyright.
drivers/gpu/drm/bridge/cadence/Kconfig| 16 +
drivers/gpu/drm/bridge/cadence/Makefile | 2 +
.../drm/bridge/cadence/cdns-mhdp8501-core.c | 316
.../drm/bridge/cadence/cdns-mhdp8501-core.h | 365 +
.../gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 699 ++
.../drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 679 +
6 files changed, 2077 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index e0973339e9e33..45848e741f5f4 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -51,3 +51,19 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_MHDP8501
+ tristate "Cadence MHDP8501 DP/HDMI bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ select DRM_DISPLAY_DP_HELPER
+ select DRM_DISPLAY_HELPER
+ select CDNS_MHDP_HELPER
+ select DRM_CDNS_AUDIO
+ depends on OF
+ help
+ Support Cadence MHDP8501 DisplayPort/HDMI bridge.
+ Cadence MHDP8501 support one or more protocols,
+ including DisplayPort and HDMI.
+ To use the DP and HDMI drivers, their respective
+ specific firmware is required.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 087dc074820d7..02c1a9f3cf6fc 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+obj-$(CONFIG_DRM_CDNS_MHDP8501) += cdns-mhdp8501.o
+cdns-mhdp8501-y := cdns-mhdp8501-core.o cdns-mhdp8501-dp.o cdns-mhdp8501-hdmi.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
new file mode 100644
index 0..bc36797b39fdb
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence Display Port Interface (DP) driver
+ *
+ * Copyright (C) 2023, 2024 NXP Semiconductor, Inc.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cdns-mhdp8501-core.h"
+
+static int cdns_mhdp8501_read_hpd(struct cdns_mhdp8501_device *mhdp)
+{
+ u8 status;
+ int ret;
+
+ mutex_lock(>mbox_mutex);
+
+ ret = cdns_mhdp_mailbox_send(>base, MB_MODULE_ID_GENERAL,
+GENERAL_GET_HPD_STATE, 0, NULL);
+ if (ret)
+ goto err_get_hpd;
+
+ ret = cdns_mhdp_mailbox_recv_header(>base, MB_MODULE_ID_GENERAL,
+ GENERAL_GET_HPD_STATE,
+ sizeof(status));
+ if (ret)
+ goto err_get_hpd;
+
+ ret = cdns_mhdp_mailbox_recv_data(>base, , sizeof(status));
+ if (ret)
+ goto err_get_hpd;
+
+ mutex_unlock(>mbox_mutex);
+
+ return status;
+
+err_get_hpd:
+ dev_err(mhdp->dev, "read hpd failed: %d\n", ret);
+ mutex_unlock(>mbox_mutex);
+
+ return ret;
+}
+
+enum drm_connector_status cdns_mhdp8501_detect(struct cdns_mhdp8501_device
*mhdp)
+{
+ u8 hpd = 0xf;
+
+ hpd = cdns_mhdp8501_read_hpd(mhdp);
+ if (hpd == 1)
+ return connector_status_connected;
+ else if (hpd == 0)
+ return connector_status_disconnected;
+
+
[PATCH v13 3/7] dt-bindings: display: bridge: Add Cadence MHDP8501
Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.
Signed-off-by: Sandor Yu
Reviewed-by: Krzysztof Kozlowski
---
v9->v13:
*No change.
.../display/bridge/cdns,mhdp8501.yaml | 104 ++
1 file changed, 104 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml
new file mode 100644
index 0..3ae643845cfee
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8501.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP8501 DP/HDMI bridge
+
+maintainers:
+ - Sandor Yu
+
+description:
+ Cadence MHDP8501 DisplayPort/HDMI interface.
+
+properties:
+ compatible:
+enum:
+ - fsl,imx8mq-mhdp8501
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+description: MHDP8501 DP/HDMI APB clock.
+
+ phys:
+maxItems: 1
+description:
+ phandle to the DisplayPort or HDMI PHY
+
+ interrupts:
+items:
+ - description: Hotplug cable plugin.
+ - description: Hotplug cable plugout.
+
+ interrupt-names:
+items:
+ - const: plug_in
+ - const: plug_out
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Input port from display controller output.
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Output port to DisplayPort or HDMI connector.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - interrupt-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+mhdp: display-bridge@32c0 {
+compatible = "fsl,imx8mq-mhdp8501";
+reg = <0x32c0 0x10>;
+interrupts = ,
+ ;
+interrupt-names = "plug_in", "plug_out";
+clocks = < IMX8MQ_CLK_DISP_APB_ROOT>;
+phys = <_phy>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+
+mhdp_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+
+mhdp_out: endpoint {
+remote-endpoint = <_connector>;
+};
+};
+};
+};
--
2.34.1
[PATCH v13 2/7] phy: Add HDMI configuration options
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor Yu
Reviewed-by: Dmitry Baryshkov
Acked-by: Vinod Koul
---
v9->v13:
*No change.
include/linux/phy/phy-hdmi.h | 24
include/linux/phy/phy.h | 7 ++-
2 files changed, 30 insertions(+), 1 deletion(-)
create mode 100644 include/linux/phy/phy-hdmi.h
diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
new file mode 100644
index 0..b7de88e9090f0
--- /dev/null
+++ b/include/linux/phy/phy-hdmi.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+#include
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate: Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+ unsigned int pixel_clk_rate;
+ unsigned int bpc;
+ enum hdmi_colorspace color_space;
+};
+
+#endif /* __PHY_HDMI_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index aa76609ba2580..0731b8b707f7c 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
#include
#include
+#include
#include
#include
@@ -42,7 +43,8 @@ enum phy_mode {
PHY_MODE_MIPI_DPHY,
PHY_MODE_SATA,
PHY_MODE_LVDS,
- PHY_MODE_DP
+ PHY_MODE_DP,
+ PHY_MODE_HDMI,
};
enum phy_media {
@@ -60,11 +62,14 @@ enum phy_media {
* the DisplayPort protocol.
* @lvds: Configuration set applicable for phys supporting
* the LVDS phy mode.
+ * @hdmi: Configuration set applicable for phys supporting
+ * the HDMI phy mode.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
struct phy_configure_opts_dpdp;
struct phy_configure_opts_lvds lvds;
+ struct phy_configure_opts_hdmi hdmi;
};
/**
--
2.34.1
[PATCH v13 1/7] drm: bridge: Cadence: Create mhdp helper driver
MHDP8546 mailbox access functions will be share to other mhdp driver
and Cadence HDP-TX HDMI/DP PHY drivers.
Create a new mhdp helper driver and move all those functions into.
cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(),
because it use the DPTX command ID DPTX_WRITE_REGISTER.
New cdns_mhdp_reg_write() is created with the general command ID
GENERAL_REGISTER_WRITE.
rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver,
use cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write()
same as the other mailbox access functions.
Signed-off-by: Sandor Yu
---
v12->v13:
*No change.
V11->v12:
- Move status initialize out of mbox_mutex.
- Reorder API functions in alphabetical.
- Add notes for malibox access functions.
- Add year 2024 to copyright.
drivers/gpu/drm/bridge/cadence/Kconfig| 4 +
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 304 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 403 +++---
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 44 +-
include/drm/bridge/cdns-mhdp-helper.h | 97 +
6 files changed, 479 insertions(+), 374 deletions(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
create mode 100644 include/drm/bridge/cdns-mhdp-helper.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index cced81633ddcd..e0973339e9e33 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -21,6 +21,9 @@ config DRM_CDNS_DSI_J721E
the routing of the DSS DPI signal to the Cadence DSI.
endif
+config CDNS_MHDP_HELPER
+ tristate
+
config DRM_CDNS_MHDP8546
tristate "Cadence DPI/DP bridge"
select DRM_DISPLAY_DP_HELPER
@@ -28,6 +31,7 @@ config DRM_CDNS_MHDP8546
select DRM_DISPLAY_HELPER
select DRM_KMS_HELPER
select DRM_PANEL_BRIDGE
+ select CDNS_MHDP_HELPER
depends on OF
help
Support Cadence DPI to DP bridge. This is an internal
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index c95fd5b81d137..087dc074820d7 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
cdns-dsi-y := cdns-dsi-core.o
cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
+obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
new file mode 100644
index 0..ba31695b483ac
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, 2024 NXP Semiconductor, Inc.
+ *
+ */
+#include
+#include
+#include
+
+/* Mailbox helper functions */
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_base *base)
+{
+ int ret, empty;
+
+ WARN_ON(!mutex_is_locked(base->mbox_mutex));
+
+ ret = readx_poll_timeout(readl, base->regs + CDNS_MAILBOX_EMPTY,
+empty, !empty, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(base->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_base *base, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(base->mbox_mutex));
+
+ ret = readx_poll_timeout(readl, base->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, base->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_base *base,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < sizeof(header); i++) {
+ ret = cdns_mhdp_mailbox_read(base);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2);
+
+ if (opcode != header[0] || module_id != header[1] ||
+ req_size != mbox_size) {
+ /*
+* If the message in mailbox is not what we want, we need to
+* clear the mailbox by reading its contents.
+*/
+ for (i = 0; i < mbox_size; i++)
+ if
[PATCH v13 0/7] Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ
The patch set initial support Cadence MHDP8501(HDMI/DP) DRM bridge driver and Cadence HDP-TX PHY(HDMI/DP) drivers for Freescale i.MX8MQ. The patch set compose of DRM bridge drivers and PHY drivers. Both of them need by patch #1 and #2 to pass build. DRM bridges driver patches: #1: drm: bridge: Cadence: Creat mhdp helper driver #2: phy: Add HDMI configuration options #3: dt-bindings: display: bridge: Add Cadence MHDP8501 #4: drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver PHY driver patches: #1: drm: bridge: Cadence: Creat mhdp helper driver #2: phy: Add HDMI configuration options #5: dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY #6: phy: freescale: Add DisplayPort PHY driver for i.MX8MQ #7: phy: freescale: Add HDMI PHY driver for i.MX8MQ v12->v13: Patch #4: - Explicitly include linux/platform_device.h for cdns-mhdp8501-core.c - Fix build warning - Order bit bpc and color_space in descending shit. Patch #7: - Fix build warning v11->v12: Patch #1: - Move status initialize out of mbox_mutex. - Reorder API functions in alphabetical. - Add notes for malibox access functions. - Add year 2024 to copyright. Patch #4: - Replace DRM_INFO with dev_info or dev_warn. - Replace DRM_ERROR with dev_err. - Return ret when cdns_mhdp_dpcd_read failed in function cdns_dp_aux_transferi(). - Remove unused parmeter in function cdns_dp_get_msa_misc and use two separate variables for color space and bpc. - Add year 2024 to copyright. Patch #6: - Return error code to replace -1 for function wait_for_ack(). - Set cdns_phy->power_up = false in phy_power_down function. - Remove "RATE_8_1 = 81", it is not used in driver. - Add year 2024 to copyright. Patch #7: - Adjust clk disable order. - Return error code to replace -1 for function wait_for_ack(). - Use bool for variable pclk_in. - Add year 2024 to copyright. v10->v11: - rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver, use cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write() same as the other mailbox access functions. - use static for cdns_mhdp_mailbox_write() and cdns_mhdp_mailbox_read() and remove them from EXPORT_SYMBOL_GPL(). - remove MODULE_ALIAS() from mhdp8501 driver. v9->v10: - Create mhdp helper driver to replace macro functions, move all mhdp mailbox access functions and common functions into the helper driver. Patch #1:drm: bridge: Cadence: Creat mhdp helper driver it is totaly different with v9. v8->v9: - Remove compatible string "cdns,mhdp8501" that had removed from dt-bindings file in v8. - Add Dmitry's R-b tag to patch #2 - Add Krzysztof's R-b tag to patch #3 v7->v8: MHDP8501 HDMI/DP: - Correct DT node name to "display-bridge". - Remove "cdns,mhdp8501" from mhdp8501 dt-binding doc. HDMI/DP PHY: - Introduced functions `wait_for_ack` and `wait_for_ack_clear` to handle waiting with acknowledgment bits set and cleared respectively. - Use FIELD_PRE() to set bitfields for both HDMI and DP PHY. v6->v7: MHDP8501 HDMI/DP: - Combine HDMI and DP driver into one mhdp8501 driver. Use the connector type to load the corresponding functions. - Remove connector init functions. - Add in phy_hdmi.h to reuse ‘enum hdmi_colorspace’. HDMI/DP PHY: - Lowercase hex values - Fix parameters indent issue on some functions - Replace ‘udelay’ with ‘usleep_range’ v5->v6: HDMI/DP bridge driver - 8501 is the part number of Cadence MHDP on i.MX8MQ. Use MHDP8501 to name hdmi/dp drivers and files. - Add compatible "fsl,imx8mq-mhdp8501-dp" for i.MX8MQ DP driver - Add compatible "fsl,imx8mq-mhdp8501-hdmi" for i.MX8MQ HDMI driver - Combine HDMI and DP dt-bindings into one file cdns,mhdp8501.yaml - Fix HDMI scrambling is not enable issue when driver working in 4Kp60 mode. - Add HDMI/DP PHY API mailbox protect. HDMI/DP PHY driver: - Rename DP and HDMI PHY files and move to folder phy/freescale/ - Remove properties num_lanes and link_rate from DP PHY driver. - Combine HDMI and DP dt-bindings into one file fsl,imx8mq-dp-hdmi-phy.yaml - Update compatible string to "fsl,imx8mq-dp-phy". - Update compatible string to "fsl,imx8mq-hdmi-phy". v4->v5: - Drop "clk" suffix in clock name. - Add output port property in the example of hdmi/dp. v3->v4: dt-bindings: - Correct dt-bindings coding style and address review comments. - Add apb_clk description. - Add output port for HDMI/DP connector PHY: - Alphabetically sorted in Kconfig and Makefile for DP and HDMI PHY - Remove unused registers define from HDMI and DP PHY drivers. - More description in phy_hdmi.h. - Add apb_clk to HDMI and DP phy driver. HDMI/DP: - Use get_unaligned_le32() to replace hardcode type conversion in HDMI AVI infoframe data fill function. - Add mailbox mutex lock in HDMI/DP driver for phy functions to reslove race conditions between HDMI/DP and PHY drivers. - Add apb_clk to both HDMI and DP driver. - Rename some function names and add prefix with "cdns_hdmi/cdns_dp". - Remove bpc 12 and 16 optional that not supported. v2->v3: Address comments for
Re: [PATCH v4 00/14] drm: Add a driver for CSF-based Mali GPUs
On Sun, 4 Feb 2024 09:14:44 +0800 (CST)
"Andy Yan" wrote:
> Hi Boris：
> I saw this warning sometimes（Run on a armbain based bookworm），not sure is a
> know issue or something else。
No it's not, and I didn't manage to reproduce locally. Looks like
you're using a 6.8 kernel, but my panthor-v4/next branches are still
based on drm-misc-next from 2 weeks ago, which was based on a 6.7
kernel. Can you share the kernel branch you're using?
> [15368.293031] systemd-journald[715]: Received client request to relinquish
> /var/log/journal/1bc4a340506142af9bd31a6a3d2170ba access.
> [37743.040737] [ cut here ]
> [37743.040764] panthor fb00.gpu: drm_WARN_ON(shmem->pages_use_count)
> [37743.040890] WARNING: CPU: 2 PID: 5702 at
> drivers/gpu/drm/drm_gem_shmem_helper.c:158 drm_gem_shmem_free+0x144/0x14c
> [drm_shmem_helper]
> [37743.040929] Modules linked in: joydev rfkill sunrpc lz4hc lz4 zram
> binfmt_misc hantro_vpu crct10dif_ce v4l2_vp9 v4l2_h264
> snd_soc_simple_amplifier v4l2_mem2mem videobuf2_dma_contig snd_soc_es8328_i2c
> videobuf2_memops rk_crypto2 snd_soc_es8328 videobuf2_v4l2 sm3_generic
> videodev crypto_engine sm3 rockchip_rng videobuf2_common nvmem_rockchip_otp
> snd_soc_rockchip_i2s_tdm snd_soc_hdmi_codec snd_soc_simple_card mc
> snd_soc_simple_card_utils snd_soc_core snd_compress ac97_bus
> snd_pcm_dmaengine snd_pcm snd_timer snd soundcore dm_mod ip_tables x_tables
> autofs4 dw_hdmi_qp_i2s_audio dw_hdmi_qp_cec rk808_regulator rockchipdrm
> dw_mipi_dsi dw_hdmi_qp dw_hdmi analogix_dp drm_dma_helper fusb302
> display_connector rk8xx_spi drm_display_helper phy_rockchip_snps_pcie3
> phy_rockchip_samsung_hdptx_hdmi panthor tcpm rk8xx_core cec drm_gpuvm
> gpu_sched drm_kms_helper drm_shmem_helper drm_exec r8169 drm pwm_bl adc_keys
> [37743.041108] CPU: 2 PID: 5702 Comm: kworker/u16:8 Not tainted
> 6.8.0-rc1-edge-rockchip-rk3588 #2
> [37743.041115] Hardware name: Rockchip RK3588 EVB1 V10 Board (DT)
> [37743.041120] Workqueue: panthor-cleanup
> panthor_vm_bind_job_cleanup_op_ctx_work [panthor]
> [37743.041151] pstate: 6049 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [37743.041157] pc : drm_gem_shmem_free+0x144/0x14c [drm_shmem_helper]
> [37743.041169] lr : drm_gem_shmem_free+0x144/0x14c [drm_shmem_helper]
> [37743.041181] sp : 80008d37bcc0
> [37743.041184] x29: 80008d37bcc0 x28: 800081d379c0 x27:
> 800081d37000
> [37743.041196] x26: 00019909a280 x25: 00019909a2c0 x24:
> 0001017a4c05
> [37743.041206] x23: dead0100 x22: dead0122 x21:
> 0001627ac1a0
> [37743.041217] x20: x19: 0001627ac000 x18:
>
> [37743.041227] x17: 00040044 x16: 005000f2b5503510 x15:
> fff91b77
> [37743.041238] x14: 0001 x13: 03c5 x12:
> ffea
> [37743.041248] x11: dfff x10: dfff x9 :
> 800081e0e818
> [37743.041259] x8 : 0002ffe8 x7 : c000dfff x6 :
> 000affa8
> [37743.041269] x5 : 1fff x4 : x3 :
> 8000819a6008
> [37743.041279] x2 : x1 : x0 :
> 00018465e900
> [37743.041290] Call trace:
> [37743.041293] drm_gem_shmem_free+0x144/0x14c [drm_shmem_helper]
> [37743.041306] panthor_gem_free_object+0x24/0xa0 [panthor]
> [37743.041321] drm_gem_object_free+0x1c/0x30 [drm]
> [37743.041452] panthor_vm_bo_put+0xc4/0x12c [panthor]
I checked the _pin/_unpin calls in panthor, and they seem to be
balanced (we take a ref when we allocate a gpuvm_bo and release it
when the gpuvm_bo is gone). I wonder if something else is calling
_pin_pages() or _get_pages() without holding a GEM ref...
While investigating I found a double-cleanup in the code (see below)
which explains why those memset(0) were required in
panthor_vm_cleanup_op_ctx()), but I doubt it fixes your issue.
--->8---
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c
b/drivers/gpu/drm/panthor/panthor_mmu.c
index d3ce29cd0662..5606ab4d6289 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu.c
+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
@@ -1085,17 +1085,12 @@ static void panthor_vm_cleanup_op_ctx(struct
panthor_vm_op_ctx *op_ctx,
}
kfree(op_ctx->rsvd_page_tables.pages);
- memset(_ctx->rsvd_page_tables, 0, sizeof(op_ctx->rsvd_page_tables));
if (op_ctx->map.vm_bo)
panthor_vm_bo_put(op_ctx->map.vm_bo);
- memset(_ctx->map, 0, sizeof(op_ctx->map));
-
- for (u32 i = 0; i < ARRAY_SIZE(op_ctx->preallocated_vmas); i++) {
+ for (u32 i = 0; i < ARRAY_SIZE(op_ctx->preallocated_vmas); i++)
kfree(op_ctx->preallocated_vmas[i]);
- op_ctx->preallocated_vmas[i] = NULL;
- }
list_for_each_entry_safe(vma, tmp_vma, _ctx->returned_vmas, node) {
list_del(>node);
@@ -2382,7 +2377,6 @@ static void
panthor_vm_bind_job_cleanup_op_ctx_work(struct work_struct *work)
struct
Re: RE: Re: [PATCH 0/4] Fixing live video input in ZynqMP DPSUB
On Thu, Feb 01, 2024 at 06:01:01PM +0100, Maxime Ripard wrote: > On Fri, Jan 26, 2024 at 11:18:30PM +, Klymenko, Anatoliy wrote: > > On Friday, January 26, 2024 4:26 AM, Maxime Ripard wrote: > > > On Wed, Jan 17, 2024 at 04:23:43PM +0200, Laurent Pinchart wrote: > > > > On Mon, Jan 15, 2024 at 09:28:39AM +0100, Maxime Ripard wrote: > > > > > On Fri, Jan 12, 2024 at 03:42:18PM -0800, Anatoliy Klymenko wrote: > > > > > > Patches 1/4,2/4,3/4 are minor fixes. > > > > > > > > > > > > DPSUB requires input live video format to be configured. > > > > > > Patch 4/4: The DP Subsystem requires the input live video format to > > > > > > be > > > > > > configured. In this patch we are assuming that the CRTC's bus > > > > > > format is fixed > > > > > > and comes from the device tree. This is a proposed solution, as > > > > > > there are no api > > > > > > to query CRTC output bus format. > > > > > > > > > > > > Is this a good approach to go with? > > > > > > > > > > I guess you would need to expand a bit on what "live video input" is? > > > > > Is > > > > > it some kind of mechanism to bypass memory and take your pixels > > > > > straight > > > > > from a FIFO from another device, or something else? > > > > > > > > Yes and no. > > > > > > > > The DPSUB integrates DMA engines, a blending engine (two planes), and a > > > > DP encoder. The dpsub driver supports all of this, and creates a DRM > > > > device. The DP encoder hardware always takes its input data from the > > > > output of the blending engine. > > > > > > > > The blending engine can optionally take input data from a bus connected > > > > to the FPGA fabric, instead of taking it from the DPSUB internal DMA > > > > engines. When operating in that mode, the dpsub driver exposes the DP > > > > encoder as a bridge, and internally programs the blending engine to > > > > disable blending. Typically, the FPGA fabric will then contain a CRTC of > > > > some sort, with a driver that will acquire the DP encoder bridge as > > > > usually done. > > > > > > > > In this mode of operation, it is typical for the IP cores in FPGA fabric > > > > to be synthesized with a fixed format (as that saves resources), while > > > > the DPSUB supports multiple input formats. > > > > > > Where is that CRTC driver? It's not clear to me why the format would > > > need to be in the device tree at all. Format negociation between the > > > CRTC and whatever comes next is already done in a number of drivers so > > > it would be useful to have that kind of API outside of the bridge > > > support. > > > > One example of such CRTC driver: > > https://github.com/Xilinx/linux-xlnx/blob/master/drivers/gpu/drm/xlnx/xlnx_mixer.c > > It's not > > upstreamed yet. Bus format negotiations here are handled by utilizing > > Xilinx-specific bridge > > framework. Ideally, it would be nice to rework this to comply with the > > upstream DRM bridge > > framework. > > > > > > Bridge drivers in the upstream kernel work the other way around, with > > > > the bridge hardware supporting a limited set of formats, and the CRTC > > > > then being programmed with whatever the bridges chain needs. Here, the > > > > negotiation needs to go the other way around, as the CRTC is the > > > > limiting factor, not the bridge. > > > > > > Sounds like there's something to rework in the API then? > > > > > Adding an optional CRTC callback imposing CRTC specific bus format > > restrictions, which may be > > called from here > > https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/drm_bridge.c#L935 > > would solve the problem. > > CRTCs and bridges are orthogonal. If anything, I'd expect that callback > to be set at the CRTC, encoder and connector levels and filled by the > drm_bridge code if relevant. I'm thinking about a new CRTC operation that would be called by the bridge chain format negotiation helper drm_atomic_bridge_chain_select_bus_fmts() (or one of the functions it calls), to filter the list of formats supported by the chain based on what the CRTC supports, or possibly to pick a format in that list. This needs to be prototyped -- Regards, Laurent Pinchart
Re: [PATCH 2/2] drm: mipi-dsi: make mipi_dsi_bus_type const
On Sat, 3 Feb 2024 at 22:20, Ricardo B. Marliere wrote: > > Now that the driver core can properly handle constant struct bus_type, > move the mipi_dsi_bus_type variable to be a constant structure as well, > placing it into read-only memory which can not be modified at runtime. > > Cc: Greg Kroah-Hartman > Suggested-by: Greg Kroah-Hartman > Signed-off-by: Ricardo B. Marliere > --- > drivers/gpu/drm/drm_mipi_dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH 1/2] drm: display: make dp_aux_bus_type const
On Sat, 3 Feb 2024 at 22:20, Ricardo B. Marliere wrote: > > Now that the driver core can properly handle constant struct bus_type, > move the dp_aux_bus_type variable to be a constant structure as well, > placing it into read-only memory which can not be modified at runtime. > > Cc: Greg Kroah-Hartman > Suggested-by: Greg Kroah-Hartman > Signed-off-by: Ricardo B. Marliere Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/display/drm_dp_aux_bus.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) -- With best wishes Dmitry
Re: [PATCH V8 02/12] phy: freescale: add Samsung HDMI PHY
On Sat, 3 Feb 2024 at 17:53, Adam Ford wrote:
>
> From: Lucas Stach
>
> This adds the driver for the Samsung HDMI PHY found on the
> i.MX8MP SoC.
>
> Signed-off-by: Lucas Stach
> Signed-off-by: Adam Ford
> Tested-by: Alexander Stein
> ---
> V4: Make lookup table hex values lower case.
>
> V3: Re-order the Makefile to keep it alphabetical
> Remove unused defines
>
> V2: Fixed some whitespace found from checkpatch
> Change error handling when enabling apbclk to use dev_err_probe
> Rebase on Linux-Next
>
> I (Adam) tried to help move this along, so I took Lucas' patch and
> attempted to apply fixes based on feedback. I don't have
> all the history, so apologies for that.
> ---
> drivers/phy/freescale/Kconfig|6 +
> drivers/phy/freescale/Makefile |1 +
> drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1075 ++
> 3 files changed, 1082 insertions(+)
> create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c
>
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index 853958fb2c06..5c2b73042dfc 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE
> Enable this to add support for the PCIE PHY as found on
> i.MX8M family of SOCs.
>
> +config PHY_FSL_SAMSUNG_HDMI_PHY
> + tristate "Samsung HDMI PHY support"
> + depends on OF && HAS_IOMEM
> + help
> + Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
> +
> endif
>
> config PHY_FSL_LYNX_28G
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index cedb328bc4d2..79e5f16d3ce8 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY)+=
> phy-fsl-imx8qm-lvds-phy.o
> obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
> obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
> +obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o
> diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> new file mode 100644
> index ..bf0e2299d00f
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> @@ -0,0 +1,1075 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 NXP
> + * Copyright 2022 Pengutronix, Lucas Stach
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define PHY_REG_33 0x84
> +#define REG33_MODE_SET_DONE BIT(7)
> +#define REG33_FIX_DA BIT(1)
> +
> +#define PHY_REG_34 0x88
> +#define REG34_PHY_READY BIT(7)
> +#define REG34_PLL_LOCKBIT(6)
> +#define REG34_PHY_CLK_READY BIT(5)
> +
> +
> +#define PHY_PLL_REGS_NUM 48
> +
> +struct phy_config {
> + u32 clk_rate;
> + u8 regs[PHY_PLL_REGS_NUM];
> +};
> +
> +const struct phy_config phy_pll_cfg[] = {
> + { 2225, {
> + 0x00, 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40,
> + 0x4f, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80,
> + 0x6c, 0xf2, 0x67, 0x00, 0x10, 0x8f, 0x30, 0x32,
> + 0x60, 0x8f, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0xe0, 0x83, 0x0f, 0x3e, 0xf8, 0x00, 0x00,
> + },
> + }, {
> + 2375, {
> + 0x00, 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40,
> + 0x4f, 0x30, 0x33, 0x65, 0x00, 0x03, 0x25, 0x80,
> + 0x6c, 0xf2, 0x67, 0x00, 0x10, 0x8f, 0x30, 0x32,
> + 0x60, 0x8f, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0xe0, 0x83, 0x0f, 0x3e, 0xf8, 0x00, 0x00,
> + },
Generally I see that these entries contain a high level of duplication.
Could you please extract the common part and a rate-dependent part.
Next, it would be best if instead of writing the register values via
the rate LUT, the driver could calculate those values.
This allows us to support other HDMI modes if the need arises at some point.
> + }, {
> + 2400, {
> + 0x00, 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00,
> + 0x4f, 0x30, 0x33, 0x65, 0x00, 0x01, 0x25, 0x80,
> + 0x6c, 0xf2, 0x67, 0x00, 0x10, 0x8f, 0x30, 0x32,
> + 0x60, 0x8f, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0xe0, 0x83, 0x0f, 0x3e,
