[DynInst_API:] [dyninst/dyninst] 7b1511: Template for adding instructions
Branch: refs/heads/new-parallel-parsing Home: https://github.com/dyninst/dyninst Commit: 7b1511943e76cdef96b9c7e7ede4989805965d52 https://github.com/dyninst/dyninst/commit/7b1511943e76cdef96b9c7e7ede4989805965d52 Author: Benjamin Welton Date: 2018-09-20 (Thu, 20 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- Template for adding instructions Commit: 1707147ae4e3f6f78aa0eba5952bf45fbbd7793a https://github.com/dyninst/dyninst/commit/1707147ae4e3f6f78aa0eba5952bf45fbbd7793a Author: Yuhan Xie Date: 2018-09-20 (Thu, 20 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- added power operations, stopped on pg491 of the manual page, lxvll Commit: 1d4fc85ec0ff17ab3d14941253a9f114c7731439 https://github.com/dyninst/dyninst/commit/1d4fc85ec0ff17ab3d14941253a9f114c7731439 Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- P492-523 Commit: 6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca https://github.com/dyninst/dyninst/commit/6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- 09/25 p492-523(not including p523) skipped: lxv (P492, new keyword DQ; TX not at the last bit), lxvx (P492, a slash in the memory map and two numbers are included) stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0]) stxssp (P501, VRS) stxv (P507, new keyword DQ) xsabsqp (P512, 0 in it) new keywords included: -included new keywords "XS", it should be the storing version of "XT") -included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction) -included VRA, VRB (page 520 of manual) Additional: --xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual) Commit: 5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6 https://github.com/dyninst/dyninst/commit/5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6 Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Log Message: --- Merge branch 'power_vector' of github.com:dyninst/dyninst into power_vector Commit: 2c8113207782d5f032271773403e78be0e977bde https://github.com/dyninst/dyninst/commit/2c8113207782d5f032271773403e78be0e977bde Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Changed paths: M instructionAPI/src/power_opcode_tables.C Log Message: --- 09/25 p492-523(not including p523) skipped: lxv (P492, new keyword DQ; TX not at the last bit), lxvx (P492, a slash in the memory map and two numbers are included) stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0]) stxssp (P501, VRS) stxv (P507, new keyword DQ) xsabsqp (P512, 0 in it) new keywords included: -included new keywords "XS", it should be the storing version of "XT") -included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction) -included VRA, VRB (page 520 of manual) Additional: --xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual) Commit: 0a3c9f6730e67eed51a9335b95863650a4844027 https://github.com/dyninst/dyninst/commit/0a3c9f6730e67eed51a9335b95863650a4844027 Author: Yuhan Xie Date: 2018-09-27 (Thu, 27 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- 09/27/2018 New opcodes added p523-576(not including p576) skipped: nothing new: -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25 -new extended opcodes (opcode 60/61/63), added on 09/25 but was not included in the last log. -new keyword included: VRS -lxvx: page 492, a slash inside the extened opcode.two entries in the opcode table are included: 31-268 & 31-300 Commit: 7f04267bcb623d12e846c68d815d30b41d72a513 https://github.com/dyninst/dyninst/commit/7f04267bcb623d12e846c68d815d30b41d72a513 Author: Yuhan Xie Date: 2018-09-27 (Thu, 27 Sep 2018) Changed paths: M common/h/entryIDs.h Log Message: --- 09/27/2018 New opcodes added p523-576(not including p576) skipped: nothing new: -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25 -new extended opcodes (opcode 60/61/63), added on 09/25 but
[DynInst_API:] [dyninst/dyninst] 7b1511: Template for adding instructions
Branch: refs/heads/master Home: https://github.com/dyninst/dyninst Commit: 7b1511943e76cdef96b9c7e7ede4989805965d52 https://github.com/dyninst/dyninst/commit/7b1511943e76cdef96b9c7e7ede4989805965d52 Author: Benjamin Welton Date: 2018-09-20 (Thu, 20 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- Template for adding instructions Commit: 1707147ae4e3f6f78aa0eba5952bf45fbbd7793a https://github.com/dyninst/dyninst/commit/1707147ae4e3f6f78aa0eba5952bf45fbbd7793a Author: Yuhan Xie Date: 2018-09-20 (Thu, 20 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- added power operations, stopped on pg491 of the manual page, lxvll Commit: 1d4fc85ec0ff17ab3d14941253a9f114c7731439 https://github.com/dyninst/dyninst/commit/1d4fc85ec0ff17ab3d14941253a9f114c7731439 Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- P492-523 Commit: 6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca https://github.com/dyninst/dyninst/commit/6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- 09/25 p492-523(not including p523) skipped: lxv (P492, new keyword DQ; TX not at the last bit), lxvx (P492, a slash in the memory map and two numbers are included) stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0]) stxssp (P501, VRS) stxv (P507, new keyword DQ) xsabsqp (P512, 0 in it) new keywords included: -included new keywords "XS", it should be the storing version of "XT") -included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction) -included VRA, VRB (page 520 of manual) Additional: --xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual) Commit: 5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6 https://github.com/dyninst/dyninst/commit/5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6 Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Log Message: --- Merge branch 'power_vector' of github.com:dyninst/dyninst into power_vector Commit: 2c8113207782d5f032271773403e78be0e977bde https://github.com/dyninst/dyninst/commit/2c8113207782d5f032271773403e78be0e977bde Author: Yuhan Xie Date: 2018-09-25 (Tue, 25 Sep 2018) Changed paths: M instructionAPI/src/power_opcode_tables.C Log Message: --- 09/25 p492-523(not including p523) skipped: lxv (P492, new keyword DQ; TX not at the last bit), lxvx (P492, a slash in the memory map and two numbers are included) stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0]) stxssp (P501, VRS) stxv (P507, new keyword DQ) xsabsqp (P512, 0 in it) new keywords included: -included new keywords "XS", it should be the storing version of "XT") -included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction) -included VRA, VRB (page 520 of manual) Additional: --xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual) Commit: 0a3c9f6730e67eed51a9335b95863650a4844027 https://github.com/dyninst/dyninst/commit/0a3c9f6730e67eed51a9335b95863650a4844027 Author: Yuhan Xie Date: 2018-09-27 (Thu, 27 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- 09/27/2018 New opcodes added p523-576(not including p576) skipped: nothing new: -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25 -new extended opcodes (opcode 60/61/63), added on 09/25 but was not included in the last log. -new keyword included: VRS -lxvx: page 492, a slash inside the extened opcode.two entries in the opcode table are included: 31-268 & 31-300 Commit: 7f04267bcb623d12e846c68d815d30b41d72a513 https://github.com/dyninst/dyninst/commit/7f04267bcb623d12e846c68d815d30b41d72a513 Author: Yuhan Xie Date: 2018-09-27 (Thu, 27 Sep 2018) Changed paths: M common/h/entryIDs.h Log Message: --- 09/27/2018 New opcodes added p523-576(not including p576) skipped: nothing new: -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25 -new extended opcodes (opcode 60/61/63), added on 09/25 but was not
[DynInst_API:] [dyninst/dyninst] 7b1511: Template for adding instructions
Branch: refs/heads/power_vector Home: https://github.com/dyninst/dyninst Commit: 7b1511943e76cdef96b9c7e7ede4989805965d52 https://github.com/dyninst/dyninst/commit/7b1511943e76cdef96b9c7e7ede4989805965d52 Author: Benjamin Welton Date: 2018-09-20 (Thu, 20 Sep 2018) Changed paths: M common/h/entryIDs.h M instructionAPI/src/power_opcode_tables.C Log Message: --- Template for adding instructions **NOTE:** This service has been marked for deprecation: https://developer.github.com/changes/2018-04-25-github-services-deprecation/ Functionality will be removed from GitHub.com on January 31st, 2019. ___ Dyninst-api mailing list Dyninst-api@cs.wisc.edu https://lists.cs.wisc.edu/mailman/listinfo/dyninst-api
