[edk2] [PATCH] FVP: ACPI Add iort and GICv3 ITS support
Since ARM VExpress FVP platform will support some PCIe devices
(e.g, SMMU Test Engine) behind the PCIe Root Complex and SMMUv3 which
can generate PCI ITS-MSI/memory transaction to the core. Moreover, the
IORT based SMMU patch has been merged into the linux kernel, in order
to ease the testing/verification effort of those features, we need to
integrate those ACPI tables (mcfg, iort...) into the FVP UEFI binary.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dennis Chen <dennis.c...@arm.com>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Lorenzo Pieralisi <lorenzo.pieral...@arm.com>
Cc: Steve Capper <steve.cap...@arm.com>
---
Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf | 4 +
Platforms/ARM/VExpress/AcpiTables/Madt.aslc| 54 ++--
Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl | 89
Platforms/ARM/VExpress/AcpiTables/mcfg.asl | 25 ++
Platforms/ARM/VExpress/AcpiTables/ssdt.asl | 98 ++
Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 +
6 files changed, 247 insertions(+), 24 deletions(-)
create mode 100644 Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl
create mode 100644 Platforms/ARM/VExpress/AcpiTables/mcfg.asl
create mode 100644 Platforms/ARM/VExpress/AcpiTables/ssdt.asl
diff --git a/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
index 59d3238..000e83d 100644
--- a/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
+++ b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
@@ -27,6 +27,9 @@
Fadt.aslc
Gtdt.aslc
Madt.aslc
+ mcfg.asl
+ ssdt.asl
+ iort-smmuv3.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -41,3 +44,4 @@
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGicItsBase
diff --git a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
index bf90a9f..d2d9d9a 100644
--- a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
+++ b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
@@ -30,8 +30,15 @@ typedef struct {
EFI_ACPI_6_1_GIC_STRUCTUREGicInterfaces[8];
EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
+ EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicIts;
} FVP_MULTIPLE_APIC_DESCRIPTION_TABLE;
+#define FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr) \
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( \
+GicId, AcpiCpuUid, Mpidr, \
+EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),\
+0x2C02F000, 0x2C01, 0x19, 0, 0)
+
#pragma pack ()
FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
@@ -47,33 +54,22 @@ FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
0, // LocalApicAddress
0, // Flags
},
+
+ /* Gic Interfaces array */
{
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-4, 4, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-5, 5, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-6, 6, GET_MPID(1, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
-EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
-7, 7, GET_MPID(1, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64
(PcdGicInterruptInterfaceBase),
-0x2C02F000, 0x2C01, 0x19, 0, 0),
+FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, 0, GET_MPID(0, 0)),
+FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, 1, GET_MPID(0, 1)),
+FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, 2, GET_MPID(0, 2)),
+FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, 3, GET_MPID(0, 3)),
+FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(4, 4, GET_MPID(1, 0)),
+FVP_EFI_ACPI_6_0_GICC_STRU
[edk2] [PATCH] ArmPkg: Add GICv3 ITS token
We add this token in order to support the GICv3 ITS feature on ARM VExpress FVP platform (related patch will be based on OpenPlatformPkg git repository) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dennis Chen <dennis.c...@arm.com> Cc: Leif Lindholm <leif.lindh...@linaro.org> Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Cc: Lorenzo Pieralisi <lorenzo.pieral...@arm.com> Cc: Steve Capper <steve.cap...@arm.com> --- ArmPkg/ArmPkg.dec | 1 + 1 file changed, 1 insertion(+) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 090ed99..1d6f9d2 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -263,6 +263,7 @@ # Base address for the GIC Redistributor region that contains the boot CPU gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x000E gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x000D + gArmTokenSpaceGuid.PcdGicItsBase|0|UINT64|0x000F gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x0025 # -- 2.7.4 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [RESEND PATCH] ArmVirtPkg: Bit width adaption in ASSERT()
Hello Laszlo,
On Fri, Oct 21, 2016 at 10:02:45AM +0200, Laszlo Ersek wrote:
> On 10/21/16 07:50, Dennis Chen wrote:
> > Since All the GIC base address variables has been aligned to 64-bit, it
> > doesn't make sense to continue use MAX_UINT32 in ASSERT() statement, so
> > this patch uses MAX_UINTN to adapt to this kind of change.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
> > Cc: Leif Lindholm <leif.lindh...@linaro.org>
> > Cc: Laszlo Ersek <ler...@redhat.com>
> > Signed-off-by: Dennis Chen <dennis.c...@arm.com>
> > ---
> > ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 8
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > index 64afc4d..6488061 100644
> > --- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > +++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > @@ -79,11 +79,11 @@ ArmVirtGicArchLibConstructor (
> >
> > // RegProp[0..1] == { GICD base, GICD size }
> > DistBase = SwapBytes64 (Reg[0]);
> > -ASSERT (DistBase < MAX_UINT32);
> > +ASSERT (DistBase < MAX_UINTN);
> >
> > // RegProp[2..3] == { GICR base, GICR size }
> > RedistBase = SwapBytes64 (Reg[2]);
> > -ASSERT (RedistBase < MAX_UINT32);
> > +ASSERT (RedistBase < MAX_UINTN);
> >
> > PcdSet64 (PcdGicDistributorBase, DistBase);
> > PcdSet64 (PcdGicRedistributorsBase, RedistBase);
> > @@ -117,8 +117,8 @@ ArmVirtGicArchLibConstructor (
> >
> > DistBase = SwapBytes64 (Reg[0]);
> > CpuBase = SwapBytes64 (Reg[2]);
> > -ASSERT (DistBase < MAX_UINT32);
> > -ASSERT (CpuBase < MAX_UINT32);
> > +ASSERT (DistBase < MAX_UINTN);
> > +ASSERT (CpuBase < MAX_UINTN);
> >
> > PcdSet64 (PcdGicDistributorBase, DistBase);
> > PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase);
> >
>
> Ard, can you please handle this iteration of the patch as well?
>
> I do have one suggestion, for the subject:
>
> ArmVirtPkg/ArmVirtGicArchLib: adapt ASSERT()s to 64-bit base addresses
>
> If you guys agree, I think it can be done on commit. With that,
>
I think Ard will not have any reason to reject this nice suggestion :), so do I.
so it's a deal...
Thanks,
Dennis
>
> Acked-by: Laszlo Ersek <ler...@redhat.com>
>
> Thanks
> Laszlo
>
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Re: [edk2] [RESEND PATCH] ARMPkg: Unify the GIC base address variables as 64-bit
Hello Ard,
On Fri, Oct 21, 2016 at 09:34:32AM +0100, Ard Biesheuvel wrote:
> Hi Dennis,
>
> On 21 October 2016 at 06:50, Dennis Chen <dennis.c...@arm.com> wrote:
> > Since ACPI spec defines the GIC base addresses (CPU interface,
> > Distributor and Redistributor*GICv3 only*) as 64-bit, so we should
> > define these corresponding base address variables as 64-bit instead of
> > 32-bit. This patch redefines them according to the ACPI spec.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
> > Cc: Leif Lindholm <leif.lindh...@linaro.org>
> > Signed-off-by: Dennis Chen <dennis.c...@arm.com>
>
> Even if this is GICv3 only, you are breaking the build for 32-bit
> because of some changes that also affect GICv2
>
> /home/ard/build/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c:20:1:
> error: conflicting types for ‘ArmGicV2AcknowledgeInterrupt’
> ArmGicV2AcknowledgeInterrupt (
> ^
> In file included from
> /home/ard/build/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c:15:0:
> /home/ard/build/edk2/ArmPkg/Include/Library/ArmGicLib.h:252:1: note:
> previous declaration of ‘ArmGicV2AcknowledgeInterrupt’ was here
> ArmGicV2AcknowledgeInterrupt (
> ^
> /home/ard/build/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c:30:1:
> error: conflicting types for ‘ArmGicV2EndOfInterrupt’
> ArmGicV2EndOfInterrupt (
> ^
> In file included from
> /home/ard/build/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c:15:0:
> /home/ard/build/edk2/ArmPkg/Include/Library/ArmGicLib.h:258:1: note:
> previous declaration of ‘ArmGicV2EndOfInterrupt’ was here
> ArmGicV2EndOfInterrupt (
> ^
>
> When you propose changes like this one, please make sure if works on
> 64-bit as well as 32-bit
>
Thanks for spotting that! My fault not to try the 32-bit in my always 64-bit
environment, but that's not to seek some kind of excuse. In order to make you
guys feel a little bit comfortable ;-), I will give a quick fix about that.
So fingers crossed, that's the last issue with this patch blatted...
Thanks,
Dennis
>
> Thanks,
> Ard.
>
>
> > ---
> > ArmPkg/Drivers/ArmGic/ArmGicLib.c | 64 ++--
> > ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c | 2 +-
> > ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 4 +-
> > ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c | 4 +-
> > ArmPkg/Include/Library/ArmGicLib.h | 78
> > -
> > 5 files changed, 76 insertions(+), 76 deletions(-)
> >
> > diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> > b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> > index e658e9b..733488c 100644
> > --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> > +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> > @@ -41,18 +41,18 @@ SourceIsSpi (
> > * @retval Base address of the associated GIC Redistributor
> > */
> > STATIC
> > -UINTN
> > +UINT64
> > GicGetCpuRedistributorBase (
> > - IN UINTN GicRedistributorBase,
> > - IN ARM_GIC_ARCH_REVISION Revision
> > + IN UINT64 GicRedistributorBase,
> > + IN ARM_GIC_ARCH_REVISION Revision
> >)
> > {
> > - UINTN Index;
> > - UINTN MpId;
> > - UINTN CpuAffinity;
> > - UINTN Affinity;
> > - UINTN GicRedistributorGranularity;
> > - UINTN GicCpuRedistributorBase;
> > + UINTN Index;
> > + UINTN MpId;
> > + UINTN CpuAffinity;
> > + UINTN Affinity;
> > + UINTN GicRedistributorGranularity;
> > + UINT64 GicCpuRedistributorBase;
> >
> >MpId = ArmReadMpidr ();
> >// Define CPU affinity as Affinity0[0:8], Affinity1[9:15],
> > Affinity2[16:23], Affinity3[24:32]
> > @@ -87,7 +87,7 @@ GicGetCpuRedistributorBase (
> > UINTN
> > EFIAPI
> > ArmGicGetInterfaceIdentification (
> > - IN INTN GicInterruptInterfaceBase
> > + IN UINT64 GicInterruptInterfaceBase
> >)
> > {
> >// Read the GIC Identification Register
> > @@ -97,7 +97,7 @@ ArmGicGetInterfaceIdentification (
> > UINTN
> > EFIAPI
> > ArmGicGetMaxNumInterrupts (
> > - IN INTN GicDistributorBase
> > + IN UINT64 GicDistributorBase
> >)
> > {
> >return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F)
> > + 1);
> > @@ -106,10 +106,10 @@ ArmGicGetMaxNumInterrupts (
> > VOID
> > EFIAPI
> > ArmGicSendSgiTo (
> > - IN INTN GicDistributorBase,
> > - IN INTN TargetListFilter,
>
[edk2] [PATCH] ArmPkg: Assign the real INTID value for sanity check
Current implementation doesn't assign the INTID value readed from
GICC_IAR to the @InterruptId parameter in case of GICv3, thus make
the sanity check of the INTID in the caller becomes untrustworthy, this
patch is trying to re-assign the @InterruptId to mitigate this issue.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Signed-off-by: Dennis Chen <dennis.c...@arm.com>
---
ArmPkg/Drivers/ArmGic/ArmGicLib.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 733488c..6c9ee8b 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -135,27 +135,32 @@ ArmGicAcknowledgeInterrupt (
OUT UINTN *InterruptId
)
{
- UINTN Value;
+ UINTN Value, IntID;
ARM_GIC_ARCH_REVISION Revision;
+ // InterruptId is required for the caller to know if a valid or spurious
+ // interrupt has been read
+ ASSERT (InterruptId != NULL);
+
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);
-// InterruptId is required for the caller to know if a valid or spurious
-// interrupt has been read
-ASSERT (InterruptId != NULL);
-if (InterruptId != NULL) {
- *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;
-}
+IntID = Value & ARM_GIC_ICCIAR_ACKINTID;
} else if (Revision == ARM_GIC_ARCH_REVISION_3) {
Value = ArmGicV3AcknowledgeInterrupt ();
+// For GICv3, the Value readed from GICC_IAR is the final INTID
+IntID = Value;
} else {
ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
// Report Spurious interrupt which is what the above controllers would
// return if no interrupt was available
Value = 1023;
+IntID = Value;
}
+ if (InterruptId != NULL)
+ *InterruptId = IntID;
+
return Value;
}
--
2.7.4
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[edk2] [RESEND PATCH] ARMPkg: Unify the GIC base address variables as 64-bit
Since ACPI spec defines the GIC base addresses (CPU interface,
Distributor and Redistributor*GICv3 only*) as 64-bit, so we should
define these corresponding base address variables as 64-bit instead of
32-bit. This patch redefines them according to the ACPI spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Signed-off-by: Dennis Chen <dennis.c...@arm.com>
---
ArmPkg/Drivers/ArmGic/ArmGicLib.c | 64 ++--
ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c | 2 +-
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 4 +-
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c | 4 +-
ArmPkg/Include/Library/ArmGicLib.h | 78 -
5 files changed, 76 insertions(+), 76 deletions(-)
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index e658e9b..733488c 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -41,18 +41,18 @@ SourceIsSpi (
* @retval Base address of the associated GIC Redistributor
*/
STATIC
-UINTN
+UINT64
GicGetCpuRedistributorBase (
- IN UINTN GicRedistributorBase,
- IN ARM_GIC_ARCH_REVISION Revision
+ IN UINT64 GicRedistributorBase,
+ IN ARM_GIC_ARCH_REVISION Revision
)
{
- UINTN Index;
- UINTN MpId;
- UINTN CpuAffinity;
- UINTN Affinity;
- UINTN GicRedistributorGranularity;
- UINTN GicCpuRedistributorBase;
+ UINTN Index;
+ UINTN MpId;
+ UINTN CpuAffinity;
+ UINTN Affinity;
+ UINTN GicRedistributorGranularity;
+ UINT64 GicCpuRedistributorBase;
MpId = ArmReadMpidr ();
// Define CPU affinity as Affinity0[0:8], Affinity1[9:15], Affinity2[16:23],
Affinity3[24:32]
@@ -87,7 +87,7 @@ GicGetCpuRedistributorBase (
UINTN
EFIAPI
ArmGicGetInterfaceIdentification (
- IN INTN GicInterruptInterfaceBase
+ IN UINT64 GicInterruptInterfaceBase
)
{
// Read the GIC Identification Register
@@ -97,7 +97,7 @@ ArmGicGetInterfaceIdentification (
UINTN
EFIAPI
ArmGicGetMaxNumInterrupts (
- IN INTN GicDistributorBase
+ IN UINT64 GicDistributorBase
)
{
return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
@@ -106,10 +106,10 @@ ArmGicGetMaxNumInterrupts (
VOID
EFIAPI
ArmGicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList,
- IN INTN SgiId
+ IN UINT64 GicDistributorBase,
+ IN UINTN TargetListFilter,
+ IN UINTN CPUTargetList,
+ IN UINTN SgiId
)
{
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3)
<< 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
@@ -131,8 +131,8 @@ ArmGicSendSgiTo (
UINTN
EFIAPI
ArmGicAcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- OUT UINTN *InterruptId
+ IN UINT64 GicInterruptInterfaceBase,
+ OUT UINTN *InterruptId
)
{
UINTN Value;
@@ -162,8 +162,8 @@ ArmGicAcknowledgeInterrupt (
VOID
EFIAPI
ArmGicEndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
+ IN UINT64 GicInterruptInterfaceBase,
+ IN UINTN Source
)
{
ARM_GIC_ARCH_REVISION Revision;
@@ -181,9 +181,9 @@ ArmGicEndOfInterrupt (
VOID
EFIAPI
ArmGicEnableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINT64 GicDistributorBase,
+ IN UINT64 GicRedistributorBase,
+ IN UINTN Source
)
{
UINT32RegOffset;
@@ -216,9 +216,9 @@ ArmGicEnableInterrupt (
VOID
EFIAPI
ArmGicDisableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINT64 GicDistributorBase,
+ IN UINT64 GicRedistributorBase,
+ IN UINTN Source
)
{
UINT32RegOffset;
@@ -250,15 +250,15 @@ ArmGicDisableInterrupt (
BOOLEAN
EFIAPI
ArmGicIsInterruptEnabled (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINT64 GicDistributorBase,
+ IN UINT64 GicRedistributorBase,
+ IN UINTN Source
)
{
UINT32RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
+ UINT64GicCpuRedistributorBase;
UINT32Interrupts;
// Calculate enable register offset and bit position
@@ -286,7 +286,7 @@ ArmGicIsInterruptEnabled (
VOID
EFIA
[edk2] [RESEND PATCH] ArmVirtPkg: Bit width adaption in ASSERT()
Since All the GIC base address variables has been aligned to 64-bit, it
doesn't make sense to continue use MAX_UINT32 in ASSERT() statement, so
this patch uses MAX_UINTN to adapt to this kind of change.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Laszlo Ersek <ler...@redhat.com>
Signed-off-by: Dennis Chen <dennis.c...@arm.com>
---
ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
index 64afc4d..6488061 100644
--- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
+++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
@@ -79,11 +79,11 @@ ArmVirtGicArchLibConstructor (
// RegProp[0..1] == { GICD base, GICD size }
DistBase = SwapBytes64 (Reg[0]);
-ASSERT (DistBase < MAX_UINT32);
+ASSERT (DistBase < MAX_UINTN);
// RegProp[2..3] == { GICR base, GICR size }
RedistBase = SwapBytes64 (Reg[2]);
-ASSERT (RedistBase < MAX_UINT32);
+ASSERT (RedistBase < MAX_UINTN);
PcdSet64 (PcdGicDistributorBase, DistBase);
PcdSet64 (PcdGicRedistributorsBase, RedistBase);
@@ -117,8 +117,8 @@ ArmVirtGicArchLibConstructor (
DistBase = SwapBytes64 (Reg[0]);
CpuBase = SwapBytes64 (Reg[2]);
-ASSERT (DistBase < MAX_UINT32);
-ASSERT (CpuBase < MAX_UINT32);
+ASSERT (DistBase < MAX_UINTN);
+ASSERT (CpuBase < MAX_UINTN);
PcdSet64 (PcdGicDistributorBase, DistBase);
PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase);
--
2.7.4
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Re: [edk2] [PATCH] ArmPkg: Fix the GIC base address variables as 64-bit
Hello Ard, On Tue, Oct 18, 2016 at 09:40:42AM +0100, Ard Biesheuvel wrote: > On 18 October 2016 at 03:50, Dennis Chen <dennis.c...@arm.com> wrote: > > Hello Ard, > > > > On Mon, Oct 17, 2016 at 06:09:00PM +0100, Ard Biesheuvel wrote: > >> On 17 October 2016 at 09:54, Dennis Chen <dennis.c...@arm.com> wrote: > >> > Since ACPI spec defines the GIC base addresses (CPU interface, > >> > Distributor and Redistributor*GICv3 only*) as 64-bit, so we should > >> > define these corresponding base address variables as 64-bit instead of > >> > 32-bit. This patch redefines them according to the ACPI spec. > >> > > >> > Contributed-under: TianoCore Contribution Agreement 1.0 > >> > Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> > >> > Cc: Leif Lindholm <leif.lindh...@linaro.org> > >> > Signed-off-by: Dennis Chen <dennis.c...@arm.com> > >> > >> After a closer look, I noticed the following: > >> > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN GicDistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicInterruptInterfaceBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicInterruptInterfaceBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicDistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicRedistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicDistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicRedistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicDistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicRedistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase, > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN INTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicInterruptInterfaceBase > >> ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > >> GicInterruptInterfaceBase, > >> > >> so I think we need to clean up the use of these values more widely > >> than we have done up till now > >> > > I am not very sure if we still need to support UEFI on 32-bit ARM platform, > > as Leif mentioned > > if we use INTN or UINTN that will be more generic to embrace both 32 > > &64-bit platform, at least > > in form of. Currently we are only focused on 64-bit platform, let's wait > > for Leif's comment then > > I can re-work my patch to adapt it after we have reached a wider agreement. > > > > Hi Dennis, > > My primary concern is the sloppiness regarding INTN/UINTN, so it seem > a major cleanup is due. I'd prefer using UINT64 everywhere: we can > still assert that an UINT64 *value* does not exceed MAX_UINTN if we > want to > Indeed, INTN/UINTN usage is very inconsistent in that header file. I suppose you have considered the 32-bit case when you say you prefer using UNIT64 everywhere, thus I have no objection for that since I always work on 64-bit area. I will hold on this patch for a while and resend the revised patch if no more comments inputted. Thanks, Dennis > > -- > Ard. > ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH] ArmPkg: Fix the GIC base address variables as 64-bit
Hello Ard, On Mon, Oct 17, 2016 at 06:09:00PM +0100, Ard Biesheuvel wrote: > On 17 October 2016 at 09:54, Dennis Chen <dennis.c...@arm.com> wrote: > > Since ACPI spec defines the GIC base addresses (CPU interface, > > Distributor and Redistributor*GICv3 only*) as 64-bit, so we should > > define these corresponding base address variables as 64-bit instead of > > 32-bit. This patch redefines them according to the ACPI spec. > > > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> > > Cc: Leif Lindholm <leif.lindh...@linaro.org> > > Signed-off-by: Dennis Chen <dennis.c...@arm.com> > > After a closer look, I noticed the following: > > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN GicDistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicInterruptInterfaceBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicInterruptInterfaceBase, > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicDistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicRedistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicDistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicRedistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicDistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicRedistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN INTN GicDistributorBase, > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN INTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicInterruptInterfaceBase > ArmPkg/Include/Library/ArmGicLib.h: IN UINTN > GicInterruptInterfaceBase, > > so I think we need to clean up the use of these values more widely > than we have done up till now > I am not very sure if we still need to support UEFI on 32-bit ARM platform, as Leif mentioned if we use INTN or UINTN that will be more generic to embrace both 32 &64-bit platform, at least in form of. Currently we are only focused on 64-bit platform, let's wait for Leif's comment then I can re-work my patch to adapt it after we have reached a wider agreement. Thanks, Dennis > > Leif: I was wondering if EFI_PHYSICAL_ADDRESS would be more > appropriate for MMIO base addresses? > ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] ArmVirtPkg: Drop the nonsense ASSERT() statement
Since All the GIC base address variables now are 64-bit, given
that a UNIT64 var cannot exceed MAX_UNIT64, it doesn't make sense
to continue keep them in the codes, so this patch just simply drop
those ASSERT() statements as it should be.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Laszlo Ersek <ler...@redhat.com>
Signed-off-by: Dennis Chen <dennis.c...@arm.com>
---
ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 4
1 file changed, 4 deletions(-)
diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
index 64afc4d..7a312e5 100644
--- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
+++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
@@ -79,11 +79,9 @@ ArmVirtGicArchLibConstructor (
// RegProp[0..1] == { GICD base, GICD size }
DistBase = SwapBytes64 (Reg[0]);
-ASSERT (DistBase < MAX_UINT32);
// RegProp[2..3] == { GICR base, GICR size }
RedistBase = SwapBytes64 (Reg[2]);
-ASSERT (RedistBase < MAX_UINT32);
PcdSet64 (PcdGicDistributorBase, DistBase);
PcdSet64 (PcdGicRedistributorsBase, RedistBase);
@@ -117,8 +115,6 @@ ArmVirtGicArchLibConstructor (
DistBase = SwapBytes64 (Reg[0]);
CpuBase = SwapBytes64 (Reg[2]);
-ASSERT (DistBase < MAX_UINT32);
-ASSERT (CpuBase < MAX_UINT32);
PcdSet64 (PcdGicDistributorBase, DistBase);
PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase);
--
2.7.4
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[edk2] [PATCH] ArmPkg: Fix the GIC base address variables as 64-bit
Since ACPI spec defines the GIC base addresses (CPU interface, Distributor and Redistributor*GICv3 only*) as 64-bit, so we should define these corresponding base address variables as 64-bit instead of 32-bit. This patch redefines them according to the ACPI spec. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Cc: Leif Lindholm <leif.lindh...@linaro.org> Signed-off-by: Dennis Chen <dennis.c...@arm.com> --- ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c index b9ecd55..c7c5af1 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -30,8 +30,8 @@ Abstract: extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol; -STATIC UINT32 mGicInterruptInterfaceBase; -STATIC UINT32 mGicDistributorBase; +STATIC UINT64 mGicInterruptInterfaceBase; +STATIC UINT64 mGicDistributorBase; /** Enable interrupt source Source. -- 2.7.4 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH] ArmPkg ArmVirtPkg: fix the GIC base address variables as 64-bit
Hello Ard,
Thanks for the comments! I will split this patch into 2 and for ArmVirtPkg
patch,
we just need to simply drop the original ASSERT() since it's nonsensical any
more.
Thanks,
Dennis
On Mon, Oct 17, 2016 at 08:28:50AM +0100, Ard Biesheuvel wrote:
> Hi Dennis,
>
> On 17 October 2016 at 06:03, Dennis Chen <dennis.c...@arm.com> wrote:
> > Since ACPI spec defines the GIC base addresses (CPU interface,
> > Distributor and Redistributor*GICv3 only*) as 64-bit, so we
> > should define these corresponding base address variables as 64-bit
> > instead of 32-bit. This patch redefines them according to the
> > ACPI spec.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
> > Cc: Leif Lindholm <leif.lindh...@linaro.org>
> > Signed-off-by: Dennis Chen <dennis.c...@arm.com>
> > ---
> > ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c| 4 ++--
> > ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 8
>
> Could you split this patch in 2 please, and put Laszlo Ersek on cc for
> the ArmVirtPkg patch?
>
>
> > 2 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
> > b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
> > index b9ecd55..a4ba5cf 100644
> > --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
> > +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
> > @@ -30,8 +30,8 @@ Abstract:
> >
> > extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
> >
> > -STATIC UINT32 mGicInterruptInterfaceBase;
> > -STATIC UINT32 mGicDistributorBase;
> > +STATIC UINTN mGicInterruptInterfaceBase;
> > +STATIC UINTN mGicDistributorBase;
> >
>
> This should be UINT64 not UINTN
>
> > /**
> >Enable interrupt source Source.
> > diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > index 64afc4d..16683ef 100644
> > --- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > +++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
> > @@ -79,11 +79,11 @@ ArmVirtGicArchLibConstructor (
> >
> > // RegProp[0..1] == { GICD base, GICD size }
> > DistBase = SwapBytes64 (Reg[0]);
> > -ASSERT (DistBase < MAX_UINT32);
> > +ASSERT (DistBase < MAX_UINT64);
> >
>
> This becomes equivalent to 'DistBase != MAX_UINT64' given that a
> UINT64 cannot exceed MAX_UINT64. That is a nonsensical thing to
> assert, so it is better to simply drop it
>
> > // RegProp[2..3] == { GICR base, GICR size }
> > RedistBase = SwapBytes64 (Reg[2]);
> > -ASSERT (RedistBase < MAX_UINT32);
> > +ASSERT (RedistBase < MAX_UINT64);
> >
>
> Likewise
>
> > PcdSet64 (PcdGicDistributorBase, DistBase);
> > PcdSet64 (PcdGicRedistributorsBase, RedistBase);
> > @@ -117,8 +117,8 @@ ArmVirtGicArchLibConstructor (
> >
> > DistBase = SwapBytes64 (Reg[0]);
> > CpuBase = SwapBytes64 (Reg[2]);
> > -ASSERT (DistBase < MAX_UINT32);
> > -ASSERT (CpuBase < MAX_UINT32);
> > +ASSERT (DistBase < MAX_UINT64);
> > +ASSERT (CpuBase < MAX_UINT64);
> >
>
> Likewise
>
> > PcdSet64 (PcdGicDistributorBase, DistBase);
> > PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase);
> > --
> > 2.7.4
> >
>
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[edk2] [PATCH] ArmPkg ArmVirtPkg: fix the GIC base address variables as 64-bit
Since ACPI spec defines the GIC base addresses (CPU interface,
Distributor and Redistributor*GICv3 only*) as 64-bit, so we
should define these corresponding base address variables as 64-bit
instead of 32-bit. This patch redefines them according to the
ACPI spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Signed-off-by: Dennis Chen <dennis.c...@arm.com>
---
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c| 4 ++--
ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
index b9ecd55..a4ba5cf 100644
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
@@ -30,8 +30,8 @@ Abstract:
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
-STATIC UINT32 mGicInterruptInterfaceBase;
-STATIC UINT32 mGicDistributorBase;
+STATIC UINTN mGicInterruptInterfaceBase;
+STATIC UINTN mGicDistributorBase;
/**
Enable interrupt source Source.
diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
index 64afc4d..16683ef 100644
--- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
+++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c
@@ -79,11 +79,11 @@ ArmVirtGicArchLibConstructor (
// RegProp[0..1] == { GICD base, GICD size }
DistBase = SwapBytes64 (Reg[0]);
-ASSERT (DistBase < MAX_UINT32);
+ASSERT (DistBase < MAX_UINT64);
// RegProp[2..3] == { GICR base, GICR size }
RedistBase = SwapBytes64 (Reg[2]);
-ASSERT (RedistBase < MAX_UINT32);
+ASSERT (RedistBase < MAX_UINT64);
PcdSet64 (PcdGicDistributorBase, DistBase);
PcdSet64 (PcdGicRedistributorsBase, RedistBase);
@@ -117,8 +117,8 @@ ArmVirtGicArchLibConstructor (
DistBase = SwapBytes64 (Reg[0]);
CpuBase = SwapBytes64 (Reg[2]);
-ASSERT (DistBase < MAX_UINT32);
-ASSERT (CpuBase < MAX_UINT32);
+ASSERT (DistBase < MAX_UINT64);
+ASSERT (CpuBase < MAX_UINT64);
PcdSet64 (PcdGicDistributorBase, DistBase);
PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase);
--
2.7.4
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