[edk2] [Patch v2] UefiCpuPkg/MpInitLib: Fix MemTest86 failure.
V2 changes:
Update the commit message and comments in the code.
When waking vector buffer allocated by CpuDxe is tested by MemTest86
in MP mode, an error is reported because the same range of memory is
modified by both CpuDxe driver and MemTest86.
The waking vector buffer is not expected to be tested by MemTest86 if
it is allocated out because MemTest86 only tests free memory. But
current CpuDxe driver "borrows" buffer instead of allocate buffer for
waking vector buffer (through allocate & free to get the buffer
pointer, backup the buffer data before using it and restore it after
using). With this implementation, if the buffer borrowed is not used
by any other drivers, MemTest86 tool will treat it as free memory
and test it.
In order to fix the above issue, CpuDxe changes to allocate the
buffer below 1M instead of borrowing it. But directly allocating
memory below 1MB causes LegacyBios driver fails to start. LegacyBios
driver allocates memory range from
"0xA - PcdEbdaReservedMemorySize" to 0xA as Ebda Reserved
Memory. The minimum value for "0xA - PcdEbdaReservedMemorySize"
is 0x88000. If LegacyBios driver allocate this range failed, it
asserts.
LegacyBios also reserves range from 0x6 to
"0x6 + PcdOpromReservedMemorySize", it will be used as Oprom
Reserve Memory. The maximum value for "0x6 +
PcdOpromReservedMemorySize" is 0x88000. LegacyBios driver tries to
allocate these range page(4K size) by page. It just reports warning
message if some pages are already allocated by others.
Base on above investigation, one page in range 0x6 ~ 0x88000 can
be used as the waking vector buffer.
LegacyBios driver only reports warning when page allocation in range
[0x6, 0x88000) fails. This library is consumed by CpuDxe driver
to produce CPU Arch protocol. LagacyBios driver depends on CPU Arch
protocol which guarantees below allocation runs earlier than
LegacyBios driver.
Cc: Ray Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 26 ++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index b2307cbb61..cef5b49dde 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -76,7 +76,7 @@ SaveCpuMpData (
}
/**
- Get available system memory below 1MB by specified size.
+ Get available system memory below 0x88000 by specified size.
@param[in] WakeupBufferSize Wakeup buffer size required
@@ -91,7 +91,15 @@ GetWakeupBuffer (
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESSStartAddress;
- StartAddress = BASE_1MB;
+ //
+ // Try to allocate buffer below 1M for waking vector.
+ // LegacyBios driver only reports warning when page allocation in range
+ // [0x6, 0x88000) fails.
+ // This library is consumed by CpuDxe driver to produce CPU Arch protocol.
+ // LagacyBios driver depends on CPU Arch protocol which guarantees below
+ // allocation runs earlier than LegacyBios driver.
+ //
+ StartAddress = 0x88000;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiBootServicesData,
@@ -99,17 +107,13 @@ GetWakeupBuffer (
);
ASSERT_EFI_ERROR (Status);
- if (!EFI_ERROR (Status)) {
-Status = gBS->FreePages(
- StartAddress,
- EFI_SIZE_TO_PAGES (WakeupBufferSize)
- );
-ASSERT_EFI_ERROR (Status);
-DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
-(UINTN) StartAddress, WakeupBufferSize));
- } else {
+ if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
}
+
+ DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
+ (UINTN) StartAddress, WakeupBufferSize));
+
return (UINTN) StartAddress;
}
--
2.21.0.windows.1
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[edk2] [edk2-platforms/devel-MinPlatform][Patch] AdvancedFeaturePkg/AcpiDebug: Add new AcpiDebug modules.
V2 change:
Update the patch header.
Add new AcpiDebug modules which provide ACPI Debug feature.
Detail about this feature see the readme.txt in the patch.
Cc: Hao Wu
Cc: Michael Kubacki
Cc: Nate Desimone
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../AcpiDebug/AcpiDebug.asl | 109
.../AdvancedFeaturePkg/AcpiDebug/AcpiDebug.c | 485 ++
.../AcpiDebug/AcpiDebugDxe.inf| 63 +++
.../AcpiDebug/AcpiDebugSmm.inf| 65 +++
.../AdvancedFeaturePkg/AcpiDebug/Readme.txt | 47 ++
.../AdvancedFeaturePkg/AdvancedFeaturePkg.dec | 6 +
.../AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 2 +
7 files changed, 777 insertions(+)
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.c
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebugDxe.inf
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebugSmm.inf
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/Readme.txt
diff --git a/Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
b/Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
new file mode 100644
index 000..62d2a1b
--- /dev/null
+++ b/Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
@@ -0,0 +1,109 @@
+/** @file
+ Acpi Debug ASL code.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "AcpiDebug.aml",
+ "SSDT",
+ 2,
+ "Intel ",
+ "ADebTabl",
+ 0x1000
+ )
+{
+ Scope(\)
+ {
+//
+// These pointers are patched during POST.
+//
+Name (DPTR, 0x8000) // Address of Acpi debug memory buffer, fixed up
during POST
+Name (EPTR, 0x8000) // End of Acpi debug memory buffer, fixed up
during POST
+Name (CPTR, 0x8000) // Current pointer used as an index into the
buffer(starts after the Acpi Debug head), fixed up during POST
+
+//
+// Use a Mutex to prevent multiple calls from simutaneously writing to the
same memory.
+//
+Mutex (MMUT, 0)
+
+//
+// Operational region for SMI port access
+//
+OperationRegion (ADBP, SystemIO, 0xB2, 2)
+Field (ADBP, ByteAcc, NoLock, Preserve)
+{
+B2PT, 8,
+B3PT, 8,
+}
+
+//
+// Write a string to a memory buffer
+//
+Method (MDBG, 1, Serialized)
+{
+ OperationRegion (ADHD, SystemMemory, DPTR, 32) // Operation region for
Acpi Debug buffer first 0x20 bytes
+ Field (ADHD, ByteAcc, NoLock, Preserve)
+ {
+Offset (0x0),
+ASIG, 128, // 16 bytes is Signature
+Offset (0x10),
+ASIZ, 32, // 4 bytes is buffer size
+ACHP, 32, // 4 bytes is current head pointer, normally is DPTR +
0x20,
+// if there's SMM handler to print, then it's the
starting of the info hasn't been printed yet.
+ACTP, 32, // 4 bytes is current tail pointer, is the same as CPTR
+SMIN, 8,// 1 byte of SMI Number for trigger callback
+WRAP, 8,// 1 byte of wrap status
+SMMV, 8,// 1 byte of SMM version status
+TRUN, 8 // 1 byte of truncate status
+ }
+
+ Store (Acquire (MMUT, 1000), Local0) // save Acquire result so we can
check for Mutex acquired
+ If (LEqual (Local0, Zero)) // check for Mutex acquired
+ {
+OperationRegion (ABLK, SystemMemory, CPTR, 32) // Operation region to
allow writes to ACPI debug buffer
+Field (ABLK, ByteAcc, NoLock, Preserve)
+{
+ Offset (0x0),
+ , 256 // 32 bytes is max size for string or data
+}
+ToHexString (Arg0, Local1) // convert argument to Hexadecimal String
+Store (0, TRUN)
+If (LGreaterEqual (SizeOf (Local1), 32))
+{
+ Store (1, TRUN) // the input from ASL >= 32
+}
+Mid (Local1, 0, 31, ) // extract the input to current buffer
+
+Add (CPTR, 32, CPTR) // advance current pointer to next string
location in memory buffer
+If (LGreaterEqual (CPTR, EPTR) ) // check for end of 64kb Acpi debug
buffer
+{
+ Add (DPTR, 32, CPTR) // wrap around to beginning of buffer if the
end has been reached
+ Store (1, WRAP)
+}
+Store (CPTR, ACTP)
+
+If (SMMV)
+{
+ //
+ // Triggle the SMI to print
+ //
+
[edk2] [Patch] AdvancedFeaturePkg/AcpiDebug: Add new AcpiDebug modules.
Add new AcpiDebug modules which provide ACPI Debug feature.
Detail about this feature see the readme.txt in the patch.
Change-Id: Ib977ece46f3494301574b04af32282b99045f673
Cc: Hao Wu
Cc: Michael Kubacki
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../AcpiDebug/AcpiDebug.asl | 109
.../AdvancedFeaturePkg/AcpiDebug/AcpiDebug.c | 485 ++
.../AcpiDebug/AcpiDebugDxe.inf| 63 +++
.../AcpiDebug/AcpiDebugSmm.inf| 65 +++
.../AdvancedFeaturePkg/AcpiDebug/Readme.txt | 47 ++
.../AdvancedFeaturePkg/AdvancedFeaturePkg.dec | 6 +
.../AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 2 +
7 files changed, 777 insertions(+)
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.c
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebugDxe.inf
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebugSmm.inf
create mode 100644 Platform/Intel/AdvancedFeaturePkg/AcpiDebug/Readme.txt
diff --git a/Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
b/Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
new file mode 100644
index 000..62d2a1b
--- /dev/null
+++ b/Platform/Intel/AdvancedFeaturePkg/AcpiDebug/AcpiDebug.asl
@@ -0,0 +1,109 @@
+/** @file
+ Acpi Debug ASL code.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "AcpiDebug.aml",
+ "SSDT",
+ 2,
+ "Intel ",
+ "ADebTabl",
+ 0x1000
+ )
+{
+ Scope(\)
+ {
+//
+// These pointers are patched during POST.
+//
+Name (DPTR, 0x8000) // Address of Acpi debug memory buffer, fixed up
during POST
+Name (EPTR, 0x8000) // End of Acpi debug memory buffer, fixed up
during POST
+Name (CPTR, 0x8000) // Current pointer used as an index into the
buffer(starts after the Acpi Debug head), fixed up during POST
+
+//
+// Use a Mutex to prevent multiple calls from simutaneously writing to the
same memory.
+//
+Mutex (MMUT, 0)
+
+//
+// Operational region for SMI port access
+//
+OperationRegion (ADBP, SystemIO, 0xB2, 2)
+Field (ADBP, ByteAcc, NoLock, Preserve)
+{
+B2PT, 8,
+B3PT, 8,
+}
+
+//
+// Write a string to a memory buffer
+//
+Method (MDBG, 1, Serialized)
+{
+ OperationRegion (ADHD, SystemMemory, DPTR, 32) // Operation region for
Acpi Debug buffer first 0x20 bytes
+ Field (ADHD, ByteAcc, NoLock, Preserve)
+ {
+Offset (0x0),
+ASIG, 128, // 16 bytes is Signature
+Offset (0x10),
+ASIZ, 32, // 4 bytes is buffer size
+ACHP, 32, // 4 bytes is current head pointer, normally is DPTR +
0x20,
+// if there's SMM handler to print, then it's the
starting of the info hasn't been printed yet.
+ACTP, 32, // 4 bytes is current tail pointer, is the same as CPTR
+SMIN, 8,// 1 byte of SMI Number for trigger callback
+WRAP, 8,// 1 byte of wrap status
+SMMV, 8,// 1 byte of SMM version status
+TRUN, 8 // 1 byte of truncate status
+ }
+
+ Store (Acquire (MMUT, 1000), Local0) // save Acquire result so we can
check for Mutex acquired
+ If (LEqual (Local0, Zero)) // check for Mutex acquired
+ {
+OperationRegion (ABLK, SystemMemory, CPTR, 32) // Operation region to
allow writes to ACPI debug buffer
+Field (ABLK, ByteAcc, NoLock, Preserve)
+{
+ Offset (0x0),
+ , 256 // 32 bytes is max size for string or data
+}
+ToHexString (Arg0, Local1) // convert argument to Hexadecimal String
+Store (0, TRUN)
+If (LGreaterEqual (SizeOf (Local1), 32))
+{
+ Store (1, TRUN) // the input from ASL >= 32
+}
+Mid (Local1, 0, 31, ) // extract the input to current buffer
+
+Add (CPTR, 32, CPTR) // advance current pointer to next string
location in memory buffer
+If (LGreaterEqual (CPTR, EPTR) ) // check for end of 64kb Acpi debug
buffer
+{
+ Add (DPTR, 32, CPTR) // wrap around to beginning of buffer if the
end has been reached
+ Store (1, WRAP)
+}
+Store (CPTR, ACTP)
+
+If (SMMV)
+{
+ //
+ // Triggle the SMI to print
+ //
+
[edk2] [Patch] UefiCpuPkg/MpInitLib: Direct allocate buffer for Wake up Buffer.
https://bugzilla.tianocore.org/show_bug.cgi?id=1538
Current CpuDxe driver "borrows" Wakeup Buffer (through Allocate & free
to get the buffer pointer, backup the buffer data before using it and
restore it after using). Now this logic met a problem described in
the above BZ because the test tool and the CpuDxe both use the same
memory at the same time.
In order to fix the above issue, CpuDxe changed to allocate the buffer
below 1M instead of borrow it. After investigation, we found below
0x88000 is the possible space which can be used. For now, range
0x6 ~ 0x88000 used for Legacy OPROMs by LegacyBios driver. And it
tries to allocate these range page(4K size) by page. It just reports
warning message if specific page been used by others already.
Also CpuDxe driver will produce CPU arch protocol and LegacyBios driver
has dependency for this protocol. So CpuDxe driver will start before
LegacyBios driver and CpuDxe driver can allocate that space successful.
With this change, CpuDxe driver will use 0x87000 ~ 0x88000 as wakeup
buffer.
Cc: Ray Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index b2307cbb61..5bc9a47efb 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -76,7 +76,7 @@ SaveCpuMpData (
}
/**
- Get available system memory below 1MB by specified size.
+ Get available system memory below 0x88000 by specified size.
@param[in] WakeupBufferSize Wakeup buffer size required
@@ -91,7 +91,19 @@ GetWakeupBuffer (
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESSStartAddress;
- StartAddress = BASE_1MB;
+ //
+ // Current "Borrow" space mechanism caused potential race condition if both
+ // AP and the original owner use the share space.
+ //
+ // LegacyBios driver tries to allocate 4K pages between 0x6 ~ 0x88000
+ // space. It will just report an waring message if the page has been allocate
+ // by other drivers.
+ // LagacyBios driver depends on CPU Arch protocol, so it will start after
+ // CpuDxe driver which produce Cpu Arch Protocol and use this library.
+ // So below allocate logic will be trigged before LegacyBios driver and it
+ // will always return success.
+ //
+ StartAddress = BASE_512KB + BASE_32KB;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiBootServicesData,
@@ -99,17 +111,13 @@ GetWakeupBuffer (
);
ASSERT_EFI_ERROR (Status);
- if (!EFI_ERROR (Status)) {
-Status = gBS->FreePages(
- StartAddress,
- EFI_SIZE_TO_PAGES (WakeupBufferSize)
- );
-ASSERT_EFI_ERROR (Status);
-DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
-(UINTN) StartAddress, WakeupBufferSize));
- } else {
+ if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
}
+
+ DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
+ (UINTN) StartAddress, WakeupBufferSize));
+
return (UINTN) StartAddress;
}
--
2.15.0.windows.1
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[edk2] [Patch] MdeModulePkg/PiSmmCore: Control S3 related functionality with flag.
https://bugzilla.tianocore.org/show_bug.cgi?id=1590
Use PcdAcpiS3Enable to control whether need to enable S3 related functionality
in Pi SMM Core.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 70 ++-
MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf | 1 +
2 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
b/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
index d0bc65b564..bd19803c37 100644
--- a/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
+++ b/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
@@ -77,6 +77,12 @@ BOOLEAN mInLegacyBoot = FALSE;
//
BOOLEAN mDuringS3Resume = FALSE;
+//
+// Flag to determine if platform enabled S3.
+// Get the value from PcdAcpiS3Enable.
+//
+BOOLEAN mAcpiS3Enable = FALSE;
+
//
// Table of SMI Handlers that are registered by the SMM Core when it is
initialized
//
@@ -87,6 +93,13 @@ SMM_CORE_SMI_HANDLERS mSmmCoreSmiHandlers[] = {
{ SmmExitBootServicesHandler, , NULL,
FALSE },
{ SmmReadyToBootHandler, , NULL,
FALSE },
{ SmmEndOfDxeHandler, , NULL,
TRUE },
+ { NULL, NULL,NULL,
FALSE }
+};
+
+//
+// Table of SMI Handlers that are registered by the SMM Core when it is
initialized
+//
+SMM_CORE_SMI_HANDLERS mSmmCoreS3SmiHandlers[] = {
{ SmmS3SmmInitDoneHandler,,NULL,
FALSE },
{ SmmEndOfS3ResumeHandler,,NULL,
FALSE },
{ NULL, NULL,NULL,
FALSE }
@@ -445,28 +458,30 @@ SmmEndOfDxeHandler (
NULL
);
- //
- // Locate SmmSxDispatch2 protocol.
- //
- Status = SmmLocateProtocol (
- ,
- NULL,
- (VOID **)
- );
- if (!EFI_ERROR (Status) && (SxDispatch != NULL)) {
+ if (mAcpiS3Enable) {
//
-// Register a S3 entry callback function to
-// determine if it will be during S3 resume.
+// Locate SmmSxDispatch2 protocol.
//
-EntryRegisterContext.Type = SxS3;
-EntryRegisterContext.Phase = SxEntry;
-Status = SxDispatch->Register (
- SxDispatch,
- SmmS3EntryCallBack,
- ,
-
- );
-ASSERT_EFI_ERROR (Status);
+Status = SmmLocateProtocol (
+ ,
+ NULL,
+ (VOID **)
+ );
+if (!EFI_ERROR (Status) && (SxDispatch != NULL)) {
+ //
+ // Register a S3 entry callback function to
+ // determine if it will be during S3 resume.
+ //
+ EntryRegisterContext.Type = SxS3;
+ EntryRegisterContext.Phase = SxEntry;
+ Status = SxDispatch->Register (
+ SxDispatch,
+ SmmS3EntryCallBack,
+ ,
+
+ );
+ ASSERT_EFI_ERROR (Status);
+}
}
return EFI_SUCCESS;
@@ -883,6 +898,21 @@ SmmMain (
ASSERT_EFI_ERROR (Status);
}
+ mAcpiS3Enable = PcdGetBool (PcdAcpiS3Enable);
+ if (mAcpiS3Enable) {
+//
+// Register all S3 related SMI Handlers required by the SMM Core
+//
+for (Index = 0; mSmmCoreS3SmiHandlers[Index].HandlerType != NULL; Index++)
{
+ Status = SmiHandlerRegister (
+ mSmmCoreS3SmiHandlers[Index].Handler,
+ mSmmCoreS3SmiHandlers[Index].HandlerType,
+ [Index].DispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+ }
+
RegisterSmramProfileHandler ();
SmramProfileInstallProtocol ();
diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
b/MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
index f3ece22121..9a31cb79d6 100644
--- a/MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+++ b/MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
@@ -101,6 +101,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPageType ##
CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPoolType ##
CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable##
CONSUMES
[Guids]
gAprioriGuid ## SOMETIMES_CONSUMES ## File
--
2.15.0.windows.1
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[edk2] [Patch v2 4/4] UefiCpuPkg/RegisterCpuFeaturesLib: Correct comments.
Cc: Ray Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 3e8e899766..a78ef44491 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -1174,8 +1174,8 @@ PreSmmCpuRegisterTableWrite ( @param[in] CpuBitMaskSize The size of CPU feature bit mask buffer @param[in] Feature The bit number of the CPU feature - @retval TRUE The CPU feature is set in PcdCpuFeaturesSupport. - @retval FALSE The CPU feature is not set in PcdCpuFeaturesSupport. + @retval TRUE The CPU feature is set in CpuBitMask. + @retval FALSE The CPU feature is not set in CpuBitMask. **/ BOOLEAN -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 1/4] UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions.
Remove useless APIs, simplify the code logic.
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../Include/Library/RegisterCpuFeaturesLib.h | 34 ---
.../RegisterCpuFeaturesLib.c | 50 --
2 files changed, 84 deletions(-)
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index 2f7e71c833..073f020d0b 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -166,40 +166,6 @@ IsCpuFeatureInSetting (
IN UINT32 Feature
);
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesCapability bit mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesCapability.
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesCapability.
- @retval FALSE The CPU feature is not set in PcdCpuFeaturesCapability.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureCapability (
- IN UINT32 Feature
- );
-
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesUserConfiguration bit
mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesUserConfiguration.
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesUserConfiguration.
- @retval FALSE The CPU feature is not set in
PcdCpuFeaturesUserConfiguration.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureUserConfiguration (
- IN UINT32 Feature
- );
-
/**
Prepares for the data used by CPU feature detection and initialization.
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index ed8d526325..3540029079 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -1242,56 +1242,6 @@ IsCpuFeatureInSetting (
);
}
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesCapability bit mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesCapability
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesCapability.
- @retval FALSE The CPU feature is not set in PcdCpuFeaturesCapability.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureCapability (
- IN UINT32 Feature
- )
-{
- return IsCpuFeatureSetInCpuPcd (
- (UINT8 *)PcdGetPtr (PcdCpuFeaturesCapability),
- PcdGetSize (PcdCpuFeaturesCapability),
- Feature
- );
-
-}
-
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesUserConfiguration bit
mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesUserConfiguration
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesUserConfiguration.
- @retval FALSE The CPU feature is not set in
PcdCpuFeaturesUserConfiguration.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureUserConfiguration (
- IN UINT32 Feature
- )
-{
- return IsCpuFeatureSetInCpuPcd (
- (UINT8 *)PcdGetPtr (PcdCpuFeaturesUserConfiguration),
- PcdGetSize (PcdCpuFeaturesUserConfiguration),
- Feature
- );
-
-}
-
/**
Switches to assigned BSP after CPU features initialization.
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 0/4] Simplify CPU Features solution.
V2 Changes include: 1. Add ASSERT to make sure PcdCpuFeaturesSetting and PcdCpuFeaturesCapability have equal size. 2. Correct comment block on IsCpuFeatureSetInCpuPcd() references "PcdCpuFeaturesSupport". It should reference "CpuBitMask". V1 Changes includes: 1. Optimize PCD PcdCpuFeaturesUserConfiguration 2. Limit useage of PcdCpuFeaturesSupport 3. Remove some useless APIs. Detail explanation please check each patch's introduction. Cc: Ray Ni Cc: Laszlo Ersek Eric Dong (4): UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions. UefiCpuPkg/RegisterCpuFeaturesLib: Optimize PCD PcdCpuFeaturesUserConfiguration. UefiCpuPkg/RegisterCpuFeaturesLib: Simplify PcdCpuFeaturesSupport. UefiCpuPkg/RegisterCpuFeaturesLib: Correct comments. .../Include/Library/RegisterCpuFeaturesLib.h | 34 -- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 114 ++--- .../DxeRegisterCpuFeaturesLib.inf | 3 +- .../PeiRegisterCpuFeaturesLib.inf | 3 +- .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 2 - .../RegisterCpuFeaturesLib.c | 64 ++-- UefiCpuPkg/UefiCpuPkg.dec | 9 +- 7 files changed, 45 insertions(+), 184 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 3/4] UefiCpuPkg/RegisterCpuFeaturesLib: Simplify PcdCpuFeaturesSupport.
PcdCpuFeaturesSupport used to specify the platform policy about
what CPU features this platform supports. This PCD will be used
in IsCpuFeatureSupported only.
Now RegisterCpuFeaturesLib use this PCD as an template to Get the
pcd size. Update the code logic to replace it with
PcdCpuFeaturesSetting.
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 43 +-
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 1 -
.../RegisterCpuFeaturesLib.c | 10 ++---
3 files changed, 22 insertions(+), 32 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index d877caff74..c82f848b97 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -245,11 +245,6 @@ CpuInitDataInitialize (
ASSERT (CpuFeaturesData->CpuFlags.CoreSemaphoreCount != NULL);
CpuFeaturesData->CpuFlags.PackageSemaphoreCount = AllocateZeroPool (sizeof
(UINT32) * CpuStatus->PackageCount * CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount);
ASSERT (CpuFeaturesData->CpuFlags.PackageSemaphoreCount != NULL);
-
- //
- // Get support and configuration PCDs
- //
- CpuFeaturesData->SupportPcd = GetSupportPcd ();
}
/**
@@ -269,7 +264,7 @@ SupportedMaskOr (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = OrFeatureBitMask;
for (Index = 0; Index < BitMaskSize; Index++) {
@@ -294,7 +289,7 @@ SupportedMaskAnd (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = AndFeatureBitMask;
for (Index = 0; Index < BitMaskSize; Index++) {
@@ -319,7 +314,7 @@ SupportedMaskCleanBit (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = AndFeatureBitMask;
for (Index = 0; Index < BitMaskSize; Index++) {
@@ -350,7 +345,7 @@ IsBitMaskMatch (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = ComparedFeatureBitMask;
@@ -389,21 +384,19 @@ CollectProcessorData (
Entry = GetFirstNode (>FeatureList);
while (!IsNull (>FeatureList, Entry)) {
CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
-if (IsBitMaskMatch (CpuFeaturesData->SupportPcd, CpuFeature->FeatureMask))
{
- if (CpuFeature->SupportFunc == NULL) {
-//
-// If SupportFunc is NULL, then the feature is supported.
-//
-SupportedMaskOr (
- CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
- CpuFeature->FeatureMask
- );
- } else if (CpuFeature->SupportFunc (ProcessorNumber, CpuInfo,
CpuFeature->ConfigData)) {
-SupportedMaskOr (
- CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
- CpuFeature->FeatureMask
- );
- }
+if (CpuFeature->SupportFunc == NULL) {
+ //
+ // If SupportFunc is NULL, then the feature is supported.
+ //
+ SupportedMaskOr (
+CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
+CpuFeature->FeatureMask
+);
+} else if (CpuFeature->SupportFunc (ProcessorNumber, CpuInfo,
CpuFeature->ConfigData)) {
+ SupportedMaskOr (
+CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
+CpuFeature->FeatureMask
+);
}
Entry = Entry->ForwardLink;
}
@@ -596,8 +589,6 @@ AnalysisProcessorFeatures (
DumpCpuFeature (CpuFeature);
Entry = Entry->ForwardLink;
}
-DEBUG ((DEBUG_INFO, "PcdCpuFeaturesSupport:\n"));
-DumpCpuFeatureMask (CpuFeaturesData->SupportPcd);
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));
DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd);
DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
index 3e0a342fd1..836ed3549c 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/
[edk2] [Patch v2 2/4] UefiCpuPkg/RegisterCpuFeaturesLib: Optimize PCD PcdCpuFeaturesUserConfiguration.
Merge PcdCpuFeaturesUserConfiguration into PcdCpuFeaturesSetting.
Use PcdCpuFeaturesSetting as input for the user input feature setting
Use PcdCpuFeaturesSetting as output for the final CPU feature setting
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 71 +-
.../DxeRegisterCpuFeaturesLib.inf | 3 +-
.../PeiRegisterCpuFeaturesLib.inf | 3 +-
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 1 -
UefiCpuPkg/UefiCpuPkg.dec | 9 +--
5 files changed, 21 insertions(+), 66 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index bae92b89a6..d877caff74 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -21,16 +21,21 @@ CHAR16 *mRegisterTypeStr[] = {L"MSR", L"CR", L"MMIO",
L"CACHE", L"SEMAP", L"INVA
Worker function to save PcdCpuFeaturesCapability.
@param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+ @param[in] FeatureMaskSize CPU feature bits mask buffer size.
+
**/
VOID
SetCapabilityPcd (
- IN UINT8 *SupportedFeatureMask
+ IN UINT8 *SupportedFeatureMask,
+ IN UINT32 FeatureMaskSize
)
{
EFI_STATUS Status;
UINTN BitMaskSize;
BitMaskSize = PcdGetSize (PcdCpuFeaturesCapability);
+ ASSERT (FeatureMaskSize == BitMaskSize);
+
Status = PcdSetPtrS (PcdCpuFeaturesCapability, ,
SupportedFeatureMask);
ASSERT_EFI_ERROR (Status);
}
@@ -53,48 +58,6 @@ SetSettingPcd (
ASSERT_EFI_ERROR (Status);
}
-/**
- Worker function to get PcdCpuFeaturesSupport.
-
- @return The pointer to CPU feature bits mask buffer.
-**/
-UINT8 *
-GetSupportPcd (
- VOID
- )
-{
- UINT8 *SupportBitMask;
-
- SupportBitMask = AllocateCopyPool (
- PcdGetSize (PcdCpuFeaturesSupport),
- PcdGetPtr (PcdCpuFeaturesSupport)
- );
- ASSERT (SupportBitMask != NULL);
-
- return SupportBitMask;
-}
-
-/**
- Worker function to get PcdCpuFeaturesUserConfiguration.
-
- @return The pointer to CPU feature bits mask buffer.
-**/
-UINT8 *
-GetConfigurationPcd (
- VOID
- )
-{
- UINT8 *SupportBitMask;
-
- SupportBitMask = AllocateCopyPool (
- PcdGetSize (PcdCpuFeaturesUserConfiguration),
- PcdGetPtr (PcdCpuFeaturesUserConfiguration)
- );
- ASSERT (SupportBitMask != NULL);
-
- return SupportBitMask;
-}
-
/**
Collects CPU type and feature information.
@@ -287,7 +250,6 @@ CpuInitDataInitialize (
// Get support and configuration PCDs
//
CpuFeaturesData->SupportPcd = GetSupportPcd ();
- CpuFeaturesData->ConfigurationPcd = GetConfigurationPcd ();
}
/**
@@ -610,16 +572,9 @@ AnalysisProcessorFeatures (
//
// Calculate the last setting
//
-
CpuFeaturesData->SettingPcd = AllocateCopyPool
(CpuFeaturesData->BitMaskSize, CpuFeaturesData->CapabilityPcd);
ASSERT (CpuFeaturesData->SettingPcd != NULL);
- SupportedMaskAnd (CpuFeaturesData->SettingPcd,
CpuFeaturesData->ConfigurationPcd);
-
- //
- // Save PCDs and display CPU PCDs
- //
- SetCapabilityPcd (CpuFeaturesData->CapabilityPcd);
- SetSettingPcd (CpuFeaturesData->SettingPcd);
+ SupportedMaskAnd (CpuFeaturesData->SettingPcd, PcdGetPtr
(PcdCpuFeaturesSetting));
//
// Dump the last CPU feature list
@@ -643,14 +598,20 @@ AnalysisProcessorFeatures (
}
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesSupport:\n"));
DumpCpuFeatureMask (CpuFeaturesData->SupportPcd);
-DEBUG ((DEBUG_INFO, "PcdCpuFeaturesUserConfiguration:\n"));
-DumpCpuFeatureMask (CpuFeaturesData->ConfigurationPcd);
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));
DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd);
-DEBUG ((DEBUG_INFO, "PcdCpuFeaturesSetting:\n"));
+DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));
+DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting));
+DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n"));
DumpCpuFeatureMask (CpuFeaturesData->SettingPcd);
);
+ //
+ // Save PCDs and display CPU PCDs
+ //
+ SetCapabilityPcd (CpuFeaturesData->CapabilityPcd,
CpuFeaturesData->BitMaskSize);
+ SetSettingPcd (CpuFeaturesData->SettingPcd);
+
for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++)
{
CpuInitOrder = >InitOrder[ProcessorNumber];
Entry = GetFirstNode (>FeatureList);
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegiste
[edk2] [Patch] SecurityPkg/OpalPassword: Fix incorrect line ending issue.
Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- SecurityPkg/Tcg/Opal/OpalPassword/OpalHiiCallbacks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SecurityPkg/Tcg/Opal/OpalPassword/OpalHiiCallbacks.c b/SecurityPkg/Tcg/Opal/OpalPassword/OpalHiiCallbacks.c index 6d1a3a9b25..a1802313c3 100644 --- a/SecurityPkg/Tcg/Opal/OpalPassword/OpalHiiCallbacks.c +++ b/SecurityPkg/Tcg/Opal/OpalPassword/OpalHiiCallbacks.c @@ -115,4 +115,4 @@ HiiDiskGetNameCB( return Ctx->NameZ; } return NULL; -} \ No newline at end of file +} \ No newline at end of file -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 3/3] UefiCpuPkg/RegisterCpuFeaturesLib: Simplify PcdCpuFeaturesSupport.
PcdCpuFeaturesSupport used to specify the platform policy about
what CPU features this platform supports. This value is decide by
platform owner, not by hardware. After this change, this PCD will
be used in IsCpuFeatureSupported function only.
Now RegisterCpuFeaturesLib use this PCD as an template to Get the
pcd size. Update the code logic to replace it with
PcdCpuFeaturesSetting.
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 66 +++---
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 1 -
.../RegisterCpuFeaturesLib.c | 10 ++--
3 files changed, 24 insertions(+), 53 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 4ebd0025b4..762eaec277 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -74,27 +74,6 @@ GetSettingPcd (
return SettingBitMask;
}
-/**
- Worker function to get PcdCpuFeaturesSupport.
-
- @return The pointer to CPU feature bits mask buffer.
-**/
-UINT8 *
-GetSupportPcd (
- VOID
- )
-{
- UINT8 *SupportBitMask;
-
- SupportBitMask = AllocateCopyPool (
- PcdGetSize (PcdCpuFeaturesSupport),
- PcdGetPtr (PcdCpuFeaturesSupport)
- );
- ASSERT (SupportBitMask != NULL);
-
- return SupportBitMask;
-}
-
/**
Collects CPU type and feature information.
@@ -282,11 +261,6 @@ CpuInitDataInitialize (
ASSERT (CpuFeaturesData->CpuFlags.CoreSemaphoreCount != NULL);
CpuFeaturesData->CpuFlags.PackageSemaphoreCount = AllocateZeroPool (sizeof
(UINT32) * CpuStatus->PackageCount * CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount);
ASSERT (CpuFeaturesData->CpuFlags.PackageSemaphoreCount != NULL);
-
- //
- // Get support and configuration PCDs
- //
- CpuFeaturesData->SupportPcd = GetSupportPcd ();
}
/**
@@ -306,7 +280,7 @@ SupportedMaskOr (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = OrFeatureBitMask;
for (Index = 0; Index < BitMaskSize; Index++) {
@@ -331,7 +305,7 @@ SupportedMaskAnd (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = AndFeatureBitMask;
for (Index = 0; Index < BitMaskSize; Index++) {
@@ -356,7 +330,7 @@ SupportedMaskCleanBit (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = AndFeatureBitMask;
for (Index = 0; Index < BitMaskSize; Index++) {
@@ -387,7 +361,7 @@ IsBitMaskMatch (
UINT8 *Data1;
UINT8 *Data2;
- BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
Data1 = SupportedFeatureMask;
Data2 = ComparedFeatureBitMask;
@@ -426,22 +400,22 @@ CollectProcessorData (
Entry = GetFirstNode (>FeatureList);
while (!IsNull (>FeatureList, Entry)) {
CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
-if (IsBitMaskMatch (CpuFeaturesData->SupportPcd, CpuFeature->FeatureMask))
{
- if (CpuFeature->SupportFunc == NULL) {
-//
-// If SupportFunc is NULL, then the feature is supported.
-//
-SupportedMaskOr (
- CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
- CpuFeature->FeatureMask
- );
- } else if (CpuFeature->SupportFunc (ProcessorNumber, CpuInfo,
CpuFeature->ConfigData)) {
-SupportedMaskOr (
- CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
- CpuFeature->FeatureMask
- );
- }
+
+if (CpuFeature->SupportFunc == NULL) {
+ //
+ // If SupportFunc is NULL, then the feature is supported.
+ //
+ SupportedMaskOr (
+CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
+CpuFeature->FeatureMask
+);
+} else if (CpuFeature->SupportFunc (ProcessorNumber, CpuInfo,
CpuFeature->ConfigData)) {
+ SupportedMaskOr (
+CpuFeaturesData->InitOrder[ProcessorNumber].FeaturesSupportedMask,
+CpuFeature->FeatureMask
+);
}
+
Entry = Entry->ForwardLink;
}
}
@@ -646,8 +620,6 @@ AnalysisProcessorFeatures (
DumpCpuFeature (CpuFeature);
[edk2] [Patch 1/3] UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions.
Remove useless APIs, simply the code logic.
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../Include/Library/RegisterCpuFeaturesLib.h | 34 ---
.../RegisterCpuFeaturesLib.c | 50 --
2 files changed, 84 deletions(-)
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index 2f7e71c833..073f020d0b 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -166,40 +166,6 @@ IsCpuFeatureInSetting (
IN UINT32 Feature
);
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesCapability bit mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesCapability.
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesCapability.
- @retval FALSE The CPU feature is not set in PcdCpuFeaturesCapability.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureCapability (
- IN UINT32 Feature
- );
-
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesUserConfiguration bit
mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesUserConfiguration.
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesUserConfiguration.
- @retval FALSE The CPU feature is not set in
PcdCpuFeaturesUserConfiguration.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureUserConfiguration (
- IN UINT32 Feature
- );
-
/**
Prepares for the data used by CPU feature detection and initialization.
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index ed8d526325..3540029079 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -1242,56 +1242,6 @@ IsCpuFeatureInSetting (
);
}
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesCapability bit mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesCapability
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesCapability.
- @retval FALSE The CPU feature is not set in PcdCpuFeaturesCapability.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureCapability (
- IN UINT32 Feature
- )
-{
- return IsCpuFeatureSetInCpuPcd (
- (UINT8 *)PcdGetPtr (PcdCpuFeaturesCapability),
- PcdGetSize (PcdCpuFeaturesCapability),
- Feature
- );
-
-}
-
-/**
- Determines if a CPU feature is set in PcdCpuFeaturesUserConfiguration bit
mask.
-
- @param[in] Feature The bit number of the CPU feature to check in the PCD
- PcdCpuFeaturesUserConfiguration
-
- @retval TRUE The CPU feature is set in PcdCpuFeaturesUserConfiguration.
- @retval FALSE The CPU feature is not set in
PcdCpuFeaturesUserConfiguration.
-
- @note This service could be called by BSP only.
-**/
-BOOLEAN
-EFIAPI
-IsCpuFeatureUserConfiguration (
- IN UINT32 Feature
- )
-{
- return IsCpuFeatureSetInCpuPcd (
- (UINT8 *)PcdGetPtr (PcdCpuFeaturesUserConfiguration),
- PcdGetSize (PcdCpuFeaturesUserConfiguration),
- Feature
- );
-
-}
-
/**
Switches to assigned BSP after CPU features initialization.
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 2/3] UefiCpuPkg/RegisterCpuFeaturesLib: Optimize PCD PcdCpuFeaturesUserConfiguration.
In current implementation, PCD PcdCpuFeaturesUserConfiguration used as
user enabled CPU features list. It is initialzied in platform driver
and as an input for CpuFeatures driver. PCD PcdCpuFeaturesSetting used
as an output for the final enabled CPU features list. For now,
PcdCpuFeaturesUserConfiguration is only used as an input and
PcdCpuFeaturesSetting only used as an output.
This change merge PcdCpuFeaturesUserConfiguration into
PcdCpuFeaturesSetting.
Use PcdCpuFeaturesSetting as input for the user input feature setting
Use PcdCpuFeaturesSetting as output for the final CPU feature setting
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 37 --
.../DxeRegisterCpuFeaturesLib.inf | 1 -
.../PeiRegisterCpuFeaturesLib.inf | 1 -
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 1 -
UefiCpuPkg/UefiCpuPkg.dec | 7 ++--
5 files changed, 22 insertions(+), 25 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index bae92b89a6..4ebd0025b4 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -54,41 +54,41 @@ SetSettingPcd (
}
/**
- Worker function to get PcdCpuFeaturesSupport.
+ Worker function to get PcdCpuFeaturesSetting.
@return The pointer to CPU feature bits mask buffer.
**/
UINT8 *
-GetSupportPcd (
+GetSettingPcd (
VOID
)
{
- UINT8 *SupportBitMask;
+ UINT8 *SettingBitMask;
- SupportBitMask = AllocateCopyPool (
- PcdGetSize (PcdCpuFeaturesSupport),
- PcdGetPtr (PcdCpuFeaturesSupport)
+ SettingBitMask = AllocateCopyPool (
+ PcdGetSize (PcdCpuFeaturesSetting),
+ PcdGetPtr (PcdCpuFeaturesSetting)
);
- ASSERT (SupportBitMask != NULL);
+ ASSERT (SettingBitMask != NULL);
- return SupportBitMask;
+ return SettingBitMask;
}
/**
- Worker function to get PcdCpuFeaturesUserConfiguration.
+ Worker function to get PcdCpuFeaturesSupport.
@return The pointer to CPU feature bits mask buffer.
**/
UINT8 *
-GetConfigurationPcd (
+GetSupportPcd (
VOID
)
{
UINT8 *SupportBitMask;
SupportBitMask = AllocateCopyPool (
- PcdGetSize (PcdCpuFeaturesUserConfiguration),
- PcdGetPtr (PcdCpuFeaturesUserConfiguration)
+ PcdGetSize (PcdCpuFeaturesSupport),
+ PcdGetPtr (PcdCpuFeaturesSupport)
);
ASSERT (SupportBitMask != NULL);
@@ -287,7 +287,6 @@ CpuInitDataInitialize (
// Get support and configuration PCDs
//
CpuFeaturesData->SupportPcd = GetSupportPcd ();
- CpuFeaturesData->ConfigurationPcd = GetConfigurationPcd ();
}
/**
@@ -595,6 +594,9 @@ AnalysisProcessorFeatures (
CPU_FEATURE_DEPENDENCE_TYPE AfterDep;
CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep;
CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep;
+ UINT8*ConfigurationPcd;
+
+ ConfigurationPcd = NULL;
CpuFeaturesData = GetCpuFeaturesData ();
CpuFeaturesData->CapabilityPcd = AllocatePool (CpuFeaturesData->BitMaskSize);
@@ -610,10 +612,13 @@ AnalysisProcessorFeatures (
//
// Calculate the last setting
//
-
CpuFeaturesData->SettingPcd = AllocateCopyPool
(CpuFeaturesData->BitMaskSize, CpuFeaturesData->CapabilityPcd);
ASSERT (CpuFeaturesData->SettingPcd != NULL);
- SupportedMaskAnd (CpuFeaturesData->SettingPcd,
CpuFeaturesData->ConfigurationPcd);
+ ConfigurationPcd = GetSettingPcd ();
+ SupportedMaskAnd (CpuFeaturesData->SettingPcd, ConfigurationPcd);
+ if (ConfigurationPcd != NULL) {
+FreePool (ConfigurationPcd);
+ }
//
// Save PCDs and display CPU PCDs
@@ -643,8 +648,6 @@ AnalysisProcessorFeatures (
}
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesSupport:\n"));
DumpCpuFeatureMask (CpuFeaturesData->SupportPcd);
-DEBUG ((DEBUG_INFO, "PcdCpuFeaturesUserConfiguration:\n"));
-DumpCpuFeatureMask (CpuFeaturesData->ConfigurationPcd);
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));
DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd);
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesSetting:\n"));
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
index 362e0c6cd1..b7dc70808f 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
@@ -56,7 +56,6 @@
[Pcd]
[edk2] [Patch 0/3] Simplify CPU Features solution.
Changes includes: 1. Optimize PCD PcdCpuFeaturesUserConfiguration 2. Limit useage of PcdCpuFeaturesSupport 3. Remove some useless APIs. Detail explanation please check each patch's introduction. Cc: Ray Ni Cc: Laszlo Ersek Eric Dong (3): UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions. UefiCpuPkg/RegisterCpuFeaturesLib: Optimize PCD PcdCpuFeaturesUserConfiguration. UefiCpuPkg/RegisterCpuFeaturesLib: Simplify PcdCpuFeaturesSupport. .../Include/Library/RegisterCpuFeaturesLib.h | 34 .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 95 -- .../DxeRegisterCpuFeaturesLib.inf | 1 - .../PeiRegisterCpuFeaturesLib.inf | 1 - .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 2 - .../RegisterCpuFeaturesLib.c | 60 ++ UefiCpuPkg/UefiCpuPkg.dec | 7 +- 7 files changed, 42 insertions(+), 158 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 2/2] MdeModulePkg/BootScriptExecuteorDxe: Use correct field name.
((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))
In above code, Facs->OspmFlags should be used instead.
EFI_ACPI_4_0_OSPM_64BIT_WAKE__F is a bit in OSPM Enabled Firmware
Control Structure Flags field, not in Firmware Control Structure
Feature Flags.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1430
Cc: Aleksiy
Cc: Jian Wang
Contributed-under: TianoCore Contribution Agreement 1.1
signed-off-by: Eric Dong
Signed-off-by: Eric Dong
---
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c | 4 ++--
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
index e76abb7b7b..13af957a4d 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
@@ -4,7 +4,7 @@
This driver is dispatched by Dxe core and the driver will reload itself to
ACPI reserved memory
in the entry point. The functionality is to interpret and restore the S3
boot script
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -156,7 +156,7 @@ S3BootScriptExecutorEntryFunction (
TempStackTop = (UINTN) + sizeof(TempStack);
if ((Facs->Version ==
EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
-((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
+((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
//
// X64 long mode waking vector
//
diff --git
a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
index 1c6bb47b60..7b9627d579 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
@@ -3,7 +3,7 @@
Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
@@ -117,7 +117,7 @@ IsLongModeWakingVector (
if (Facs->XFirmwareWakingVector != 0) {
if ((Facs->Version ==
EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
-((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
+((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
// Both BIOS and OS wants 64bit vector
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
return TRUE;
--
2.15.0.windows.1
___
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[edk2] [Patch 0/2] Use correct field name.
((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) In above code, Facs->OspmFlags should be used instead. EFI_ACPI_4_0_OSPM_64BIT_WAKE__F is a bit in OSPM Enabled Firmware Control Structure Flags field, not in Firmware Control Structure Feature Flags. Update all related code to use correct field name. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1430 Cc: Aleksiy Cc: Ray Ni Cc: Laszlo Ersek Cc: Jian Wang Eric Dong (2): UefiCpuPkg/S3Resume2Pei: Use correct field name. MdeModulePkg/BootScriptExecuteorDxe: Use correct field name. MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c | 4 ++-- MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 ++-- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 1/2] UefiCpuPkg/S3Resume2Pei: Use correct field name.
((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))
In above code, Facs->OspmFlags should be used instead.
EFI_ACPI_4_0_OSPM_64BIT_WAKE__F is a bit in OSPM Enabled Firmware
Control Structure Flags field, not in Firmware Control Structure
Feature Flags.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1430
Cc: Aleksiy
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
signed-off-by: Eric Dong
Signed-off-by: Eric Dong
---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index 05234a6312..c85dfc0290 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -4,7 +4,7 @@
This module will execute the boot script saved during last boot and after
that,
control is passed to OS waking up handler.
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -316,7 +316,7 @@ IsLongModeWakingVector (
if (Facs->XFirmwareWakingVector != 0) {
if ((Facs->Version ==
EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
-((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
+((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
// Both BIOS and OS wants 64bit vector
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
return TRUE;
@@ -499,7 +499,7 @@ S3ResumeBootOs (
));
if ((Facs->Version ==
EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
-((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
+((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
//
// X64 long mode waking vector
//
--
2.15.0.windows.1
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[edk2] [Patch v4 2/2] UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.
V3:
1. Define union to specify the ppi or protocol.
V2:
1. Initialize CpuFeaturesData->MpService in CpuInitDataInitialize
and make this function been called at the begin of the
initialization.
2. let all other functions use CpuFeaturesData->MpService install
of locate the protocol itself.
V1:
GetProcessorIndex function calls GetMpPpi to get the MP Ppi.
Ap will calls GetProcessorIndex function which final let AP calls
PeiService.
This patch avoid GetProcessorIndex call PeiService.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 22 ---
.../DxeRegisterCpuFeaturesLib.c| 59 ++
.../PeiRegisterCpuFeaturesLib.c| 70 +-
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 25 +++-
4 files changed, 99 insertions(+), 77 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 624ddee055..5866e022f0 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -138,7 +138,7 @@ FillProcessorInfo (
**/
VOID
CpuInitDataInitialize (
- IN UINTN NumberOfCpus
+ VOID
)
{
EFI_STATUS Status;
@@ -157,12 +157,22 @@ CpuInitDataInitialize (
ACPI_CPU_DATA*AcpiCpuData;
CPU_STATUS_INFORMATION *CpuStatus;
UINT32 *ValidCoreCountPerPackage;
+ UINTNNumberOfCpus;
+ UINTNNumberOfEnabledProcessors;
Core= 0;
Package = 0;
Thread = 0;
CpuFeaturesData = GetCpuFeaturesData ();
+
+ //
+ // Initialize CpuFeaturesData->MpService as early as possile, so later
function can use it.
+ //
+ CpuFeaturesData->MpService = GetMpService ();
+
+ GetNumberOfProcessor (, );
+
CpuFeaturesData->InitOrder = AllocateZeroPool (sizeof
(CPU_FEATURES_INIT_ORDER) * NumberOfCpus);
ASSERT (CpuFeaturesData->InitOrder != NULL);
@@ -409,7 +419,7 @@ CollectProcessorData (
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;
- ProcessorNumber = GetProcessorIndex ();
+ ProcessorNumber = GetProcessorIndex (CpuFeaturesData);
CpuInfo = >InitOrder[ProcessorNumber].CpuInfo;
//
// collect processor information
@@ -1105,15 +1115,11 @@ CpuFeaturesDetect (
VOID
)
{
- UINTN NumberOfCpus;
- UINTN NumberOfEnabledProcessors;
CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData();
- GetNumberOfProcessor (, );
-
- CpuInitDataInitialize (NumberOfCpus);
+ CpuInitDataInitialize ();
//
// Wakeup all APs for data collection.
@@ -1125,6 +1131,6 @@ CpuFeaturesDetect (
//
CollectProcessorData (CpuFeaturesData);
- AnalysisProcessorFeatures (NumberOfCpus);
+ AnalysisProcessorFeatures (CpuFeaturesData->NumberOfCpus);
}
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
index 926698dc95..3654c105ef 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
@@ -20,7 +20,6 @@
#include "RegisterCpuFeatures.h"
CPU_FEATURES_DATA mCpuFeaturesData = {0};
-EFI_MP_SERVICES_PROTOCOL *mCpuFeaturesMpServices = NULL;
/**
Worker function to get CPU_FEATURES_DATA pointer.
@@ -38,46 +37,46 @@ GetCpuFeaturesData (
/**
Worker function to get EFI_MP_SERVICES_PROTOCOL pointer.
- @return Pointer to EFI_MP_SERVICES_PROTOCOL.
+ @return MP_SERVICES variable.
**/
-EFI_MP_SERVICES_PROTOCOL *
-GetMpProtocol (
+MP_SERVICES
+GetMpService (
VOID
)
{
- EFI_STATUS Status;
-
- if (mCpuFeaturesMpServices == NULL) {
-//
-// Get MP Services Protocol
-//
-Status = gBS->LocateProtocol (
- ,
- NULL,
- (VOID **)
- );
-ASSERT_EFI_ERROR (Status);
- }
+ EFI_STATUSStatus;
+ MP_SERVICES MpService;
- ASSERT (mCpuFeaturesMpServices != NULL);
- return mCpuFeaturesMpServices;
+ //
+ // Get MP Services Protocol
+ //
+ Status = gBS->LocateProtocol (
+,
+NULL,
+(VOID **)
+);
+ ASSERT_EFI_ERROR (Status);
+
+ return MpService;
}
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcesso
[edk2] [Patch v4 0/2] Avoid AP calls PeiServices table.
AP should not use PeiServices. The patch serial fix one issue related to this. This serial also include one patch used to refine the debug message. Cc: Ruiyu Ni Eric Dong (2): UefiCpuPkg/RegisterCpuFeaturesLib: Enhance debug message. UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService. .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 39 +++- .../DxeRegisterCpuFeaturesLib.c| 59 ++ .../PeiRegisterCpuFeaturesLib.c| 70 +- .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 25 +++- 4 files changed, 110 insertions(+), 83 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v4 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Enhance debug message.
Enhance debug message format to let them easy to read. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Ray Ni --- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 0a74d448c8..624ddee055 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -473,8 +473,9 @@ DumpRegisterTableOnProcessor ( case Msr: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: MSR: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index, RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -484,8 +485,9 @@ DumpRegisterTableOnProcessor ( case ControlRegister: DEBUG (( DebugPrintErrorLevel, -"Processor: %d:CR: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index, RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -495,8 +497,9 @@ DumpRegisterTableOnProcessor ( case MemoryMapped: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: MMIO: %lx, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, MMIO : %08lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32), RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -506,8 +509,9 @@ DumpRegisterTableOnProcessor ( case CacheControl: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: CACHE: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, CACHE: %08lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index, RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -517,8 +521,9 @@ DumpRegisterTableOnProcessor ( case Semaphore: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: Semaphore: Scope Value: %s\r\n", +"Processor: %04d: Index %04d, SEMAP: %s\r\n", ProcessorNumber, +FeatureIndex, mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)] )); break; @@ -833,7 +838,7 @@ ProgramProcessorRegister ( ApLocation->Thread; DEBUG (( DEBUG_INFO, -"Processor = %lu, Entry Index %lu, Type = %s!\n", +"Processor = %08lu, Index %08lu, Type = %s!\n", (UINT64)ThreadIndex, (UINT64)Index, mRegisterTypeStr[MIN ((REGISTER_TYPE)RegisterTableEntry->RegisterType, InvalidReg)] -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 2/2] UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.
V2:
1. Initialize CpuFeaturesData->MpService in CpuInitDataInitialize
and make this function been called at the begin of the
initialization.
2. let all other functions use CpuFeaturesData->MpService install
of locate the protocol itself.
V1:
GetProcessorIndex function calls GetMpPpi to get the MP Ppi.
Ap will calls GetProcessorIndex function which final let AP calls
PeiService.
This patch avoid GetProcessorIndex call PeiService.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 22 +---
.../DxeRegisterCpuFeaturesLib.c| 57 +++-
.../PeiRegisterCpuFeaturesLib.c| 62 +-
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 16 +-
4 files changed, 85 insertions(+), 72 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 624ddee055..5866e022f0 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -138,7 +138,7 @@ FillProcessorInfo (
**/
VOID
CpuInitDataInitialize (
- IN UINTN NumberOfCpus
+ VOID
)
{
EFI_STATUS Status;
@@ -157,12 +157,22 @@ CpuInitDataInitialize (
ACPI_CPU_DATA*AcpiCpuData;
CPU_STATUS_INFORMATION *CpuStatus;
UINT32 *ValidCoreCountPerPackage;
+ UINTNNumberOfCpus;
+ UINTNNumberOfEnabledProcessors;
Core= 0;
Package = 0;
Thread = 0;
CpuFeaturesData = GetCpuFeaturesData ();
+
+ //
+ // Initialize CpuFeaturesData->MpService as early as possile, so later
function can use it.
+ //
+ CpuFeaturesData->MpService = GetMpService ();
+
+ GetNumberOfProcessor (, );
+
CpuFeaturesData->InitOrder = AllocateZeroPool (sizeof
(CPU_FEATURES_INIT_ORDER) * NumberOfCpus);
ASSERT (CpuFeaturesData->InitOrder != NULL);
@@ -409,7 +419,7 @@ CollectProcessorData (
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;
- ProcessorNumber = GetProcessorIndex ();
+ ProcessorNumber = GetProcessorIndex (CpuFeaturesData);
CpuInfo = >InitOrder[ProcessorNumber].CpuInfo;
//
// collect processor information
@@ -1105,15 +1115,11 @@ CpuFeaturesDetect (
VOID
)
{
- UINTN NumberOfCpus;
- UINTN NumberOfEnabledProcessors;
CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData();
- GetNumberOfProcessor (, );
-
- CpuInitDataInitialize (NumberOfCpus);
+ CpuInitDataInitialize ();
//
// Wakeup all APs for data collection.
@@ -1125,6 +1131,6 @@ CpuFeaturesDetect (
//
CollectProcessorData (CpuFeaturesData);
- AnalysisProcessorFeatures (NumberOfCpus);
+ AnalysisProcessorFeatures (CpuFeaturesData->NumberOfCpus);
}
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
index 926698dc95..2d2095e437 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
@@ -20,7 +20,6 @@
#include "RegisterCpuFeatures.h"
CPU_FEATURES_DATA mCpuFeaturesData = {0};
-EFI_MP_SERVICES_PROTOCOL *mCpuFeaturesMpServices = NULL;
/**
Worker function to get CPU_FEATURES_DATA pointer.
@@ -40,44 +39,44 @@ GetCpuFeaturesData (
@return Pointer to EFI_MP_SERVICES_PROTOCOL.
**/
-EFI_MP_SERVICES_PROTOCOL *
-GetMpProtocol (
+VOID *
+GetMpService (
VOID
)
{
- EFI_STATUS Status;
-
- if (mCpuFeaturesMpServices == NULL) {
-//
-// Get MP Services Protocol
-//
-Status = gBS->LocateProtocol (
- ,
- NULL,
- (VOID **)
- );
-ASSERT_EFI_ERROR (Status);
- }
+ EFI_STATUSStatus;
+ EFI_MP_SERVICES_PROTOCOL *MpServices;
- ASSERT (mCpuFeaturesMpServices != NULL);
- return mCpuFeaturesMpServices;
+ //
+ // Get MP Services Protocol
+ //
+ Status = gBS->LocateProtocol (
+,
+NULL,
+(VOID **)
+);
+ ASSERT_EFI_ERROR (Status);
+
+ return MpServices;
}
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcessorIndex (
- VOID
+ IN CPU_FEATURES_DATA*CpuFeaturesData
)
{
EFI_STATUS Status;
UINTN
[edk2] [Patch v2 0/2] Avoid AP calls PeiServices table.
AP should not use PeiServices. The patch serial fix one issue related to this. This serial also include one patch used to refine the debug message. Eric Dong (2): UefiCpuPkg/RegisterCpuFeaturesLib: Enhance debug message. UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService. .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 39 +- .../DxeRegisterCpuFeaturesLib.c| 57 +++- .../PeiRegisterCpuFeaturesLib.c| 62 +- .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 16 +- 4 files changed, 96 insertions(+), 78 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Enhance debug message.
Enhance debug message format to let them easy to read. Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 0a74d448c8..624ddee055 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -473,8 +473,9 @@ DumpRegisterTableOnProcessor ( case Msr: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: MSR: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index, RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -484,8 +485,9 @@ DumpRegisterTableOnProcessor ( case ControlRegister: DEBUG (( DebugPrintErrorLevel, -"Processor: %d:CR: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index, RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -495,8 +497,9 @@ DumpRegisterTableOnProcessor ( case MemoryMapped: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: MMIO: %lx, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, MMIO : %08lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32), RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -506,8 +509,9 @@ DumpRegisterTableOnProcessor ( case CacheControl: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: CACHE: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", +"Processor: %04d: Index %04d, CACHE: %08lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", ProcessorNumber, +FeatureIndex, RegisterTableEntry->Index, RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, @@ -517,8 +521,9 @@ DumpRegisterTableOnProcessor ( case Semaphore: DEBUG (( DebugPrintErrorLevel, -"Processor: %d: Semaphore: Scope Value: %s\r\n", +"Processor: %04d: Index %04d, SEMAP: %s\r\n", ProcessorNumber, +FeatureIndex, mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)] )); break; @@ -833,7 +838,7 @@ ProgramProcessorRegister ( ApLocation->Thread; DEBUG (( DEBUG_INFO, -"Processor = %lu, Entry Index %lu, Type = %s!\n", +"Processor = %08lu, Index %08lu, Type = %s!\n", (UINT64)ThreadIndex, (UINT64)Index, mRegisterTypeStr[MIN ((REGISTER_TYPE)RegisterTableEntry->RegisterType, InvalidReg)] -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 2/2] UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless function.
Directly call the API instead of create function for it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Reviewed-by: Ruiyu Ni
---
.../PeiRegisterCpuFeaturesLib.c| 35 +-
1 file changed, 8 insertions(+), 27 deletions(-)
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 0bbcb50181..fdd0791c89 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
@@ -67,32 +67,6 @@ GetCpuFeaturesData (
return CpuInitData;
}
-/**
- Worker function to get MP PPI service pointer.
-
- @return PEI PPI service pointer.
-**/
-EFI_PEI_MP_SERVICES_PPI *
-GetMpPpi (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
-
- //
- // Get MP Services Protocol
- //
- Status = PeiServicesLocatePpi (
- ,
- 0,
- NULL,
- (VOID **)
- );
- ASSERT_EFI_ERROR (Status);
- return CpuMpPpi;
-}
-
/**
Worker function to return processor index.
@@ -139,7 +113,14 @@ GetProcessorInformation (
EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
EFI_STATUS Status;
- CpuMpPpi = GetMpPpi ();
+ Status = PeiServicesLocatePpi (
+ ,
+ 0,
+ NULL,
+ (VOID **)
+ );
+ ASSERT_EFI_ERROR (Status);
+
Status = CpuMpPpi->GetProcessorInfo (
GetPeiServicesTablePointer(),
CpuMpPpi,
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 0/2] Avoid AP calls PeiService
AP should not use PeiServices. The patch serial fix one issue related to this. This serial also include one patch used to clean up the code after this fix. Eric Dong (2): UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService. UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless function. .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 2 +- .../DxeRegisterCpuFeaturesLib.c| 6 ++- .../PeiRegisterCpuFeaturesLib.c| 56 ++ .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 6 ++- 4 files changed, 34 insertions(+), 36 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.
GetProcessorIndex function calls GetMpPpi to get the MP Ppi.
Ap will calls GetProcessorIndex function which final let AP
calls PeiService.
This patch avoid GetProcessorIndex call PeiService.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 2 +-
.../DxeRegisterCpuFeaturesLib.c | 6 --
.../PeiRegisterCpuFeaturesLib.c | 21 -
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h| 6 +-
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 624ddee055..6dcc73765b 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -409,7 +409,7 @@ CollectProcessorData (
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;
- ProcessorNumber = GetProcessorIndex ();
+ ProcessorNumber = GetProcessorIndex (CpuFeaturesData);
CpuInfo = >InitOrder[ProcessorNumber].CpuInfo;
//
// collect processor information
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
index 926698dc95..6f3e5bd2a8 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
@@ -66,11 +66,13 @@ GetMpProtocol (
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcessorIndex (
- VOID
+ IN CPU_FEATURES_DATA*CpuFeaturesData
)
{
EFI_STATUS Status;
@@ -225,7 +227,7 @@ CpuFeaturesInitialize (
CpuFeaturesData = GetCpuFeaturesData ();
- OldBspNumber = GetProcessorIndex();
+ OldBspNumber = GetProcessorIndex(CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber;
Status = gBS->CreateEvent (
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 0bb3dee8b6..0bbcb50181 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
@@ -96,20 +96,26 @@ GetMpPpi (
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcessorIndex (
- VOID
+ IN CPU_FEATURES_DATA*CpuFeaturesData
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
UINTN ProcessorIndex;
+ EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
- CpuMpPpi = GetMpPpi ();
+ ASSERT (CpuFeaturesData->CpuMpPpi != NULL);
+ if (CpuFeaturesData->CpuMpPpi == NULL) {
+return (UINTN) (-1);
+ }
+ CpuMpPpi = (EFI_PEI_MP_SERVICES_PPI *)CpuFeaturesData->CpuMpPpi;
- Status = CpuMpPpi->WhoAmI(GetPeiServicesTablePointer (), CpuMpPpi,
);
+ Status = CpuMpPpi->WhoAmI(NULL, CpuMpPpi, );
ASSERT_EFI_ERROR (Status);
return ProcessorIndex;
}
@@ -286,6 +292,9 @@ GetNumberOfProcessor (
{
EFI_STATUS Status;
EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+
+ CpuFeaturesData = GetCpuFeaturesData();
//
// Get MP Services Protocol
@@ -298,6 +307,8 @@ GetNumberOfProcessor (
);
ASSERT_EFI_ERROR (Status);
+ CpuFeaturesData->CpuMpPpi = CpuMpPpi;
+
//
// Get the number of CPUs
//
@@ -329,7 +340,7 @@ CpuFeaturesInitialize (
CpuFeaturesData = GetCpuFeaturesData ();
- OldBspNumber = GetProcessorIndex();
+ OldBspNumber = GetProcessorIndex (CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber;
//
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
index cf3da84837..19c3420511 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
@@ -85,6 +85,8 @@ typedef struct {
UINTNBspNumber;
PROGRAM_CPU_REGISTER_FLAGS CpuFlags;
+
+ VOID *CpuMpPpi;
} CPU_FEATURES_DATA;
#define CPU_FEATURE_ENTRY_FROM_LINK(a) \
@@ -108,11 +110,13 @@ GetCpuFeaturesData (
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcessorIndex (
- VOID
+ IN CPU_FEATURE
[edk2] [Patch 2/3] UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.
GetProcessorIndex function calls GetMpPpi to get the MP Ppi.
Ap will calls GetProcessorIndex function which final let AP
calls PeiService.
This patch avoid GetProcessorIndex call PeiService.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 2 +-
.../DxeRegisterCpuFeaturesLib.c | 6 --
.../PeiRegisterCpuFeaturesLib.c | 21 -
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h| 6 +-
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index a64326239f..81f4652a03 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -409,7 +409,7 @@ CollectProcessorData (
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;
- ProcessorNumber = GetProcessorIndex ();
+ ProcessorNumber = GetProcessorIndex (CpuFeaturesData);
CpuInfo = >InitOrder[ProcessorNumber].CpuInfo;
//
// collect processor information
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
index 926698dc95..6f3e5bd2a8 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
@@ -66,11 +66,13 @@ GetMpProtocol (
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcessorIndex (
- VOID
+ IN CPU_FEATURES_DATA*CpuFeaturesData
)
{
EFI_STATUS Status;
@@ -225,7 +227,7 @@ CpuFeaturesInitialize (
CpuFeaturesData = GetCpuFeaturesData ();
- OldBspNumber = GetProcessorIndex();
+ OldBspNumber = GetProcessorIndex(CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber;
Status = gBS->CreateEvent (
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 0bb3dee8b6..0bbcb50181 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
@@ -96,20 +96,26 @@ GetMpPpi (
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcessorIndex (
- VOID
+ IN CPU_FEATURES_DATA*CpuFeaturesData
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
UINTN ProcessorIndex;
+ EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
- CpuMpPpi = GetMpPpi ();
+ ASSERT (CpuFeaturesData->CpuMpPpi != NULL);
+ if (CpuFeaturesData->CpuMpPpi == NULL) {
+return (UINTN) (-1);
+ }
+ CpuMpPpi = (EFI_PEI_MP_SERVICES_PPI *)CpuFeaturesData->CpuMpPpi;
- Status = CpuMpPpi->WhoAmI(GetPeiServicesTablePointer (), CpuMpPpi,
);
+ Status = CpuMpPpi->WhoAmI(NULL, CpuMpPpi, );
ASSERT_EFI_ERROR (Status);
return ProcessorIndex;
}
@@ -286,6 +292,9 @@ GetNumberOfProcessor (
{
EFI_STATUS Status;
EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+
+ CpuFeaturesData = GetCpuFeaturesData();
//
// Get MP Services Protocol
@@ -298,6 +307,8 @@ GetNumberOfProcessor (
);
ASSERT_EFI_ERROR (Status);
+ CpuFeaturesData->CpuMpPpi = CpuMpPpi;
+
//
// Get the number of CPUs
//
@@ -329,7 +340,7 @@ CpuFeaturesInitialize (
CpuFeaturesData = GetCpuFeaturesData ();
- OldBspNumber = GetProcessorIndex();
+ OldBspNumber = GetProcessorIndex (CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber;
//
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
index cf3da84837..19c3420511 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
@@ -85,6 +85,8 @@ typedef struct {
UINTNBspNumber;
PROGRAM_CPU_REGISTER_FLAGS CpuFlags;
+
+ VOID *CpuMpPpi;
} CPU_FEATURES_DATA;
#define CPU_FEATURE_ENTRY_FROM_LINK(a) \
@@ -108,11 +110,13 @@ GetCpuFeaturesData (
/**
Worker function to return processor index.
+ @param CpuFeaturesDataCpu Feature Data structure.
+
@return The processor index.
**/
UINTN
GetProcessorIndex (
- VOID
+ IN CPU_FEATURE
[edk2] [Patch 1/3] UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.
In AcquireSpinLock function, it calls GetPerformanceCounter which
final calls PeiService service. This patch avoid to call
AcquireSpinLock function.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 624ddee055..a64326239f 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -832,7 +832,12 @@ ProgramProcessorRegister (
RegisterTableEntry = [Index];
DEBUG_CODE_BEGIN ();
- AcquireSpinLock (>ConsoleLogLock);
+ //
+ // Wait for the AP to release the MSR spin lock.
+ //
+ while (!AcquireSpinLockOrFail (>ConsoleLogLock)) {
+CpuPause ();
+ }
ThreadIndex = ApLocation->Package * CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount +
ApLocation->Core * CpuStatus->MaxThreadCount +
ApLocation->Thread;
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 0/3] Avoid AP calls PeiService
AP should not use PeiServices. This patches fixed two issues which both caused by AP try to call PeiServices. Eric Dong (3): UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService. UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService. UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless function. .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 9 +++- .../DxeRegisterCpuFeaturesLib.c| 6 ++- .../PeiRegisterCpuFeaturesLib.c| 56 ++ .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 6 ++- 4 files changed, 40 insertions(+), 37 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 3/3] UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless function.
Directly call the API instead of create function for it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../PeiRegisterCpuFeaturesLib.c| 35 +-
1 file changed, 8 insertions(+), 27 deletions(-)
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 0bbcb50181..fdd0791c89 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
@@ -67,32 +67,6 @@ GetCpuFeaturesData (
return CpuInitData;
}
-/**
- Worker function to get MP PPI service pointer.
-
- @return PEI PPI service pointer.
-**/
-EFI_PEI_MP_SERVICES_PPI *
-GetMpPpi (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
-
- //
- // Get MP Services Protocol
- //
- Status = PeiServicesLocatePpi (
- ,
- 0,
- NULL,
- (VOID **)
- );
- ASSERT_EFI_ERROR (Status);
- return CpuMpPpi;
-}
-
/**
Worker function to return processor index.
@@ -139,7 +113,14 @@ GetProcessorInformation (
EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
EFI_STATUS Status;
- CpuMpPpi = GetMpPpi ();
+ Status = PeiServicesLocatePpi (
+ ,
+ 0,
+ NULL,
+ (VOID **)
+ );
+ ASSERT_EFI_ERROR (Status);
+
Status = CpuMpPpi->GetProcessorInfo (
GetPeiServicesTablePointer(),
CpuMpPpi,
--
2.15.0.windows.1
___
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edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 0/2] Update CPUID related definition.
Update CPUID definition to follow SDM 2018'11 version, changes Include: 1. Add new fields to the existed data structure, impact CPUIDs include: 1. CPUID_THERMAL_POWER_MANAGEMENT 0x06 CPUID_THERMAL_POWER_MANAGEMENT_EAX 2. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX 3. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX 4. CPUID_EXTENDED_STATE 0x0D CPUID_EXTENDED_STATE_MAIN_LEAF_EAX CPUID_EXTENDED_STATE_SUB_LEAF_ECX 5. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX 6. CPUID_INTEL_SGX0x12 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX 2. Add new data structures which not existed before, impact CPUID includes: 1. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX 3. Remove fields which defined before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF0x01 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX 4. Add new sub leaf which not existed before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF0x03 5. Add new CPUIDs which not exist before, new CPUIDs include: 1. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 2. CPUID_V2_EXTENDED_TOPOLOGY_ENUMERATION 0x1F Also update Cpuid application in UefiCpuPkg/Application folder. Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Eric Dong (2): UefiCpuPkg/Cpuid.h: Sync CPUID definition to latest SDM. UefiCpuPkg/Cpuid: Add code to support new definition. UefiCpuPkg/Application/Cpuid/Cpuid.c | 147 - UefiCpuPkg/Include/Register/Cpuid.h | 620 +-- 2 files changed, 739 insertions(+), 28 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 1/2] UefiCpuPkg/Cpuid.h: Sync CPUID definition to latest SDM.
Update CPUID definition to follow SDM 2018'11 version, changes Include:
1. Add new fields to the existed data structure, impact CPUIDs include:
1. CPUID_THERMAL_POWER_MANAGEMENT 0x06
CPUID_THERMAL_POWER_MANAGEMENT_EAX
2. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS0x07
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
3. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
4. CPUID_EXTENDED_STATE 0x0D
CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
CPUID_EXTENDED_STATE_SUB_LEAF_ECX
5. CPUID_INTEL_RDT_ALLOCATION 0x10
CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
6. CPUID_INTEL_SGX0x12
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
2. Add new data structures which not existed before, impact CPUID includes:
1. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS0x07
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX
3. Remove fields which defined before, impact CPUID includes:
1. CPUID_INTEL_RDT_ALLOCATION 0x10
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF0x01
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
4. Add new sub leaf which not existed before, impact CPUID includes:
1. CPUID_INTEL_RDT_ALLOCATION 0x10
CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF0x03
5. Add new CPUIDs which not exist before, new CPUIDs include:
1. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
2. CPUID_V2_EXTENDED_TOPOLOGY_ENUMERATION 0x1F
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Cpuid.h | 620 ++--
1 file changed, 597 insertions(+), 23 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Cpuid.h
b/UefiCpuPkg/Include/Register/Cpuid.h
index 5eb9650553..81ae5afd17 100644
--- a/UefiCpuPkg/Include/Register/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Cpuid.h
@@ -6,7 +6,7 @@
If a register returned is a single 32-bit value, then a data structure is
not provided for that register.
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available
under
the terms and conditions of the BSD License which accompanies this
distribution.
The full text of the license may be found at
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
- September 2016, CPUID instruction.
+ November 2018, CPUID instruction.
**/
@@ -707,6 +707,8 @@ typedef union {
0xEC Cache3rd-level cache: 24MByte, 24-way
set associative, 64 byte line size
0xF0 Prefetch 64-Byte prefetching
0xF1 Prefetch 128-Byte prefetching
+ 0xFE General CPUID leaf 2 does not report TLB
descriptor information; use CPUID
+leaf 18H to query TLB and other
address translation parameters.
0xFF General CPUID leaf 2 does not report cache
descriptor information,
use CPUID leaf 4 to query cache
parameters
@@ -1182,7 +1184,33 @@ typedef union {
/// IA32_THREAD_STALL MSRs are supported if set.
///
UINT32 HDC:1;
-UINT32 Reserved3:18;
+///
+/// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
+///
+UINT32 TurboBoostMaxTechnology30:1;
+///
+/// [Bit 15] HWP Capabilities.
+/// Highest Performance change is supported if set.
+///
+UINT32 HWPCapabilities:1;
+///
+/// [Bit 16] HWP PECI override is supported if set.
+///
+UINT32 HWPPECIOverride:1;
+///
+/// [Bit 17] Flexible HWP is supported if set.
+///
+UINT32 FlexibleHWP:1;
+///
+/// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if
set.
+///
+UINT32 FastAccessMode:1;
+UINT32 Reserved4:1;
+///
+/// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if
set.
+///
+UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;
+UINT32 Reserved5:11;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -1369,7 +1397,14 @@ typedef union {
/// Allocation capability if 1.
///
UINT32 RDT_A:1;
-UINT32 Reserved2:2;
+///
+/// [Bit 16] AVX512F.
+///
+UINT32 AVX512F:1;
+///
+/// [Bit 17] AVX512DQ.
+///
+UINT32 AVX512DQ:1;
///
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction
[edk2] [Patch 2/2] UefiCpuPkg/Cpuid: Add code to support new definition.
Add code to support new definitions added for SDM 2018'11
version.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Application/Cpuid/Cpuid.c | 147 +--
1 file changed, 142 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c
b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index b44266e538..da87f0aef4 100644
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -153,6 +153,7 @@ CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[]
= {
{ 0xEC , "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64
byte line size" },
{ 0xF0 , "Prefetch" , "64-Byte prefetching" },
{ 0xF1 , "Prefetch" , "128-Byte prefetching" },
+ { 0xFE , "General" , "CPUID leaf 2 does not report TLB descriptor
information; use CPUID leaf 18H to query TLB and other address translation
parameters." },
{ 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor
information, use CPUID leaf 4 to query cache parameters" }
};
@@ -557,6 +558,12 @@ CpuidThermalPowerManagement (
PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);
PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);
PRINT_BIT_FIELD (Eax, HDC);
+ PRINT_BIT_FIELD (Eax, TurboBoostMaxTechnology30);
+ PRINT_BIT_FIELD (Eax, HWPCapabilities);
+ PRINT_BIT_FIELD (Eax, HWPPECIOverride);
+ PRINT_BIT_FIELD (Eax, FlexibleHWP);
+ PRINT_BIT_FIELD (Eax, FastAccessMode);
+ PRINT_BIT_FIELD (Eax, IgnoringIdleLogicalProcessorHWPRequest);
PRINT_BIT_FIELD (Ebx, InterruptThresholds);
PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);
PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);
@@ -574,6 +581,8 @@ CpuidStructuredExtendedFeatureFlags (
UINT32 Eax;
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;
+
UINT32 SubLeaf;
if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {
@@ -589,11 +598,11 @@ CpuidStructuredExtendedFeatureFlags (
AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
SubLeaf,
- NULL, , , NULL
+ NULL, , ,
);
-if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0) {
+if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) {
Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf
%08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);
- Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32,
Ecx.Uint32, 0);
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32,
Ecx.Uint32, Edx.Uint32);
PRINT_BIT_FIELD (Ebx, FSGSBASE);
PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);
PRINT_BIT_FIELD (Ebx, SGX);
@@ -610,20 +619,39 @@ CpuidStructuredExtendedFeatureFlags (
PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);
PRINT_BIT_FIELD (Ebx, MPX);
PRINT_BIT_FIELD (Ebx, RDT_A);
+ PRINT_BIT_FIELD (Ebx, AVX512F);
+ PRINT_BIT_FIELD (Ebx, AVX512DQ);
PRINT_BIT_FIELD (Ebx, RDSEED);
PRINT_BIT_FIELD (Ebx, ADX);
PRINT_BIT_FIELD (Ebx, SMAP);
+ PRINT_BIT_FIELD (Ebx, AVX512_IFMA);
PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);
PRINT_BIT_FIELD (Ebx, CLWB);
PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);
+ PRINT_BIT_FIELD (Ebx, AVX512PF);
+ PRINT_BIT_FIELD (Ebx, AVX512ER);
+ PRINT_BIT_FIELD (Ebx, AVX512CD);
PRINT_BIT_FIELD (Ebx, SHA);
+ PRINT_BIT_FIELD (Ebx, AVX512BW);
+ PRINT_BIT_FIELD (Ebx, AVX512VL);
+
PRINT_BIT_FIELD (Ecx, PREFETCHWT1);
+ PRINT_BIT_FIELD (Ecx, AVX512_VBMI);
PRINT_BIT_FIELD (Ecx, UMIP);
PRINT_BIT_FIELD (Ecx, PKU);
PRINT_BIT_FIELD (Ecx, OSPKE);
+ PRINT_BIT_FIELD (Ecx, AVX512_VPOPCNTDQ);
PRINT_BIT_FIELD (Ecx, MAWAU);
PRINT_BIT_FIELD (Ecx, RDPID);
PRINT_BIT_FIELD (Ecx, SGX_LC);
+
+ PRINT_BIT_FIELD (Edx, AVX512_4VNNIW);
+ PRINT_BIT_FIELD (Edx, AVX512_4FMAPS);
+ PRINT_BIT_FIELD (Edx, EnumeratesSupportForIBRSAndIBPB);
+ PRINT_BIT_FIELD (Edx, EnumeratesSupportForSTIBP);
+ PRINT_BIT_FIELD (Edx, EnumeratesSupportForL1D_FLUSH);
+ PRINT_BIT_FIELD (Edx, EnumeratesSupportForCapability);
+ PRINT_BIT_FIELD (Edx, EnumeratesSupportForSSBD);
}
}
}
@@ -681,6 +709,7 @@ CpuidArchitecturalPerformanceMonitoring (
PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);
PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);
PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);
+ PRINT_BIT_FIELD (Edx, AnyThreadDeprecation);
}
/**
@@ -747,6 +776,7 @@ CpuidExtendedStateSubLeaf (
PRINT_BIT_FIELD (Eax, XSAVES);
PRINT_VALUE (Ebx,
[edk2] [Patch] UefiCpuPkg/RegisterCpuFeaturesLib: Adjust Order.
V2 changes:
V1 change has regression which caused by change feature order.
V2 changes logic to detect dependence not only for the
neighborhood features. It need to check all features in the list.
V1 Changes:
In current code logic, only adjust feature position if current
CPU feature position not follow the request order. Just like
Feature A need to be executed before feature B, but current
feature A registers after feature B. So code will adjust the
position for feature A, move it to just before feature B. If
the position already met the requirement, code will not adjust
the position.
This logic has issue when met all below cases:
1. feature A has core or package level dependence with feature B.
2. feature A is register before feature B.
3. Also exist other features exist between feature A and B.
Root cause is driver ignores the dependence for this case, so
threads may execute not follow the dependence order.
Fix this issue by change code logic to adjust feature position
for CPU features which has dependence relationship.
Cc: Laszlo Ersek
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 71
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 16 +++
.../RegisterCpuFeaturesLib.c | 122 +
3 files changed, 189 insertions(+), 20 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 4bed0ce3a4..69e2c04daf 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -534,6 +534,28 @@ DumpRegisterTableOnProcessor (
}
}
+/**
+ Get the biggest dependence type.
+ PackageDepType > CoreDepType > ThreadDepType > NoneDepType.
+
+ @param[in] BeforeDep Before dependence type.
+ @param[in] AfterDepAfter dependence type.
+ @param[in] NoneNeibBeforeDep Before dependence type for not neighborhood
features.
+ @param[in] NoneNeibAfterDepAfter dependence type for not neighborhood
features.
+
+ @retval Return the biggest dependence type.
+**/
+CPU_FEATURE_DEPENDENCE_TYPE
+BiggestDep (
+ IN CPU_FEATURE_DEPENDENCE_TYPE BeforeDep,
+ IN CPU_FEATURE_DEPENDENCE_TYPE AfterDep,
+ IN CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep,
+ IN CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep
+ )
+{
+ return MAX(MAX (MAX(BeforeDep, AfterDep), NoneNeibBeforeDep),
NoneNeibAfterDep);
+}
+
/**
Analysis register CPU features on each processor and save CPU setting in CPU
register table.
@@ -558,6 +580,8 @@ AnalysisProcessorFeatures (
BOOLEAN Success;
CPU_FEATURE_DEPENDENCE_TYPE BeforeDep;
CPU_FEATURE_DEPENDENCE_TYPE AfterDep;
+ CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep;
+ CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep;
CpuFeaturesData = GetCpuFeaturesData ();
CpuFeaturesData->CapabilityPcd = AllocatePool (CpuFeaturesData->BitMaskSize);
@@ -634,14 +658,9 @@ AnalysisProcessorFeatures (
//
CpuInfo = >InitOrder[ProcessorNumber].CpuInfo;
Entry = GetFirstNode (>OrderList);
-NextEntry = Entry->ForwardLink;
while (!IsNull (>OrderList, Entry)) {
CpuFeatureInOrder = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
- if (!IsNull (>OrderList, NextEntry)) {
-NextCpuFeatureInOrder = CPU_FEATURE_ENTRY_FROM_LINK (NextEntry);
- } else {
-NextCpuFeatureInOrder = NULL;
- }
+
Success = FALSE;
if (IsBitMaskMatch (CpuFeatureInOrder->FeatureMask,
CpuFeaturesData->SettingPcd)) {
Status = CpuFeatureInOrder->InitializeFunc (ProcessorNumber, CpuInfo,
CpuFeatureInOrder->ConfigData, TRUE);
@@ -674,31 +693,43 @@ AnalysisProcessorFeatures (
}
if (Success) {
-//
-// If feature has dependence with the next feature (ONLY care
core/package dependency).
-// and feature initialize succeed, add sync semaphere here.
-//
-if (NextCpuFeatureInOrder != NULL) {
+NextEntry = Entry->ForwardLink;
+if (!IsNull (>OrderList, NextEntry)) {
+ NextCpuFeatureInOrder = CPU_FEATURE_ENTRY_FROM_LINK (NextEntry);
+
+ //
+ // If feature has dependence with the next feature (ONLY care
core/package dependency).
+ // and feature initialize succeed, add sync semaphere here.
+ //
BeforeDep = DetectFeatureScope (CpuFeatureInOrder, TRUE,
NextCpuFeatureInOrder->FeatureMask);
AfterDep = DetectFeatureScope (NextCpuFeatureInOrder, FALSE,
CpuFeatureInOrder->FeatureMask);
+ //
+ // Check whether next feature has After type dependence with not
neighborhood CPU
+ // Features in former C
[edk2] [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Separate semaphore container.
In current implementation, core level semaphore use same container
with package level semaphore. This design will let the core level
semaphore not works as expected in below case:
1. Feature A has CPU_FEATURE_CORE_BEFORE dependence with Feature B.
2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependence with Feature B.
in this case an core level semaphore will be add between A and B, and
an package level semaphore will be add between B and C.
For a CPU has one package, two cores and 4 threads. Execute like below:
Thread 1 Thread 2. Thread 4
ReleaseSemaph(1,2) -|
WaitForSemaph(1(2)) -|<---These two are Core Semaph
ReleaseSemaph(1,2) -|
WaitForSemaph(2) -| <--- Core Semaph
ReleaseSemaph (1,2,3,4) -|
WaitForSemaph (1(4))-| < Package Semaph
ReleaseSemaph(3,4)
WaitForSemaph(4(2)) <- Core Semaph
In above case, for thread 4, when it executes a core semaphore, i will
found WaitForSemaph(4(2)) is met because Thread 1 has execute a package
semaphore and ReleaseSemaph(4) for it before. This is not an expect
behavior. Thread 4 should wait for thread 3 to do this.
Fix this issue by separate the semaphore container for core level and
package level.
Cc: Laszlo Ersek
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index a45e2dd3d7..65461485a4 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -41,9 +41,10 @@ typedef struct {
// Flags used when program the register.
//
typedef struct {
- volatile UINTN ConsoleLogLock; // Spinlock used to control
console.
- volatile UINTN MemoryMappedLock; // Spinlock used to program
mmio
- volatile UINT32 *SemaphoreCount; // Semaphore used to program
semaphore.
+ volatile UINTN ConsoleLogLock; // Spinlock used to
control console.
+ volatile UINTN MemoryMappedLock;// Spinlock used to
program mmio
+ volatile UINT32 *CoreSemaphoreCount; // Semaphore used to
program semaphore.
+ volatile UINT32 *PackageSemaphoreCount; // Semaphore used to
program semaphore.
} PROGRAM_CPU_REGISTER_FLAGS;
//
@@ -348,11 +349,12 @@ ProgramProcessorRegister (
ASSERT (
(ApLocation != NULL) &&
(CpuStatus->ValidCoreCountPerPackage != 0) &&
-(CpuFlags->SemaphoreCount) != NULL
+(CpuFlags->CoreSemaphoreCount != NULL) &&
+(CpuFlags->PackageSemaphoreCount != NULL)
);
- SemaphorePtr = CpuFlags->SemaphoreCount;
switch (RegisterTableEntry->Value) {
case CoreDepType:
+SemaphorePtr = CpuFlags->CoreSemaphoreCount;
//
// Get Offset info for the first thread in the core which current
thread belongs to.
//
@@ -373,6 +375,7 @@ ProgramProcessorRegister (
break;
case PackageDepType:
+SemaphorePtr = CpuFlags->PackageSemaphoreCount;
ValidCoreCountPerPackage = (UINT32
*)(UINTN)CpuStatus->ValidCoreCountPerPackage;
//
// Get Offset info for the first thread in the package which current
thread belongs to.
@@ -1037,10 +1040,14 @@ GetAcpiCpuData (
ASSERT (mAcpiCpuData.ApLocation != 0);
}
if (CpuStatus->PackageCount != 0) {
-mCpuFlags.SemaphoreCount = AllocateZeroPool (
+mCpuFlags.CoreSemaphoreCount = AllocateZeroPool (
sizeof (UINT32) * CpuStatus->PackageCount *
CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount);
-ASSERT (mCpuFlags.SemaphoreCount != NULL);
+ASSERT (mCpuFlags.CoreSemaphoreCount != NULL);
+mCpuFlags.PackageSemaphoreCount = AllocateZeroPool (
+ sizeof (UINT32) * CpuStatus->PackageCount *
+ CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount);
+ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
}
InitializeSpinLock((SPIN_LOCK*) );
InitializeSpinLock((SPIN_LOCK*) );
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Separate semaphore container.
In current implementation, core level semaphore use same container
with package level semaphore. This design will let the core level
semaphore not works as expected in below case:
1. Feature A has CPU_FEATURE_CORE_BEFORE dependence with Feature B.
2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependence with Feature B.
in this case an core level semaphore will be add between A and B, and
an package level semaphore will be add between B and C.
For a CPU has one package, two cores and 4 threads. Execute like below:
Thread 1 Thread 2. Thread 4
ReleaseSemaph(1,2) -|
WaitForSemaph(1(2)) -|<---These two are Core Semaph
ReleaseSemaph(1,2) -|
WaitForSemaph(2) -| <--- Core Semaph
ReleaseSemaph (1,2,3,4) -|
WaitForSemaph (1(4))-| < Package Semaph
ReleaseSemaph(3,4)
WaitForSemaph(4(2)) <- Core Semaph
In above case, for thread 4, when it executes a core semaphore, i will
found WaitForSemaph(4(2)) is met because Thread 1 has execute a package
semaphore and ReleaseSemaph(4) for it before. This is not an expect
behavior. Thread 4 should wait for thread 3 to do this.
Fix this issue by separate the semaphore container for core level and
package level.
Cc: Laszlo Ersek
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 9 ++---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 7 ---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 7f208dbe6a..4bed0ce3a4 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -269,8 +269,10 @@ CpuInitDataInitialize (
DEBUG ((DEBUG_INFO, "Package: %d, Valid Core : %d\n", Index,
ValidCoreCountPerPackage[Index]));
}
- CpuFeaturesData->CpuFlags.SemaphoreCount = AllocateZeroPool (sizeof (UINT32)
* CpuStatus->PackageCount * CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount);
- ASSERT (CpuFeaturesData->CpuFlags.SemaphoreCount != NULL);
+ CpuFeaturesData->CpuFlags.CoreSemaphoreCount = AllocateZeroPool (sizeof
(UINT32) * CpuStatus->PackageCount * CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount);
+ ASSERT (CpuFeaturesData->CpuFlags.CoreSemaphoreCount != NULL);
+ CpuFeaturesData->CpuFlags.PackageSemaphoreCount = AllocateZeroPool (sizeof
(UINT32) * CpuStatus->PackageCount * CpuStatus->MaxCoreCount *
CpuStatus->MaxThreadCount);
+ ASSERT (CpuFeaturesData->CpuFlags.PackageSemaphoreCount != NULL);
//
// Get support and configuration PCDs
@@ -933,9 +935,9 @@ ProgramProcessorRegister (
// V(0...n) V(0...n) ... V(0...n)
// n * P(0) n * P(1) ... n * P(n)
//
- SemaphorePtr = CpuFlags->SemaphoreCount;
switch (RegisterTableEntry->Value) {
case CoreDepType:
+SemaphorePtr = CpuFlags->CoreSemaphoreCount;
//
// Get Offset info for the first thread in the core which current
thread belongs to.
//
@@ -956,6 +958,7 @@ ProgramProcessorRegister (
break;
case PackageDepType:
+SemaphorePtr = CpuFlags->PackageSemaphoreCount;
ValidCoreCountPerPackage = (UINT32
*)(UINTN)CpuStatus->ValidCoreCountPerPackage;
//
// Get Offset info for the first thread in the package which current
thread belongs to.
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
index b4c8ab777e..4898a80827 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
@@ -60,9 +60,10 @@ typedef struct {
// Flags used when program the register.
//
typedef struct {
- volatile UINTN ConsoleLogLock; // Spinlock used to control
console.
- volatile UINTN MemoryMappedLock; // Spinlock used to program
mmio
- volatile UINT32 *SemaphoreCount; // Semaphore used to program
semaphore.
+ volatile UINTN ConsoleLogLock; // Spinlock used to
control console.
+ volatile UINTN MemoryMappedLock;// Spinlock used to
program mmio
+ volatile UINT32 *CoreSemaphoreCount; // Semaphore containers
used to program Core semaphore.
+ volatile UINT32 *PackageSemaphoreCount; // Semaphore containers
used to program Package semaphore.
} PROGRAM_CPU_REGISTER_FLAGS;
typedef struct {
--
2.15.0.windows.1
__
[edk2] [Patch 0/2] Separate semaphore container.
In current implementation, core level semaphore use same container with package level semaphore. This design will let the core level semaphore not works as expected in below case: 1. Feature A has CPU_FEATURE_CORE_BEFORE dependence with Feature B. 2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependence with Feature B. in this case an core level semaphore will be add between A and B, and an package level semaphore will be add between B and C. For a CPU has one package, two cores and 4 threads. Execute like below: Thread 1 Thread 2. Thread 4 ReleaseSemaph(1,2) -| WaitForSemaph(1(2)) -|<---These two are Core Semaph ReleaseSemaph(1,2) -| WaitForSemaph(2) -| <--- Core Semaph ReleaseSemaph (1,2,3,4) -| WaitForSemaph (1(4))-| < Package Semaph ReleaseSemaph(3,4) WaitForSemaph(4(2)) <- Core Semaph In above case, for thread 4, when it executes a core semaphore, i will found WaitForSemaph(4(2)) is met because Thread 1 has execute a package semaphore and ReleaseSemaph(4) for it before. This is not an expect behavior. Thread 4 should wait for thread 3 to do this. Fix this issue by separate the semaphore container for core level and package level. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Eric Dong (2): UefiCpuPkg/RegisterCpuFeaturesLib: Separate semaphore container. UefiCpuPkg/PiSmmCpuDxeSmm: Separate semaphore container. .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 9 ++--- .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h| 7 --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 21 ++--- 3 files changed, 24 insertions(+), 13 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch] UefiCpuPkg/RegisterCpuFeaturesLib: Adjust Order.
In current code logic, only adjust feature position if current CPU
feature position not follow the request order. Just like Feature A
need to be executed before feature B, but current feature A registers
after feature B. So code will adjust the position for feature A, move
it to just before feature B. If the position already met the
requirement, code will not adjust the position.
This logic has issue when met all below cases:
1. feature A has core or package level dependence with feature B.
2. feature A is register before feature B.
3. Also exist other features exist between feature A and B.
Root cause is driver ignores the dependence for this case, so threads
may execute not follow the dependence order.
Fix this issue by change code logic to adjust feature position for
CPU features which has dependence relationship.
Change-Id: I86171cb1dbf44a2f6fd8d5d2209cafee9451b866
Cc: Laszlo Ersek
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib.c | 62 --
1 file changed, 58 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 394695baf2..31a44b6bad 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -271,6 +271,10 @@ AdjustEntry (
PreviousEntry = GetNextNode (FeatureList, FindEntry);
}
+ if (PreviousEntry == CurrentEntry) {
+return;
+ }
+
CurrentFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry);
RemoveEntryList (CurrentEntry);
@@ -389,6 +393,56 @@ InsertToAfterEntry (
return Swapped;
}
+/**
+ Checks and adjusts current CPU features per dependency relationship.
+
+ @param[in] FeatureListPointer to CPU feature list
+ @param[in] CurrentEntry Pointer to current checked CPU feature
+ @param[in] FeatureMaskThe feature bit mask.
+ @param[in] Before The dependence is before type or after type.
+
+ @retval return Swapped info.
+**/
+BOOLEAN
+AdjustToAllEntry (
+ IN LIST_ENTRY *FeatureList,
+ IN LIST_ENTRY *CurrentEntry,
+ IN UINT8 *FeatureMask,
+ IN BOOLEAN Before
+ )
+{
+ LIST_ENTRY *CheckEntry;
+ CPU_FEATURES_ENTRY *CheckFeature;
+ BOOLEANSwapped;
+ LIST_ENTRY *NextEntry;
+
+ Swapped = FALSE;
+ //
+ // Record neighbor for later compre.
+ //
+ NextEntry = CurrentEntry->ForwardLink;
+ //
+ // Check all features in current list.
+ //
+ CheckEntry = GetFirstNode (FeatureList);
+ while (!IsNull (FeatureList, CheckEntry)) {
+CheckFeature = CPU_FEATURE_ENTRY_FROM_LINK (CheckEntry);
+if (IsBitMaskMatchCheck (CheckFeature->FeatureMask, FeatureMask)) {
+ AdjustEntry (FeatureList, CheckEntry, CurrentEntry, Before);
+ //
+ // Base on former record neighbor to detect whether current entry
+ // adjust the position.
+ // Current Entry position maybe changed in AdjustEntry function.
+ //
+ Swapped = (NextEntry != CurrentEntry->ForwardLink);
+ break;
+}
+CheckEntry = CheckEntry->ForwardLink;
+ }
+
+ return Swapped;
+}
+
/**
Checks and adjusts CPU features order per dependency relationship.
@@ -479,28 +533,28 @@ CheckCpuFeaturesDependency (
}
if (CpuFeature->CoreBeforeFeatureBitMask != NULL) {
- Swapped = InsertToBeforeEntry (FeatureList, CurrentEntry,
CpuFeature->CoreBeforeFeatureBitMask);
+ Swapped = AdjustToAllEntry (FeatureList, CurrentEntry,
CpuFeature->CoreBeforeFeatureBitMask, TRUE);
if (Swapped) {
continue;
}
}
if (CpuFeature->CoreAfterFeatureBitMask != NULL) {
- Swapped = InsertToAfterEntry (FeatureList, CurrentEntry,
CpuFeature->CoreAfterFeatureBitMask);
+ Swapped = AdjustToAllEntry (FeatureList, CurrentEntry,
CpuFeature->CoreAfterFeatureBitMask, FALSE);
if (Swapped) {
continue;
}
}
if (CpuFeature->PackageBeforeFeatureBitMask != NULL) {
- Swapped = InsertToBeforeEntry (FeatureList, CurrentEntry,
CpuFeature->PackageBeforeFeatureBitMask);
+ Swapped = AdjustToAllEntry (FeatureList, CurrentEntry,
CpuFeature->PackageBeforeFeatureBitMask, TRUE);
if (Swapped) {
continue;
}
}
if (CpuFeature->PackageAfterFeatureBitMask != NULL) {
- Swapped = InsertToAfterEntry (FeatureList, CurrentEntry,
CpuFeature->PackageAfterFeatureBitMask);
+ Swapped = AdjustToAllEntry (FeatureList, CurrentEntry,
CpuFeature->PackageAfterFeatureBitMask, FALSE);
if (Swapped) {
continue;
}
--
2.15.0.windows.1
___
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[edk2] [Patch] UefiCpuPkg/MpInitLib: Rollback old change 2a5997f8.
In some special cases, after BSP send Init-sipi-sipi signal
AP need more time to start the Ap procedure. In this case
BSP may think AP has finish its task but truly AP not begin
yet.
Rollback former change to keep the status which only used
when AP truly finished task.
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 10 ++
UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 +
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 85ca4a2946..7f4d6e60bd 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -696,7 +696,7 @@ ApWakeupFunction (
}
}
}
-SetApState (>CpuData[ProcessorNumber], CpuStateIdle);
+SetApState (>CpuData[ProcessorNumber], CpuStateFinished);
}
}
@@ -1370,10 +1370,11 @@ CheckThisAP (
//
// If the AP finishes for StartupThisAP(), return EFI_SUCCESS.
//
- if (GetApState(CpuData) == CpuStateIdle) {
+ if (GetApState(CpuData) == CpuStateFinished) {
if (CpuData->Finished != NULL) {
*(CpuData->Finished) = TRUE;
}
+SetApState (CpuData, CpuStateIdle);
return EFI_SUCCESS;
} else {
//
@@ -1434,9 +1435,10 @@ CheckAllAPs (
// Only BSP and corresponding AP access this unit of CPU Data. This means
the AP will not modify the
// value of state after setting the it to CpuStateIdle, so BSP can safely
make use of its value.
//
-if (GetApState(CpuData) == CpuStateIdle) {
+if (GetApState(CpuData) == CpuStateFinished) {
CpuMpData->RunningCount --;
CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE;
+ SetApState(CpuData, CpuStateIdle);
//
// If in Single Thread mode, then search for the next waiting AP for
execution.
@@ -1937,7 +1939,7 @@ SwitchBSPWorker (
//
// Wait for old BSP finished AP task
//
- while (GetApState (>CpuData[CallerNumber]) != CpuStateIdle) {
+ while (GetApState (>CpuData[CallerNumber]) != CpuStateFinished) {
CpuPause ();
}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h
b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index 773db76b61..5f6986c240 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -89,6 +89,7 @@ typedef enum {
CpuStateIdle,
CpuStateReady,
CpuStateBusy,
+ CpuStateFinished,
CpuStateDisabled
} CPU_STATE;
--
2.15.0.windows.1
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[edk2] [Patch] UefiCpuPkg/RegisterCpuFeaturesLib: Fix build failure.
Build UefiCpuPkg with below configuration: Architecture(s) = IA32 Build target = NOOPT Toolchain= VS2015x86 Below error info shows up: DxeRegisterCpuFeaturesLib.lib(CpuFeaturesInitialize.obj) : error LNK2001: unresolved external symbol __allmul Valid mDependTypeStr type only have 5 items, use UINT32 type cast to fix this error. Cc: Dandan Bi Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index bc372a338f..8588800e4a 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -517,7 +517,7 @@ DumpRegisterTableOnProcessor ( DebugPrintErrorLevel, "Processor: %d: Semaphore: Scope Value: %s\r\n", ProcessorNumber, -mDependTypeStr[MIN (RegisterTableEntry->Value, InvalidDepType)] +mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)] )); break; -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch] UefiCpuPkg/RegisterCpuFeaturesLib: Fix GCC build failure.
Cc: Liming Gao
Cc: Dandan Bi
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h| 2 +-
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
index b5fe8fbce1..b4c8ab777e 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
@@ -203,7 +203,7 @@ CPU_FEATURE_DEPENDENCE_TYPE
DetectFeatureScope (
IN CPU_FEATURES_ENTRY *CpuFeature,
IN BOOLEANBefore,
- IN CHAR8 *NextCpuFeatureMask
+ IN UINT8 *NextCpuFeatureMask
);
/**
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 9a66bc49ff..394695baf2 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -125,7 +125,7 @@ CPU_FEATURE_DEPENDENCE_TYPE
DetectFeatureScope (
IN CPU_FEATURES_ENTRY *CpuFeature,
IN BOOLEANBefore,
- IN CHAR8 *NextCpuFeatureMask
+ IN UINT8 *NextCpuFeatureMask
)
{
//
--
2.16.2.windows.1
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[edk2] [Patch] SecurityPkg/Include/Library/TcgStorageOpalLib.h: Update Pyrite spec revision.
Pyrite 2.0 spec has been published, update the spec link info for this file. Cc: Hao Wu Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- SecurityPkg/Include/Library/TcgStorageOpalLib.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/SecurityPkg/Include/Library/TcgStorageOpalLib.h b/SecurityPkg/Include/Library/TcgStorageOpalLib.h index 33f8fee183..ef882d5301 100644 --- a/SecurityPkg/Include/Library/TcgStorageOpalLib.h +++ b/SecurityPkg/Include/Library/TcgStorageOpalLib.h @@ -4,8 +4,8 @@ (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00, https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/ - Storage Work Group Storage Security Subsystem Class: Pyrite, Version 1.00 Final, Revision 1.00, - https://trustedcomputinggroup.org/tcg-storage-security-subsystem-class-pyrite/ + Storage Work Group Storage Security Subsystem Class: Pyrite, Specification Version 2.00, Revision 1.00, + https://trustedcomputinggroup.org/resource/tcg-storage-security-subsystem-class-pyrite/ Storage Work Group Storage Security Subsystem Class: Opal, Version 2.01 Final, Revision 1.00, https://trustedcomputinggroup.org/storage-work-group-storage-security-subsystem-class-opal/ -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch] UefiCpuPkg/RegisterCpuFeaturesLib: Support combo CPU feature style.
Current code assume only one dependence (before or after) for one
feature. Enhance code logic to support feature has two dependence
(before and after) type.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 5 +-
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 8 +-
.../RegisterCpuFeaturesLib.c | 99 --
3 files changed, 45 insertions(+), 67 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 173f2edbea..bc372a338f 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -671,10 +671,11 @@ AnalysisProcessorFeatures (
// If feature has dependence with the next feature (ONLY care
core/package dependency).
// and feature initialize succeed, add sync semaphere here.
//
-BeforeDep = DetectFeatureScope (CpuFeatureInOrder, TRUE);
if (NextCpuFeatureInOrder != NULL) {
- AfterDep = DetectFeatureScope (NextCpuFeatureInOrder, FALSE);
+ BeforeDep = DetectFeatureScope (CpuFeatureInOrder, TRUE,
NextCpuFeatureInOrder->FeatureMask);
+ AfterDep = DetectFeatureScope (NextCpuFeatureInOrder, FALSE,
CpuFeatureInOrder->FeatureMask);
} else {
+ BeforeDep = DetectFeatureScope (CpuFeatureInOrder, TRUE, NULL);
AfterDep = NoneDepType;
}
//
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
index 42a3f91fbf..b5fe8fbce1 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
@@ -193,15 +193,17 @@ DumpCpuFeature (
/**
Return feature dependence result.
- @param[in] CpuFeaturePointer to CPU feature.
- @param[in] BeforeCheck before dependence or after.
+ @param[in] CpuFeaturePointer to CPU feature.
+ @param[in] BeforeCheck before dependence or after.
+ @param[in] NextCpuFeatureMaskPointer to next CPU feature Mask.
@retval return the dependence result.
**/
CPU_FEATURE_DEPENDENCE_TYPE
DetectFeatureScope (
IN CPU_FEATURES_ENTRY *CpuFeature,
- IN BOOLEANBefore
+ IN BOOLEANBefore,
+ IN CHAR8 *NextCpuFeatureMask
);
/**
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index b6e108b8ad..9a66bc49ff 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -115,90 +115,69 @@ IsBitMaskMatchCheck (
/**
Return feature dependence result.
- @param[in] CpuFeaturePointer to CPU feature.
- @param[in] BeforeCheck before dependence or after.
+ @param[in] CpuFeaturePointer to CPU feature.
+ @param[in] BeforeCheck before dependence or after.
+ @param[in] NextCpuFeatureMaskPointer to next CPU feature Mask.
@retval return the dependence result.
**/
CPU_FEATURE_DEPENDENCE_TYPE
DetectFeatureScope (
IN CPU_FEATURES_ENTRY *CpuFeature,
- IN BOOLEANBefore
+ IN BOOLEANBefore,
+ IN CHAR8 *NextCpuFeatureMask
)
{
+ //
+ // if need to check before type dependence but the feature after current
feature is not
+ // exist, means this before type dependence not valid, just return
NoneDepType.
+ // Just like Feature A has a dependence of feature B, but Feature B not
installed, so
+ // Feature A maybe insert to the last entry of the list. In this case, for
below code,
+ // Featrure A has depend of feature B, but it is the last entry of the list,
so the
+ // NextCpuFeatureMask is NULL, so the dependence for feature A here is
useless and code
+ // just return NoneDepType.
+ //
+ if (NextCpuFeatureMask == NULL) {
+return NoneDepType;
+ }
+
if (Before) {
-if (CpuFeature->PackageBeforeFeatureBitMask != NULL) {
+if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&
+IsBitMaskMatchCheck (NextCpuFeatureMask,
CpuFeature->PackageBeforeFeatureBitMask)) {
return PackageDepType;
}
-if (CpuFeature->CoreBeforeFeatureBitMask != NULL) {
+if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&
+IsBitMaskMatchCheck (NextCpuFeatureMask,
CpuFeature->CoreBeforeFeatureBitMask)) {
return CoreDepType;
}
-if (CpuFeature->BeforeFeatureBitMask != NULL) {
+if
[edk2] [Patch 2/6] UefiCpuPkg/CpuCommonFeaturesLib: Remove white space at line end.
Remove extra white space at the end of line. Cc: Ruiyu Ni Cc: Laszlo Ersek Cc: Dandan Bi Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index f8bee53819..57648352ec 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -328,7 +328,7 @@ LmceInitialize ( MSR_IA32_FEATURE_CONTROL_REGISTER*MsrRegister; // - // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program + // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program // MSR_IA32_MISC_ENABLE for thread 0 in each core. // if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Fix build failure for VS2012 and GCC49.
Code initialized in function can't be correctly detected by build tool.
Add code to clearly initialize the local variable before use it.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Dandan Bi
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 7a5939c966..173f2edbea 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -1029,6 +1029,7 @@ SetProcessorRegister (
InitApicId = GetInitialApicId ();
RegisterTable = NULL;
+ ProcIndex = (UINTN)-1;
for (Index = 0; Index < AcpiCpuData->NumberOfCpus; Index++) {
if (RegisterTables[Index].InitialApicId == InitApicId) {
RegisterTable = [Index];
--
2.15.0.windows.1
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[edk2] [Patch 4/6] UefiCpuPkg/PiSmmCpuDxeSmm: Remove white space at line end.
Remove extra white space at the end of line. Cc: Ruiyu Ni Cc: Laszlo Ersek Cc: Dandan Bi Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index fec53c522f..5193fea2b3 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -346,7 +346,7 @@ ProgramProcessorRegister ( // n * P(0) n * P(1) ... n * P(n) // ASSERT ( -(ApLocation != NULL) && +(ApLocation != NULL) && (CpuStatus->ValidCoreCountPerPackage != 0) && (CpuFlags->SemaphoreCount) != NULL ); @@ -428,7 +428,7 @@ ProgramProcessorRegister ( /** Set Processor register for one AP. - + @param PreSmmRegisterTable Use pre Smm register table or register table. **/ -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 6/6] UefiCpuPkg/PiSmmCpuDxeSmm: Fix build failure for VS2012 and GCC49.
Code initialized in function can't be correctly detected by build tool.
Add code to clearly initialize the local variable before use it.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Dandan Bi
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 5193fea2b3..a45e2dd3d7 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -451,6 +451,7 @@ SetRegister (
InitApicId = GetInitialApicId ();
RegisterTable = NULL;
+ ProcIndex = (UINTN)-1;
for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
if (RegisterTables[Index].InitialApicId == InitApicId) {
RegisterTable = [Index];
--
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[edk2] [Patch 5/6] UefiCpuPkg/PiSmmCpuDxeSmm: Clean up useless code.
Remove useless code after change 93324390.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Dandan Bi
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 10 +-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 16
2 files changed, 1 insertion(+), 25 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 42b040531e..abcc3eea05 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1272,7 +1272,6 @@ InitializeSmmCpuSemaphores (
UINTN TotalSize;
UINTN GlobalSemaphoresSize;
UINTN CpuSemaphoresSize;
- UINTN MsrSemahporeSize;
UINTN SemaphoreSize;
UINTN Pages;
UINTN *SemaphoreBlock;
@@ -1282,8 +1281,7 @@ InitializeSmmCpuSemaphores (
ProcessorCount = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *))
* SemaphoreSize;
CpuSemaphoresSize= (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) *
ProcessorCount * SemaphoreSize;
- MsrSemahporeSize = MSR_SPIN_LOCK_INIT_NUM * SemaphoreSize;
- TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize + MsrSemahporeSize;
+ TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize;
DEBUG((EFI_D_INFO, "One Semaphore Size= 0x%x\n", SemaphoreSize));
DEBUG((EFI_D_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));
Pages = EFI_SIZE_TO_PAGES (TotalSize);
@@ -1311,12 +1309,6 @@ InitializeSmmCpuSemaphores (
SemaphoreAddr += ProcessorCount * SemaphoreSize;
mSmmCpuSemaphores.SemaphoreCpu.Present = (BOOLEAN *)SemaphoreAddr;
- SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize +
CpuSemaphoresSize;
- mSmmCpuSemaphores.SemaphoreMsr.Msr = (SPIN_LOCK *)SemaphoreAddr;
- mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter =
-((UINTN)SemaphoreBlock + Pages * SIZE_4KB - SemaphoreAddr) /
SemaphoreSize;
- ASSERT (mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter >=
MSR_SPIN_LOCK_INIT_NUM);
-
mPFLock = mSmmCpuSemaphores.SemaphoreGlobal.PFLock;
mConfigSmmCodeAccessCheckLock =
mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index e2970308fe..61d4bd3085 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -347,13 +347,6 @@ typedef struct {
volatile BOOLEAN *CandidateBsp;
} SMM_DISPATCHER_MP_SYNC_DATA;
-#define MSR_SPIN_LOCK_INIT_NUM 15
-
-typedef struct {
- SPIN_LOCK*SpinLock;
- UINT32 MsrIndex;
-} MP_MSR_LOCK;
-
#define SMM_PSD_OFFSET 0xfb00
///
@@ -376,21 +369,12 @@ typedef struct {
volatile BOOLEAN *Present;
} SMM_CPU_SEMAPHORE_CPU;
-///
-/// All MSRs semaphores' pointer and counter
-///
-typedef struct {
- SPIN_LOCK*Msr;
- UINTNAvailableCounter;
-} SMM_CPU_SEMAPHORE_MSR;
-
///
/// All semaphores' information
///
typedef struct {
SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;
SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;
- SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;
} SMM_CPU_SEMAPHORES;
extern IA32_DESCRIPTOR gcSmiGdtr;
--
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[edk2] [Patch 0/6] Fix coding style issues.
Fixed ECC issues caused by change serial from d5aa2078 to d28daadd. Eric Dong (6): UefiCpuPkg/RegisterCpuFeaturesLib: Fix build failure for VS2012 and GCC49. UefiCpuPkg/CpuCommonFeaturesLib: Remove white space at line end. UefiCpuPkg/RegisterCpuFeaturesLib: Fix ECC issues. UefiCpuPkg/PiSmmCpuDxeSmm: Remove white space at line end. UefiCpuPkg/PiSmmCpuDxeSmm: Clean up useless code. UefiCpuPkg/PiSmmCpuDxeSmm: Fix build failure for VS2012 and GCC49. .../Library/CpuCommonFeaturesLib/MachineCheck.c| 2 +- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 1 + .../PeiRegisterCpuFeaturesLib.c| 2 ++ .../RegisterCpuFeaturesLib.c | 24 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 5 +++-- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 10 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 16 --- 7 files changed, 20 insertions(+), 40 deletions(-) -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v4 6/6] UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.
Because MSR has scope attribute, driver has no needs to set
MSR for all APs if MSR scope is core or package type. This patch
updates code to base on the MSR scope value to add MSR to the register
table.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Reviewed-by: Ruiyu Ni
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 8 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 12 +++
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 10 ++
.../Library/CpuCommonFeaturesLib/FastStrings.c | 12 +++
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 38 ++
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 14
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 38 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 15 +
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 11 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 11 +++
.../Library/CpuCommonFeaturesLib/ProcTrace.c | 11 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 10 ++
12 files changed, 190 insertions(+)
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index 47116355a8..1beaebe69c 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -67,6 +67,14 @@ C1eInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, only
program
+ // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.
+ //
+ if ((CpuInfo->ProcessorInfo.Location.Thread != 0) ||
(CpuInfo->ProcessorInfo.Location.Core != 0)) {
+ return RETURN_SUCCESS;
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
index 2038171a14..f30117d2c5 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
@@ -69,6 +69,18 @@ EistInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type,
only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
index 921656a1e8..ff06cb9b60 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
@@ -79,6 +79,16 @@ ExecuteDisableInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of the MSR_IA32_EFER is core for below processor type, only
program
+ // MSR_IA32_EFER for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
index 029bcf87b3..2682093c23 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
@@ -40,6 +40,18 @@ FastStringsInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for
below processor type, only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)
||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index d28c4ec51a..8c1eb5eb4f 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -96,6 +96,19 @@ VmxInitialize (
{
MSR_IA32_FEATURE_CONTROL_REGISTER*MsrReg
[edk2] [Patch v4 5/6] UefiCpuPkg/CpuS3DataDxe: Keep old data if value already existed.
AcpiCpuData add new fields, keep these fields if old data already existed.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Reviewed-by: Ruiyu Ni
---
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index ef98239844..1b847e453a 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -259,6 +259,8 @@ CpuS3DataInitialize (
if (OldAcpiCpuData != NULL) {
AcpiCpuData->RegisterTable = OldAcpiCpuData->RegisterTable;
AcpiCpuData->PreSmmInitRegisterTable =
OldAcpiCpuData->PreSmmInitRegisterTable;
+AcpiCpuData->ApLocation = OldAcpiCpuData->ApLocation;
+CopyMem (>CpuStatus, >CpuStatus, sizeof
(CPU_STATUS_INFORMATION));
} else {
//
// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for
all CPUs
--
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[edk2] [Patch v4 4/6] UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
V4 changes:
1. Serial console log for different threads when program register table.
2. Check the AcpiCpuData before use it to avoid potential ASSERT.
V3 changes:
1. Use global variable instead of internal function to return string for
register type
and dependence type.
2. Add comments for some complicated logic.
V1 changes:
Because this driver needs to set MSRs saved in normal boot phase, sync
semaphore logic from RegisterCpuFeaturesLib code which used for normal boot
phase.
Detail see below change for RegisterCpuFeaturesLib:
UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 413 +++--
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 3 -
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 3 +-
3 files changed, 276 insertions(+), 143 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 52ff9679d5..fec53c522f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -38,9 +38,13 @@ typedef struct {
} MP_ASSEMBLY_ADDRESS_MAP;
//
-// Spin lock used to serialize MemoryMapped operation
+// Flags used when program the register.
//
-SPIN_LOCK*mMemoryMappedLock = NULL;
+typedef struct {
+ volatile UINTN ConsoleLogLock; // Spinlock used to control
console.
+ volatile UINTN MemoryMappedLock; // Spinlock used to program
mmio
+ volatile UINT32 *SemaphoreCount; // Semaphore used to program
semaphore.
+} PROGRAM_CPU_REGISTER_FLAGS;
//
// Signal that SMM BASE relocation is complete.
@@ -62,13 +66,11 @@ AsmGetAddressMap (
#define LEGACY_REGION_SIZE(2 * 0x1000)
#define LEGACY_REGION_BASE(0xA - LEGACY_REGION_SIZE)
+PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
ACPI_CPU_DATAmAcpiCpuData;
volatile UINT32 mNumberToFinish;
MP_CPU_EXCHANGE_INFO *mExchangeInfo;
BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
-MP_MSR_LOCK *mMsrSpinLocks = NULL;
-UINTNmMsrSpinLockCount;
-UINTNmMsrCount = 0;
//
// S3 boot flag
@@ -91,88 +93,7 @@ UINT8mApHltLoopCodeTemplate[] = {
0xEB, 0xFC // jmp $-2
};
-/**
- Get MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
- @return Pointer to MSR spin lock.
-
-**/
-SPIN_LOCK *
-GetMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTN Index;
- for (Index = 0; Index < mMsrCount; Index++) {
-if (MsrIndex == mMsrSpinLocks[Index].MsrIndex) {
- return mMsrSpinLocks[Index].SpinLock;
-}
- }
- return NULL;
-}
-
-/**
- Initialize MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
-**/
-VOID
-InitMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTNMsrSpinLockCount;
- UINTNNewMsrSpinLockCount;
- UINTNIndex;
- UINTNAddedSize;
-
- if (mMsrSpinLocks == NULL) {
-MsrSpinLockCount = mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter;
-mMsrSpinLocks = (MP_MSR_LOCK *) AllocatePool (sizeof (MP_MSR_LOCK) *
MsrSpinLockCount);
-ASSERT (mMsrSpinLocks != NULL);
-for (Index = 0; Index < MsrSpinLockCount; Index++) {
- mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr + Index *
mSemaphoreSize);
- mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;
-}
-mMsrSpinLockCount = MsrSpinLockCount;
-mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter = 0;
- }
- if (GetMsrSpinLockByIndex (MsrIndex) == NULL) {
-//
-// Initialize spin lock for MSR programming
-//
-mMsrSpinLocks[mMsrCount].MsrIndex = MsrIndex;
-InitializeSpinLock (mMsrSpinLocks[mMsrCount].SpinLock);
-mMsrCount ++;
-if (mMsrCount == mMsrSpinLockCount) {
- //
- // If MSR spin lock buffer is full, enlarge it
- //
- AddedSize = SIZE_4KB;
- mSmmCpuSemaphores.SemaphoreMsr.Msr =
-AllocatePages (EFI_SIZE_TO_PAGES(AddedSize));
- ASSERT (mSmmCpuSemaphores.SemaphoreMsr.Msr != NULL);
- NewMsrSpinLockCount = mMsrSpinLockCount + AddedSize / mSemaphoreSize;
- mMsrSpinLocks = ReallocatePool (
-sizeof (MP_MSR_LOCK) * mMsrSpinLockCount,
-sizeof (MP_MSR_LOCK) * NewMsrSpinLockCount,
-mMsrSpinLocks
-);
- ASSERT (mMsrSpinLocks != NULL);
- mMsrSpinLockCount = NewMsrSpinLockCount;
- for (Index = mMsrCount; Index < mMsrSpinLockCount; Index++) {
-mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr +
- (Index - mMsrCount) * mSema
[edk2] [Patch v4 3/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.
V4 changes include:
1. Serial debug message for different threads when program the register table.
V3 changes include:
1. Use global variable instead of internal function to return string for
register type
and dependence type.
2. Add comments for some complicated logic.
V2 changes include:
1. Add more description for the code part which need easy to understand.
2. Refine some code base on feedback for V1 changes.
V1 changes include:
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 396 ++---
.../DxeRegisterCpuFeaturesLib.c| 71 ++-
.../DxeRegisterCpuFeaturesLib.inf | 2 +
.../PeiRegisterCpuFeaturesLib.c| 55 ++-
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 62 ++-
.../RegisterCpuFeaturesLib.c | 485 ++---
6 files changed, 938 insertions(+), 133 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index ba3fb3250f..f7dbc1abbf 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -14,6 +14,9 @@
#include "RegisterCpuFeatures.h"
+CHAR16 *mDependTypeStr[] = {L"None", L"Thread", L"Core", L"Package",
L"Invalid" };
+CHAR16 *mRegisterTypeStr[] = {L"MSR", L"CR", L"MMIO", L"CACHE", L"SEMAP",
L"INVALID" };
+
/**
Worker function to save PcdCpuFeaturesCapability.
@@ -145,6 +148,19 @@ CpuInitDataInitialize (
CPU_FEATURES_INIT_ORDER *InitOrder;
CPU_FEATURES_DATA*CpuFeaturesData;
LIST_ENTRY *Entry;
+ UINT32 Core;
+ UINT32 Package;
+ UINT32
[edk2] [Patch v4 2/6] UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
V4 changes: 1. Update comments. v3 changes: 1. Move CPU_FEATURE_DEPENDENCE_TYPE definition to AcpiCpuData.h. 2. Add comments for CPU_FEATURE_BEFORE/CPU_FEATURE_AFTER. v1 changes: Add new core/package dependence types which consumed by different MSRs. Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Ruiyu Ni --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h index 9331e49d13..2f7e71c833 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -73,10 +73,23 @@ #define CPU_FEATURE_PPIN(32+11) #define CPU_FEATURE_PROC_TRACE (32+12) -#define CPU_FEATURE_BEFORE_ALL BIT27 -#define CPU_FEATURE_AFTER_ALL BIT28 -#define CPU_FEATURE_BEFORE BIT29 -#define CPU_FEATURE_AFTER BIT30 +#define CPU_FEATURE_BEFORE_ALL BIT23 +#define CPU_FEATURE_AFTER_ALL BIT24 +// +// CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER only mean Thread scope +// before and Thread scope after. +// It will be replace with CPU_FEATURE_THREAD_BEFORE and +// CPU_FEATURE_THREAD_AFTER, and should not be used anymore. +// +#define CPU_FEATURE_BEFORE BIT25 +#define CPU_FEATURE_AFTER BIT26 + +#define CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_BEFORE +#define CPU_FEATURE_THREAD_AFTERCPU_FEATURE_AFTER +#define CPU_FEATURE_CORE_BEFORE BIT27 +#define CPU_FEATURE_CORE_AFTER BIT28 +#define CPU_FEATURE_PACKAGE_BEFORE BIT29 +#define CPU_FEATURE_PACKAGE_AFTER BIT30 #define CPU_FEATURE_END MAX_UINT32 /// @} -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v4 1/6] UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
v3 changes:
1. Move CPU_FEATURE_DEPENDENCE_TYPE definition here from
RegisterCpuFeaturesLib.h file.
2. Add Invalid type for REGISTER_TYPE which will be used in code.
v2 changes:
1. Add more description about why we do this change.
2. Change structure field type from pointer to EFI_PHYSICAL_ADDRESS because it
will
be share between PEI and DXE.
v1 Changes:
In order to support semaphore related logic, add new definition for it.
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Reviewed-by: Ruiyu Ni
Reviewed-by: Laszlo Ersek
---
UefiCpuPkg/Include/AcpiCpuData.h | 67 +++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 9e51145c08..005d48d7ca 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -22,9 +22,60 @@ typedef enum {
Msr,
ControlRegister,
MemoryMapped,
- CacheControl
+ CacheControl,
+
+ //
+ // Semaphore type used to control the execute sequence of the Msr.
+ // It will be insert between two Msr which has execute dependence.
+ //
+ Semaphore,
+ InvalidReg
} REGISTER_TYPE;
+//
+// Describe the dependency type for different features.
+// The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is
Semaphore.
+//
+typedef enum {
+ NoneDepType,
+ ThreadDepType,
+ CoreDepType,
+ PackageDepType,
+ InvalidDepType
+} CPU_FEATURE_DEPENDENCE_TYPE;
+
+//
+// CPU information.
+//
+typedef struct {
+ //
+ // Record the package count in this CPU.
+ //
+ UINT32 PackageCount;
+ //
+ // Record the max core count in this CPU.
+ // Different packages may have different core count, this value
+ // save the max core count in all the packages.
+ //
+ UINT32 MaxCoreCount;
+ //
+ // Record the max thread count in this CPU.
+ // Different cores may have different thread count, this value
+ // save the max thread count in all the cores.
+ //
+
[edk2] [Patch v4 0/6] Fix performance issue caused by Set MSR task
V4 changes include:
1. Add SpinLock to serial console log for different threads when set register
table.
2. For PiSmmCpuDxeSmm driver, check the AcpiCpuData structure data before use
it to
avoid potential assert case.
V3 changes include:
1. Add comments for some complicate logic.
2. Use global variable instead of internal function to return string for
register type
and dependence type.
3. Verify the solution with internal server platform(2 socket/56 Core/112
thread), set
MSRs costs time change from 2849ms to 87ms.
V2 changes include:
1. Include the change for CpuCommonFeaturesLib which used to set MSR base on
its scope info.
2. Include the change for CpuS3DataDxe driver which also handle the AcpiCpuData
data.
3. Update code base on feedback for V1 changes.
V1 changes include:
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses SpinLock to let set MSR task as an single thread task for all cores.
Because MSR has scope attribute which may cause GP fault if multiple APs set
MSR at the same time, current logic use an easiest solution (use SpinLock) to
avoid this issue, but it will cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope attribute. After this, the SpinLock will not needed. Without
SpinLock, new issue raised which is caused by MSR dependence. For example, MSR
A depends on MSR B which means MSR A must been set after MSR B has been set.
Also MSR B is package scope level and MSR A is thread scope level. If system
has multiple threads, Thread 1 needs to set the thread level MSRs and thread 2
needs to set thread and package level MSRs. Set MSRs task for thread 1 and
thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but at this time, MSR B not been executed yet by thread 2. system may
trig exception at this time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR execute sequence. For the above case, a semaphore will be add between
MSR A and B for all threads. Semaphore has scope info for it. The possible
scope value is core or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release semaphore (+1) for each threads in this core or package(based on the
scope info for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based on the scope info for this semaphore). With these two steps,
driver can control MSR sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
2. Current execute MSR task code in duplicated in PiSmmCpuDxeSmm driver and
RegisterCpuFeaturesLib library because the schedule limitation. Will merge
the code to
RegisterCpuFeaturesLib and export as an API in phase 2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Eric Dong (6):
UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore
type.
UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
UefiCpuPkg/CpuS3DataDxe: Keep old data if value already existed.
UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c| 2 +
UefiCpuPkg/Include/AcpiCpuData.h | 67 ++-
.../Include/Library/RegisterCpuFeaturesLib.h | 21 +-
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 8 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 12 +
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 10 +
.../Library/CpuCommonFeaturesLib/FastStrings.c | 12 +
.../Library/CpuCommonFeaturesLib/FeatureControl.c
[edk2] [Patch v3 5/6] UefiCpuPkg/CpuS3DataDxe: Keep old data if value already existed.
AcpiCpuData add new fields, keep these fields if old data already existed.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Reviewed-by: Ruiyu Ni
---
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index ef98239844..1b847e453a 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -259,6 +259,8 @@ CpuS3DataInitialize (
if (OldAcpiCpuData != NULL) {
AcpiCpuData->RegisterTable = OldAcpiCpuData->RegisterTable;
AcpiCpuData->PreSmmInitRegisterTable =
OldAcpiCpuData->PreSmmInitRegisterTable;
+AcpiCpuData->ApLocation = OldAcpiCpuData->ApLocation;
+CopyMem (>CpuStatus, >CpuStatus, sizeof
(CPU_STATUS_INFORMATION));
} else {
//
// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for
all CPUs
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v3 4/6] UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
V3 changes:
1. Use global variable instead of internal function to return string for
register type
and dependence type.
2. Add comments for some complicated logic.
V1 changes:
Because this driver needs to set MSRs saved in normal boot phase, sync
semaphore logic from RegisterCpuFeaturesLib code which used for normal boot
phase.
Detail see below change for RegisterCpuFeaturesLib:
UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 385 ++---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 3 -
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 3 +-
3 files changed, 248 insertions(+), 143 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 52ff9679d5..c5f4d16487 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -38,9 +38,12 @@ typedef struct {
} MP_ASSEMBLY_ADDRESS_MAP;
//
-// Spin lock used to serialize MemoryMapped operation
+// Flags used when program the register.
//
-SPIN_LOCK*mMemoryMappedLock = NULL;
+typedef struct {
+ volatile UINTN MemoryMappedLock; // Spinlock used to program
mmio
+ volatile UINT32 *SemaphoreCount; // Semaphore used to program
semaphore.
+} PROGRAM_CPU_REGISTER_FLAGS;
//
// Signal that SMM BASE relocation is complete.
@@ -62,13 +65,11 @@ AsmGetAddressMap (
#define LEGACY_REGION_SIZE(2 * 0x1000)
#define LEGACY_REGION_BASE(0xA - LEGACY_REGION_SIZE)
+PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
ACPI_CPU_DATAmAcpiCpuData;
volatile UINT32 mNumberToFinish;
MP_CPU_EXCHANGE_INFO *mExchangeInfo;
BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
-MP_MSR_LOCK *mMsrSpinLocks = NULL;
-UINTNmMsrSpinLockCount;
-UINTNmMsrCount = 0;
//
// S3 boot flag
@@ -91,88 +92,7 @@ UINT8mApHltLoopCodeTemplate[] = {
0xEB, 0xFC // jmp $-2
};
-/**
- Get MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
- @return Pointer to MSR spin lock.
-
-**/
-SPIN_LOCK *
-GetMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTN Index;
- for (Index = 0; Index < mMsrCount; Index++) {
-if (MsrIndex == mMsrSpinLocks[Index].MsrIndex) {
- return mMsrSpinLocks[Index].SpinLock;
-}
- }
- return NULL;
-}
-
-/**
- Initialize MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
-**/
-VOID
-InitMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTNMsrSpinLockCount;
- UINTNNewMsrSpinLockCount;
- UINTNIndex;
- UINTNAddedSize;
-
- if (mMsrSpinLocks == NULL) {
-MsrSpinLockCount = mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter;
-mMsrSpinLocks = (MP_MSR_LOCK *) AllocatePool (sizeof (MP_MSR_LOCK) *
MsrSpinLockCount);
-ASSERT (mMsrSpinLocks != NULL);
-for (Index = 0; Index < MsrSpinLockCount; Index++) {
- mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr + Index *
mSemaphoreSize);
- mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;
-}
-mMsrSpinLockCount = MsrSpinLockCount;
-mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter = 0;
- }
- if (GetMsrSpinLockByIndex (MsrIndex) == NULL) {
-//
-// Initialize spin lock for MSR programming
-//
-mMsrSpinLocks[mMsrCount].MsrIndex = MsrIndex;
-InitializeSpinLock (mMsrSpinLocks[mMsrCount].SpinLock);
-mMsrCount ++;
-if (mMsrCount == mMsrSpinLockCount) {
- //
- // If MSR spin lock buffer is full, enlarge it
- //
- AddedSize = SIZE_4KB;
- mSmmCpuSemaphores.SemaphoreMsr.Msr =
-AllocatePages (EFI_SIZE_TO_PAGES(AddedSize));
- ASSERT (mSmmCpuSemaphores.SemaphoreMsr.Msr != NULL);
- NewMsrSpinLockCount = mMsrSpinLockCount + AddedSize / mSemaphoreSize;
- mMsrSpinLocks = ReallocatePool (
-sizeof (MP_MSR_LOCK) * mMsrSpinLockCount,
-sizeof (MP_MSR_LOCK) * NewMsrSpinLockCount,
-mMsrSpinLocks
-);
- ASSERT (mMsrSpinLocks != NULL);
- mMsrSpinLockCount = NewMsrSpinLockCount;
- for (Index = mMsrCount; Index < mMsrSpinLockCount; Index++) {
-mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr +
- (Index - mMsrCount) * mSemaphoreSize);
-mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;
- }
-}
- }
-}
+CHAR16 *mRegisterTypeStr[] = {L"MSR", L"CR", L"MMIO", L"CACHE", L"SEMAP",
L"INVALID" };
[edk2] [Patch v3 6/6] UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.
Because MSR has scope attribute, driver has no needs to set
MSR for all APs if MSR scope is core or package type. This patch
updates code to base on the MSR scope value to add MSR to the register
table.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Reviewed-by: Ruiyu Ni
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 8 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 12 +++
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 10 ++
.../Library/CpuCommonFeaturesLib/FastStrings.c | 12 +++
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 38 ++
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 14
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 38 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 15 +
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 11 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 11 +++
.../Library/CpuCommonFeaturesLib/ProcTrace.c | 11 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 10 ++
12 files changed, 190 insertions(+)
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index 47116355a8..1beaebe69c 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -67,6 +67,14 @@ C1eInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, only
program
+ // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.
+ //
+ if ((CpuInfo->ProcessorInfo.Location.Thread != 0) ||
(CpuInfo->ProcessorInfo.Location.Core != 0)) {
+ return RETURN_SUCCESS;
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
index 2038171a14..f30117d2c5 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
@@ -69,6 +69,18 @@ EistInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type,
only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
index 921656a1e8..ff06cb9b60 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
@@ -79,6 +79,16 @@ ExecuteDisableInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of the MSR_IA32_EFER is core for below processor type, only
program
+ // MSR_IA32_EFER for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
index 029bcf87b3..2682093c23 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
@@ -40,6 +40,18 @@ FastStringsInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for
below processor type, only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)
||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index d28c4ec51a..8c1eb5eb4f 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -96,6 +96,19 @@ VmxInitialize (
{
MSR_IA32_FEATURE_CONTROL_REGISTER*MsrReg
[edk2] [Patch v3 2/6] UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
v3 changes: 1. Move CPU_FEATURE_DEPENDENCE_TYPE definition to AcpiCpuData.h. 2. Add comments for CPU_FEATURE_BEFORE/CPU_FEATURE_AFTER. v1 changes: Add new core/package dependence types which consumed by different MSRs. Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h index 9331e49d13..e41f0dc7f6 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -73,10 +73,23 @@ #define CPU_FEATURE_PPIN(32+11) #define CPU_FEATURE_PROC_TRACE (32+12) -#define CPU_FEATURE_BEFORE_ALL BIT27 -#define CPU_FEATURE_AFTER_ALL BIT28 -#define CPU_FEATURE_BEFORE BIT29 -#define CPU_FEATURE_AFTER BIT30 +#define CPU_FEATURE_BEFORE_ALL BIT23 +#define CPU_FEATURE_AFTER_ALL BIT24 +// +// CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER only mean Thread scope +// before and Thread scope after. +// It will be replace with CPU_FEATURE_THREAD_BEFORE and +// CPU_FEATURE_THREAD_AFTER, and should not been used anymore. +// +#define CPU_FEATURE_BEFORE BIT25 +#define CPU_FEATURE_AFTER BIT26 + +#define CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_BEFORE +#define CPU_FEATURE_THREAD_AFTERCPU_FEATURE_AFTER +#define CPU_FEATURE_CORE_BEFORE BIT27 +#define CPU_FEATURE_CORE_AFTER BIT28 +#define CPU_FEATURE_PACKAGE_BEFORE BIT29 +#define CPU_FEATURE_PACKAGE_AFTER BIT30 #define CPU_FEATURE_END MAX_UINT32 /// @} -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v3 3/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.
V3 changes include:
1. Use global variable instead of internal function to return string for
register type
and dependence type.
2. Add comments for some complicated logic.
V2 changes include:
1. Add more description for the code part which need easy to understand.
2. Refine some code base on feedback for V1 changes.
V1 changes include:
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 392 ++---
.../DxeRegisterCpuFeaturesLib.c| 71 ++-
.../DxeRegisterCpuFeaturesLib.inf | 2 +
.../PeiRegisterCpuFeaturesLib.c| 55 ++-
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 61 ++-
.../RegisterCpuFeaturesLib.c | 484 ++---
6 files changed, 932 insertions(+), 133 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index ba3fb3250f..16d2b71fd8 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -14,6 +14,9 @@
#include "RegisterCpuFeatures.h"
+CHAR16 *mDependTypeStr[] = {L"None", L"Thread", L"Core", L"Package",
L"Invalid" };
+CHAR16 *mRegisterTypeStr[] = {L"MSR", L"CR", L"MMIO", L"CACHE", L"SEMAP",
L"INVALID" };
+
/**
Worker function to save PcdCpuFeaturesCapability.
@@ -145,6 +148,19 @@ CpuInitDataInitialize (
CPU_FEATURES_INIT_ORDER *InitOrder;
CPU_FEATURES_DATA*CpuFeaturesData;
LIST_ENTRY *Entry;
+ UINT32 Core;
+ UINT32 Package;
+ UINT32 Thread;
+ EFI_CPU_PHYSICAL_LOCATION*Lo
[edk2] [Patch v3 1/6] UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
v3 changes:
1. Move CPU_FEATURE_DEPENDENCE_TYPE definition here from
RegisterCpuFeaturesLib.h file.
2. Add Invalid type for REGISTER_TYPE which will be used in code.
v2 changes:
1. Add more description about why we do this change.
2. Change structure field type from pointer to EFI_PHYSICAL_ADDRESS because it
will
be share between PEI and DXE.
v1 Changes:
In order to support semaphore related logic, add new definition for it.
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/AcpiCpuData.h | 59 +++-
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 9e51145c08..9fd87c1a8d 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -22,9 +22,56 @@ typedef enum {
Msr,
ControlRegister,
MemoryMapped,
- CacheControl
+ CacheControl,
+
+ //
+ // Semaphore type used to control the execute sequence of the Msr.
+ // It will be insert between two Msr which has execute dependence.
+ //
+ Semaphore,
+ InvalidReg
} REGISTER_TYPE;
+//
+// Describe the dependency type for different features.
+// The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is
Semaphore.
+//
+typedef enum {
+ NoneDepType,
+ ThreadDepType,
+ CoreDepType,
+ PackageDepType,
+ InvalidDepType
+} CPU_FEATURE_DEPENDENCE_TYPE;
+
+//
+// CPU information.
+//
+typedef struct {
+ //
+ // Record the package count in this CPU.
+ //
+ UINT32 PackageCount;
+ //
+ // Record the max core count in this CPU.
+ // Different packages may have different core count, this value
+ // save the max core count in all the packages.
+ //
+ UINT32 MaxCoreCount;
+ //
+ // Record the max thread count in this CPU.
+ // Different cores may have different thread count, this value
+ // save the max thread count in all the cores.
+ //
+ UINT32 MaxThrea
[edk2] [Patch 0/6] Fix performance issue caused by Set MSR task
V3 changes include:
1. Add comments for some complicate logic.
2. Use global variable instead of internal function to return string for
register type
and dependence type.
3. Verify the solution with internal server platform(2 socket/56 Core/112
thread), set
MSRs costs time change from 2849ms to 87ms.
V2 changes include:
1. Include the change for CpuCommonFeaturesLib which used to set MSR base on
its scope info.
2. Include the change for CpuS3DataDxe driver which also handle the AcpiCpuData
data.
3. Update code base on feedback for V1 changes.
V1 changes include:
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses SpinLock to let set MSR task as an single thread task for all cores.
Because MSR has scope attribute which may cause GP fault if multiple APs set
MSR at the same time, current logic use an easiest solution (use SpinLock) to
avoid this issue, but it will cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope attribute. After this, the SpinLock will not needed. Without
SpinLock, new issue raised which is caused by MSR dependence. For example, MSR
A depends on MSR B which means MSR A must been set after MSR B has been set.
Also MSR B is package scope level and MSR A is thread scope level. If system
has multiple threads, Thread 1 needs to set the thread level MSRs and thread 2
needs to set thread and package level MSRs. Set MSRs task for thread 1 and
thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but at this time, MSR B not been executed yet by thread 2. system may
trig exception at this time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR execute sequence. For the above case, a semaphore will be add between
MSR A and B for all threads. Semaphore has scope info for it. The possible
scope value is core or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release semaphore (+1) for each threads in this core or package(based on the
scope info for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based on the scope info for this semaphore). With these two steps,
driver can control MSR sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
2. Current execute MSR task code in duplicated in PiSmmCpuDxeSmm driver and
RegisterCpuFeaturesLib library because the schedule limitation. Will merge
the code to
RegisterCpuFeaturesLib and export as an API in phase 2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Eric Dong (6):
UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore
type.
UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
UefiCpuPkg/CpuS3DataDxe: Keep old data if value already existed.
UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c| 2 +
UefiCpuPkg/Include/AcpiCpuData.h | 59 ++-
.../Include/Library/RegisterCpuFeaturesLib.h | 21 +-
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 8 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 12 +
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 10 +
.../Library/CpuCommonFeaturesLib/FastStrings.c | 12 +
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 38 ++
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 14 +
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 38 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 15 +
.../Library/CpuCommonFeaturesLib/PendingB
[edk2] [Patch v2 3/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.
V2 changes include:
1. Add more description for the code part which need easy to understand.
2. Refine some code base on feedback for V1 changes.
V1 changes include:
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 438 ---
.../DxeRegisterCpuFeaturesLib.c| 71 ++-
.../DxeRegisterCpuFeaturesLib.inf | 3 +
.../PeiRegisterCpuFeaturesLib.c| 55 ++-
.../PeiRegisterCpuFeaturesLib.inf | 1 +
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 61 ++-
.../RegisterCpuFeaturesLib.c | 484 ++---
7 files changed, 980 insertions(+), 133 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index ba3fb3250f..2bf2254602 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -145,6 +145,19 @@ CpuInitDataInitialize (
CPU_FEATURES_INIT_ORDER *InitOrder;
CPU_FEATURES_DATA*CpuFeaturesData;
LIST_ENTRY *Entry;
+ UINT32 Core;
+ UINT32 Package;
+ UINT32 Thread;
+ EFI_CPU_PHYSICAL_LOCATION*Location;
+ BOOLEAN *CoresVisited;
+ UINTNIndex;
+ ACPI_CPU_DATA*AcpiCpuData;
+ CPU_STATUS_INFORMATION *CpuStatus;
+ UINT32 *ValidCorePerPackage;
+
+ Core= 0;
+ Package = 0;
+ Thread = 0;
CpuFeaturesData = GetCpuFeaturesData ();
CpuFeaturesData->InitOrder = AllocateZeroPool (sizeof
(CPU_FEATURES_INIT_ORDER) * NumberOfCpus);
@@ -163,6 +176,17 @@ CpuInitDataInitialize (
Entry = Entry->
[edk2] [Patch v2 5/6] UefiCpuPkg/CpuS3DataDxe: Keep old data if value already existed.
AcpiCpuData add new fields, keep these fields if old data already existed.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index ef98239844..1b847e453a 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -259,6 +259,8 @@ CpuS3DataInitialize (
if (OldAcpiCpuData != NULL) {
AcpiCpuData->RegisterTable = OldAcpiCpuData->RegisterTable;
AcpiCpuData->PreSmmInitRegisterTable =
OldAcpiCpuData->PreSmmInitRegisterTable;
+AcpiCpuData->ApLocation = OldAcpiCpuData->ApLocation;
+CopyMem (>CpuStatus, >CpuStatus, sizeof
(CPU_STATUS_INFORMATION));
} else {
//
// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for
all CPUs
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 6/6] UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.
Because MSR has scope attribute, driver has no needs to set
MSR for all APs if MSR scope is core or package type. This patch
updates code to base on the MSR scope value to add MSR to the register
table.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 8 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 12 +++
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 10 ++
.../Library/CpuCommonFeaturesLib/FastStrings.c | 12 +++
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 38 ++
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 14
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 38 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 15 +
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 11 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 11 +++
.../Library/CpuCommonFeaturesLib/ProcTrace.c | 11 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 10 ++
12 files changed, 190 insertions(+)
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index 47116355a8..1beaebe69c 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -67,6 +67,14 @@ C1eInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, only
program
+ // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.
+ //
+ if ((CpuInfo->ProcessorInfo.Location.Thread != 0) ||
(CpuInfo->ProcessorInfo.Location.Core != 0)) {
+ return RETURN_SUCCESS;
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
index 2038171a14..f30117d2c5 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
@@ -69,6 +69,18 @@ EistInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type,
only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
index 921656a1e8..ff06cb9b60 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
@@ -79,6 +79,16 @@ ExecuteDisableInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of the MSR_IA32_EFER is core for below processor type, only
program
+ // MSR_IA32_EFER for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
index 029bcf87b3..2682093c23 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
@@ -40,6 +40,18 @@ FastStringsInitialize (
IN BOOLEAN State
)
{
+ //
+ // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for
below processor type, only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)
||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+}
+ }
+
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index d28c4ec51a..8c1eb5eb4f 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -96,6 +96,19 @@ VmxInitialize (
{
MSR_IA32_FEATURE_CONTROL_REGISTER*MsrRegister;
+ //
+ // The scope of EnableV
[edk2] [Patch v2 4/6] UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
Because this driver needs to set MSRs saved in normal boot phase, sync semaphore
logic from RegisterCpuFeaturesLib code which used for normal boot phase.
Detail see below change for RegisterCpuFeaturesLib:
UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 406 +++--
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 3 -
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 3 +-
3 files changed, 268 insertions(+), 144 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 52ff9679d5..42a889f08f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -38,9 +38,12 @@ typedef struct {
} MP_ASSEMBLY_ADDRESS_MAP;
//
-// Spin lock used to serialize MemoryMapped operation
+// Flags used when program the register.
//
-SPIN_LOCK*mMemoryMappedLock = NULL;
+typedef struct {
+ volatile UINTN MemoryMappedLock; // Spinlock used to program
mmio
+ volatile UINT32 *SemaphoreCount; // Semaphore used to program
semaphore.
+} PROGRAM_CPU_REGISTER_FLAGS;
//
// Signal that SMM BASE relocation is complete.
@@ -62,13 +65,11 @@ AsmGetAddressMap (
#define LEGACY_REGION_SIZE(2 * 0x1000)
#define LEGACY_REGION_BASE(0xA - LEGACY_REGION_SIZE)
+PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
ACPI_CPU_DATAmAcpiCpuData;
volatile UINT32 mNumberToFinish;
MP_CPU_EXCHANGE_INFO *mExchangeInfo;
BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
-MP_MSR_LOCK *mMsrSpinLocks = NULL;
-UINTNmMsrSpinLockCount;
-UINTNmMsrCount = 0;
//
// S3 boot flag
@@ -91,89 +92,6 @@ UINT8mApHltLoopCodeTemplate[] = {
0xEB, 0xFC // jmp $-2
};
-/**
- Get MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
- @return Pointer to MSR spin lock.
-
-**/
-SPIN_LOCK *
-GetMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTN Index;
- for (Index = 0; Index < mMsrCount; Index++) {
-if (MsrIndex == mMsrSpinLocks[Index].MsrIndex) {
- return mMsrSpinLocks[Index].SpinLock;
-}
- }
- return NULL;
-}
-
-/**
- Initialize MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
-**/
-VOID
-InitMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTNMsrSpinLockCount;
- UINTNNewMsrSpinLockCount;
- UINTNIndex;
- UINTNAddedSize;
-
- if (mMsrSpinLocks == NULL) {
-MsrSpinLockCount = mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter;
-mMsrSpinLocks = (MP_MSR_LOCK *) AllocatePool (sizeof (MP_MSR_LOCK) *
MsrSpinLockCount);
-ASSERT (mMsrSpinLocks != NULL);
-for (Index = 0; Index < MsrSpinLockCount; Index++) {
- mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr + Index *
mSemaphoreSize);
- mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;
-}
-mMsrSpinLockCount = MsrSpinLockCount;
-mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter = 0;
- }
- if (GetMsrSpinLockByIndex (MsrIndex) == NULL) {
-//
-// Initialize spin lock for MSR programming
-//
-mMsrSpinLocks[mMsrCount].MsrIndex = MsrIndex;
-InitializeSpinLock (mMsrSpinLocks[mMsrCount].SpinLock);
-mMsrCount ++;
-if (mMsrCount == mMsrSpinLockCount) {
- //
- // If MSR spin lock buffer is full, enlarge it
- //
- AddedSize = SIZE_4KB;
- mSmmCpuSemaphores.SemaphoreMsr.Msr =
-AllocatePages (EFI_SIZE_TO_PAGES(AddedSize));
- ASSERT (mSmmCpuSemaphores.SemaphoreMsr.Msr != NULL);
- NewMsrSpinLockCount = mMsrSpinLockCount + AddedSize / mSemaphoreSize;
- mMsrSpinLocks = ReallocatePool (
-sizeof (MP_MSR_LOCK) * mMsrSpinLockCount,
-sizeof (MP_MSR_LOCK) * NewMsrSpinLockCount,
-mMsrSpinLocks
-);
- ASSERT (mMsrSpinLocks != NULL);
- mMsrSpinLockCount = NewMsrSpinLockCount;
- for (Index = mMsrCount; Index < mMsrSpinLockCount; Index++) {
-mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr +
- (Index - mMsrCount) * mSemaphoreSize);
-mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;
- }
-}
- }
-}
-
/**
Sync up the MTRR values for all processors.
@@ -204,42 +122,131 @@ Returns:
}
/**
- Programs registers for the calling processor.
+ Increment semaphore by 1.
+
+ @param SemIN: 32-bit unsigned integer
+
+**/
+VOID
+S3ReleaseSemaphore (
+ IN OUT volatile UINT32 *Sem
+ )
+{
+ Interlocked
[edk2] [Patch v2 2/6] UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
Add new core/package dependence types which consumed by different MSRs.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../Include/Library/RegisterCpuFeaturesLib.h | 25 ++
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index 9331e49d13..e6f0ebe4bc 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -73,10 +73,17 @@
#define CPU_FEATURE_PPIN(32+11)
#define CPU_FEATURE_PROC_TRACE (32+12)
-#define CPU_FEATURE_BEFORE_ALL BIT27
-#define CPU_FEATURE_AFTER_ALL BIT28
-#define CPU_FEATURE_BEFORE BIT29
-#define CPU_FEATURE_AFTER BIT30
+#define CPU_FEATURE_BEFORE_ALL BIT23
+#define CPU_FEATURE_AFTER_ALL BIT24
+#define CPU_FEATURE_BEFORE BIT25
+#define CPU_FEATURE_AFTER BIT26
+
+#define CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_BEFORE
+#define CPU_FEATURE_THREAD_AFTERCPU_FEATURE_AFTER
+#define CPU_FEATURE_CORE_BEFORE BIT27
+#define CPU_FEATURE_CORE_AFTER BIT28
+#define CPU_FEATURE_PACKAGE_BEFORE BIT29
+#define CPU_FEATURE_PACKAGE_AFTER BIT30
#define CPU_FEATURE_END MAX_UINT32
/// @}
@@ -116,6 +123,16 @@ typedef struct {
CPUID_VERSION_INFO_EDX CpuIdVersionInfoEdx;
} REGISTER_CPU_FEATURE_INFORMATION;
+//
+// Describe the dependency type for different features.
+//
+typedef enum {
+ NoneDepType,
+ ThreadDepType,
+ CoreDepType,
+ PackageDepType
+} CPU_FEATURE_DEPENDENCE_TYPE;
+
/**
Determines if a CPU feature is enabled in PcdCpuFeaturesSupport bit mask.
If a CPU feature is disabled in PcdCpuFeaturesSupport then all the code/data
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v2 0/6] Fix performance issue caused by Set MSR task.
V2 changes include:
1. Include the change for CpuCommonFeaturesLib which used to set MSR base on
its scope info.
2. Include the change for CpuS3DataDxe driver which also handle the AcpiCpuData
data.
3. Update code base on feedback for V1 changes.
V1 changes include:
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses SpinLock to let set MSR task as an single thread task for all cores.
Because MSR has scope attribute which may cause GP fault if multiple APs set
MSR at the same time, current logic use an easiest solution (use SpinLock) to
avoid this issue, but it will cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope attribute. After this, the SpinLock will not needed. Without
SpinLock, new issue raised which is caused by MSR dependence. For example, MSR
A depends on MSR B which means MSR A must been set after MSR B has been set.
Also MSR B is package scope level and MSR A is thread scope level. If system
has multiple threads, Thread 1 needs to set the thread level MSRs and thread 2
needs to set thread and package level MSRs. Set MSRs task for thread 1 and
thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but at this time, MSR B not been executed yet by thread 2. system may
trig exception at this time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR execute sequence. For the above case, a semaphore will be add between
MSR A and B for all threads. Semaphore has scope info for it. The possible
scope value is core or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release semaphore (+1) for each threads in this core or package(based on the
scope info for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based on the scope info for this semaphore). With these two steps,
driver can control MSR sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
2. Current execute MSR task code in duplicated in PiSmmCpuDxeSmm driver and
RegisterCpuFeaturesLib library because the schedule limitation. Will merge
the code to
RegisterCpuFeaturesLib and export as an API in phase 2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Eric Dong (6):
UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore
type.
UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
UefiCpuPkg/CpuS3DataDxe: Keep old data if value already existed.
UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c| 2 +
UefiCpuPkg/Include/AcpiCpuData.h | 45 +-
.../Include/Library/RegisterCpuFeaturesLib.h | 25 +-
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 8 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 12 +
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 10 +
.../Library/CpuCommonFeaturesLib/FastStrings.c | 12 +
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 38 ++
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 14 +
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 38 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 15 +
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 11 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 11 +
.../Library/CpuCommonFeaturesLib/ProcTrace.c | 11 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 10 +
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 438 ---
.../DxeRegisterCpuFeature
[edk2] [Patch v2 1/6] UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
v2 changes:
1. Add more description about why we do this change.
2. Change structure field type from pointer to EFI_PHYSICAL_ADDRESS because it
will
be share between PEI and DXE.
In order to support semaphore related logic, add new definition for it.
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/AcpiCpuData.h | 45 +++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 9e51145c08..f1439dcf9a 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -22,9 +22,42 @@ typedef enum {
Msr,
ControlRegister,
MemoryMapped,
- CacheControl
+ CacheControl,
+ //
+ // Semaphore type used to control the execute sequence of the Msr.
+ // It will be insert between two Msr which has execute dependence.
+ //
+ Semaphore
} REGISTER_TYPE;
+//
+// CPU information.
+//
+typedef struct {
+ //
+ // Record the package count in this CPU.
+ //
+ UINT32 PackageCount;
+ //
+ // Record the max core count in this CPU.
+ // Different packages may have different core count, this value
+ // save the max core count in all the packages.
+ //
+ UINT32 MaxCoreCount;
+ //
+ // Record the max thread count in this CPU.
+ // Different cores may have different thread count, this value
+ // save the max thread count in all the cores.
+ //
+ UINT32 MaxThreadCount;
+ //
+ // This fild is an pointer type which point to an array.
+ // This array used to save the valid cores in different packages in this CPU.
+ // The array count is the package number in this CPU.
+ //
+ EFI_PHYSICAL_ADDRESSValidCoresPerPackages;
+} CPU_STATUS_INFORMATION;
+
//
// Element of register table entry
//
@@ -147,6 +180,16 @@ typedef struct {
// provided.
//
UINT32ApMachineCheckHandlerSize;
+ //
+ // CPU information which is required wh
[edk2] [Patch 2/4] UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
Add new core/package dependence types which consumed by different MSRs.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../Include/Library/RegisterCpuFeaturesLib.h | 25 ++
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index 9331e49d13..e6f0ebe4bc 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -73,10 +73,17 @@
#define CPU_FEATURE_PPIN(32+11)
#define CPU_FEATURE_PROC_TRACE (32+12)
-#define CPU_FEATURE_BEFORE_ALL BIT27
-#define CPU_FEATURE_AFTER_ALL BIT28
-#define CPU_FEATURE_BEFORE BIT29
-#define CPU_FEATURE_AFTER BIT30
+#define CPU_FEATURE_BEFORE_ALL BIT23
+#define CPU_FEATURE_AFTER_ALL BIT24
+#define CPU_FEATURE_BEFORE BIT25
+#define CPU_FEATURE_AFTER BIT26
+
+#define CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_BEFORE
+#define CPU_FEATURE_THREAD_AFTERCPU_FEATURE_AFTER
+#define CPU_FEATURE_CORE_BEFORE BIT27
+#define CPU_FEATURE_CORE_AFTER BIT28
+#define CPU_FEATURE_PACKAGE_BEFORE BIT29
+#define CPU_FEATURE_PACKAGE_AFTER BIT30
#define CPU_FEATURE_END MAX_UINT32
/// @}
@@ -116,6 +123,16 @@ typedef struct {
CPUID_VERSION_INFO_EDX CpuIdVersionInfoEdx;
} REGISTER_CPU_FEATURE_INFORMATION;
+//
+// Describe the dependency type for different features.
+//
+typedef enum {
+ NoneDepType,
+ ThreadDepType,
+ CoreDepType,
+ PackageDepType
+} CPU_FEATURE_DEPENDENCE_TYPE;
+
/**
Determines if a CPU feature is enabled in PcdCpuFeaturesSupport bit mask.
If a CPU feature is disabled in PcdCpuFeaturesSupport then all the code/data
--
2.15.0.windows.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch 0/4] Fix performance issue caused by Set MSR task.
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
2. Current execute MSR task code in duplicated in PiSmmCpuDxeSmm driver and
RegisterCpuFeaturesLib library because the schedule limitation. Will merge
the code to
RegisterCpuFeaturesLib and export as an API in phase 2 for this task.
Extra Notes:
I will send the other patch to set MSR base on scope info and check in it
before check in
this serial.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
Eric Dong (4):
UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.
UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore
type.
UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
UefiCpuPkg/Include/AcpiCpuData.h | 23 +-
.../Include/Library/RegisterCpuFeaturesLib.h | 25 +-
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 324 ---
.../DxeRegisterCpuFeaturesLib.c| 71 +++-
.../DxeRegisterCpuFeaturesLib.inf | 3 +
.../PeiRegisterCpuFeaturesLib.c| 55 ++-
.../PeiRegisterCpuFeaturesLib.inf | 1 +
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 51 ++-
.../RegisterCpuFeaturesLib.c | 452 ++---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 316 +++---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 3 -
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 3 +-
12 files changed, 1063 insertions(+), 264 deletions(-)
--
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[edk2] [Patch 3/4] UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.
In a system which has multiple cores, current set register value task costs
huge times.
After investigation, current set MSR task costs most of the times. Current
logic uses
SpinLock to let set MSR task as an single thread task for all cores. Because
MSR has
scope attribute which may cause GP fault if multiple APs set MSR at the same
time,
current logic use an easiest solution (use SpinLock) to avoid this issue, but
it will
cost huge times.
In order to fix this performance issue, new solution will set MSRs base on
their scope
attribute. After this, the SpinLock will not needed. Without SpinLock, new
issue raised
which is caused by MSR dependence. For example, MSR A depends on MSR B which
means MSR A
must been set after MSR B has been set. Also MSR B is package scope level and
MSR A is
thread scope level. If system has multiple threads, Thread 1 needs to set the
thread level
MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for
thread 1
and thread 2 like below:
Thread 1 Thread 2
MSR B NY
MSR A YY
If driver don't control execute MSR order, for thread 1, it will execute MSR A
first, but
at this time, MSR B not been executed yet by thread 2. system may trig
exception at this
time.
In order to fix the above issue, driver introduces semaphore logic to control
the MSR
execute sequence. For the above case, a semaphore will be add between MSR A and
B for
all threads. Semaphore has scope info for it. The possible scope value is core
or package.
For each thread, when it meets a semaphore during it set registers, it will 1)
release
semaphore (+1) for each threads in this core or package(based on the scope info
for this
semaphore) 2) acquire semaphore (-1) for all the threads in this core or
package(based
on the scope info for this semaphore). With these two steps, driver can control
MSR
sequence. Sample code logic like below:
//
// First increase semaphore count by 1 for processors in this package.
//
for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ;
ProcessorIndex ++) {
LibReleaseSemaphore ((UINT32 *) [PackageOffset +
ProcessorIndex]);
}
//
// Second, check whether the count has reach the check number.
//
for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) {
LibWaitForSemaphore ([ApOffset]);
}
Platform Requirement:
1. This change requires register MSR setting base on MSR scope info. If still
register MSR
for all threads, exception may raised.
Known limitation:
1. Current CpuFeatures driver supports DXE instance and PEI instance. But
semaphore logic
requires Aps execute in async mode which is not supported by PEI driver. So
CpuFeature
PEI instance not works after this change. We plan to support async mode for
PEI in phase
2 for this task.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 324 ---
.../DxeRegisterCpuFeaturesLib.c| 71 +++-
.../DxeRegisterCpuFeaturesLib.inf | 3 +
.../PeiRegisterCpuFeaturesLib.c| 55 ++-
.../PeiRegisterCpuFeaturesLib.inf | 1 +
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 51 ++-
.../RegisterCpuFeaturesLib.c | 452 ++---
7 files changed, 840 insertions(+), 117 deletions(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index ba3fb3250f..f820b4fed7 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -145,6 +145,20 @@ CpuInitDataInitialize (
CPU_FEATURES_INIT_ORDER *InitOrder;
CPU_FEATURES_DATA*CpuFeaturesData;
LIST_ENTRY *Entry;
+ UINT32 Core;
+ UINT32 Package;
+ UINT32 Thread;
+ EFI_CPU_PHYSICAL_LOCATION*Location;
+ UINT32 *CoreArray;
+ UINTNIndex;
+ UINT32 ValidCount;
+ UINTNCoreIndex;
+ ACPI_CPU_DATA*AcpiCpuData;
+ CPU_STATUS_INFORMATION *CpuStatus;
+
+ Core= 0;
+ Package = 0;
+ Thread = 0;
CpuFeaturesData = GetCpuFeaturesData ();
CpuFeaturesData->InitOrder = AllocateZeroPool (sizeof
(CPU_FEATURES_INIT_ORDER) * NumberOfCpus);
@@ -163,6 +177,16 @@ CpuInitDataInitialize (
Entry = Entry->ForwardLink;
}
+ CpuFeaturesData->NumberOfCpus = (UINT32) NumberOfCpus;
+
+ AcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdC
[edk2] [Patch 1/4] UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.
In order to support semaphore related logic, add new definition for it.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/AcpiCpuData.h | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 9e51145c08..b3cf2f664a 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -15,6 +15,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
#ifndef _ACPI_CPU_DATA_H_
#define _ACPI_CPU_DATA_H_
+#include
+
//
// Register types in register table
//
@@ -22,9 +24,20 @@ typedef enum {
Msr,
ControlRegister,
MemoryMapped,
- CacheControl
+ CacheControl,
+ Semaphore
} REGISTER_TYPE;
+//
+// CPU information.
+//
+typedef struct {
+ UINT32PackageCount; // Packages in this CPU.
+ UINT32CoreCount;// Max Core count in the packages.
+ UINT32ThreadCount; // MAx thread count in the cores.
+ UINT32*ValidCoresInPackages;// Valid cores in each package.
+} CPU_STATUS_INFORMATION;
+
//
// Element of register table entry
//
@@ -147,6 +160,14 @@ typedef struct {
// provided.
//
UINT32ApMachineCheckHandlerSize;
+ //
+ // CPU information which is required when set the register table.
+ //
+ CPU_STATUS_INFORMATION CpuStatus;
+ //
+ // Location info for each ap.
+ //
+ EFI_CPU_PHYSICAL_LOCATION *ApLocation;
} ACPI_CPU_DATA;
#endif
--
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[edk2] [Patch 4/4] UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type.
Because this driver needs to set MSRs saved in normal boot phase, sync semaphore
logic from RegisterCpuFeaturesLib code which used for normal boot phase.
Detail see change SHA-1: dcdf1774212d87e2d7feb36286a408ea7475fd7b for
RegisterCpuFeaturesLib.
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 316 -
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 3 -
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 3 +-
3 files changed, 180 insertions(+), 142 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 52ff9679d5..5a35f7a634 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -38,9 +38,12 @@ typedef struct {
} MP_ASSEMBLY_ADDRESS_MAP;
//
-// Spin lock used to serialize MemoryMapped operation
+// Flags used when program the register.
//
-SPIN_LOCK*mMemoryMappedLock = NULL;
+typedef struct {
+ volatile UINTN MemoryMappedLock; // Spinlock used to program
mmio
+ volatile UINT32 *SemaphoreCount; // Semaphore used to program
semaphore.
+} PROGRAM_CPU_REGISTER_FLAGS;
//
// Signal that SMM BASE relocation is complete.
@@ -62,13 +65,11 @@ AsmGetAddressMap (
#define LEGACY_REGION_SIZE(2 * 0x1000)
#define LEGACY_REGION_BASE(0xA - LEGACY_REGION_SIZE)
+PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
ACPI_CPU_DATAmAcpiCpuData;
volatile UINT32 mNumberToFinish;
MP_CPU_EXCHANGE_INFO *mExchangeInfo;
BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
-MP_MSR_LOCK *mMsrSpinLocks = NULL;
-UINTNmMsrSpinLockCount;
-UINTNmMsrCount = 0;
//
// S3 boot flag
@@ -91,89 +92,6 @@ UINT8mApHltLoopCodeTemplate[] = {
0xEB, 0xFC // jmp $-2
};
-/**
- Get MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
- @return Pointer to MSR spin lock.
-
-**/
-SPIN_LOCK *
-GetMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTN Index;
- for (Index = 0; Index < mMsrCount; Index++) {
-if (MsrIndex == mMsrSpinLocks[Index].MsrIndex) {
- return mMsrSpinLocks[Index].SpinLock;
-}
- }
- return NULL;
-}
-
-/**
- Initialize MSR spin lock by MSR index.
-
- @param MsrIndex MSR index value.
-
-**/
-VOID
-InitMsrSpinLockByIndex (
- IN UINT32 MsrIndex
- )
-{
- UINTNMsrSpinLockCount;
- UINTNNewMsrSpinLockCount;
- UINTNIndex;
- UINTNAddedSize;
-
- if (mMsrSpinLocks == NULL) {
-MsrSpinLockCount = mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter;
-mMsrSpinLocks = (MP_MSR_LOCK *) AllocatePool (sizeof (MP_MSR_LOCK) *
MsrSpinLockCount);
-ASSERT (mMsrSpinLocks != NULL);
-for (Index = 0; Index < MsrSpinLockCount; Index++) {
- mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr + Index *
mSemaphoreSize);
- mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;
-}
-mMsrSpinLockCount = MsrSpinLockCount;
-mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter = 0;
- }
- if (GetMsrSpinLockByIndex (MsrIndex) == NULL) {
-//
-// Initialize spin lock for MSR programming
-//
-mMsrSpinLocks[mMsrCount].MsrIndex = MsrIndex;
-InitializeSpinLock (mMsrSpinLocks[mMsrCount].SpinLock);
-mMsrCount ++;
-if (mMsrCount == mMsrSpinLockCount) {
- //
- // If MSR spin lock buffer is full, enlarge it
- //
- AddedSize = SIZE_4KB;
- mSmmCpuSemaphores.SemaphoreMsr.Msr =
-AllocatePages (EFI_SIZE_TO_PAGES(AddedSize));
- ASSERT (mSmmCpuSemaphores.SemaphoreMsr.Msr != NULL);
- NewMsrSpinLockCount = mMsrSpinLockCount + AddedSize / mSemaphoreSize;
- mMsrSpinLocks = ReallocatePool (
-sizeof (MP_MSR_LOCK) * mMsrSpinLockCount,
-sizeof (MP_MSR_LOCK) * NewMsrSpinLockCount,
-mMsrSpinLocks
-);
- ASSERT (mMsrSpinLocks != NULL);
- mMsrSpinLockCount = NewMsrSpinLockCount;
- for (Index = mMsrCount; Index < mMsrSpinLockCount; Index++) {
-mMsrSpinLocks[Index].SpinLock =
- (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr +
- (Index - mMsrCount) * mSemaphoreSize);
-mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;
- }
-}
- }
-}
-
/**
Sync up the MTRR values for all processors.
@@ -204,42 +122,89 @@ Returns:
}
/**
- Programs registers for the calling processor.
+ Increment semaphore by 1.
- This function programs registers for the calling processor.
+ @param SemIN: 32-bit unsigned integer
- @param RegisterTablesPointer to register table of th
[edk2] [Patch v5] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
V5:
1. Add ASSERT to indicate this assumption that environment is 32 bit mode.
2. Add description in INF about this driver's expected result
in different environment.
V4:
Only disable paging when it is enabled.
V3 changes:
No need to change inf file.
V2 changes:
Only disable paging in 32 bit mode, no matter it is enable or not.
V1 changes:
PEI Stack Guard needs to enable paging. This might cause #GP if code
trying to write CR3 register with PML4 page table while the processor
is enabled with PAE paging.
Simply disabling paging before updating CR3 can solve this conflict.
It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Jian J Wang
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 17 +
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 10 ++
2 files changed, 27 insertions(+)
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index f164c1713b..8415ab1583 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -964,6 +964,7 @@ S3RestoreConfig2 (
VOID *GuidHob;
BOOLEAN Build4GPageTableOnly;
BOOLEAN InterruptStatus;
+ IA32_CR0 CR0Reg;
TempAcpiS3Context = 0;
TempEfiBootScriptExecutorVariable = 0;
@@ -1045,6 +1046,13 @@ S3RestoreConfig2 (
//
GuidHob = GetFirstGuidHob ();
if (GuidHob != NULL) {
+//
+// Below SwitchStack/AsmEnablePaging64 function has
+// assumption that it's in 32 bits mode now.
+// Add ASSERT code to indicate this assumption.
+//
+ASSERT(sizeof (UINTN) == sizeof (UINT32));
+
Status = PeiServicesLocatePpi (
,
0,
@@ -1105,6 +1113,15 @@ S3RestoreConfig2 (
//
SetInterruptState (InterruptStatus);
+ CR0Reg.UintN = AsmReadCr0 ();
+ if (CR0Reg.Bits.PG != 0) {
+//
+// We're in 32-bit mode, with paging enabled. We can't set CR3 to
+// the 64-bit page tables without first disabling paging.
+//
+CR0Reg.Bits.PG = 0;
+AsmWriteCr0 (CR0Reg.UintN);
+ }
AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
//
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
index 6ce1bf944c..1d0740526f 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
@@ -33,6 +33,16 @@
# VALID_ARCHITECTURES = IA32 X64
#
+#
+# This module is not always workable in IA32 and X64 mode. It has below
result:
+# when it works with SMM mode:
+# ===
+# SMM:used SMM:unused
+# PEI:IA32 works works
+# PEI:X64fails works
+# ===
+#
+
[Sources]
S3Resume.c
--
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[edk2] [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
V4:
Only disable paging when it is enabled.
V3 changes:
No need to change inf file.
V2 changes:
Only disable paging in 32 bit mode, no matter it is enable or not.
V1 changes:
PEI Stack Guard needs to enable paging. This might cause #GP if code
trying to write CR3 register with PML4 page table while the processor
is enabled with PAE paging.
Simply disabling paging before updating CR3 can solve this conflict.
It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232
Change-Id: I99bfdba5daa48a95a4c4ef97eeca1af086558957
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Jian J Wang
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by:Eric Dong
Signed-off-by: Eric Dong
---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 12
1 file changed, 12 insertions(+)
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index f164c1713b..c059c42db5 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -964,6 +964,7 @@ S3RestoreConfig2 (
VOID *GuidHob;
BOOLEAN Build4GPageTableOnly;
BOOLEAN InterruptStatus;
+ IA32_CR0 CR0Reg;
TempAcpiS3Context = 0;
TempEfiBootScriptExecutorVariable = 0;
@@ -1105,6 +1106,17 @@ S3RestoreConfig2 (
//
SetInterruptState (InterruptStatus);
+ if (sizeof (UINTN) == sizeof (UINT32)) {
+CR0Reg.UintN = AsmReadCr0 ();
+if (CR0Reg.Bits.PG != 0) {
+ //
+ // We're in 32-bit mode, with paging enabled. We can't set CR3 to
+ // the 64-bit page tables without first disabling paging.
+ //
+ CR0Reg.Bits.PG = 0;
+ AsmWriteCr0 (CR0Reg.UintN);
+}
+ }
AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
//
--
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[edk2] [Patch v3] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
V3 changes:
No need to change inf file. Also update commit message to include regression
info.
V2 changes:
Only disable paging in 32 bit mode, no matter it is enable or not.
V1 changes:
PEI Stack Guard needs to enable paging. This might cause #GP if code
trying to write CR3 register with PML4 page table while the processor
is enabled with PAE paging.
Simply disabling paging before updating CR3 can solve this conflict.
It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Jian J Wang
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by:Eric Dong
---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 8
1 file changed, 8 insertions(+)
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index f164c1713b..53ed76c6e6 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -1105,6 +1105,14 @@ S3RestoreConfig2 (
//
SetInterruptState (InterruptStatus);
+ if (sizeof(UINTN) == sizeof(UINT32)) {
+//
+// Paging maybe enabled. If current mode is 32 bit mode and code try to
+// enable 64 bit mode page table, it will cause GP fault.
+// To avoid conflict configuration, disable paging first anyway.
+//
+AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
+ }
AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
//
--
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[edk2] [Patch v2] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
V2 changes:
Only disable paging in 32 bit mode, no matter it is enable or not.
V1 changes:
PEI Stack Guard needs to enable paging. This might cause #GP in the
transition from 32-bit PEI to 64-bit SMM due to the code trying to
write CR3 register with PML4 page table while the processor is enabled
with PAE paging.
Simply disabling paging before updating CR3 can solve this conflict.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Jian J Wang
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by:Eric Dong
Signed-off-by: Eric Dong
---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 8
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 1 +
2 files changed, 9 insertions(+)
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index f164c1713b..53ed76c6e6 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -1105,6 +1105,14 @@ S3RestoreConfig2 (
//
SetInterruptState (InterruptStatus);
+ if (sizeof(UINTN) == sizeof(UINT32)) {
+//
+// Paging maybe enabled. If current mode is 32 bit mode and code try to
+// enable 64 bit mode page table, it will cause GP fault.
+// To avoid conflict configuration, disable paging first anyway.
+//
+AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
+ }
AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
//
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
index 6ce1bf944c..0f131d19df 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
@@ -90,6 +90,7 @@
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask##
CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
CONSUMES
[Depex]
TRUE
--
2.15.0.windows.1
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[edk2] [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
PEI Stack Guard needs to enable paging. This might cause #GP in the
transition from 32-bit PEI to 64-bit SMM due to the code trying to
write CR3 register with PML4 page table while the processor is enabled
with PAE paging.
Simply disabling paging before updating CR3 can solve this conflict.
Change-Id: I99bfdba5daa48a95a4c4ef97eeca1af086558957
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Cc: Jian J Wang
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by:Eric Dong
Signed-off-by: Eric Dong
---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 7 +++
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 1 +
2 files changed, 8 insertions(+)
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index f164c1713b..b3bf56e13d 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -1105,6 +1105,13 @@ S3RestoreConfig2 (
//
SetInterruptState (InterruptStatus);
+ if (PcdGetBool (PcdCpuStackGuard)) {
+//
+// Paging already been enabled, to avoid conflict configuration,
+// disable paging first anyway.
+//
+AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
+ }
AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
//
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
index 6ce1bf944c..0f131d19df 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
@@ -90,6 +90,7 @@
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask##
CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
CONSUMES
[Depex]
TRUE
--
2.15.0.windows.1
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[edk2] [Patch] UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Change to DOS format file.
Follow EDKII coding style, change file format to dos style.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1213
Cc: Dandan Bi
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 544 +++---
1 file changed, 272 insertions(+), 272 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
index d050464b7f..64f3e14db3 100644
--- a/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
@@ -1,272 +1,272 @@
-/** @file
- MSR Defintions for Intel Atom processors based on the Goldmont Plus
microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2018, Intel Corporation. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD
License
- which accompanies this distribution. The full text of the license may be
found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
- May 2018, Volume 4: Model-Specific-Registers (MSR)
-
-**/
-
-#ifndef __GOLDMONT_PLUS_MSR_H__
-#define __GOLDMONT_PLUS_MSR_H__
-
-#include
-
-/**
- Is Intel Atom processors based on the Goldmont plus microarchitecture?
-
- @param DisplayFamily Display Family ID
- @param DisplayModel Display Model ID
-
- @retval TRUE Yes, it is.
- @retval FALSE No, it isn't.
-**/
-#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
- (DisplayFamily == 0x06 && \
- (\
-DisplayModel == 0x7A\
-) \
- )
-
-/**
- Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
- Sampling (PEBS).".
-
- @param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x03F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
-
- Example usage
- @code
- MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_GOLDMONT_PLUS_PEBS_ENABLE0x03F1
-
-/**
- MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
-///
-/// [Bit 0] Enable PEBS trigger and recording for the programmed event
-/// (precise or otherwise) on IA32_PMC0.
-///
-UINT32 Fix_Me_1:1;
-///
-/// [Bit 1] Enable PEBS trigger and recording for the programmed event
-/// (precise or otherwise) on IA32_PMC1.
-///
-UINT32 Fix_Me_2:1;
-///
-/// [Bit 2] Enable PEBS trigger and recording for the programmed event
-/// (precise or otherwise) on IA32_PMC2.
-///
-UINT32 Fix_Me_3:1;
-///
-/// [Bit 3] Enable PEBS trigger and recording for the programmed event
-/// (precise or otherwise) on IA32_PMC3.
-///
-UINT32 Fix_Me_4:1;
-UINT32 Reserved1:28;
-///
-/// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
-///
-UINT32 Fix_Me_5:1;
-///
-/// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
-///
-UINT32 Fix_Me_6:1;
-///
-/// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
-///
-UINT32 Fix_Me_7:1;
-UINT32 Reserved2:29;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
-
-
-/**
- Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
- the first entry of the 32-entry LBR stack. The From_IP part of the stack
- contains pointers to the source instruction. See also: - Last Branch Record
- Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and
- .. Exception Recording for Processors based on Goldmont Plus
- Microarchitecture.".
-
- @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x068N)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
- AsmWriteMsr64 (MSR_G
[edk2] [Patch v3 12/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one.
Changes includes:
1. Change MSR name:
1. MSR_SKYLAKE_SGXOWNER0 => MSR_SKYLAKE_SGXOWNEREPOCH0
2. MSR_SKYLAKE_SGXOWNER1 => MSR_SKYLAKE_SGXOWNEREPOCH1
2. Keep old MSR definition(MSR_SKYLAKE_SGXOWNER0/1) for compatibility
1. Use below coding style to define old MSR
#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 40 +++-
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 90cde86ccb..88f2c28eae 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -197,10 +197,12 @@ typedef union {
/**
- Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
+ Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+ the package. Lower 64 bits of an 128-bit external entropy value for key
+ derivation of an enclave.
- @param ECX MSR_SKYLAKE_SGXOWNER0 (0x0300)
+ @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x0300)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -208,18 +210,24 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
+ Msr = 0;
+ AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);
@endcode
- @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
+ @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.
**/
-#define MSR_SKYLAKE_SGXOWNER00x0300
-
+#define MSR_SKYLAKE_SGXOWNEREPOCH00x0300
+//
+// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the
SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER0
MSR_SKYLAKE_SGXOWNEREPOCH0
/**
- Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
+ Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+ the package. Upper 64 bits of an 128-bit external entropy value for key
+ derivation of an enclave.
- @param ECX MSR_SKYLAKE_SGXOWNER1 (0x0301)
+ @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x0301)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -227,11 +235,17 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
+ Msr = 0;
+ AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);
@endcode
- @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
+ @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.
**/
-#define MSR_SKYLAKE_SGXOWNER10x0301
+#define MSR_SKYLAKE_SGXOWNEREPOCH10x0301
+
+//
+// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the
SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1
/**
--
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[edk2] [Patch v3 14/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition.
V3 changes include:
1. Keep the ReservedX not change if bit info not changed for this field.
V2 changes include:
1. Use X in ReservedX fields from totally new value if MSR structure
definition changed.
For example, if in current structure, the max reserved variable is
Reserved2, in new
definition, reserved variable is begin with Reserved3.
V1 Changes:
Changes includes:
1. Update MSR structure definition, change some reserved fields to useful
fields:
1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the
field range.
Old definition like below:
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 15:0] LVL_2 Base Address (R/W).
///
UINT32 Lvl2Base:16;
///
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value
of the
/// maximum C-State code name to be included when IO read to MWAIT
/// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]:
100b - C4
/// is the max C-State to include 110b - C6 is the max C-State to
include.
///
UINT32 CStateRange:3;
UINT32 Reserved1:13;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
This patch make below changes for this data structure, it expand
"CStateRange" field width.
old one:
UINT32 CStateRange:3;
UINT32 Reserved1:13;
new one:
UINT32 CStateRange:7;
UINT32 Reserved1:9;
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 49 +++-
1 file changed, 40 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index da74c2402c..1e22d98ad8 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -278,7 +278,25 @@ typedef union {
/// [Bit 15] CFG Lock (R/WO).
///
UINT32 CFGLock:1;
-UINT32 Reserved3:16;
+UINT32 Reserved5:10;
+///
+/// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
+/// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+/// auto-demote information.
+///
+UINT32 C1StateAutoDemotionEnable:1;
+UINT32 Reserved6:1;
+///
+/// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
+/// Undemotion from Demoted C1.
+///
+UINT32 C1StateAutoUndemotionEnable:1;
+///
+/// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
+/// Package C state demotion.
+///
+UINT32 PKGC_StateAutoDemotionEnable:1;
+UINT32 Reserved7:2;
UINT32 Reserved4:32;
} Bits;
///
@@ -325,13 +343,12 @@ typedef union {
///
UINT32 Lvl2Base:16;
///
-/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
-/// maximum C-State code name to be included when IO read to MWAIT
-/// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
-/// is the max C-State to include 110b - C6 is the max C-State to include.
+/// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
+/// IO-redirection will be executed (0-127). Should be programmed based on
+/// the number of LVLx registers existing in the chipset.
///
-UINT32 CStateRange:3;
-UINT32 Reserved1:13;
+UINT32 CStateRange:7;
+UINT32 Reserved3:9;
UINT32 Reserved2:32;
} Bits;
///
@@ -477,8 +494,22 @@ typedef union {
/// Individual bit fields
///
struct {
-UINT32 Reserved1:32;
-UINT32 Reserved2:26;
+///
+/// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is
+/// set, that bank supports Enhanced MCA (Default all 0; does not support
+/// EMCA).
+///
+UINT32 BankSupport:32;
+UINT32 Reserved4:24;
+///
+/// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
+///
+UINT32 TargetedSMI:1;
+///
+/// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
+/// is supported.
+///
+UINT32 SMM_CPU_SVRSTR:1;
///
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
/// SMM code access restriction is supported and a host-space interface
--
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[edk2] [Patch v3 09/14] UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.
Changes includes:
1. Remove old MSR which not existed in 2018-05 version spec:
1. MSR_CORE2_BBL_CR_CTL3
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 60 --
1 file changed, 60 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 22317fa1de..f01f7c5c97 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -471,66 +471,6 @@ typedef union {
UINT64 Uint64;
} MSR_CORE2_FSB_FREQ_REGISTER;
-
-/**
- Shared.
-
- @param ECX MSR_CORE2_BBL_CR_CTL3 (0x011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
-
- Example usage
- @code
- MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
- @endcode
- @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
-**/
-#define MSR_CORE2_BBL_CR_CTL30x011E
-
-/**
- MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
-///
-/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
-/// Indicates if the L2 is hardware-disabled.
-///
-UINT32 L2HardwareEnabled:1;
-UINT32 Reserved1:7;
-///
-/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
-/// Disabled (default) Until this bit is set the processor will not
-/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
-///
-UINT32 L2Enabled:1;
-UINT32 Reserved2:14;
-///
-/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
-///
-UINT32 L2NotPresent:1;
-UINT32 Reserved3:8;
-UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_BBL_CR_CTL3_REGISTER;
-
-
/**
Shared.
--
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[edk2] [Patch v3 10/14] UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.
Changes includes:
1. Remove MSR which not existed in 2018-05 version spec:
MSR_P6_ROB_CR_BKUPTMPDR6.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 48 -
1 file changed, 48 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index d8af2db3da..9cef72b239 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -1153,54 +1153,6 @@ typedef union {
**/
#define MSR_P6_LASTINTTOIP 0x01DE
-
-/**
-
-
- @param ECX MSR_P6_ROB_CR_BKUPTMPDR6 (0x01E0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
-
- Example usage
- @code
- MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);
- AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);
- @endcode
- @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
-**/
-#define MSR_P6_ROB_CR_BKUPTMPDR6 0x01E0
-
-/**
- MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
-UINT32 Reserved1:2;
-///
-/// [Bit 2] Fast Strings Enable bit. Default is enabled.
-///
-UINT32 FastStrings:1;
-UINT32 Reserved2:29;
-UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
/**
--
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[edk2] [Patch v3 11/14] UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.
Changes includes:
1. Remove old MSR which not existed in 2018-05 version spec:
1. MSR_CORE_ROB_CR_BKUPTMPDR6
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 48 ---
1 file changed, 48 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index bb2bdd2ca1..a4315d6e56 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -555,54 +555,6 @@ typedef union {
**/
#define MSR_CORE_LER_TO_LIP 0x01DE
-
-/**
- Unique.
-
- @param ECX MSR_CORE_ROB_CR_BKUPTMPDR6 (0x01E0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
-
- Example usage
- @code
- MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
- AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
- @endcode
- @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
-**/
-#define MSR_CORE_ROB_CR_BKUPTMPDR6 0x01E0
-
-/**
- MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
-UINT32 Reserved1:2;
-///
-/// [Bit 2] Fast Strings Enable bit. (Default, enabled).
-///
-UINT32 FastStrings:1;
-UINT32 Reserved2:29;
-UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
/**
Unique.
--
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[edk2] [Patch v3 13/14] UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and keep old one.
Changes includes:
1. Change MSR name:
1. MSR_GOLDMONT_SGXOWNER0 => MSR_GOLDMONT_SGXOWNEREPOCH0
2. MSR_GOLDMONT_SGXOWNER1 => MSR_GOLDMONT_SGXOWNEREPOCH1
2. Keep old MSR definition (MSR_GOLDMONT_SGXOWNER0/1) for compatibility.
1. Define old MSR like below style:
#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 34 +++
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
index a9061133c9..383f31ee55 100644
--- a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
@@ -843,10 +843,12 @@ typedef union {
/**
- Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
+ Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+ the package. Lower 64 bits of an 128-bit external entropy value for key
+ derivation of an enclave.
- @param ECX MSR_GOLDMONT_SGXOWNER0 (0x0300)
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x0300)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -854,18 +856,24 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER0);
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);
@endcode
- @note MSR_GOLDMONT_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
+ @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.
**/
-#define MSR_GOLDMONT_SGXOWNER0 0x0300
+#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x0300
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the
SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER0
MSR_GOLDMONT_SGXOWNEREPOCH0
/**
Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
an 128-bit external entropy value for key derivation of an enclave.
- @param ECX MSR_GOLDMONT_SGXOWNER1 (0x0301)
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x0301)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -873,11 +881,17 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER1);
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);
@endcode
- @note MSR_GOLDMONT_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
+ @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.
**/
-#define MSR_GOLDMONT_SGXOWNER1 0x0301
+#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x0301
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the
SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER1
MSR_GOLDMONT_SGXOWNEREPOCH1
/**
--
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[edk2] [Patch v3 07/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.
Changes includes:
1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 64 ++
1 file changed, 64 insertions(+)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 5d2242aa80..b467ffaf26 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -5908,6 +5908,51 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_L3_QOS_CFG_REGISTER;
+/**
+ L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
+
+ @param ECX MSR_IA32_L2_QOS_CFG (0x0C82)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+
+ Example usage
+ @code
+ MSR_IA32_L2_QOS_CFG_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
+ AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
+ @endcode
+ @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
+**/
+#define MSR_IA32_L2_QOS_CFG 0x0C82
+
+/**
+ MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
+/// in Code and Data Prioritization (CDP) mode.
+///
+UINT32 Enable:1;
+UINT32 Reserved1:31;
+UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_IA32_L2_QOS_CFG_REGISTER;
/**
Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
@@ -6380,6 +6425,25 @@ typedef union {
**/
#define MSR_IA32_LSTAR 0xC082
+/**
+ IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
+ instruction is not recognized in compatibility mode. If
+ CPUID.8001:EDX.[29] = 1.
+
+ @param ECX MSR_IA32_CSTAR (0xC083)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ Example usage
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
+ AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
+ @endcode
+ @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
+**/
+#define MSR_IA32_CSTAR 0xC083
/**
System Call Flag Mask (R/W). If CPUID.8001:EDX.[29] = 1.
--
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[edk2] [Patch v3 03/14] UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.
Changes includes:
1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 48 +
1 file changed, 48 insertions(+)
diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index 03bbd0af7c..c3d0f8c208 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -375,6 +375,54 @@ typedef union {
} MSR_SILVERMONT_FSB_FREQ_REGISTER;
+/**
+ Package. Platform Information: Contains power management and other model
+ specific features enumeration. See http://biosbits.org.
+
+ @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x00CE)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+
+ Example usage
+ @code
+ MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);
+ AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SILVERMONT_PLATFORM_INFO 0x00CE
+
+/**
+ MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+UINT32 Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio
+/// of the maximum frequency that does not require turbo. Frequency =
+/// ratio * Scalable Bus Frequency.
+///
+UINT32 MaximumNon_TurboRatio:8;
+UINT32 Reserved2:16;
+UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
+
/**
Module. C-State Configuration Control (R/W) Note: C-state values are
processor specific C-state code names, unrelated to MWAIT extension C-state
--
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[edk2] [Patch v3 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.
V3 changes include:
1. Keep ReservedX not change if bit info not changed for this field.
V2 changes include:
1. Use X in ReservedX fields from totally new value if MSR structure
definition changed.
For example, if in current structure, the max reserved variable is
Reserved2, in new
definition, reserved variable is begin with Reserved3.
V1 Changes includes:
1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index b467ffaf26..22d64e995b 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -4647,7 +4647,14 @@ typedef union {
/// [Bit 3] User.
///
UINT32 User:1;
-UINT32 Reserved1:2;
+///
+/// [Bit 4] PwrEvtEn.
+///
+UINT32 PwrEvtEn:1;
+///
+/// [Bit 5] FUPonPTW.
+///
+UINT32 FUPonPTW:1;
///
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
///
@@ -4672,7 +4679,10 @@ typedef union {
/// [Bit 11] DisRETC.
///
UINT32 DisRETC:1;
-UINT32 Reserved2:1;
+///
+/// [Bit 12] PTWEn.
+///
+UINT32 PTWEn:1;
///
/// [Bit 13] BranchEn.
///
--
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[edk2] [Patch v3 01/14] UefiCpuPkg/Include/Register/Msr: Update reference spec info.
Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4
chapter 2. Current MSR's comments need to be updated to reference the new
chapter info.
Changes includes:
1. Update referenced chapter info from some MSRs.
2. Update referenced SDM version info.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 44 ++---
UefiCpuPkg/Include/Register/Msr/AtomMsr.h| 28 ++--
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 42 ++---
UefiCpuPkg/Include/Register/Msr/CoreMsr.h| 26 +--
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h| 54 +++---
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h| 6 +-
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 34 ++--
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 52 +++---
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 12 +-
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h| 202 +++
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h| 22 +--
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 12 +-
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 49 +++---
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 52 +++---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 14 +-
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h| 8 +-
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 28 ++--
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 6 +-
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 24 +--
21 files changed, 359 insertions(+), 372 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 34fdf5be3a..5d2242aa80 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -16,16 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -33,7 +25,7 @@
#define __ARCHITECTURAL_MSR_H__
/**
- See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
+ See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
@param ECX MSR_IA32_P5_MC_ADDR (0x)
@param EAX Lower 32-bits of MSR value.
@@ -52,7 +44,7 @@
/**
- See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
+ See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@param ECX MSR_IA32_P5_MC_TYPE (0x0001)
@param EAX Lower 32-bits of MSR value.
@@ -91,7 +83,7 @@
/**
- See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /
+ See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
Display Model 05_01H.
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x0010)
@@ -493,9 +485,8 @@ typedef union {
UINT32 Valid:1;
UINT32 Reserved1:1;
///
-/// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
-/// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
-/// unless bit 2 is 1 (the value of bit 0 is irrelevant).
+/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
+/// IA32_VMX_MISC[28].
///
UINT32 BlockSmi:1;
UINT32 Reserved2:9;
@@ -1953,7 +1944,7 @@ typedef union {
/**
- SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
+ SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
IA32_MTRRCAP[SMRR] = 1.
@param ECX MSR_IA32_SMRR_PHYSMASK (0x01F3)
@@ -4417,13 +4408,13 @@
[edk2] [Patch v3 00/14] Update MSR definitions
Current MSR definition are follow the SDM 2016-09 version. The latest SDM is 2018-05. This patch serial update the MSR related definition to follow the latest SDM 2018-05 version. MSR related defintion are saved at UefiCpuPkg\Include\Register\. V3 changes includes: 1. Only change Patch 8 and 14 which changed MSR data structures. 2. Keep ReservedX not change if bit info not changed for this field. V2 changes include: 1. Only change Patch 8 and 14 which changed MSR data structures. 2. Use X in ReservedX fields from totally new value if MSR structure definition changed. For example, if in current structure, the max reserved variable is Reserved2, in new definition, reserved variable is begin with Reserved3. V1 Changes include: The changes for this serial includes: 1. Add new MSR definition and file. 2. Remove old MSR definition which not defined in new SDM. 3. Change MSR name to follow new SDM, keep old one for compatibility. 4. Change MSR data structure definition to follow new SDM. 5. Update comments to follow the new SDM, mainly related to chapter info. Below changes are incompatible changes: 2. Remove old MSR definition which not defined in new SDM. For this one, i search edk2 codebase, not found any code uses it. so no impact for edk2 codebase. Detail changes see patch 9 ~ 11. 4. Change MSR data structure definition to follow new SDM. For this one, new data structure just change the original reserved bits to valid bits, should have no impact for the current code. Detail see patch 8 and patch 14 Cc: Michael D Kinney Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Eric Dong (14): UefiCpuPkg/Include/Register/Msr: Update reference spec info. UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture. UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR. UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR. UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR. UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs. UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR. UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition. UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR. UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR. UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR. UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one. UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and keep old one. UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition. UefiCpuPkg/Include/Register/ArchitecturalMsr.h| 130 +- UefiCpuPkg/Include/Register/Msr.h |7 +- UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 28 +- UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h| 62 +- UefiCpuPkg/Include/Register/Msr/Core2Msr.h| 102 +- UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 74 +- UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 88 +- UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 272 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 62 +- UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 34 +- UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h|8 +- UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 52 +- UefiCpuPkg/Include/Register/Msr/P6Msr.h | 60 +- UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 202 +-- UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 22 +- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 12 +- UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 49 +- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 100 +- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1602 - UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h |8 +- UefiCpuPkg/Include/Register/Msr/XeonDMsr.h| 84 +- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h |6 +- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 332 - 23 files changed, 2816 insertions(+), 580 deletions(-) create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h -- 2.15.0.windows.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [Patch v3 02/14] UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture.
Changes includes:
1. Add new MSR file which used for goldmont plus microarchitecture.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr.h | 7 +-
UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 272 ++
2 files changed, 276 insertions(+), 3 deletions(-)
create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
diff --git a/UefiCpuPkg/Include/Register/Msr.h
b/UefiCpuPkg/Include/Register/Msr.h
index 0ac8d5bdfd..abe0e136de 100644
--- a/UefiCpuPkg/Include/Register/Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
#include
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
new file mode 100644
index 00..d050464b7f
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
@@ -0,0 +1,272 @@
+/** @file
+ MSR Defintions for Intel Atom processors based on the Goldmont Plus
microarchitecture.
+
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+ are provided for MSRs that contain one or more bit fields. If the MSR value
+ returned is a single 32-bit or 64-bit value, then a data structure is not
+ provided for that MSR.
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __GOLDMONT_PLUS_MSR_H__
+#define __GOLDMONT_PLUS_MSR_H__
+
+#include
+
+/**
+ Is Intel Atom processors based on the Goldmont plus microarchitecture?
+
+ @param DisplayFamily Display Family ID
+ @param DisplayModel Display Model ID
+
+ @retval TRUE Yes, it is.
+ @retval FALSE No, it isn't.
+**/
+#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
+ (DisplayFamily == 0x06 && \
+ (\
+DisplayModel == 0x7A\
+) \
+ )
+
+/**
+ Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
+ Sampling (PEBS).".
+
+ @param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x03F1)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+
+ Example usage
+ @code
+ MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
+ @endcode
+**/
+#define MSR_GOLDMONT_PLUS_PEBS_ENABLE0x03F1
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bit 0] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC0.
+///
+UINT32 Fix_Me_1:1;
+///
+/// [Bit 1] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC1.
+///
+UINT32 Fix_Me_2:1;
+///
+/// [Bit 2] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC2.
+///
+UINT32 Fix_Me_3:1;
+///
+/// [Bit 3] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC3.
+
[edk2] [Patch v3 06/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.
Changes includes:
1. Add new MSR definitions.
2. Add support platform info.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1548 +-
1 file changed, 1547 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 866fe30f05..90cde86ccb 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -39,7 +39,11 @@
(DisplayFamily == 0x06 && \
(\
DisplayModel == 0x4E || \
-DisplayModel == 0x5E\
+DisplayModel == 0x5E || \
+DisplayModel == 0x55 || \
+DisplayModel == 0x8E || \
+DisplayModel == 0x9E || \
+DisplayModel == 0x66\
) \
)
@@ -124,6 +128,74 @@ typedef union {
#define MSR_SKYLAKE_LASTBRANCH_TOS 0x01C9
+/**
+ Core. Power Control Register See http://biosbits.org.
+
+ @param ECX MSR_SKYLAKE_POWER_CTL (0x01FC)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+
+ Example usage
+ @code
+ MSR_SKYLAKE_POWER_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
+ AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_POWER_CTL 0x01FC
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+UINT32 Reserved1:1;
+///
+/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
+/// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
+/// point when all execution cores enter MWAIT (C1).
+///
+UINT32 C1EEnable:1;
+UINT32 Reserved2:17;
+///
+/// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
+/// disables the Race to Halt optimization and avoids this optimization
+/// limitation to execute below the most efficient frequency ratio.
+/// Default value is 0 for processors that support Race to Halt
+/// optimization. Default value is 1 for processors that do not support
+/// Race to Halt optimization.
+///
+UINT32 Fix_Me_1:1;
+///
+/// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
+/// disables the P-States energy efficiency optimization. Default value is
+/// 0. Disable/enable the energy efficiency optimization in P-State legacy
+/// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
+/// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
+/// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
+/// desired or OS maximize to the OS minimize performance setting.
+///
+UINT32 DisableEnergyEfficiencyOptimization:1;
+UINT32 Reserved3:11;
+UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_POWER_CTL_REGISTER;
+
+
/**
Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
an 128-bit external entropy value for key derivation of an enclave.
@@ -2254,4 +2326,1478 @@ typedef union {
UINT64 Uint64;
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
+/**
+ Package. NPK Address Used by AET Messages (R/W).
+
+ @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x0080)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+
+ Example usage
+ @code
+ MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
+ AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x0080
+
+/**
+ MSR information returned for MSR index
+ #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
+/// bit has to be set in order for the AET packets to be directed to NPK
+/// MMIO.
+///
+UINT32 Fix_Me_1:1;
+UINT32 Reserved:17;
+///
+/// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+///
+UINT32 ACPIBAR_BASE_ADDRESS:14;
+///
+/// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target
[edk2] [Patch v3 04/14] UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.
Changes includes:
1. Add new MSR: MSR_*_MSRUNCORE_RATIO_LIMIT
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 54 +
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 56 +-
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 56 +-
3 files changed, 164 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 4e50f72008..a7a1967420 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -285,6 +285,60 @@ typedef union {
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
+/**
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x0620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ Example usage
+ @code
+ MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x0620
+
+/**
+ MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+/// LLC/Ring.
+///
+UINT32 MAX_RATIO:7;
+UINT32 Reserved2:1;
+///
+/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+/// possible ratio of the LLC/Ring.
+///
+UINT32 MIN_RATIO:7;
+UINT32 Reserved3:17;
+UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains.".
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index a75bdb2e13..985183b320 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -846,7 +846,61 @@ typedef union {
/**
- Package. Reserved (R/O) Reads return 0.
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x0620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ Example usage
+ @code
+ MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x0620
+
+/**
+ MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+/// LLC/Ring.
+///
+UINT32 MAX_RATIO:7;
+UINT32 Reserved1:1;
+///
+/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+/// possible ratio of the LLC/Ring.
+///
+UINT32 MIN_RATIO:7;
+UINT32 Reserved2:17;
+UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+ Package. Reserved (R/O) Reads return 0.
@param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x0639)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index cf013ea887..6dc4ee999e 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -754,7 +754,61 @@ typ
[edk2] [Patch v3 05/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.
Changes includes:
1. Add new MSR definition:
1. MSR_XEON_PHI_PPIN_CTL
2. MSR_XEON_PHI_PPIN
3. MSR_XEON_PHI_MISC_FEATURE_ENABLES
4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
2. Add DisplayModule == 0x85 supports.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 249 ++-
1 file changed, 246 insertions(+), 3 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index d7aa3ae850..da74c2402c 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -38,7 +38,8 @@
#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
(\
-DisplayModel == 0x57\
+DisplayModel == 0x57 || \
+DisplayModel == 0x85\
) \
)
@@ -85,9 +86,89 @@ typedef union {
UINT64 Uint64;
} MSR_XEON_PHI_SMI_COUNT_REGISTER;
+/**
+ Package. Protected Processor Inventory Number Enable Control (R/W).
+
+ @param ECX MSR_XEON_PHI_PPIN_CTL (0x004E)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+
+ Example usage
+ @code
+ MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
+ AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_PHI_PPIN_CTL0x004E
/**
- Package. See http://biosbits.org.
+ MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
+/// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
+/// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
+/// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
+/// privileged inventory initialization agent to access MSR_PPIN. After
+/// reading MSR_PPIN, the privileged inventory initialization agent should
+/// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
+/// prevent unauthorized modification to MSR_PPIN_CTL.
+///
+UINT32 LockOut:1;
+///
+/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
+/// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
+/// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
+/// Default is 0.
+///
+UINT32 Enable_PPIN:1;
+UINT32 Reserved1:30;
+UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_PPIN_CTL_REGISTER;
+
+
+/**
+ Package. Protected Processor Inventory Number (R/O). Protected Processor
+ Inventory Number (R/O) A unique value within a given CPUID
+ family/model/stepping signature that a privileged inventory initialization
+ agent can access to identify each physical processor, when access to
+ MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
+ MSR_PPIN_CTL[bits 1:0] = '10b'.
+
+ @param ECX MSR_XEON_PHI_PPIN (0x004F)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ Example usage
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
+ @endcode
+**/
+#define MSR_XEON_PHI_PPIN0x004F
+
+/**
+ Package. Platform Information Contains power management and other model
+ specific features enumeration. See http://biosbits.org.
@param ECX MSR_XEON_PHI_PLATFORM_INFO (0x00CE)
@param EAX Lower 32-bits of MSR value.
@@ -317,6 +398,56 @@ typedef union {
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
+/**
+ Thread. MISC_FEATURE_ENABLES.
+
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x0140)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+
+ Example usage
+ @code
+ MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES0x0140
+
+/**
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+UINT32 Reserved1:1;
+///
+/// [Bit 1] User Mode
[edk2] [Patch v2 06/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.
Changes includes:
1. Add new MSR definitions.
2. Add support platform info.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1548 +-
1 file changed, 1547 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 866fe30f05..90cde86ccb 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -39,7 +39,11 @@
(DisplayFamily == 0x06 && \
(\
DisplayModel == 0x4E || \
-DisplayModel == 0x5E\
+DisplayModel == 0x5E || \
+DisplayModel == 0x55 || \
+DisplayModel == 0x8E || \
+DisplayModel == 0x9E || \
+DisplayModel == 0x66\
) \
)
@@ -124,6 +128,74 @@ typedef union {
#define MSR_SKYLAKE_LASTBRANCH_TOS 0x01C9
+/**
+ Core. Power Control Register See http://biosbits.org.
+
+ @param ECX MSR_SKYLAKE_POWER_CTL (0x01FC)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+
+ Example usage
+ @code
+ MSR_SKYLAKE_POWER_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
+ AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_POWER_CTL 0x01FC
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+UINT32 Reserved1:1;
+///
+/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
+/// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
+/// point when all execution cores enter MWAIT (C1).
+///
+UINT32 C1EEnable:1;
+UINT32 Reserved2:17;
+///
+/// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
+/// disables the Race to Halt optimization and avoids this optimization
+/// limitation to execute below the most efficient frequency ratio.
+/// Default value is 0 for processors that support Race to Halt
+/// optimization. Default value is 1 for processors that do not support
+/// Race to Halt optimization.
+///
+UINT32 Fix_Me_1:1;
+///
+/// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
+/// disables the P-States energy efficiency optimization. Default value is
+/// 0. Disable/enable the energy efficiency optimization in P-State legacy
+/// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
+/// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
+/// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
+/// desired or OS maximize to the OS minimize performance setting.
+///
+UINT32 DisableEnergyEfficiencyOptimization:1;
+UINT32 Reserved3:11;
+UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_POWER_CTL_REGISTER;
+
+
/**
Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
an 128-bit external entropy value for key derivation of an enclave.
@@ -2254,4 +2326,1478 @@ typedef union {
UINT64 Uint64;
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
+/**
+ Package. NPK Address Used by AET Messages (R/W).
+
+ @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x0080)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+
+ Example usage
+ @code
+ MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
+ AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x0080
+
+/**
+ MSR information returned for MSR index
+ #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
+/// bit has to be set in order for the AET packets to be directed to NPK
+/// MMIO.
+///
+UINT32 Fix_Me_1:1;
+UINT32 Reserved:17;
+///
+/// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+///
+UINT32 ACPIBAR_BASE_ADDRESS:14;
+///
+/// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target
[edk2] [Patch v2 05/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.
Changes includes:
1. Add new MSR definition:
1. MSR_XEON_PHI_PPIN_CTL
2. MSR_XEON_PHI_PPIN
3. MSR_XEON_PHI_MISC_FEATURE_ENABLES
4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
2. Add DisplayModule == 0x85 supports.
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 249 ++-
1 file changed, 246 insertions(+), 3 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index d7aa3ae850..da74c2402c 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -38,7 +38,8 @@
#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
(\
-DisplayModel == 0x57\
+DisplayModel == 0x57 || \
+DisplayModel == 0x85\
) \
)
@@ -85,9 +86,89 @@ typedef union {
UINT64 Uint64;
} MSR_XEON_PHI_SMI_COUNT_REGISTER;
+/**
+ Package. Protected Processor Inventory Number Enable Control (R/W).
+
+ @param ECX MSR_XEON_PHI_PPIN_CTL (0x004E)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+
+ Example usage
+ @code
+ MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
+ AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_PHI_PPIN_CTL0x004E
/**
- Package. See http://biosbits.org.
+ MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+///
+/// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
+/// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
+/// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
+/// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
+/// privileged inventory initialization agent to access MSR_PPIN. After
+/// reading MSR_PPIN, the privileged inventory initialization agent should
+/// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
+/// prevent unauthorized modification to MSR_PPIN_CTL.
+///
+UINT32 LockOut:1;
+///
+/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
+/// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
+/// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
+/// Default is 0.
+///
+UINT32 Enable_PPIN:1;
+UINT32 Reserved1:30;
+UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_PPIN_CTL_REGISTER;
+
+
+/**
+ Package. Protected Processor Inventory Number (R/O). Protected Processor
+ Inventory Number (R/O) A unique value within a given CPUID
+ family/model/stepping signature that a privileged inventory initialization
+ agent can access to identify each physical processor, when access to
+ MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
+ MSR_PPIN_CTL[bits 1:0] = '10b'.
+
+ @param ECX MSR_XEON_PHI_PPIN (0x004F)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ Example usage
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
+ @endcode
+**/
+#define MSR_XEON_PHI_PPIN0x004F
+
+/**
+ Package. Platform Information Contains power management and other model
+ specific features enumeration. See http://biosbits.org.
@param ECX MSR_XEON_PHI_PLATFORM_INFO (0x00CE)
@param EAX Lower 32-bits of MSR value.
@@ -317,6 +398,56 @@ typedef union {
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
+/**
+ Thread. MISC_FEATURE_ENABLES.
+
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x0140)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+
+ Example usage
+ @code
+ MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES0x0140
+
+/**
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+UINT32 Reserved1:1;
+///
+/// [Bit 1] User Mode
[edk2] [Patch v2 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.
V2 changes include:
1. Use X in ReservedX fields from totally new value if MSR structure definition
changed.
For example, if in current structure, the max reserved variable is
Reserved2, in new
definition, reserved variable is begin with Reserved3.
V1 Changes includes:
1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER
Cc: Michael D Kinney
Cc: Ruiyu Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index b467ffaf26..3be0c31c68 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -4647,7 +4647,14 @@ typedef union {
/// [Bit 3] User.
///
UINT32 User:1;
-UINT32 Reserved1:2;
+///
+/// [Bit 4] PwrEvtEn.
+///
+UINT32 PwrEvtEn:1;
+///
+/// [Bit 5] FUPonPTW.
+///
+UINT32 FUPonPTW:1;
///
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
///
@@ -4672,7 +4679,10 @@ typedef union {
/// [Bit 11] DisRETC.
///
UINT32 DisRETC:1;
-UINT32 Reserved2:1;
+///
+/// [Bit 12] PTWEn.
+///
+UINT32 PTWEn:1;
///
/// [Bit 13] BranchEn.
///
@@ -4681,17 +4691,17 @@ typedef union {
/// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
///
UINT32 MTCFreq:4;
-UINT32 Reserved3:1;
+UINT32 Reserved7:1;
///
/// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
UINT32 CYCThresh:4;
-UINT32 Reserved4:1;
+UINT32 Reserved8:1;
///
/// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
UINT32 PSBFreq:4;
-UINT32 Reserved5:4;
+UINT32 Reserved9:4;
///
/// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
///
@@ -4708,7 +4718,7 @@ typedef union {
/// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
///
UINT32 ADDR3_CFG:4;
-UINT32 Reserved6:16;
+UINT32 Reserved10:16;
} Bits;
///
/// All bit fields as a 64-bit value
--
2.15.0.windows.1
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