[edk2] [Patch] Vlv2TbltDevicePkg: ECP Cleanup.

[zwei4]

Remove modules of EdkCompatibilityPkg from DSC/FDF of Vlv2TbltDevicePkg to make 
this platform ECP free.

Test: Boot to 64-bit Windows 10.

Cc: Zailiang Sun 
Cc: Yi Qian 
Cc: Michael Kinney 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
---
 Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c  |  8 +-
 Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf|  4 +-
 Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c|  8 +-
 Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf  |  4 +-
 Vlv2TbltDevicePkg/PlatformPei/BootMode.c   | 56 +
 Vlv2TbltDevicePkg/PlatformPei/PlatformPei.inf  |  4 +-
 Vlv2TbltDevicePkg/PlatformPkg.fdf  | 11 +--
 Vlv2TbltDevicePkg/PlatformPkgGcc.fdf   | 10 ---
 Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc| 87 -
 Vlv2TbltDevicePkg/PlatformPkgIA32.dsc  | 91 +-
 Vlv2TbltDevicePkg/PlatformPkgX64.dsc   | 87 -
 Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf  |  6 +-
 Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c | 10 +--
 .../VlvPlatformInitDxe/VlvPlatformInitDxe.inf  |  6 +-
 14 files changed, 30 insertions(+), 362 deletions(-)

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c 
b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
index 4a913eb723..d575533319 100644
--- a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2004  - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2004  - 2018, Intel Corporation. All rights reserved.
 
 
   This program and the accompanying materials are licensed and made available 
under
@@ -35,7 +35,7 @@ Abstract:
 
 #include 
 #include 
-#include 
+#include 
 #include "AcpiPlatform.h"
 #include "AcpiPlatformHooks.h"
 #include "AcpiPlatformHooksLib.h"
@@ -785,7 +785,7 @@ AcpiPlatformEntryPoint (
   EFI_STATUSStatus;
   EFI_STATUSAcpiStatus;
   EFI_ACPI_SUPPORT_PROTOCOL *AcpiSupport;
-  EFI_FIRMWARE_VOLUME_PROTOCOL  *FwVol;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL  *FwVol;
   INTN  Instance;
   EFI_ACPI_COMMON_HEADER*CurrentTable;
   UINTN TableHandle;
@@ -856,7 +856,7 @@ AcpiPlatformEntryPoint (
   //
   // Locate the firmware volume protocol.
   //
-  Status = LocateSupportProtocol (, (VOID **) 
, 1);
+  Status = LocateSupportProtocol (, (VOID **) 
, 1);
   ASSERT_EFI_ERROR (Status);
 
   //
diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf 
b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
index 24fa913b33..74a531369d 100644
--- a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
@@ -1,6 +1,6 @@
 #
 #
-# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+# Copyright (c)  1999  - 2018, Intel Corporation. All rights reserved
 #  


 # This program and the accompanying materials are licensed and made available 
under

 # the terms and conditions of the BSD License that accompanies this 
distribution.  

@@ -77,7 +77,7 @@
   gEfiMpServiceProtocolGuid
   gEfiGlobalNvsAreaProtocolGuid
   gEfiTcgProtocolGuid
-  gEfiFirmwareVolumeProtocolGuid
+  gEfiFirmwareVolume2ProtocolGuid
   gIgdOpRegionProtocolGuid
 
 [Pcd]
diff --git a/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c 
b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
index 08f5df2a25..27ae9de7a0 100644
--- a/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
+++ b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
@@ -36,7 +36,7 @@ Abstract:
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 
@@ -66,12 +66,12 @@ GetRawImage (
   EFI_HANDLE*HandleBuffer;
   UINTN HandleCount;
   UINTN Index;
-  EFI_FIRMWARE_VOLUME_PROTOCOL  *Fv;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL  *Fv;
   UINT32AuthenticationStatus;
 
   Status = gBS->LocateHandleBuffer (
   ByProtocol,
-  ,
+  ,
   NULL,
   ,
   
@@ -86,7 +86,7 @@ GetRawImage (
   for (Index = 0; Index < HandleCount; Index++) {
 Status = gBS->HandleProtocol(
 HandleBuffer[Index],
-,
+,
 (VOID **) 
 );
 
diff --git a/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf 
b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
index a296c24b75..ce3140f830 100644
--- a/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
+++ b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
@@ -1,6 +1,6 @@
 #/*++
 #
-# Copyright (c)  2003  - 2014, Intel Corporation. All rights reserved
+# Copyright (c)  2003  - 2018, Intel Corporation. All rights reserved
 #

[edk2] [Patch] Vlv2TbltDevicePkg: Add build instructions for Minnowboard Max.

[zwei4]

Add build instructions for Minnowboard Max platform on edk2 master. Change 
stitching script to follow this new build instructions.

Test: Boot to Windows 10.

Cc: Zailiang Sun 
Cc: Yi Qian 
Cc: Michael Kinney 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
---
 Vlv2TbltDevicePkg/Documents/BuildInstructions.txt | 128 ++
 Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat   |   2 +-
 2 files changed, 129 insertions(+), 1 deletion(-)
 create mode 100644 Vlv2TbltDevicePkg/Documents/BuildInstructions.txt

diff --git a/Vlv2TbltDevicePkg/Documents/BuildInstructions.txt 
b/Vlv2TbltDevicePkg/Documents/BuildInstructions.txt
new file mode 100644
index 00..a03c6ce3c4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Documents/BuildInstructions.txt
@@ -0,0 +1,128 @@
+## @file
+# Build Instructions for Minnowboard Max platform on edk2 master. 
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+#
+##
+
+
+  HOW TO CREATE A FULL SOURCE TREE
+
+1) Create a new folder (directory) on the root of your local hard drive 
(development
+   machine) for use as your work space (this example uses "C:\MyWorkspace").
+   Some paths are very long and placing the working directory too deep in the 
directory 
+   structure may cause the path to be longer than Windows maximum path length.
+
+2) Checkout edk2 from GitHub with the following command.
+i)  Run "git clone https://github.com/tianocore/edk2.git;
+* This step will created a new folder C:\MyWorkspace\edk2, which holds 
edk2 source code downloaded.
+
+5) Download MinnowBoard MAX Binary Object Modules from : (To be updated)
+   
https://firmware.intel.com/sites/default/files/MinnowBoard_MAX-0.97-Binary.Objects.zip
+
+   The MinnowBoard MAX Binary Object Modules contain three additional
+   folders required for the full source tree.
+
+IA32FamilyCpuPkg
+Vlv2BinaryPkg
+Vlv2MiscBinariesPkg
+
+   Copy above 3 packages into "C:\MyWorkspace\edk2".
+
+
+6) Follow the instructions found in the file "OpenSSL-HOWTO.txt" located in 
your
+   workspace (e.g. 
"C:\MyWorkspace\edk2\CryptoPkg\Library\OpensslLib\OpenSSL-HOWTO.txt")
+   to install the Openssl source code.
+  
+
+  HOW TO BUILD (WINDOWS ENVIRONMENT)
+
+Windows System Configuration:
+  Microsoft Windows 10 Enterprise 64-bit*
+
+   Note: Below steps could also apply to Microsoft Windows 8.1 and other 
version of Windows 10,
+ but Intel only verify these steps on Microsoft Windows 10 Enterprise 
64-bit*.
+
+1. Setup Build Environment
+   1) Install C compiler Microsoft Visual Studio 2015 with Update 3 in the 
build machine
+
+  Note: Visual Studio 2008, 2010, 2012 and 2013 are also supported, but 
Intel only verify
+with VS2015.
+
+   2) Obtain and install Python 2.7.10 from: 
https://www.python.org/downloads/release/python-2710/
+  Make sure that a file with the extension of ".py" will be opened by 
Python.exe.
+
+2. Extract Source Code
+   1) Follow the instructions of "HOW TO CREATE A FULL SOURCE TREE" (step 
above)
+  to create a full source tree.
+
+3. Install the iasl compiler by downloading iasl-win-20160527.zip from the 
following
+   location: "https://acpica.org/downloads/; and place the unzipped
+   content ("iasl.exe") into the directory "C:\ASL" on your local hard drive
+   (create the folder "C:\ASL" if it does not exist).
+
+4. Install the NASM* assembly language compiler:
+   Download NASM* 2.12.02 binaries from 
+   
http://www.nasm.us/pub/nasm/releasebuilds/2.12.02/win64/nasm-2.12.02-win64.zip 
and place the
+   unzipped content ("nasm.exe") into the directory "C:\NASM" on your local 
hard drive
+   (create the folder "C:\NASM" if it does not exist).
+
+5. Download a pre-compiled Openssl Windows binary from 
+   https://wiki.openssl.org/index.php/Binaries. Search for a Windows binary in 
the list 
+   of "Third Party OpenSSL Related Binary Distributions". Go to the third 
party site to 
+   download the latest version. Download and extract to C:\Openssl, add the 
path of openssl.exe 
+   ("C:\openssl") to system environment variable OPENSSL_PATH.
+
+6a. Build Steps (32-bit)
+   1) To build a 32-bit release 

[edk2] [Patch] Vlv2TbltDevicePkg:Fix build and boot failure of Minnowboard Max platform.

[zwei4]

Remove the duplicated IScsiDxe driver from FDF; Add required shell libraries; 
Update SYSTEM_CONFIGURATION data structure.

Test: Install and boot Windows 10.

Cc: Zailiang Sun 
Cc: Yi Qian 
Cc: Michael Kinney 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
---
 Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h | 5 -
 Vlv2TbltDevicePkg/PlatformPkg.fdf  | 1 -
 Vlv2TbltDevicePkg/PlatformPkgGcc.fdf   | 1 -
 Vlv2TbltDevicePkg/PlatformPkgX64.dsc   | 2 ++
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h 
b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
index d9ac9f79e1..b37be5ca6f 100644
--- a/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
+++ b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2004  - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2004  - 2018, Intel Corporation. All rights reserved.
 
 
   This program and the accompanying materials are licensed and made available 
under
@@ -1310,6 +1310,9 @@ typedef struct {
   UINT8   GpioWakeCapability;
   UINT8   RtcBattery;
   UINT8   LpeAudioReportedByDSDT;
+  
+  UINT8   Uart1Int3511Com; // Report UART1 as COM with _HID INT3511
+  CHAR16  SystemUuid[37];
 
 } SYSTEM_CONFIGURATION;
 #pragma pack()
diff --git a/Vlv2TbltDevicePkg/PlatformPkg.fdf 
b/Vlv2TbltDevicePkg/PlatformPkg.fdf
index f976b9fa40..0d13ad9f56 100644
--- a/Vlv2TbltDevicePkg/PlatformPkg.fdf
+++ b/Vlv2TbltDevicePkg/PlatformPkg.fdf
@@ -743,7 +743,6 @@ FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA {
   INF  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
   INF  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
   INF  NetworkPkg/TcpDxe/TcpDxe.inf
-  INF  NetworkPkg/IScsiDxe/IScsiDxe.inf
   !if $(NETWORK_IP6_ENABLE) == TRUE
   INF  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
   INF  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
diff --git a/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf 
b/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
index 50032f7d5f..847286328a 100644
--- a/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
+++ b/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
@@ -699,7 +699,6 @@ FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA {
   INF  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
   INF  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
   INF  NetworkPkg/TcpDxe/TcpDxe.inf
-  INF  NetworkPkg/IScsiDxe/IScsiDxe.inf
   !if $(NETWORK_IP6_ENABLE) == TRUE
   INF  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
   INF  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
diff --git a/Vlv2TbltDevicePkg/PlatformPkgX64.dsc 
b/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
index 81f36bd73b..ccdd856cee 100644
--- a/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
+++ b/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
@@ -283,6 +283,8 @@
 !endif
   ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
   ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+  
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
   FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
   SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
 !if $(FTPM_ENABLE) == TRUE || $(NETWORK_ISCSI_ENABLE) == TRUE
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Change BIOS Version.

[zwei4]

From: Bright 

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sun, Zailiang 
CC: David Wei 
---
 Vlv2TbltDevicePkg/BiosId.env | 2 +-
 Vlv2TbltDevicePkg/BiosIdD.env| 2 +-
 Vlv2TbltDevicePkg/BiosIdR.env| 2 +-
 Vlv2TbltDevicePkg/BiosIdx64D.env | 2 +-
 Vlv2TbltDevicePkg/BiosIdx64R.env | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Vlv2TbltDevicePkg/BiosId.env b/Vlv2TbltDevicePkg/BiosId.env
index 35314db780..dfdcb34f41 100644
--- a/Vlv2TbltDevicePkg/BiosId.env
+++ b/Vlv2TbltDevicePkg/BiosId.env
@@ -24,6 +24,6 @@
 BOARD_ID  = MNW2MAX
 BOARD_REV = 1
 BUILD_TYPE= D
-VERSION_MAJOR = 0099
+VERSION_MAJOR = 0100
 VERSION_MINOR = 01
 BOARD_EXT = X64
diff --git a/Vlv2TbltDevicePkg/BiosIdD.env b/Vlv2TbltDevicePkg/BiosIdD.env
index 0e8f680a69..e3bd0053b6 100644
--- a/Vlv2TbltDevicePkg/BiosIdD.env
+++ b/Vlv2TbltDevicePkg/BiosIdD.env
@@ -35,5 +35,5 @@ OEM_ID= I32
 BUILD_TYPE= D
 
 BOARD_ID = BLAKCRB
-VERSION_MAJOR = 0099
+VERSION_MAJOR = 0100
 VERSION_MINOR = 01
diff --git a/Vlv2TbltDevicePkg/BiosIdR.env b/Vlv2TbltDevicePkg/BiosIdR.env
index 1ba47cbc05..4629c44d14 100644
--- a/Vlv2TbltDevicePkg/BiosIdR.env
+++ b/Vlv2TbltDevicePkg/BiosIdR.env
@@ -35,5 +35,5 @@ OEM_ID= I32
 BUILD_TYPE= R
 
 BOARD_ID = BLAKCRB
-VERSION_MAJOR = 0099
+VERSION_MAJOR = 0100
 VERSION_MINOR = 01
diff --git a/Vlv2TbltDevicePkg/BiosIdx64D.env b/Vlv2TbltDevicePkg/BiosIdx64D.env
index ba9ce76f63..902820b6c3 100644
--- a/Vlv2TbltDevicePkg/BiosIdx64D.env
+++ b/Vlv2TbltDevicePkg/BiosIdx64D.env
@@ -25,6 +25,6 @@ BOARD_REV = 1
 OEM_ID= X64
 BUILD_TYPE= D
 
-VERSION_MAJOR = 0099
+VERSION_MAJOR = 0100
 VERSION_MINOR = 01
 BOARD_ID = BBAYCRB 
diff --git a/Vlv2TbltDevicePkg/BiosIdx64R.env b/Vlv2TbltDevicePkg/BiosIdx64R.env
index 4ccb2a0583..7d06cf5bae 100644
--- a/Vlv2TbltDevicePkg/BiosIdx64R.env
+++ b/Vlv2TbltDevicePkg/BiosIdx64R.env
@@ -25,6 +25,6 @@ BOARD_REV = 1
 OEM_ID= X64
 BUILD_TYPE= R
 
-VERSION_MAJOR = 0099
+VERSION_MAJOR = 0100
 VERSION_MINOR = 01
 BOARD_ID = BBAYCRB 
-- 
2.19.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Disable DCI.

[zwei4]

Disable DCI which allows debug over USB3.0.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi   | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
index 9738e4d912..2211f56a29 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -163,8 +163,8 @@ form formid = MISC_OPTIONS_FORM_ID,
   oneof varid = Setup.DciEn,
 prompt   = STRING_TOKEN(STR_DCI_HDCIEN_PROMPT),
 help = STRING_TOKEN(STR_DCI_HDCIEN_HELP),
-option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =  
RESET_REQUIRED;
-option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =  DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
   endoneof;
 
   suppressif ideqval Setup.DciEn == 1;
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Setup Cleanup

[zwei4]

Remove TPM setup option. Add fixed PCD 
gPlatformModuleTokenSpaceGuid.PcdTpmControl to enable/disable TPM at build-time.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
CC: Steele Kelly 
---
 .../Common/Include/Guid/SetupVariable.h|  2 +-
 .../PeiPlatformConfigUpdateLib.c   | 36 +---
 .../PlatformPostMemPei/PlatformInit.c  | 15 +++--
 .../PlatformPostMemPei/PlatformPostMemPei.inf  |  3 +-
 .../PlatformSetupDxe/PlatformSetupDxe.c|  7 +--
 .../PlatformSettings/PlatformSetupDxe/Security.vfi | 25 +++--
 .../PlatformSetupDxe/SetupInfoRecords.c| 64 +-
 Platform/BroxtonPlatformPkg/PlatformPkg.dec|  4 ++
 8 files changed, 26 insertions(+), 130 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h 
b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
index 19b948c0ea..2d81068778 100644
--- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
+++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
@@ -480,7 +480,7 @@ typedef struct {
   UINT8 PanelScaling;
   UINT8 IgdLcdIGmchBlc;
   UINT8 SecEnable;
-  UINT8 TPM;
+  UINT8 TPMReserved;
   UINT8 TPMSupportedBanks;
   UINT8 TpmDetection;
   UINT8 PttSuppressCommandSend;  // For PTT Debug
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
index a003b278b4..b62db3ae8d 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
@@ -2,7 +2,7 @@
   Platform Configuration Update library implementation file.
   This library updates the setup data with platform overrides.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -30,37 +30,6 @@
 #define SETUP_NFC_IPT  1
 #define SETUP_NFC  2
 
-EFI_STATUS
-TpmSetupPolicyInit (
-  IN SYSTEM_CONFIGURATION*SystemConfiguration
-  )
-{
-#if FTPM_SUPPORT
-  EFI_STATUS   Status;
-  BOOLEAN  PttEnabledState = FALSE;
-  EFI_HOB_GUID_TYPE*FdoEnabledGuidHob = NULL;
-
-  FdoEnabledGuidHob = GetFirstGuidHob ();
-
-  if (SystemConfiguration->TpmDetection == 0) {
-Status = PttHeciGetState ();
-if (EFI_ERROR (Status)) {
-  DEBUG ((DEBUG_ERROR, "Get PTT enabled state failed.\n"));
-}
-
-if (PttEnabledState && (FdoEnabledGuidHob == NULL)) {
-  SystemConfiguration->TPM = TPM_PTT;
-} else {
-  DEBUG ((EFI_D_INFO, "TpmPolicyInit-TPM and TpmDetection is disabled 
because of FDO \n\r"));
-  SystemConfiguration->TPM = TPM_DISABLE;
-}
-SystemConfiguration->TpmDetection = 1;
-  }
-
-#endif
-  return EFI_SUCCESS;
-}
-
 
 EFI_STATUS
 GetSecureNfcInfo (
@@ -189,9 +158,6 @@ UpdateSetupDataValues (
   Status = GetSecureNfcInfo (PreDefaultSetupData);
   ASSERT_EFI_ERROR (Status);
 
-  Status = TpmSetupPolicyInit (PreDefaultSetupData);
-  ASSERT_EFI_ERROR (Status);
-
   return Status;
 }
 
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
index acaaebbfbb..412304b158 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
@@ -76,19 +76,22 @@ TpmPolicyInit (
   EFI_STATUS  Status;
   UINTN   Size;
   BOOLEAN IsPttEnabled = TRUE;
-  MBP_ME_FW_CAPS  Mbp_Me_Fw_Caps = { 0 };
+  MBP_ME_FW_CAPS  MbpMeFwCaps = { 0 };
+  UINT8   TpmControl;
 
   DEBUG ((EFI_D_ERROR, "TpmPolicyInit entry.\n"));
 
+  TpmControl = PcdGet8(PcdTpmControl);
+  
   //
   // Get ME FW Capability from MBP table to determine PTT State
   //
-  Status = HeciGetMeFwCapability (_Me_Fw_Caps);
+  Status = HeciGetMeFwCapability ();
   if (!EFI_ERROR (Status)) {
-IsPttEnabled = (BOOLEAN) Mbp_Me_Fw_Caps.CurrentFeatures.Fields.PTT;
+IsPttEnabled = (BOOLEAN) MbpMeFwCaps.CurrentFeatures.Fields.PTT;
   }
 
-  if ((IsPttEnabled) && (SystemConfiguration->TPM == TPM_PTT)) {
+  if ((IsPttEnabled) && (TpmControl == TPM_PTT)) {
 if (SystemConfiguration->PttSuppressCommandSend == 1) {
   Size = sizeof (gEfiTpmDeviceInstanceNoneGuid);
   PcdSetPtrS (PcdTpmInstanceGuid, , );
@@ -101,14 +104,14 @@ 

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Cleanup Setup Option

[zwei4]

Remove SecureBoot setup option.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
CC: Steele Kelly 
---
 .../Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c | 11 +-
 .../Smbios/SmBiosMiscDxe/SmBiosMiscDxe.inf |  1 +
 .../Common/Include/Guid/SetupVariable.h|  2 +-
 .../PeiPlatformConfigUpdateLib.c   |  3 +-
 .../PlatformSettings/PlatformSetupDxe/Boot.vfi |  7 
 .../PlatformSetupDxe/PlatformSetupDxe.c|  1 -
 .../PlatformSetupDxe/SetupInfoRecords.c| 45 --
 7 files changed, 13 insertions(+), 57 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c
 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c
index b399a5f81b..e96e3fb5a0 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c
@@ -548,6 +548,7 @@ UpdatePlatformInformation (
   MRC_PARAMS_SAVE_RESTORE  *MemInfoHob = NULL;
   UINT32   MrcVersion;
   UINTNIndex;
+  UINT8SecureBoot;
 
   DEBUG ((EFI_D_INFO, "Executing SMBIOS T0x94 Update.\n"));
   //
@@ -666,10 +667,18 @@ UpdatePlatformInformation (
   );
   ASSERT_EFI_ERROR (Status);
 
+  DataSize = sizeof (SecureBoot);
+  Status = gRT->GetVariable (
+  EFI_SECURE_BOOT_MODE_NAME,
+  ,
+  NULL,
+  ,
+  
+  );
   //
   // Secure boot
   //
-  Data8 = SystemConfiguration.SecureBoot;
+  Data8 = SecureBoot;
   UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
   HiiSetString (mHiiHandle, STRING_TOKEN (STR_MISC_SECURE_BOOT_VALUE), Buffer, 
NULL);
 
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/SmBiosMiscDxe.inf
 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/SmBiosMiscDxe.inf
index 31fd8406b2..6de2d68b57 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/SmBiosMiscDxe.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/SmBiosMiscDxe.inf
@@ -120,6 +120,7 @@
   gIFWIVersionHobGuid
   gEfiPlatformInfoGuid
   gFspNonVolatileStorageHobGuid  ##CONSUMES
+  gEfiGlobalVariableGuid
 
 [Protocols]
   gEfiSmbiosProtocolGuid# PROTOCOL ALWAYS_CONSUMED
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h 
b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
index 4f5eeb1c0f..19b948c0ea 100644
--- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
+++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
@@ -474,7 +474,7 @@ typedef struct {
   UINT8 CapOrVoltFlag;
   UINT8 BootOnInvalidBatt;
   UINT8 ScramblerSupport;
-  UINT8 SecureBoot;
+  UINT8 SecureBootReserved;
   UINT8 SecureBootCustomMode;
   UINT8 MaxPkgCState;
   UINT8 PanelScaling;
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
index f56097f3a7..a003b278b4 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiPlatformConfigUpdateLib/PeiPlatformConfigUpdateLib.c
@@ -181,10 +181,9 @@ UpdateSetupDataValues (
   }
 
   if (FdoEnabledGuidHob != NULL) {
-PreDefaultSetupData->SecureBoot = FALSE;
 PreDefaultSetupData->FprrEnable = FALSE;
 PreDefaultSetupData->ScBiosLock = FALSE;
-DEBUG ((EFI_D_INFO, "SPI FDO mode is enabled. Disabling SecureBoot, 
FprrEnable, and ScBiosLock.\n"));
+DEBUG ((EFI_D_INFO, "SPI FDO mode is enabled. Disabling FprrEnable, and 
ScBiosLock.\n"));
   }
 
   Status = GetSecureNfcInfo (PreDefaultSetupData);
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Boot.vfi 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Boot.vfi
index 6b6f262efd..c04d8d6a2a 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Boot.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Boot.vfi
@@ -44,13 +44,6 @@ form formid = BOOT_CONFIGURATION_FORM_ID,
   endoneof;
   endif; // suppressif
 
-  oneof varid  = Setup.SecureBoot,
-prompt   = STRING_TOKEN(STR_SECURITY_BOOT_PROMPT),
-help = STRING_TOKEN(STR_SECURITY_BOOT_HELP),
-option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
-option text = STRING_TOKEN(STR_ENABLE),  value=1, flags=0 | RESET_REQUIRED;
-  endoneof;
-
   oneof varid  = 

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Leaf Hill eMMC Speed.

[zwei4]

UDK2018 eMMC driver may fail to switch eMMC to HS400 mode. This platform 
temporary solution limits eMMC controller to maximal HS200 mode.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c  | 12 ++--
 .../Board/LeafHill/BoardInitPostMem/BoardInitMiscs.h | 10 +-
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
index 729b15f966..f0f89f3867 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
@@ -1,7 +1,7 @@
 /** @file
   Board Init driver.
 
-  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -60,6 +60,7 @@ LeafHillPostMemInitCallback (
   UINT8ResetType;
   UINTNBufferSize;
   UINT8MaxPkgCState;
+  UINT8MaxSpeed;
   UINTNVariableSize;
   EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariableServices;
   SYSTEM_CONFIGURATION SystemConfiguration;
@@ -135,7 +136,14 @@ LeafHillPostMemInitCallback (
   //
   // Set PcdeMMCHostMaxSpeed
   //
-  PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) 
(SystemConfiguration.ScceMMCHostMaxSpeed));
+
+  if ((SystemConfiguration.ScceMMCHostMaxSpeed == 0) || 
(SystemConfiguration.ScceMMCHostMaxSpeed == 1)) {
+MaxSpeed = EMMC_HS200_MODE;
+PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) MaxSpeed);
+  } else {
+MaxSpeed = EMMC_DDR50_MODE;
+PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) MaxSpeed);
+  }
 
   //
   // HDA audio verb table
diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitMiscs.h 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitMiscs.h
index c1ba128709..da7ccd39ba 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitMiscs.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitMiscs.h
@@ -2,7 +2,7 @@
   Multiplatform initialization header file.
   This file includes package header files, library classes.
 
-  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -92,6 +92,14 @@
 #define MAX_PKG_CSTATE_C0 0x00
 #define MAX_PKG_CSTATE_C1 0x01
 #define MAX_PKG_CSTATE_C2 0x02
+
+//
+// eMMCHostMaxSpeed identifier.
+//
+#define EMMC_HS400_MODE   0x00
+#define EMMC_HS200_MODE   0x01
+#define EMMC_DDR50_MODE   0x02
+
 EFI_STATUS
 LeafHillGetPlatformInfoHob (
   IN CONST EFI_PEI_SERVICES **PeiServices,
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Logo Update.

[zwei4]

(1) Update EDK2 TianoCore logo to the latest.
(2) Extend logo showing period to the late stage of BDS.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../AuroraGlacier/BoardInitPostMem/BoardInit.c |   2 +-
 .../BoardInitPostMem/BoardInitPostMem.inf  |   2 +-
 .../BensonGlacier/BoardInitPostMem/BoardInit.c |   2 +-
 .../BoardInitPostMem/BoardInitPostMem.inf  |   2 +-
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c|   2 +-
 .../LeafHill/BoardInitPostMem/BoardInitPostMem.inf |   2 +-
 .../MinnowBoard3/BoardInitPostMem/BoardInit.c  |   2 +-
 .../BoardInitPostMem/BoardInitPostMem.inf  |   2 +-
 .../BoardInitPostMem/BoardInit.c   |   2 +-
 .../BoardInitPostMem/BoardInitPostMem.inf  |   2 +-
 .../Board/UP2/BoardInitPostMem/BoardInit.c |   2 +-
 .../UP2/BoardInitPostMem/BoardInitPostMem.inf  |   2 +-
 .../Common/Binaries/Logo/Tianocore.bmp | Bin 0 -> 11958 bytes
 .../Common/Library/DxeLogoLib/DxeLogoLib.inf   |   1 -
 .../Common/Library/DxeLogoLib/Logo.c   | 299 -
 .../PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf|   1 -
 .../PlatformBootManagerLib/PlatformBootManager.c   |  10 +-
 .../PlatformBootManagerLib.inf |   4 +-
 Platform/BroxtonPlatformPkg/PlatformPkg.dec|   3 +-
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf|  13 +-
 20 files changed, 83 insertions(+), 272 deletions(-)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Binaries/Logo/Tianocore.bmp

diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
index 302edb8301..ce98086895 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
@@ -110,7 +110,7 @@ AuroraGlacierPostMemInitCallback (
   //
   BufferSize = sizeof (EFI_GUID);
   PcdSetPtr(PcdBoardVbtFileGuid, , (UINT8 
*));
-  PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 *));
+  PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 
*)PcdGetPtr(PcdTianoCoreLogoFileGuid));
 
   //
   // Set PcdSueCreek
diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
index 8fe5ea7e95..c619332cb1 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -64,6 +64,7 @@
   gPlatformModuleTokenSpaceGuid.PcdResetType
   gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
   gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid
+  gPlatformModuleTokenSpaceGuid.PcdTianoCoreLogoFileGuid
   gPlatformModuleTokenSpaceGuid.PcdSueCreek
   gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState
   gPlatformModuleTokenSpaceGuid.PcdTi3100AudioCodecEnable
@@ -85,7 +86,6 @@
   gEfiTpmDeviceInstanceTpm20DtpmGuid
   gTpmDeviceInstanceTpm20PttPtpGuid
   gPeiAuroraGlacierVbtGuid
-  gPeiLogoGuid
 
 [Ppis]
   gBoardPostMemInitStartGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index 60d2324d95..856d7739b0 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -110,7 +110,7 @@ BensonGlacierPostMemInitCallback (
   //
   BufferSize = sizeof (EFI_GUID);
   PcdSetPtr(PcdBoardVbtFileGuid, , (UINT8 
*));
-  PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 *));
+  PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 
*)PcdGetPtr(PcdTianoCoreLogoFileGuid));
 
   //
   // Set PcdSueCreek
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
index 782bf0d2bd..01d7f27898 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -64,6 +64,7 @@
   gPlatformModuleTokenSpaceGuid.PcdResetType
   gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
   gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid
+  gPlatformModuleTokenSpaceGuid.PcdTianoCoreLogoFileGuid
   gPlatformModuleTokenSpaceGuid.PcdSueCreek
   gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState
   gPlatformModuleTokenSpaceGuid.PcdTi3100AudioCodecEnable
@@ -85,7 +86,6 @@
   gEfiTpmDeviceInstanceTpm20DtpmGuid
   gTpmDeviceInstanceTpm20PttPtpGuid
   gPeiBensonGlacierVbtGuid
-  gPeiLogoGuid
 
 [Ppis]
   gBoardPostMemInitStartGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c 

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] BIOS Logo.

[zwei4]

Show EDK2 TianoCore log rather than Intel logo.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c | 4 ++--
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf| 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c
index de07429eb2..bf607d6b11 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c
@@ -119,8 +119,8 @@ Up2PostMemInitCallback (
   //
   BufferSize = sizeof (EFI_GUID);
   PcdSetPtr(PcdBoardVbtFileGuid, , (UINT8 *));
-  //PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 *));
-  
+  PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 *));
+
   //
   // Set PcdSueCreek
   //
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf 
b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
index 05cf299a0a..2ea7e09582 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
@@ -245,7 +245,7 @@
   
 !if $(PEI_DISPLAY_ENABLE) == TRUE
   FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
-SECTION RAW = $(PLATFORM_PACKAGE_COMMON)/Binaries/Logo/Logo.bmp
+SECTION RAW = MdeModulePkg/Logo/Logo.bmp
   }
   
   # VBT For Leaf Hill (File Guid is gPeiLeafHillVbtGuid)
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] BIOS Logo Change.

[zwei4]

Add board specific code to show OEM specific logo.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Board/AuroraGlacier/BoardInitPostMem/BoardInit.c   | 1 +
 .../Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf  | 2 ++
 .../Board/BensonGlacier/BoardInitPostMem/BoardInit.c   | 1 +
 .../Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf  | 2 ++
 .../BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c | 1 +
 .../Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf   | 2 ++
 .../BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInit.c | 1 +
 .../Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf   | 2 ++
 .../Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.c  | 3 ++-
 .../Board/MinnowBoard3Module/BoardInitPostMem/BoardInitPostMem.inf | 2 ++
 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c | 1 +
 .../BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostMem.inf | 2 ++
 .../Common/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 1 +
 .../Common/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c | 3 ++-
 .../Common/PlatformSettings/PlatformPostMemPei/PlatformPostMemPei.inf  | 1 +
 Platform/BroxtonPlatformPkg/PlatformPkg.dec| 3 +++
 16 files changed, 26 insertions(+), 2 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
index 2f33bfe21e..302edb8301 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
@@ -110,6 +110,7 @@ AuroraGlacierPostMemInitCallback (
   //
   BufferSize = sizeof (EFI_GUID);
   PcdSetPtr(PcdBoardVbtFileGuid, , (UINT8 
*));
+  PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 *));
 
   //
   // Set PcdSueCreek
diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
index 73205d7e79..8fe5ea7e95 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -63,6 +63,7 @@
   gPlatformModuleTokenSpaceGuid.PcdFabId
   gPlatformModuleTokenSpaceGuid.PcdResetType
   gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
+  gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid
   gPlatformModuleTokenSpaceGuid.PcdSueCreek
   gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState
   gPlatformModuleTokenSpaceGuid.PcdTi3100AudioCodecEnable
@@ -84,6 +85,7 @@
   gEfiTpmDeviceInstanceTpm20DtpmGuid
   gTpmDeviceInstanceTpm20PttPtpGuid
   gPeiAuroraGlacierVbtGuid
+  gPeiLogoGuid
 
 [Ppis]
   gBoardPostMemInitStartGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index aabb350e85..60d2324d95 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -110,6 +110,7 @@ BensonGlacierPostMemInitCallback (
   //
   BufferSize = sizeof (EFI_GUID);
   PcdSetPtr(PcdBoardVbtFileGuid, , (UINT8 
*));
+  PcdSetPtr(PcdOemLogoFileGuid, , (UINT8 *));
 
   //
   // Set PcdSueCreek
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
index 3a804b9558..782bf0d2bd 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -63,6 +63,7 @@
   gPlatformModuleTokenSpaceGuid.PcdFabId
   gPlatformModuleTokenSpaceGuid.PcdResetType
   gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
+  gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid
   gPlatformModuleTokenSpaceGuid.PcdSueCreek
   gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState
   gPlatformModuleTokenSpaceGuid.PcdTi3100AudioCodecEnable
@@ -84,6 +85,7 @@
   gEfiTpmDeviceInstanceTpm20DtpmGuid
   gTpmDeviceInstanceTpm20PttPtpGuid
   gPeiBensonGlacierVbtGuid
+  gPeiLogoGuid
 
 [Ppis]
   gBoardPostMemInitStartGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
index fdf2c7eaab..5c53ff135a 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
@@ -119,6 +119,7 @@ LeafHillPostMemInitCallback (
   //
   

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Graphic Change.

[zwei4]

(1) Fixed the issue that the VBT passed to OS is not the right VBT file. All 
boards are affected.
(2) For UP2, disable Onboard LSPCON for HDMI 2.0 in VBT.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin | Bin 5632 -> 5632 bytes
 .../PlatformPostMemPei/PlatformInit.c |   5 +++--
 .../PlatformPostMemPei/PlatformPostMemPei.inf |   1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin 
b/Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin
index 
0d94dac62a8e410c4f456b52f4de37a50a6655e6..e9b20fe9f7082511c467160a94d0bc00b842c052
 100644
GIT binary patch
delta 25
hcmZqBY0#M<#e9gtU~(X%@J55xjEn-C?=Y%}003j{2UY+8

delta 25
hcmZqBY0#M<#k`NfU~(X%@J55xjEo|i?=Y%}003jX2UY+8

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
index 17c09ecf6f..acaaebbfbb 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
@@ -271,7 +271,7 @@ BXTPolicyInit (
   VOID*   Buffer;
   UINT32  Size;
   EFI_GUIDPeiLogoGuid= { 0x7BB28B99, 0x61BB, 
0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D} };
-  EFI_GUIDTianmaVbtGuid  = { 0xE08CA6D5, 0x8D02, 
0x43ae, {0xAB, 0xB1, 0x95, 0x2C, 0xC7, 0x87, 0xC9, 0x33} };
+  EFI_GUIDVbtGuid;
   VBT_INFOVbtInfo;
 
 
@@ -286,7 +286,8 @@ BXTPolicyInit (
   //
   // May need a different VBT depending on PanelSel
   //
-  PeiGetSectionFromFv (TianmaVbtGuid, , );
+  CopyMem (, PcdGetPtr (PcdBoardVbtFileGuid), sizeof (EFI_GUID));
+  PeiGetSectionFromFv (VbtGuid, , );
 
   if (Buffer == NULL) {
 DEBUG (( DEBUG_ERROR, "Could not locate VBT"));
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformPostMemPei.inf
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformPostMemPei.inf
index 2fb7fb6a6f..35e6e1c4a0 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformPostMemPei.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformPostMemPei.inf
@@ -121,6 +121,7 @@
   gPlatformModuleTokenSpaceGuid.PcdVibratorFeature
   gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid   ## CONSUMES
   gPlatformModuleTokenSpaceGuid.PcdBoardPostMemInitFunc
+  gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
 
 [Depex]
   gDramPolicyPpiGuid
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] LPDDR4 Change.

[zwei4]

Change MRC parameters in FSP-M UPD to enable different memory configurations.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Board/UP2/BoardInitPreMem/BoardInitMiscs.c | 145 -
 .../Board/UP2/BoardInitPreMem/PlatformId.c |  59 +
 .../Board/UP2/BoardInitPreMem/PlatformId.h |   7 +
 .../PlatformSetupDxe/SouthClusterConfig.vfi|   4 +-
 4 files changed, 184 insertions(+), 31 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c 
b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c
index d5092c2490..b155830523 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c
@@ -15,6 +15,7 @@
 
 #include "BoardInitMiscs.h"
 #include "MmrcData.h"
+#include "PlatformId.h"
 
 UPDATE_FSPM_UPD_FUNC mUp2UpdateFspmUpdPtr = Up2UpdateFspmUpd;
 DRAM_CREATE_POLICY_DEFAULTS_FUNC   mUp2DramCreatePolicyDefaultsPtr = 
Up2DramCreatePolicyDefaults;
@@ -43,6 +44,10 @@ Up2UpdateFspmUpd (
   BOOT_VARIABLE_NV_DATA  *BootVariableNvData;
   MRC_PARAMS_SAVE_RESTORE*MrcParamsHob;
   BOOT_VARIABLE_NV_DATA  *BootVariableNvDataHob;
+  SYSTEM_CONFIGURATIONSystemConfiguration;
+  UINTN   VariableSize;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+  UINT8   DdrId;
 
   Status = (*PeiServices)->LocatePpi (
  PeiServices,
@@ -98,13 +103,6 @@ Up2UpdateFspmUpd (
 }
 
   }
-  //
-  // Override RankEnable settings for UP2
-  //
-  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;
-  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1;
-  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 0;
-  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 0;
 
   DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
   Hob.Raw = GetFirstGuidHob ();
@@ -131,34 +129,97 @@ Up2UpdateFspmUpd (
   FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;
   FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;
   FspUpdRgn->FspmConfig.DDR3LASR= 0;
-
-  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1; // 
-  FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 1; 
-  FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;
-  FspUpdRgn->FspmConfig.Ch0_Option   = 3;
-
-  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1; 
-  FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 1; // x16
-  FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2; // 8GB
-  FspUpdRgn->FspmConfig.Ch1_Option   = 3;
-
-  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 0; // empty
-  FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 1;
-  FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;
-  FspUpdRgn->FspmConfig.Ch2_Option   = 3;
-
-  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 0;
-  FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 1;
-  FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;
-  FspUpdRgn->FspmConfig.Ch3_Option   = 3;
-
   FspUpdRgn->FspmConfig.ChannelHashMask   = 0;
   FspUpdRgn->FspmConfig.SliceHashMask = 0;
   FspUpdRgn->FspmConfig.ChannelsSlicesEnable  = 0;
   FspUpdRgn->FspmConfig.ScramblerSupport  = 1;
   FspUpdRgn->FspmConfig.InterleavedMode   = 0;
   FspUpdRgn->FspmConfig.MinRefRate2xEnable= 0;
-  FspUpdRgn->FspmConfig.DualRankSupportEnable = 0;
+
+  //
+  // DDR_ID1DDR_ID0  Memory
+  // GPIO_215   GPIO_214
+  //  0  02G
+  //  0  14G
+  //  1  08G
+  //
+  Status = Up2GetDdrId(PeiServices, );
+  
+  if (DdrId == 0x00) { // 2GB, SK, Single Rank
+  
+FspUpdRgn->FspmConfig.DualRankSupportEnable = 0;
+
+FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;  
+FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 1; 
+FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;
+FspUpdRgn->FspmConfig.Ch0_Option   = 3;
+
+FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1; 
+FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 1; // x16
+FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2; // 8GB
+FspUpdRgn->FspmConfig.Ch1_Option   = 3;
+ 
+FspUpdRgn->FspmConfig.Ch2_RankEnable   = 0; // empty
+FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 1;
+FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;
+FspUpdRgn->FspmConfig.Ch2_Option   = 3;
+
+FspUpdRgn->FspmConfig.Ch3_RankEnable   = 0; // empty
+FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 1;
+FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;
+FspUpdRgn->FspmConfig.Ch3_Option   = 3;
+
+  }else if (DdrId == 0x01) { // 4GB, SK, Single Rank
+  
+FspUpdRgn->FspmConfig.DualRankSupportEnable = 0;
+
+FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1; // 
+FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 1; 
+FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;
+FspUpdRgn->FspmConfig.Ch0_Option   = 3;
+
+FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1; 
+FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 1; // x16
+FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2; // 8GB
+

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] C State Change.

[zwei4]

Monitored cached line may not wake up CPU from MWAIT on certain Goldmont based 
CPUs.
Disable MONITOR/MWAIT and use IO registers for C State instead.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c   | 1 +
 .../Common/PlatformSettings/PlatformSetupDxe/Cpu.vfi  | 4 ++--
 .../Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c   | 1 -
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
index 6c176d0685..c404116029 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
@@ -120,6 +120,7 @@ PeiFspCpuPolicyInit (
 FspsUpd->FspsConfig.PkgCStateDemotion = 
SystemConfiguration->PkgCStateDemotion;
 FspsUpd->FspsConfig.PkgCStateUnDemotion   = 
SystemConfiguration->PkgCStateUnDemotion;
 FspsUpd->FspsConfig.TurboMode = 
SystemConfiguration->TurboModeEnable;
+FspsUpd->FspsConfig.MonitorMwaitEnable= 
SystemConfiguration->MonitorMwaitEnable;
   }
 
   return EFI_SUCCESS;
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Cpu.vfi 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Cpu.vfi
index 23859e6a3a..9094794de2 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Cpu.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/Cpu.vfi
@@ -122,9 +122,9 @@ form formid = CPU_CONFIGURATION_FORM_ID,
   oneof varid   = Setup.MonitorMwaitEnable,
 prompt  = STRING_TOKEN(STR_MONITOR_MWAIT_PROMPT),
 help= STRING_TOKEN(STR_MONITOR_MWAIT_HELP),
-option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
+option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING 
| DEFAULT | RESET_REQUIRED;
 option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = RESET_REQUIRED;
-option text = STRING_TOKEN(STR_AUTO), value = 2, flags = MANUFACTURING | 
DEFAULT | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_AUTO), value = 2, flags = RESET_REQUIRED;
   endoneof;  
 
   subtitle text = STRING_TOKEN(STR_NULL_STRING);
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
index bbb31b10da..08d2fd418f 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
@@ -123,7 +123,6 @@ LoadOsDefaultValues (
 #else
   Private->FakeNvData.TPM= 0;
 #endif
-  Private->FakeNvData.MonitorMwaitEnable = 2;
   Private->FakeNvData.I2C0Speed  = 1;
   Private->FakeNvData.I2C1Speed  = 1;
   Private->FakeNvData.I2C2Speed  = 1;
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] UP2 PCIe NIC.

[zwei4]

Disable PCIe root port 1 of UP2, which is connected to a onboard RealTek PCIe 
NIC. If this PCIe NIC is enabled, Windows 10 installation will fail. This patch 
is a temporary solution.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Board/UP2/BoardInitDxe/BoardInitDxe.c  | 42 +-
 .../Board/UP2/BoardInitDxe/BoardInitDxe.h  |  1 +
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c 
b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c
index 3b5c5ac566..662d8f1991 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c
@@ -17,6 +17,7 @@
 #include "BoardInitDxe.h"
 
 GET_BOARD_NAME mUp2GetBoardNamePtr = Up2GetBoardName;
+SYSTEM_CONFIGURATION  mSystemConfiguration;
 
 CHAR16*
 EFIAPI
@@ -37,7 +38,44 @@ Up2GetBoardName (
   }
 }
 
-
+EFI_STATUS
+UpdateSetupVariable (
+  VOID
+  )
+{
+  UINTN   VarSize;
+  UINT32  VariableAttributes;
+  EFI_STATUS  Status;
+
+  //
+  // Update default value of Setup Variable for PCIe W/A.
+  // PCIe RealTek NIC on root port #1 blocks Windows 10 installation.
+  //
+  
+  VarSize = sizeof (SYSTEM_CONFIGURATION);
+  Status = gRT->GetVariable (
+L"Setup",
+,
+,
+,
+
+);
+  ASSERT_EFI_ERROR (Status);
+
+  if (Status == EFI_SUCCESS) {
+mSystemConfiguration.PcieRootPortEn[3]= (UINT8) 0;
+Status = gRT->SetVariable (
+L"Setup",
+,
+VariableAttributes,
+VarSize,
+
+);
+ASSERT_EFI_ERROR (Status);
+  }
+  
+  return Status;
+}
 /**
   Set PCDs for board specific functions
 
@@ -62,6 +100,8 @@ Up2BoardInitDxeConstructor (
   }
 
   PcdSet64 (PcdGetBoardNameFunc, (UINT64) mUp2GetBoardNamePtr);
+ 
+  UpdateSetupVariable();
 
   return EFI_SUCCESS;
 }
diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.h 
b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.h
index 61e66978ac..82e976e7ef 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.h
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.h
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 
 CHAR16*
 EFIAPI
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] UP2 Board Enabling.

[zwei4]

Add platform specific code and build script for AAEON UP2 board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 BuildBIOS.bat   |  4 +++-
 BuildBIOS.sh|  3 +++
 Platform/BroxtonPlatformPkg/BuildBxtBios.bat| 18 ++
 Platform/BroxtonPlatformPkg/BuildBxtBios.sh | 21 +
 Platform/BroxtonPlatformPkg/BuildIFWI.bat   |  7 +++
 .../Common/Include/Guid/PlatformInfo.h  |  1 +
 .../Common/Include/Guid/PlatformInfo_Aplk.h |  1 +
 .../PlatformSetupDxe/PlatformSetupDxe.c |  9 -
 .../Common/Tools/Stitch/IFWIStitch_Simple.bat   |  9 +
 Platform/BroxtonPlatformPkg/DefineAtBuildMacros.dsc |  1 +
 .../PlatformDsc/Components.IA32.dsc | 15 ++-
 .../BroxtonPlatformPkg/PlatformDsc/Components.dsc   |  1 +
 .../PlatformDsc/PcdsFixedAtBuild.dsc|  7 ++-
 Platform/BroxtonPlatformPkg/PlatformPkg.dec |  1 +
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf |  6 ++
 15 files changed, 88 insertions(+), 16 deletions(-)

diff --git a/BuildBIOS.bat b/BuildBIOS.bat
index b04150c2e0..22c8792edb 100644
--- a/BuildBIOS.bat
+++ b/BuildBIOS.bat
@@ -52,6 +52,7 @@ echo.   /?Display this help text
 echo.
 echo/m Set the build thread count to number of processors
 echo/vs13  Set Compiler to vs2013 build (default: vs2013)
+echo/vs15  Set Compiler to vs2015 build (default: vs2013)
 echo/x64   Set Arch to X64  (default: X64)
 echo/IA32  Set Arch to IA32 (default: X64)
 echo/A Set FabId to A
@@ -62,12 +63,13 @@ echo/MXMinnowBoard 3 Module
 echo/BGBenson Glacier Board
 echo/AGAurora Glacier Board
 echo/LHLeafHill CRB Board
+echo/UPAAEON UP2 Board
 echo/L Flash region access permission for host CPU
 echoPlatformName:  Broxton
 echoBuildTargets:  Release, Debug
 
 echo Examples:
-echo%thisscript% /vs13 /B /x64 Broxton Debug
+echo%thisscript% /vs13 /LH /B /x64 Broxton Debug
 
 set exitCode=1
 
diff --git a/BuildBIOS.sh b/BuildBIOS.sh
index a99f77e978..9c482697b1 100755
--- a/BuildBIOS.sh
+++ b/BuildBIOS.sh
@@ -22,6 +22,7 @@ function Usage () {
   echo "   Build_Flags: /BGBenson Glacier Board"
   echo "   Build_Flags: /MXMinnowBoard3 Module"
   echo "   Build_Flags: /LHLeafHill CRB Board"
+  echo "   Build_Flags: /UPAAEON UP2 Board"
   echo "   Build_Flags: /A Set FabId to A "
   echo "   Build_Flags: /B Set FabId to B (default:  
FAB_B)"
   echo "   Build_Flags: /D Set FabId to D "
@@ -29,6 +30,8 @@ function Usage () {
   echo "   PlatformName [optional]: Broxton  "   
   echo "   Target_Flag: Release, Debug   "
   echo
+  echo "Example: BuildBios.sh /LH /D Broxton Release"
+  echo
   echo "Press any key.."
   read
   exit 0
diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat 
b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
index bd3a7b6498..3e31d52e25 100644
--- a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
+++ b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
@@ -61,6 +61,7 @@ set SrcDebug=FALSE
 set APLK_SETUP_ENABLE_BUILD=FALSE
 set FSP_BUILD=FALSE
 set FSP_WRAPPER=FALSE
+set UP2_BOARD=FALSE
 
 :: Set Defaults of platform specific environment variables.
 set EFI_SOURCE=%CD%
@@ -199,6 +200,12 @@ if /i "%~1"=="/LH" (
 shift
 goto OptLoop
 )
+if /i "%~1"=="/UP" (
+set BoardId=UP
+echo.
+shift
+goto OptLoop
+)
 if /i "%~1"=="/m" (
 if defined NUMBER_OF_PROCESSORS (
 set /a build_threads=%NUMBER_OF_PROCESSORS%
@@ -229,6 +236,9 @@ if /i "%~1" == "%Minnow_RVP%" (
 set BOARD_ID=M3MODUL
   ) else if %BoardId%==LH (
 set BOARD_ID=LEAFHIL
+  ) else if %BoardId%==UP (
+set BOARD_ID=UPBOARD
+set UP2_BOARD=TRUE
   )
 set ENBDT_PF_BUILD=TRUE
 set PLATFORM_NAME=BroxtonPlatformPkg
@@ -264,6 +274,8 @@ if "%Arch%"=="IA32" (
 echo DEFINE X64_CONFIG  = TRUE  >> 
%Build_Macros%
 )
 
+echo DEFINE UP2_BOARD= %UP2_BOARD%   >> 
%Build_Macros%
+
 ::Stage of copy of BiosId.env in Conf/ with Platform_Type and Build_Target 
values removed
 
 if "%Arch%"=="X64" (
@@ -315,6 +327,12 @@ if %BoardId%==LH (
   )
 )
 
+if %BoardId%==UP (
+  if %FabId%==A (
+echo BOARD_REV = A >> Conf\BiosId.env
+  )
+)
+
 :: Set the Build_Type, Version_Major, and Version_Minor environment variables
 find /v "#" Conf\BiosId.env > ver_strings
 for /f "tokens=1,3" %%i in (ver_strings) do set %%i=%%j
diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.sh 

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] UP2 Board Enabling.

[zwei4]

Add board specific code for AAEON UP2 board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Board/UP2/BoardInitDxe/BoardInitDxe.c  |  68 +++
 .../Board/UP2/BoardInitDxe/BoardInitDxe.h  |  37 ++
 .../Board/UP2/BoardInitDxe/BoardInitDxe.inf|  53 +++
 .../Board/UP2/BoardInitPostMem/BoardGpios.c| 280 
 .../Board/UP2/BoardInitPostMem/BoardGpios.h| 470 +
 .../Board/UP2/BoardInitPostMem/BoardInit.c | 190 +
 .../Board/UP2/BoardInitPostMem/BoardInit.h |  30 ++
 .../Board/UP2/BoardInitPostMem/BoardInitMiscs.c| 179 
 .../Board/UP2/BoardInitPostMem/BoardInitMiscs.h| 132 ++
 .../UP2/BoardInitPostMem/BoardInitPostMem.inf  |  93 
 .../Board/UP2/BoardInitPostMem/HdaVerbTables.c | 145 +++
 .../Board/UP2/BoardInitPostMem/HdaVerbTables.h |  38 ++
 .../Board/UP2/BoardInitPostMem/PlatformInfoHob.c   |  59 +++
 .../Board/UP2/BoardInitPreMem/BoardInit.c  | 180 
 .../Board/UP2/BoardInitPreMem/BoardInit.h  |  29 ++
 .../Board/UP2/BoardInitPreMem/BoardInitMiscs.c | 342 +++
 .../Board/UP2/BoardInitPreMem/BoardInitMiscs.h |  46 ++
 .../Board/UP2/BoardInitPreMem/BoardInitPreMem.inf  |  57 +++
 .../Board/UP2/BoardInitPreMem/PlatformId.c |  57 +++
 .../Board/UP2/BoardInitPreMem/PlatformId.h |  74 
 Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin  | Bin 0 -> 5632 bytes
 21 files changed, 2559 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGpios.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGpios.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitMiscs.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitMiscs.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostMem.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerbTables.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerbTables.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/PlatformInfoHob.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInit.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInit.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitPreMem.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.h
 create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin

diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c 
b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c
new file mode 100644
index 00..3b5c5ac566
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c
@@ -0,0 +1,68 @@
+/** @file
+  Board specific functions in DXE phase to be set as dynamic PCD and consumed 
by
+  commmon platform code.
+
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitDxe.h"
+
+GET_BOARD_NAME mUp2GetBoardNamePtr = Up2GetBoardName;
+
+CHAR16*
+EFIAPI
+Up2GetBoardName (
+  IN  UINT8   BoardId
+  )
+{
+  STATIC CHAR16  BoardName[40];
+
+  DEBUG ((EFI_D_INFO,  "BoardInitDxe: GetBoardName\n"));
+  UnicodeSPrint (BoardName, sizeof (BoardName), L"UP2 "); //MyBoardPorting
+
+  if (BoardId != (UINT8) BOARD_ID_UP2) {
+return NULL;
+  } else {
+DEBUG ((EFI_D_INFO,  "It is UP2.\n"));
+return BoardName;
+  }
+}
+
+
+/**
+  Set PCDs for board specific functions
+
+  @param[in]  ImageHandle   ImageHandle of the loaded driver.
+  @param[in]  

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Add I2C Library.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Kelly Steele 
CC: Mike Wu  
CC: Mang Guo 
---
 .../SouthCluster/Include/Library/I2CLib.h  |   4 +-
 .../SouthCluster/Include/ScRegs/RegsI2c.h  |  31 +-
 .../SouthCluster/Library/I2CLib/I2CLib.c   | 719 +
 .../SouthCluster/Library/I2CLib/I2CLib.inf |  50 ++
 .../SouthCluster/Library/I2CLibPei/I2CLibPei.c |   6 +-
 5 files changed, 802 insertions(+), 8 deletions(-)
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib.c
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib.inf

diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h
index b897cb9dc4..0c50a3d9a5 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h
@@ -1,7 +1,7 @@
 /** @file
   Register Definitions for I2C Library.
 
-  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -30,7 +30,7 @@
 **/
 EFI_STATUS
 ProgramPciLpssI2C (
-  VOID
+  IN UINT8BusNo
   );
 
 /**
diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsI2c.h 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsI2c.h
index 5fc758dd07..8a7463b538 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsI2c.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsI2c.h
@@ -106,10 +106,10 @@
 #defineR_IC_CLR_START_DET(0x64) ///< Clear START_DET 
interrupt
 #defineR_IC_CLR_GEN_CALL (0x68) ///< Clear GEN_CALL 
interrupt
 #defineR_IC_ENABLE   (0x6C) ///< I2C Enable
+#defineI2C_ENABLE_ABORT  BIT1
+#defineI2C_ENABLE_ENABLE BIT0
 #defineR_IC_STATUS   (0x70) ///< I2C Status
 
-#defineR_IC_SDA_HOLD (0x7C) ///< I2C 
IC_DEFAULT_SDA_HOLD//16bits
-
 #defineSTAT_MST_ACTIVITY BIT5  ///< Master FSM Activity 
Status.
 #defineSTAT_RFF  BIT4  ///< RX FIFO is completely 
full
 #defineSTAT_RFNE BIT3  ///< RX FIFO is not empty
@@ -118,7 +118,24 @@
 
 #defineR_IC_TXFLR(0x74) ///< Transmit FIFO Level 
Register
 #defineR_IC_RXFLR(0x78) ///< Receive FIFO Level 
Register
+#defineR_IC_SDA_HOLD (0x7C) ///< I2C 
IC_DEFAULT_SDA_HOLD//16bits
 #defineR_IC_TX_ABRT_SOURCE   (0x80) ///< I2C Transmit Abort 
Status Register
+#defineI2C_ABRT_SLVRD_INTX   BIT15
+#defineI2C_ABRT_SLV_ARBLOST  BIT14
+#defineI2C_ABRT_SLVFLUSH_TXFIFO  BIT13
+#defineI2C_ARB_LOST  BIT12
+#defineI2C_ABRT_MASTER_DIS   BIT11
+#defineI2C_ABRT_10B_RD_NORSTRT   BIT10
+#defineI2C_ABRT_SBYTE_NORSTRTBIT9
+#defineI2C_ABRT_HS_NORSTRT   BIT8
+#defineI2C_ABRT_SBYTE_ACKDET BIT7
+#defineI2C_ABRT_HS_ACKDETBIT6
+#defineI2C_ABRT_GCALL_READ   BIT5
+#defineI2C_ABRT_GCALL_NOACK  BIT4
+#defineI2C_ABRT_TXDATA_NOACK BIT3
+#defineI2C_ABRT_10ADDR2_NOACKBIT2
+#defineI2C_ABRT_10ADDR1_NOACKBIT1
+#defineI2C_ABRT_7B_ADDR_NOACKBIT0
 #defineR_IC_SLV_DATA_NACK_ONLY   (0x84) ///< Generate 
SLV_DATA_NACK Register
 #defineR_IC_DMA_CR   (0x88) ///< DMA Control Register
 #defineR_IC_DMA_TDLR (0x8C) ///< DMA Transmit Data 
Level
@@ -130,7 +147,15 @@
 #defineR_IC_COMP_VERSION (0xF8) ///< Component Version ID
 #defineR_IC_COMP_TYPE(0xFC) ///< Component Type
 
-#defineR_IC_CLK_GATE (0xC0) ///< Clock Gate
+#defineR_IC_RESET_CONTROL(0x204) ///< Reset control
+#defineI2C_RESET_CONTROLLER  (BIT0 | BIT1)
+#defineI2C_RESET_IDMA(BIT2)
+
+#defineR_IC_CLK_GATE (0x238) ///< Clock Gate
+#defineI2C_FORCE_CLOCK_ON(BIT0 | BIT1)
+#defineI2C_FORCE_CLOCK_OFF   (BIT1)
+#defineI2C_FORCE_IDMA_CLOCK_ON   (BIT2 | BIT3)
+#defineI2C_FORCE_IDMA_CLOCK_OFF  (BIT3)
 
 #defineI2C_SS_SCL_HCNT_VALUE_100M 0x1DD
 #defineI2C_SS_SCL_LCNT_VALUE_100M 0x1E4
diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib.c 

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Gcc Build Fix

[zwei4]

From: xianhuix 

Reduce fv size for gcc debug build

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: xianhuix 
---
 .../BroxtonPlatformPkg/PlatformDsc/Components.dsc  | 30 +-
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
index 15b75be4a5..8f5d833668 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
@@ -501,12 +501,30 @@
 #  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
 #  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
 
-  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
-  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
-  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
-  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
-  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf  {
+   
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 
+  }
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf  {
+   
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 
+  }
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf  {
+   
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 
+  }
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf  {
+   
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 
+  }
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf  {
+   
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 
+  }
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf  {
+   
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 
+  }
   MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf {
 
 !if $(SIMICS_ENABLE) == TRUE
-- 
2.14.1.windows.1

___
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[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900 4/5] Common EEPROM library instance.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Kelly Steele 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Common/Features/Eeprom/EepromLib/EepromLib.c   | 1011 
 .../Common/Features/Eeprom/EepromLib/EepromLib.h   |   76 ++
 .../Common/Features/Eeprom/EepromLib/EepromLib.inf |   63 ++
 .../Features/Eeprom/EepromLib/EepromNullLib.inf|   36 +
 .../Features/Eeprom/EepromLib/EepromPeiLib.inf |   62 ++
 .../Features/Eeprom/EepromLib/Null/EepromNullLib.c |   82 ++
 .../Features/Eeprom/EepromLib/Null/EepromNullLib.h |   26 +
 .../Eeprom/EepromLib/Pei/ValidateHashPei.c |  251 +
 .../Features/Eeprom/EepromLib/ValidateHash.c   |  399 
 9 files changed, 2006 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromLib.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromLib.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromLib.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromNullLib.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromPeiLib.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/Null/EepromNullLib.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/Null/EepromNullLib.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/Pei/ValidateHashPei.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/ValidateHash.c

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromLib.c 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromLib.c
new file mode 100644
index 00..6ab06da2be
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromLib/EepromLib.c
@@ -0,0 +1,1011 @@
+/** @file
+  Common EEPROM library instance.
+
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "EepromLib.h"
+
+BOOLEAN *gImageValidFlag;
+UINT32   mCrcTable[256];
+BOOLEAN  mCrcInitFlag= FALSE;
+BOOLEAN  mEepromLibDebugFlag = TRUE;
+
+/**
+  This internal function reverses bits for 32bit data.
+
+  @param  Value The data to be reversed.
+
+  @return   Data reversed.
+
+**/
+UINT32
+EFIAPI
+ReverseBits (
+  UINT32  Value
+  )
+{
+  UINTN   Index;
+  UINT32  NewValue;
+
+  NewValue = 0;
+  for (Index = 0; Index < 32; Index++) {
+if ((Value & (1 << Index)) != 0) {
+  NewValue = NewValue | (1 << (31 - Index));
+}
+  }
+
+  return NewValue;
+}
+
+/**
+  Initialize CRC32 table.
+
+**/
+VOID
+EFIAPI
+InitializeCrc32Table (
+  VOID
+  )
+{
+  UINTN   TableEntry;
+  UINTN   Index;
+  UINT32  Value;
+
+  for (TableEntry = 0; TableEntry < 256; TableEntry++) {
+Value = ReverseBits ((UINT32) TableEntry);
+for (Index = 0; Index < 8; Index++) {
+  if ((Value & 0x8000) != 0) {
+Value = (Value << 1) ^ 0x04C11DB7;
+  } else {
+Value = Value << 1;
+  }
+}
+
+mCrcTable[TableEntry] = ReverseBits (Value);
+  }
+  mCrcInitFlag = TRUE;
+}
+
+/*++
+
+Routine Description:
+
+  The CalculateCrc32 routine.
+
+Arguments:
+
+  Data- The buffer contaning the data to be processed
+  DataSize- The size of data to be processed
+  CrcOut  - A pointer to the caller allocated UINT32 that on
+contains the CRC32 checksum of Data
+
+Returns:
+
+  EFI_SUCCESS   - Calculation is successful.
+  EFI_INVALID_PARAMETER - Data / CrcOut = NULL, or DataSize = 0
+
+--*/
+EFI_STATUS
+EFIAPI
+CalculateCrc32 (
+  IN UINT8*Data,
+  IN UINTN DataSize,
+  IN OUT UINT32   *CrcOut
+  )
+{
+  UINT32  Crc;
+  UINTN   Index;
+  UINT8   *Ptr;
+
+  if (mEepromLibDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Starting...\n", 
__FUNCTION__, __LINE__));
+
+  // Sanity checks
+  if ((DataSize == 0) || (Data == NULL) || (CrcOut == NULL)) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  // Table initialized?
+  if (!mCrcInitFlag) InitializeCrc32Table ();
+
+  Crc = 0x;
+  for (Index = 0, Ptr = Data; Index < DataSize; Index++, Ptr++) {
+Crc = (Crc >> 8) ^ mCrcTable[(UINT8) Crc ^ *Ptr];
+  }
+
+  *CrcOut = Crc ^ 0x;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+EepromLibNemToMemory (VOID)
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+EraseEeprom (
+  IN   UINT8

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900 1/5] Add EepromApp.

[zwei4]

Add EepromApp which could read, write, verify and dump the EERPOM data.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Kelly Steele 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Common/Features/Eeprom/EepromApp/EepromApp.c   | 2090 
 .../Common/Features/Eeprom/EepromApp/EepromApp.h   |  196 ++
 .../Common/Features/Eeprom/EepromApp/EepromApp.inf |   62 +
 3 files changed, 2348 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromApp/EepromApp.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromApp/EepromApp.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromApp/EepromApp.inf

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromApp/EepromApp.c 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromApp/EepromApp.c
new file mode 100644
index 00..9e1eb66f54
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromApp/EepromApp.c
@@ -0,0 +1,2090 @@
+/** @file
+
+  This application will read/write/verify/dump the EERPOM data.
+
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License which accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "EepromApp.h"
+
+BOOLEAN   gDebugFlag = FALSE;
+
+/**
+  UEFI application entry point which has an interface similar to a
+  standard C main function.
+
+  The ShellCEntryLib library instance wrappers the actual UEFI application
+  entry point and calls this ShellAppMain function.
+
+  @param[in] Argc The number of items in Argv.
+  @param[in] Argv Array of pointers to strings.
+
+  @retval0The application exited normally.
+  @retvalOtherAn error occurred.
+
+**/
+INTN
+EFIAPI
+ShellAppMain (
+  IN UINTN  Argc,
+  IN CHAR16   **Argv
+  )
+{
+  BOOLEAN InvalidFlag;
+  PROGRAM_INFOProgramInfo;
+  SHELL_STATUSStatus;
+
+  if (gDebugFlag) Print (L"%a(#%d) - Starting...\n", __FUNCTION__, __LINE__);
+
+  // Initialize Variables
+  InvalidFlag = FALSE;
+  Status  = SHELL_SUCCESS;
+  ZeroMem (, sizeof (ProgramInfo));
+
+
+  // Check for invalid conditions
+  if (Argv == NULL) {
+if (gDebugFlag) Print (L"ERROR: [#%d] Internal coding error!\n", __LINE__);
+Status = SHELL_INVALID_PARAMETER;
+goto Exit;
+  }
+
+  // Parse CLI parameters
+  ParseParameters (Argc, Argv, );
+
+  // Print App version
+  Print (L"EepromApp - Version #%s\n", APP_VERSION);
+  Print (L"Copyright (c) %s Intel Corporation. All rights reserved.\n\n", 
APP_COPYRIGHT);
+
+  // Help requested?
+  if (ProgramInfo.HelpFlag) {
+PrintHelp ();
+goto Exit;
+  }
+
+  // Check for invalid states
+  if (CheckForInvalidOptions () != SHELL_SUCCESS) {
+InvalidFlag = TRUE;
+Print (L"ERROR: Invalid CLI option(s)!\n");
+goto Exit;
+  }
+
+  //
+  // Test GetValidEepromLibrary()
+  //
+  if (!ProgramInfo.ScanFlag) {
+//
+// Skip this if we are doing a scan.
+//
+Print (L"- GetValidEepromLibrary() = %a\n", 
mEepromLibraryString[GetValidEepromLibrary (TRUE, TRUE)]);
+  } else {
+// Scanning
+Status = ScanOption ();
+if (Status != SHELL_SUCCESS) {
+  goto Exit;
+}
+  }
+
+  // Check?
+  if (ProgramInfo.CheckFlag) {
+if (ProgramInfo.ReadLibraryIndex > EEPROM_DATA_LIBRARY_INDEX_MAX) {
+  Print (L"ERROR: Library index you want to check is larger than %d!\n", 
EEPROM_DATA_LIBRARY_INDEX_MAX);
+  Status = SHELL_INVALID_PARAMETER;
+  goto Exit;
+}
+Status = CheckOption ();
+  } else
+
+  // Dump human?
+  if (ProgramInfo.DumpHumanFlag) {
+if (ProgramInfo.DumpHumanLibraryIndex > EEPROM_DATA_LIBRARY_INDEX_MAX) {
+  Print (L"ERROR: Library index you want to check is larger than %d!\n", 
EEPROM_DATA_LIBRARY_INDEX_MAX);
+  Status = SHELL_INVALID_PARAMETER;
+  goto Exit;
+}
+Status = DumpHumanOption ();
+  } else
+
+  // Dump raw?
+  if (ProgramInfo.DumpRawFlag) {
+if (ProgramInfo.DumpRawLibraryIndex > EEPROM_DATA_LIBRARY_INDEX_MAX) {
+  Print (L"ERROR: Library index you want to check is larger than %d!\n", 
EEPROM_DATA_LIBRARY_INDEX_MAX);
+  Status = SHELL_INVALID_PARAMETER;
+  goto Exit;
+}
+Status = DumpRawOption ();
+  } else
+
+  // Erase?
+  if (ProgramInfo.EraseFlag) {
+if (ProgramInfo.EraseLibraryIndex > EEPROM_DATA_LIBRARY_INDEX_MAX) {
+  Print (L"ERROR: Library index you want to check is larger than %d!\n", 
EEPROM_DATA_LIBRARY_INDEX_MAX);
+  Status = SHELL_INVALID_PARAMETER;
+  goto Exit;
+}
+Status = EraseOption ();
+  } else
+

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900 5/5] EEPROM header files.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Kelly Steele 
CC: Mike Wu  
CC: Mang Guo 
---
 .../Common/Features/Eeprom/Include/EepromStruct.h  | 189 +
 .../Features/Eeprom/Include/Guid/EepromVariable.h  |  26 +++
 .../Eeprom/Include/Library/EepromDataLib.h | 158 +
 .../Features/Eeprom/Include/Library/EepromLib.h| 110 
 .../Common/Features/Eeprom/ReadMe.txt  |  62 +++
 5 files changed, 545 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/Include/EepromStruct.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/Include/Guid/EepromVariable.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/Include/Library/EepromDataLib.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/Include/Library/EepromLib.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/ReadMe.txt

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/Include/EepromStruct.h 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/Include/EepromStruct.h
new file mode 100644
index 00..e3d0fa6199
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/Include/EepromStruct.h
@@ -0,0 +1,189 @@
+/** @file
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EEPROM_LAYOUT_H_
+#define _EEPROM_LAYOUT_H_
+
+#pragma pack(1)
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+}GENERIC_HEADER;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+UINT32  structlength;
+UINT32  crc32;
+UINT32  crclength;
+UINT32  version;
+CHAR8   reserved[16];
+}EEPROM_HEADER;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   reserved[16];
+//  UINT8   acpitbl[0];
+}ACPI_TABLE;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   manuname[16];
+CHAR8   brdname[16];
+CHAR8   brdserial[16];
+UINT32  boardid;
+UINT32  fabid;
+UINT32  ecid;
+UINT8   boardtype;
+CHAR8   reserved[19];
+}BOARD_INFO_TABLE;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   partlabel[16];
+UINT32  blklength;
+UINT16  pagesize;
+UINT32  partsize;
+UINT8   busnumber;
+UINT8   master;
+UINT8   speed;
+CHAR8   reserved[3];
+//  UINT8   mapdata[0];
+}EEPROM_MAP;
+
+
+typedef struct {
+CHAR8   maplabel[16];
+UINT32  length;
+UINT32  offset;
+UINT8   address;
+CHAR8   reserved[7];
+}EEPROM_MAP_RECORD;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   reserved[16];
+//  UINT8   gpiodata[0];
+}GPIO_DATA_HEADER;
+
+
+typedef struct {
+CHAR8   gpiolabel[16];
+UINT32  length;
+UINT32  offset;
+UINT32  anddata;
+UINT32  ordata;
+UINT8   datasize;
+UINT8   datatype;
+CHAR8   reserved[14];
+}GPIO_DATA_RECORD;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   reserved[16];
+//  UINT8   hdacodec[0];
+}HDA_CODEC;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+UINT16  spdslot;
+CHAR8   reserved[14];
+//  UINT8   spddata[0];
+}MEMORY_SPD;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   nicid[8];
+CHAR8   macaddr[6];
+UINT16  nicnum;
+CHAR8   reserved[16];
+//  UINT8   nicdata[0];
+}NIC_INFO;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+UINT16  hashtype;
+CHAR8   reserved[14];
+//  UINT8   eepromsig[0];
+}SIGNATURE_DATA;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   reserved[16];
+//  UINT8   ucodedata[0];
+}MICROCODE;
+
+
+typedef struct {
+CHAR8   signature[8];
+UINT16  vermajor;
+UINT16  verminor;
+UINT32  length;
+CHAR8   reserved[16];
+//  UINT8   videodata[0];
+}VIDEO_DATA;
+
+
+typedef struct {
+CHAR8   

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Enable VT-d DMA remapping for DMA protection.

[zwei4]

(1) Add VT-d modules into FDF file.
(2) Add Setup option and configuration policy for pre-boot VT-d enabling.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mang Guo 
---
 .../Common/Include/Guid/SetupVariable.h|   4 ++-
 .../Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c |   2 ++
 .../Common/PlatformSettings/PlatformDxe/Platform.c |  31 +++-
 .../PlatformSettings/PlatformDxe/PlatformDxe.inf   |   5 +++-
 .../PlatformSettings/PlatformSetupDxe/Cpu.vfi  |   9 ++
 .../PlatformSetupDxe/PlatformSetupDxe.c|   5 
 .../PlatformSettings/PlatformSetupDxe/UqiList.uni  | Bin 126916 -> 127232 bytes
 .../PlatformSetupDxe/VfrStrings.uni| Bin 306044 -> 306466 bytes
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.c|  32 +++--
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.inf  |   6 
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf|   8 ++
 .../SouthCluster/Include/ConfigBlock/VtdConfig.h   |   3 +-
 .../SouthCluster/Library/DxeVtdLib/DxeVtdLib.c |  21 +-
 .../Library/PeiScPolicyLib/ScPrintPolicy.c |   2 +-
 14 files changed, 120 insertions(+), 8 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h 
b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
index 60ffb1beb5..4f5eeb1c0f 100644
--- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
+++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h
@@ -1,7 +1,7 @@
 /** @file
   Header file for Setup Variable.
 
-  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -1130,6 +1130,8 @@ typedef struct {
   UINT8 HotThermalTripPointSen2;
   
   UINT8 SueCreekBypass;
+
+  UINT8 PrebootVTdEnable;
 } SYSTEM_CONFIGURATION;
 #pragma pack(pop)
 
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c
index e7714d189a..faf478ace8 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c
@@ -640,6 +640,8 @@ UpdatePeiScPolicy (
   }
 
   VtdConfig->VtdEnable = SystemConfiguration.VTdEnable;
+  VtdConfig->PrebootVTdEnable = SystemConfiguration.PrebootVTdEnable;
+  
   //
   // Power management Configuration
   //
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
index 712d5cd14f..31f8bedc31 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
@@ -1,7 +1,7 @@
 /** @file
   Platform Initialization Driver.
 
-  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -38,6 +38,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #if (ENBDT_PF_ENABLE == 1) //BXTP
   #include 
@@ -496,6 +499,31 @@ InitPlatformBootMode (
 
 }
 
+VOID
+InitPlatformVtdDxePolicy (
+  VOID
+  )
+{
+  SC_POLICY_HOB *ScPolicy;
+  EFI_PEI_HOB_POINTERS  HobPtr;
+  SC_VTD_CONFIG *VtdConfig;
+  EFI_STATUSStatus;
+
+  //
+  // Get SC VT-d config block
+  //
+  HobPtr.Guid = GetFirstGuidHob ();
+  ASSERT (HobPtr.Guid != NULL);
+  ScPolicy = (SC_POLICY_HOB*) GET_GUID_HOB_DATA (HobPtr.Guid);
+  Status = GetConfigBlock ((VOID *) ScPolicy, , (VOID *) 
);
+  ASSERT_EFI_ERROR (Status);
+  DEBUG ((DEBUG_INFO, "Set ScPolicy VtdConfig PrebootVTdEnable.\n"));
+  
+  VtdConfig->PrebootVTdEnable = 0;
+  if ((BOOLEAN)(mSystemConfiguration.PrebootVTdEnable) == TRUE) {
+VtdConfig->PrebootVTdEnable = 1;
+  }
+}
 
 VOID
 InitPlatformUsbPolicy (
@@ -839,6 +867,7 @@ InitializePlatform (
   IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
   IoWrite8 (PCAT_RTC_DATA_REGISTER, IoRead8 (PCAT_RTC_DATA_REGISTER) & 
~B_RTC_ALARM_INT_ENABLE);
 
+  InitPlatformVtdDxePolicy();
   InitPlatformIdePolicy ();
   InitPlatformUsbPolicy ();
   InitSioPlatformPolicy ();
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
index 440071fd41..8eb6a7aa82 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
+++ 

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] DMAR Table Installation.

[zwei4]

Move DMAR table into a separate FFS file to make it easier to be located and 
installed at proper time by VT-d library.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mang Guo 
---
 .../Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c |   4 +-
 .../Common/Acpi/AcpiTablesPCAT/AcpiTables.inf  |   4 +-
 .../PlatformDsc/Components.IA32.dsc|   8 +-
 .../BroxtonPlatformPkg/PlatformDsc/Components.dsc  |  18 +-
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf|   6 +
 Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec   |   2 +
 .../SouthCluster/AcpiTableDmar/AcpiTableDmar.inf   |  32 +++
 .../SouthCluster/AcpiTableDmar}/Dmar.aslc  |   2 +-
 .../SouthCluster/AcpiTableDmar}/Dmar.h |   2 +-
 .../SouthCluster/Library/DxeVtdLib/DxeVtdLib.c | 260 +
 .../SouthCluster/Library/DxeVtdLib/DxeVtdLib.inf   |  12 +-
 11 files changed, 294 insertions(+), 56 deletions(-)
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/AcpiTableDmar/AcpiTableDmar.inf
 rename {Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar => 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/AcpiTableDmar}/Dmar.aslc (95%)
 rename {Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar => 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/AcpiTableDmar}/Dmar.h (90%)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
index c18753b61c..6a4d675eb2 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
@@ -1,7 +1,7 @@
 /** @file
   ACPI Platform Driver.
 
-  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -1081,7 +1081,7 @@ OnReadyToBoot (
   //
   // Update the DMAR Table
   //
-  UpdateDmarOnReadyToBoot (SetupVarBuffer.VTdEnable);
+  // UpdateDmarOnReadyToBoot (SetupVarBuffer.VTdEnable);
 
   //
   // Publish ACPI 1.0 or 2.0 Tables
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf
index 1e456e3405..ea5da05602 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Component information file for the ACPI tables.
 #
-#  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+#  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
@@ -29,8 +29,6 @@
   Madt/Madt30.aslc
   Mcfg/Mcfg.aslc
   Hpet/Hpet.aslc
-  Dmar/Dmar.aslc
-  Dmar/Dmar.h
   Lpit/Lpit.aslc
   Lpit/Lpit.h
   SsdtRtd3/RvpRtd3.asl
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
index 8615ebc5c0..1aec4a9244 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
@@ -210,4 +210,10 @@
 
 !if $(SOURCE_DEBUG_ENABLE) == TRUE
   SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf
-!endif
\ No newline at end of file
+!endif
+
+#
+# VT-d for DMA Protection
+#
+$(PLATFORM_PACKAGE_COMMON)/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.inf
+IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
\ No newline at end of file
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
index f1bb26b9d9..15b75be4a5 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
@@ -18,7 +18,7 @@
   #
   MdeModulePkg/Core/Dxe/DxeMain.inf {
 
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8046
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8047
 
   !if $(DXE_CRC32_SECTION_ENABLE) == TRUE
   
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
@@ -26,7 +26,6 @@
   !if $(LZMA_ENABLE) == TRUE
   
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
   !endif
- DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 
   }
   MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
 
@@ -544,4 +543,17 @@
   # Application
   #
   $(PLATFORM_PACKAGE_COMMON)/Application/FirmwareUpdate/FirmwareUpdate.inf
-
+  MdeModulePkg/Application/VariableInfo/VariableInfo.inf
+  
+  #
+  # VT-d for DMA Protection
+  #
+  

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Enhance Implementation of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.

[zwei4]

Enhance implementation of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL by introducing 
EDKII_IOMMU_PROTOCOL to support DMA remapping when VT-d is enabled.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mang Guo 
---
 .../NorthCluster/PciHostBridge/Dxe/PciHostBridge.c | 34 +++
 .../PciHostBridge/Dxe/PciHostBridge.inf|  2 +
 .../NorthCluster/PciHostBridge/Dxe/PciRootBridge.h |  1 +
 .../PciHostBridge/Dxe/PciRootBridgeIo.c| 71 +++---
 4 files changed, 99 insertions(+), 9 deletions(-)

diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c
 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c
index 3f7a51d275..2cace7be07 100644
--- 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c
+++ 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c
@@ -22,6 +22,9 @@
 #include 
 #include 
 
+EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+EFI_EVENT   mIoMmuEvent;
+VOID*mIoMmuRegistration;
 //
 // Support 64 K IO space
 //
@@ -75,6 +78,28 @@ static PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[1][1] 
= { {{ 0, 255, 0, 0
 
 static EFI_HANDLE mDriverImageHandle;
 
+/**
+  Event notification that is fired when IOMMU protocol is installed.
+
+  @param  Event The Event that is being processed.
+  @param  Context   Event Context.
+
+**/
+VOID
+EFIAPI
+IoMmuProtocolCallback (
+  IN  EFI_EVENT   Event,
+  IN  VOID*Context
+  )
+{
+  EFI_STATUS   Status;
+
+  Status = gBS->LocateProtocol (, NULL, (VOID 
**));
+  if (!EFI_ERROR(Status)) {
+gBS->CloseEvent (mIoMmuEvent);
+  }
+}
+
 //
 // Implementation
 //
@@ -241,6 +266,15 @@ PciHostBridgeEntryPoint (
   ASSERT_EFI_ERROR (Status);
   DEBUG ((EFI_D_INFO, "Successfully changed memory attribute for PCIe\n"));
 
+
+  mIoMmuEvent = EfiCreateProtocolNotifyEvent (
+  ,
+  TPL_CALLBACK,
+  IoMmuProtocolCallback,
+  NULL,
+  
+  );
+
   return EFI_SUCCESS;
 }
 
diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.inf
 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.inf
index de77fd1552..ec0c593d5b 100644
--- 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.inf
+++ 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.inf
@@ -35,6 +35,7 @@
 
 [Packages]
   MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   BroxtonSiPkg/BroxtonSiPkg.dec
 
 [LibraryClasses]
@@ -55,6 +56,7 @@
   gEfiPciHostBridgeResourceAllocationProtocolGuid ## PRODUCES
   gEfiMetronomeArchProtocolGuid   ## CONSUMES
   gEfiCpuIo2ProtocolGuid  ## CONSUMES
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
 
 [Depex]
   gEfiCpuIo2ProtocolGuid  AND
diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridge.h
 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridge.h
index 81c143e6d1..1db17fc2da 100644
--- 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridge.h
+++ 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridge.h
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridgeIo.c
 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridgeIo.c
index e5e2e8605f..d8bdc20de1 100644
--- 
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridgeIo.c
+++ 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciRootBridgeIo.c
@@ -16,6 +16,8 @@
 #include "PciRootBridge.h"
 #include 
 
+extern EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+
 typedef struct {
   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];
   EFI_ACPI_END_TAG_DESCRIPTOR   EndDesp;
@@ -1093,11 +1095,29 @@ RootBridgeIoMap (
   if (Operation < 0 || Operation >= EfiPciOperationMaximum) {
 return EFI_INVALID_PARAMETER;
   }
-  //
-  // Most PCAT like chipsets can not handle performing DMA above 4GB.
-  // If any part of the DMA transfer being mapped is above 4GB, then
-  // map the DMA transfer to a buffer below 4GB.
-  //
+
+  if (mIoMmuProtocol != NULL) {
+//
+// Clear 64bit support
+//
+if (Operation > EfiPciOperationBusMasterCommonBuffer) {
+  Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - 
EfiPciOperationBusMasterRead64);
+}
+return mIoMmuProtocol->Map (
+   mIoMmuProtocol,
+   (EDKII_IOMMU_OPERATION) Operation,
+   HostAddress,
+  

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Platform VTd DXE Driver.

[zwei4]

Add platform driver to produce gEdkiiPlatformVTdPolicyProtocolGuid for VT-d DXE 
driver to consume.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mang Guo 
---
 .../PlatformVTdDxe/PlatformVTdDxe.c| 410 +
 .../PlatformVTdDxe/PlatformVTdDxe.inf  |  62 
 .../PlatformVTdDxe/PlatformVTdDxe.uni  |  20 +
 .../PlatformVTdDxe/PlatformVTdDxeExtra.uni |  20 +
 4 files changed, 512 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdDxe/PlatformVTdDxe.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdDxe/PlatformVTdDxe.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdDxe/PlatformVTdDxe.uni
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdDxe/PlatformVTdDxeExtra.uni

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdDxe/PlatformVTdDxe.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdDxe/PlatformVTdDxe.c
new file mode 100644
index 00..a2fb391527
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdDxe/PlatformVTdDxe.c
@@ -0,0 +1,410 @@
+/** @file
+  Platform VTd Sample driver.
+
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef struct {
+  ACPI_EXTENDED_HID_DEVICE_PATH  I2cController;
+  UINT8  HidStr[8];
+  UINT8  UidStr[1];
+  UINT8  CidStr[8];
+} PLATFORM_I2C_CONTROLLER_DEVICE_PATH;
+
+typedef struct {
+  ACPI_EXTENDED_HID_DEVICE_PATH  I2cDevice;
+  UINT8  HidStr[13];
+  UINT8  UidStr[1];
+  UINT8  CidStr[13];
+} PLATFORM_I2C_DEVICE_DEVICE_PATH;
+
+typedef struct {
+  PLATFORM_I2C_CONTROLLER_DEVICE_PATH  I2cController;
+  PLATFORM_I2C_DEVICE_DEVICE_PATH  I2cDevice;
+  EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_I2C_DEVICE_PATH;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH  PciRootBridge;
+  PCI_DEVICE_PATH   PciDevice;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PLATFORM_PCI_DEVICE_PATH;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH  PciRootBridge;
+  PCI_DEVICE_PATH   PciBridge;
+  PCI_DEVICE_PATH   PciDevice;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PLATFORM_PCI_BRIDGE_DEVICE_PATH;
+
+typedef struct {
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;
+  UINT16Segment;
+  VTD_SOURCE_ID SourceId;
+} PLATFORM_ACPI_DEVICE_MAPPING;
+
+#define PLATFORM_PCI_ROOT_BRIDGE \
+  { \
+{ \
+  ACPI_DEVICE_PATH, \
+  ACPI_DP, \
+  { \
+(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
+(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
+  }, \
+}, \
+EISA_PNP_ID (0x0A03), \
+0 \
+  }
+
+#define PLATFORM_END_ENTIRE \
+  { \
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { 
END_DEVICE_PATH_LENGTH, 0 } \
+  }
+
+#define PLATFORM_PCI(Device, Function) \
+  { \
+{ \
+  HARDWARE_DEVICE_PATH, \
+  HW_PCI_DP, \
+  { \
+(UINT8) (sizeof (PCI_DEVICE_PATH)), \
+(UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
+  } \
+}, \
+(Function), \
+(Device) \
+  }
+
+#define PLATFORM_I2C(Hid, Uid, Cid, HidStr, UidStr, CidStr) \
+  { \
+{ \
+  { \
+ACPI_DEVICE_PATH, \
+ACPI_EXTENDED_DP, \
+{sizeof(ACPI_EXTENDED_HID_DEVICE_PATH) + sizeof(HidStr) + 
sizeof(UidStr) + sizeof(CidStr), 0} \
+  }, \
+  Hid, \
+  Uid, \
+  Cid \
+}, \
+HidStr, \
+UidStr, \
+CidStr \
+  }
+
+PLATFORM_I2C_DEVICE_PATH mPlatformI2CDevicePath = {
+  PLATFORM_I2C(0, 2, 0, "INT33C3", "", "INT33C3"),
+  PLATFORM_I2C(0, 1, 0, "I2C01\\TPANEL", "", "I2C01\\TPANEL"),
+  PLATFORM_END_ENTIRE
+};
+
+PLATFORM_ACPI_DEVICE_MAPPING  mAcpiDeviceMapping[] = {
+  {
+(EFI_DEVICE_PATH_PROTOCOL *),
+0x0, // Segment
+{{0x01, 0x15, 0x00}} // Function, Device, Bus
+  }
+};
+
+PLATFORM_PCI_BRIDGE_DEVICE_PATH mPlatformPciBridgeDevicePath = {
+  PLATFORM_PCI_ROOT_BRIDGE,
+  PLATFORM_PCI(0x1C, 1),
+  PLATFORM_PCI(0, 0),
+  PLATFORM_END_ENTIRE
+};
+
+#pragma pack(1)
+
+typedef struct {
+  

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Platform VT-d Information PEIM.

[zwei4]

This platform VT-d Information PEIM produces gEdkiiVTdInfoPpiGuid to expose 
DMAR (DMA Remapping Table).

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mang Guo 
---
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.c| 334 +
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.inf  |  55 
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.uni  |  20 ++
 .../PlatformVTdInfoPei/PlatformVTdInfoPeiExtra.uni |  20 ++
 4 files changed, 429 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.uni
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPeiExtra.uni

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
new file mode 100644
index 00..b342e99f22
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
@@ -0,0 +1,334 @@
+/** @file
+  Platform VTd Info PEI driver.
+
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+#define R_SA_MCHBAR   (0x48)
+#define R_SA_GGC  (0x50)
+#define N_SKL_SA_GGC_GGMS_OFFSET  (0x6)
+#define B_SKL_SA_GGC_GGMS_MASK(0xc0)
+#define N_SKL_SA_GGC_GMS_OFFSET   (0x8)
+#define B_SKL_SA_GGC_GMS_MASK (0xff00)
+#define V_SKL_SA_GGC_GGMS_8MB 3
+#define R_SA_TOLUD(0xbc)
+
+//
+// VT-d Engine base address.
+//
+#define R_SA_MCHBAR_VTD1_OFFSET  0x6C88  ///< DMA Remapping HW UNIT1 for IGD
+#define R_SA_MCHBAR_VTD2_OFFSET  0x6C80  ///< DMA Remapping HW UNIT2 for all 
other - PEG, USB, SATA etc
+
+#define SA_VTD_ENGINE_NUMBER 2
+
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 1 - integrated graphic
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd1;
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Drhd11;
+  EFI_ACPI_DMAR_PCI_PATH   Drhd111;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+  //
+  // RMRR 1 - integrated graphic
+  //
+  EFI_ACPI_DMAR_RMRR_HEADERRmrr1;
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Rmrr11;
+  EFI_ACPI_DMAR_PCI_PATH   Rmrr111;
+} MY_VTD_INFO_PPI;
+
+MY_VTD_INFO_PPI  mPlatformVTdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd1
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+sizeof(EFI_ACPI_DMAR_PCI_PATH)
+},
+0, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED9 // RegisterBaseAddress -- TO BE PATCHED
+  },
+  { // Drhd11
+EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+  sizeof(EFI_ACPI_DMAR_PCI_PATH),
+0, // Reserved2
+0, // EnumerationId
+0  // StartBusNumber
+  },
+  { // Drhd111
+2,  // Device
+0   // Function
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+
+  { // Rmrr1
+{ // Header
+  EFI_ACPI_DMAR_TYPE_RMRR,
+  sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+sizeof(EFI_ACPI_DMAR_PCI_PATH)
+},
+{0}, // Reserved
+0, // SegmentNumber
+0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED
+0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED
+  },
+  { // Rmrr11
+EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,
+

[edk2] [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Platform VT-d Information PEIM.

[zwei4]

This platform VT-d Information PEIM produces gEdkiiVTdInfoPpiGuid to expose 
DMAR (DMA Remapping Table).

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei 
CC: Mang Guo 
---
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.c| 334 +
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.inf  |  55 
 .../PlatformVTdInfoPei/PlatformVTdInfoPei.uni  |  20 ++
 .../PlatformVTdInfoPei/PlatformVTdInfoPeiExtra.uni |  20 ++
 4 files changed, 429 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.uni
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPeiExtra.uni

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
new file mode 100644
index 00..b342e99f22
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformVTdInfoPei/PlatformVTdInfoPei.c
@@ -0,0 +1,334 @@
+/** @file
+  Platform VTd Info PEI driver.
+
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+#define R_SA_MCHBAR   (0x48)
+#define R_SA_GGC  (0x50)
+#define N_SKL_SA_GGC_GGMS_OFFSET  (0x6)
+#define B_SKL_SA_GGC_GGMS_MASK(0xc0)
+#define N_SKL_SA_GGC_GMS_OFFSET   (0x8)
+#define B_SKL_SA_GGC_GMS_MASK (0xff00)
+#define V_SKL_SA_GGC_GGMS_8MB 3
+#define R_SA_TOLUD(0xbc)
+
+//
+// VT-d Engine base address.
+//
+#define R_SA_MCHBAR_VTD1_OFFSET  0x6C88  ///< DMA Remapping HW UNIT1 for IGD
+#define R_SA_MCHBAR_VTD2_OFFSET  0x6C80  ///< DMA Remapping HW UNIT2 for all 
other - PEG, USB, SATA etc
+
+#define SA_VTD_ENGINE_NUMBER 2
+
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 1 - integrated graphic
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd1;
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Drhd11;
+  EFI_ACPI_DMAR_PCI_PATH   Drhd111;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+  //
+  // RMRR 1 - integrated graphic
+  //
+  EFI_ACPI_DMAR_RMRR_HEADERRmrr1;
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Rmrr11;
+  EFI_ACPI_DMAR_PCI_PATH   Rmrr111;
+} MY_VTD_INFO_PPI;
+
+MY_VTD_INFO_PPI  mPlatformVTdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd1
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+sizeof(EFI_ACPI_DMAR_PCI_PATH)
+},
+0, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED9 // RegisterBaseAddress -- TO BE PATCHED
+  },
+  { // Drhd11
+EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+  sizeof(EFI_ACPI_DMAR_PCI_PATH),
+0, // Reserved2
+0, // EnumerationId
+0  // StartBusNumber
+  },
+  { // Drhd111
+2,  // Device
+0   // Function
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+
+  { // Rmrr1
+{ // Header
+  EFI_ACPI_DMAR_TYPE_RMRR,
+  sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+sizeof(EFI_ACPI_DMAR_PCI_PATH)
+},
+{0}, // Reserved
+0, // SegmentNumber
+0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED
+0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED
+  },
+  { // Rmrr11
+EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,
+

[edk2] [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Fix GCC build error.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 
---
 Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c 
b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
index 8c1dc152b8..58c0e63f1e 100644
--- a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
+++ b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
@@ -267,9 +267,7 @@ VOID
   UINT32   GpioValue;
   UINT32   SSUSOffset = 0x2000;
   UINT32   IoBase = 0;
-  UINT32   MmioConf0 = 0;
   UINT32   MmioPadval = 0;
-  UINT32   PConf0Offset = 0x210; //GPIO_S5_1 pad_conf0 
register offset
   UINT32   PValueOffset = 0x218; //GPIO_S5_1 pad_value 
register offset
   
   PciD31F0RegBase = MmPciAddress (0,
@@ -283,7 +281,6 @@ VOID
   //
   // 0xFED0E1E0/0xFED0E0A8 is pad_Conf/pad_val register address of GPIO_S5_17
   //
-  MmioConf0 = IoBase + SSUSOffset + PConf0Offset;
   MmioPadval = IoBase + SSUSOffset + PValueOffset; 
 
   GpioValue = MmioRead32 (MmioPadval);
@@ -312,9 +309,7 @@ VOID
   UINT32   GpioValue;
   UINT32   SSUSOffset = 0x2000;
   UINT32   IoBase = 0;
-  UINT32   MmioConf0 = 0;
   UINT32   MmioPadval = 0;
-  UINT32   PConf0Offset = 0x1E0; //GPIO_S5_2 pad_conf0 
register offset
   UINT32   PValueOffset = 0x1E8; //GPIO_S5_2 pad_value 
register offset
   
   PciD31F0RegBase = MmPciAddress (0,
@@ -328,7 +323,6 @@ VOID
   //
   // 0xFED0E1E0/0xFED0E0A8 is pad_Conf/pad_val register address of GPIO_S5_17
   //
-  MmioConf0 = IoBase + SSUSOffset + PConf0Offset;
   MmioPadval = IoBase + SSUSOffset + PValueOffset; 
 
   GpioValue = MmioRead32 (MmioPadval);
-- 
2.14.1.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Platform DxeTrEEPhysicalPresenceLib.

[zwei4]

Add platform specific DxeTrEEPhysicalPresenceLib, which uses serial port 
message as output and GPIO pins as input to communicate with user.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 
---
 .../SouthCluster/Include/Library/PchPlatformLib.h  |  17 +
 .../DxeTrEEPhysicalPresenceLib.c   | 762 +
 .../DxeTrEEPhysicalPresenceLib.inf |  72 ++
 .../DxeTrEEPhysicalPresenceLib.uni |  27 +
 .../PhysicalPresenceStrings.uni|  29 +
 .../Library/PchPlatformLib/PchPlatformLibrary.c|  97 ++-
 Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc|   2 +-
 Vlv2TbltDevicePkg/PlatformPkgIA32.dsc  |   2 +-
 Vlv2TbltDevicePkg/PlatformPkgX64.dsc   |   2 +-
 9 files changed, 1006 insertions(+), 4 deletions(-)
 create mode 100644 
Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.c
 create mode 100644 
Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.inf
 create mode 100644 
Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.uni
 create mode 100644 
Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/PhysicalPresenceStrings.uni

diff --git 
a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h
 
b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h
index 9651f947b9..18b054ce2b 100644
--- 
a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h
+++ 
b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h
@@ -23,6 +23,8 @@ Copyright (c) 2012  - 2014, Intel Corporation. All rights 
reserved
 #ifndef _PCH_PLATFORM_LIB_H_
 #define _PCH_PLATFORM_LIB_H_
 
+#include 
+
 ///
 /// Timeout value used when Sending / Receiving messages.
 /// NOTE: this must cover the longest possible wait time
@@ -83,6 +85,7 @@ PchStepping (
 ;
 
 BOOLEAN
+EFIAPI
 IsPchSupported (
   VOID
   )
@@ -118,13 +121,27 @@ PchAlternateAccessMode (
 **/
 ;
 UINT32
+EFIAPI
 DetectTurbotBoard (
 VOID
   );
 
 UINT32
+EFIAPI
 DetectGpioPinValue (
 VOID
   );
 
+UINT32
+EFIAPI
+DetectGpioSus0PinValue (
+VOID
+  );
+
+UINT32
+EFIAPI
+DetectGpioSus1PinValue (
+VOID
+  );
+
 #endif
diff --git 
a/Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.c
 
b/Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.c
new file mode 100644
index 00..4ca2558a06
--- /dev/null
+++ 
b/Vlv2TbltDevicePkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.c
@@ -0,0 +1,762 @@
+/** @file
+  Execute pending TPM2 requests from OS or BIOS.
+
+  Caution: This module requires additional review when modified.
+  This driver will have external input - variable.
+  This external input must be validated carefully to avoid security issue.
+
+  TrEEExecutePendingTpmRequest() will receive untrusted input and do 
validation.
+
+Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+This program and the accompanying materials 
+are licensed and made available under the terms and conditions of the BSD 
License 
+which accompanies this distribution.  The full text of the license may be 
found at 
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+
+#define CONFIRM_BUFFER_SIZE 4096
+
+EFI_HII_HANDLE mTrEEPpStringPackHandle;
+
+/**
+  Get string by string id from HII Interface.
+
+  @param[in] Id  String ID.
+
+  @retvalCHAR16 *String from ID.
+  @retvalNULLIf error occurs.
+
+**/
+CHAR16 *
+TrEEPhysicalPresenceGetStringById (
+  IN  EFI_STRING_ID   Id
+  )
+{
+  return HiiGetString (mTrEEPpStringPackHandle, Id, NULL);
+}
+
+/**
+  Send ClearControl and Clear command to TPM.
+
+  @param[in]  PlatformAuth  platform auth value. NULL means no platform 
auth change.
+
+  @retval EFI_SUCCESS   Operation completed successfully.
+  @retval EFI_TIMEOUT   The register can't run into the expected 
status in time.
+  @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
+  @retval EFI_DEVICE_ERROR  Unexpected device behavior.
+
+**/
+EFI_STATUS
+EFIAPI
+TpmCommandClear (
+  IN TPM2B_AUTH*PlatformAuth  OPTIONAL
+  )
+{
+  EFI_STATUSStatus;
+  TPMS_AUTH_COMMAND *AuthSession;
+  TPMS_AUTH_COMMAND LocalAuthSession;
+
+  if (PlatformAuth == NULL) {
+AuthSession = NULL;
+  } else {
+AuthSession = 
+ZeroMem (, sizeof(LocalAuthSession));
+LocalAuthSession.sessionHandle =

[edk2] [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Lock SMRAM at proper point.

[zwei4]

(1) Lock SMRAM with EFI_SMM_ACCESS2_PROTOCOL.Lock() before PCI bus enumeration. 
This is for DMA protection.
(2) Call InstallReadyToLock after PCI enumeration and  initialization of 
trusted console. If InstallReadyToLock is called before PCI enumeration, some 
silicon drivers would fail to save S3 boot script.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 
CC: Yao, Jiewen 
CC: Mang, Guo 
---
 .../Library/PlatformBdsLib/BdsPlatform.c   | 111 -
 1 file changed, 88 insertions(+), 23 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c 
b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
index 22cdb4382f..cb5711a620 100644
--- a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -143,8 +143,8 @@ DisableAhciCtlr (
 }
 
 /**
-  Issues EndOfDxe event, installs gExitPmAuthProtocolGuid, and issues SMM lock 
envent. Bus Master DMA mus
-  not be enabled before SMM lock.
+  Lock SMRAM with EFI_SMM_ACCESS2_PROTOCOL. To prevent DMA attack, Bus Master 
DMA of untrusetd PCI devices
+  must not be enabled before SMRAM lock.
 
   @param VOID
 
@@ -152,14 +152,12 @@ DisableAhciCtlr (
 
 **/
 VOID
-InstallReadyToLock (
+SmramLock (
   VOID
   )
 {
   EFI_STATUSStatus;
-  EFI_HANDLEHandle;
   EFI_SMM_ACCESS2_PROTOCOL  *SmmAccess;
-  EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;
   UINTN  PciDeviceConfigAdd;
   UINT16 VendorID;
   UINT16 CommandReg;
@@ -167,7 +165,7 @@ InstallReadyToLock (
   UINT8  FunIndex;
 
   // 
-  // Check Buster Master Enable bit of PCI devices,including PCIe root ports, 
on bus 0.
+  // Check Buster Master Enable bit of untrusted PCI devices,including PCIe 
root ports, on bus 0.
   //
   DEBUG ((DEBUG_ERROR, "BDS: Check Bus Master Enable of PCI devices before 
SMRAM lock: \n"));
   
@@ -204,12 +202,50 @@ InstallReadyToLock (
   // Report error if Bus Master has been enabled.
   //
   if (((CommandReg & BIT2) == BIT2)) {
-  DEBUG ((DEBUG_ERROR, "Error: Bus Master is enabled before SMRAM 
lock!\n"));
+  DEBUG ((DEBUG_ERROR, "Error: Bus Master of above device is enabled 
before SMRAM lock!\n"));
   ASSERT_EFI_ERROR(FALSE);
   }
 }
   }
   
+  //
+  // Lock SMRAM.
+  //
+  Status = gBS->LocateProtocol (
+  ,
+  NULL,
+  (VOID **) 
+  );
+  if (!EFI_ERROR (Status)) {
+//
+//
+//
+Status = SmmAccess->Lock(SmmAccess);
+DEBUG ((DEBUG_ERROR, "SMRAM is locked by EFI_SMM_ACCESS2_PROTOCOL!\n"));
+ASSERT_EFI_ERROR (Status);
+  }
+
+  return ;
+}
+
+/**
+  Issues EndOfDxe event, installs gExitPmAuthProtocolGuid, and issues SMM lock 
envent.
+
+  @param VOID
+
+  @retval  None.
+
+**/
+VOID
+InstallReadyToLock (
+  VOID
+  )
+{
+  EFI_STATUSStatus;
+  EFI_HANDLEHandle;
+  EFI_SMM_ACCESS2_PROTOCOL  *SmmAccess;
+  EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;
+
   //
   // Install DxeSmmReadyToLock protocol prior to the processing of boot options
   //
@@ -240,11 +276,14 @@ InstallReadyToLock (
 NULL
 );
 ASSERT_EFI_ERROR (Status);
+
+DEBUG ((DEBUG_INFO, "Signal gEfiEndOfDxeEventGroupGuid event! End of 
DXE!\n"));
 //
 // Signal EndOfDxe PI Event
 //
 EfiEventGroupSignal ();
 
+DEBUG ((DEBUG_INFO, "Signal gEfiDxeSmmReadyToLockProtocolGuid event!\n"));
 Handle = NULL;
 Status = gBS->InstallProtocolInterface (
 ,
@@ -1855,14 +1894,19 @@ PlatformBdsPolicyBehavior (
 #ifdef FTPM_ENABLE
 TrEEPhysicalPresenceLibProcessRequest(NULL);
 #endif
+
 //
-// Close boot script and install ready to lock
+// Lock SMRAM.
 //
-InstallReadyToLock ();
+SmramLock ();
 
 PlatformBdsInitHotKeyEvent ();
 PlatformBdsConnectSimpleConsole (gPlatformSimpleConsole);
 
+//
+// Close boot script and install ready to lock.
+//
+InstallReadyToLock ();
 
 //
 // Check to see if it's needed to dispatch more DXE drivers.
@@ -1951,9 +1995,9 @@ PlatformBdsPolicyBehavior (
   case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
 
 //
-// Close boot script and install ready to lock
+// Lock SMRAM.
 //
-InstallReadyToLock ();
+SmramLock ();
 
 //
 // In no-configuration boot mode, we can connect the
@@ -1962,6 +2006,11 @@ PlatformBdsPolicyBehavior (
 BdsLibConnectAllDefaultConsoles ();
 PlatformBdsDiagnostics (IGNORE, FALSE, BaseMemoryTest);
 
+//
+// Close boot script and install ready to lock
+//
+InstallReadyToLock ();
+
 //
 // Perform some platform specific connect sequence
 //
@@ -1996,7 +2045,10 @@ PlatformBdsPolicyBehavior (
 
   case BOO

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Initialize SerialNumber of SMBIOS Type 1 Table.

[zwei4]

Get NIC MAC address and fill it into SerialNumber field of SMBIOS Type 1 Table.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../SmBiosMiscDxe/MiscBaseBoardManufacturer.uni| Bin 2448 -> 2430 bytes
 .../SmBiosMiscDxe/MiscChassisManufacturer.uni  | Bin 1990 -> 1892 bytes
 .../SmBiosMiscDxe/MiscSystemManufacturer.uni   | Bin 3406 -> 3438 bytes
 .../SmBiosMiscDxe/MiscSystemManufacturerFunction.c | 230 ++---
 .../Smbios/SmBiosMiscDxe/SmBiosMiscDxe.inf |   4 +-
 .../Common/PlatformSettings/PlatformDxe/Platform.c |   4 +-
 6 files changed, 207 insertions(+), 31 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni
 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni
index 
e53c866ce87e1aeef7f60321f975f2ac2b5c809d..4bb96b13a67a808ebba620e5ad979c92d765
 100644
GIT binary patch
delta 96
zcmbOr{7-1Y6h@1UQ|GfxzQiWQoyw5MkiwA9P{g1#c_WMM<Q_JO%@bG)n1GUEtYHks
YP~i*?H#8A3POu0cSPcU&0~Z(r0G>RR910

delta 180
zcmew-G(mX66h^a+Q|Gg=Ix@I0cus!E8oqfQYXOsH2tz)D0z(o*Dv(TL$YjU?!c>M7
ouvjIK^k>jxa0OytpcebdWgKoK>JZ^{Ga=dz1|<ew1}-oL0Jq`_I

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscChassisManufacturer.uni
 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscChassisManufacturer.uni
index 
8fc00a7beafefa077b932cd2d125b90d349e5c74..fa5f62764f00e5efff56faeaa86c45ec5ca7f458
 100644
GIT binary patch
delta 109
zcmX@c|AcQsAEU*_ennPJHwH%rCk6!u$H}tn){{lp>`+83CvRbMQ1@lXWXJ=;e1>wM
g+I)sYh9ZU(pq?-WV<3raLZtwl$DqW(%fQ6|042l}VgLXD

delta 203
zcmaFDcZ`2RAEVjEennQz5QcmP1%@PsR3Mqgkjan(gsBWEV6jRd>Cd3Y;0naPlW((G
ePyWJcM}iJ(wn`FI-)5^cAlfwyN({UVTnqr(bS7c|

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscSystemManufacturer.uni
 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscSystemManufacturer.uni
index 
da8647f6c7d31b1388c601885014a9dea40065b7..3567f72b9cfcec53748b4d5f82560a4a17ba9120
 100644
GIT binary patch
delta 167
zcmX>n^-gNS3Py{KE2pw3`!ZxQ<N;wmLpehdkW6GKVn|_7U<hMK1#aDa+pt6
zV3(L&!^5$87V8OCV_ceyff{{*T2dHF8FGLIC@{D^X-BXjhqzr79T`f1Dsq8h
dt_;QumJ9|!sK5{mR9ysgN-9G!SY;Z|3jkrKCO7~9

delta 123
zcmaDSbxvx+3P!VyE2pxsIx@I0cy3N)m1oloVaR7tU`S#}1(InDnG88Vn97g>7OMo3
a{tS8yu0ZTNIg!<T@+)o^5_PokyZ`{~K^qeQ

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscSystemManufacturerFunction.c
 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscSystemManufacturerFunction.c
index 1878ce5742..e123b1 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscSystemManufacturerFunction.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/MiscSystemManufacturerFunction.c
@@ -2,7 +2,7 @@
   This driver parses the mMiscSubclassDataTable structure and reports
   any generated data.
 
-  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -22,7 +22,176 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
+/**
+  Return the description for network boot device.
+
+  @param HandleController handle.
+
+  @return  The description string.
+**/
+CHAR16 *
+GetNetworkDescription (
+  IN EFI_HANDLE  Handle
+  )
+{
+  EFI_STATUS Status;
+  EFI_DEVICE_PATH_PROTOCOL   *DevicePath;
+  MAC_ADDR_DEVICE_PATH   *Mac;
+  VLAN_DEVICE_PATH   *Vlan;
+  EFI_DEVICE_PATH_PROTOCOL   *Ip;
+  EFI_DEVICE_PATH_PROTOCOL   *Uri;
+  CHAR16 *Description;
+  UINTN  DescriptionSize;
+
+  Status = gBS->OpenProtocol (
+  Handle,
+  ,
+  NULL,
+  gImageHandle,
+  Handle,
+  EFI_OPEN_PROTOCOL_TEST_PROTOCOL
+  );
+  if (EFI_ERROR (Status)) {
+return NULL;
+  }
+
+  Status = gBS->OpenProtocol (
+  Handle,
+  ,
+  (VOID **) ,
+  gImageHandle,
+  Handle,
+  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+  );
+  if (EFI_ERROR (Status) || (DevicePath == NULL)) {
+return NULL;
+  }
+
+  //
+  // The PXE device path is like:
+  //   ../Mac(...)[/Vlan(...)][/Wi-Fi(...)]
+  //   ../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv4(...)
+  //   ../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv6(...)
+  //
+  // The HTTP device path is like:
+  //   ../Mac(...)[/Vlan(...)][/Wi-Fi(...)]/IPv4(...)/Uri(...)
+  //   ../Mac(...)[/Vlan(...)][/W

[edk2] [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Bus Master DMA protection.

[zwei4]

(1) Clean up code which enables PCI Bus Master DMA before SMRAM lock. (2) Lock 
SMRAM before PCI bus enumeration at BDS stage.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
CC: Yao, Jiewen <jiewen@intel.com>
---
 .../Library/PlatformBdsLib/BdsPlatform.c   | 150 ++---
 .../VlvPlatformInitDxe/VlvPlatformInit.c   |  12 +-
 2 files changed, 111 insertions(+), 51 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c 
b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
index 697ad67a30..e7aa3b30e4 100644
--- a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2004  - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2004  - 2018, Intel Corporation. All rights reserved.



   This program and the accompanying materials are licensed and made available 
under

   the terms and conditions of the BSD License that accompanies this 
distribution.  

@@ -37,7 +37,7 @@ Abstract:
 #include 
 #include 
 #include "PchAccess.h"
-#include "PchRegs/PchRegsSata.h"
+#include "PchRegs.h"
 #include 
 #include 
 
@@ -142,6 +142,15 @@ DisableAhciCtlr (
   }
 }
 
+/**
+  Issues EndOfDxe event, installs gExitPmAuthProtocolGuid, and issues SMM lock 
envent. Bus Master DMA mus
+  not be enabled before SMM lock.
+
+  @param VOID
+
+  @retval  None.
+
+**/
 VOID
 InstallReadyToLock (
   VOID
@@ -151,7 +160,56 @@ InstallReadyToLock (
   EFI_HANDLEHandle;
   EFI_SMM_ACCESS2_PROTOCOL  *SmmAccess;
   EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;
+  UINTN  PciDeviceConfigAdd;
+  UINT16 VendorID;
+  UINT16 CommandReg;
+  UINT8  DevIndex;
+  UINT8  FunIndex;
+
+  // 
+  // Check Buster Master Enable bit of PCI devices,including PCIe root ports, 
on bus 0.
+  //
+  DEBUG ((DEBUG_ERROR, "BDS: Check Bus Master Enable of PCI devices before 
SMRAM lock: \n"));
+  
+  for (DevIndex = 0; DevIndex <= 31; DevIndex ++) {
+
+for (FunIndex = 0; FunIndex <= 7; FunIndex++) {
+
+  if ((DevIndex == 0x00) && (FunIndex == 0x00)) {
+continue; // Skip Root Bridge
+  }
+
+  if ((DevIndex == 0x1A) && (FunIndex == 0x00)) {
+continue; // Skip TXE
+  }
+
+  if ((DevIndex == PCI_DEVICE_NUMBER_PCH_LPC) && (FunIndex == 
PCI_FUNCTION_NUMBER_PCH_LPC)) {
+continue; // Skip LPC Bridge
+  }
+
+
+  PciDeviceConfigAdd  = MmPciAddress (0, 0, DevIndex, FunIndex, 0);
+  VendorID  = MmioRead16 (PciDeviceConfigAdd + PCI_DEVICE_ID_OFFSET);
+  //
+  // Check if PCI device is present.
+  //
+  if (VendorID == 0x) {
+continue;
+  }
 
+  CommandReg   = MmioRead16 (PciDeviceConfigAdd + PCI_COMMAND_OFFSET);
+  DEBUG ((DEBUG_ERROR, "PCI Device 0x%x  Function 0x%x, Command Register 
Value = %x \n", \
+ (UINT32)DevIndex, (UINT32)FunIndex, (UINT32)CommandReg));
+  //
+  // Report error if Bus Master has been enabled.
+  //
+  if (((CommandReg & BIT2) == BIT2)) {
+  DEBUG ((DEBUG_ERROR, "Error: Bus Master is enabled before SMRAM 
lock!\n"));
+  ASSERT_EFI_ERROR(FALSE);
+  }
+}
+  }
+  
   //
   // Install DxeSmmReadyToLock protocol prior to the processing of boot options
   //
@@ -1790,6 +1848,18 @@ PlatformBdsPolicyBehavior (
   switch (BootMode) {
 
   case BOOT_WITH_MINIMAL_CONFIGURATION:
+
+#ifdef TPM_ENABLED
+TcgPhysicalPresenceLibProcessRequest();
+#endif
+#ifdef FTPM_ENABLE
+TrEEPhysicalPresenceLibProcessRequest(NULL);
+#endif
+//
+// Close boot script and install ready to lock
+//
+InstallReadyToLock ();
+
 PlatformBdsInitHotKeyEvent ();
 PlatformBdsConnectSimpleConsole (gPlatformSimpleConsole);
 
@@ -1870,16 +1940,6 @@ PlatformBdsPolicyBehavior (
 }
 
 
-#ifdef TPM_ENABLED
-TcgPhysicalPresenceLibProcessRequest();
-#endif
-#ifdef FTPM_ENABLE
-TrEEPhysicalPresenceLibProcessRequest(NULL);
-#endif
-//
-// Close boot script and install ready to lock
-//
-InstallReadyToLock ();
 
 //
 // Give one chance to enter the setup if we 
@@ -1890,6 +1950,11 @@ PlatformBdsPolicyBehavior (
 
   case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
 
+//
+// Close boot script and install ready to lock
+//
+InstallReadyToLock ();
+
 //
 // In no-configuration boot mode, we can connect the
 // console directly.
@@ -1917,11 +1982,6 @@ PlatformBdsPolicyBehavior (
   }
 }
 
-//
-// Close boot script and install ready to lock
-//
-InstallReadyToLock 

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Update SYSTEM_CONFIGURATION and EFI_GLOBAL_NVS_AREA.

[zwei4]

Add item in SYSTEM_CONFIGURATION and EFI_GLOBAL_NVS_AREA for reporting UART 1 
as PNP0501 COM.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl   | 5 +++--
 Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h | 3 ++-
 Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h | 3 ++-
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl 
b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
index 32cfd9d411..0373e935b7 100644
--- a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
@@ -5,7 +5,7 @@
 ;*Family of Customer Reference Boards.*;
 ;**;
 ;**;
-;*Copyright (c)  1999  - 2016, Intel Corporation. All rights reserved   *;
+;*Copyright (c)  1999  - 2018, Intel Corporation. All rights reserved   *;
 ;
 ; This program and the accompanying materials are licensed and made available 
under
 ; the terms and conditions of the BSD License that accompanies this 
distribution.
@@ -349,6 +349,7 @@ Field(GNVS,AnyAcc,Lock,Preserve)
   DIDX, 32, //(793) Device ID for eDP device
   IOT,  8,  //(794) MinnowBoard Max JP1 is configured for MSFT IOT 
project.
   BATT, 8,  //(795) The Flag of RTC Battery Prensent.  
-  LPAD, 8,  //(796)   
+  LPAD, 8,  //(796) 
+  U1CM, 8,  //(797) Report UART1 as PNP0501 COM. 
 }
 
diff --git a/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h 
b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
index c7c51d0d2a..fc2fc86f77 100644
--- a/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
+++ b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
@@ -1,6 +1,6 @@
 /*++
 
-  Copyright (c) 2004  - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2004  - 2018, Intel Corporation. All rights reserved.


 
   This program and the accompanying materials are licensed and made available 
under
@@ -1310,6 +1310,7 @@ typedef struct {
   UINT8   GpioWakeCapability;
   UINT8   RtcBattery;
   UINT8   LpeAudioReportedByDSDT;
+  UINT8   Uart1Pnp0501Com; // Report UART1 as PNP0501 COM
 
 } SYSTEM_CONFIGURATION;
 #pragma pack()
diff --git a/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h 
b/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
index aa7ec9277e..03468f9357 100644
--- a/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
+++ b/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
@@ -1,6 +1,6 @@
 /*++
 
-  Copyright (c) 2004  - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2004  - 2018, Intel Corporation. All rights reserved.


 
   This program and the accompanying materials are licensed and made available 
under
@@ -473,6 +473,7 @@ typedef struct {
   UINT8   MicrosoftIoT;  // (794)JP1 pins are for 
Microsoft IoT project.
   UINT8   RtcBattery;// (795) The Flag of RTC 
Battery Present.
   UINT8   LpeAudioReportedByDSDT;// (796)
+  UINT8   Uart1Pnp0501Com;   // (797) Report UART 1 as 
PNP0501 COM.
 } EFI_GLOBAL_NVS_AREA;
 #pragma pack ()
 
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Change BIOS Version.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: David Wei 
---
 Platform/BroxtonPlatformPkg/BiosId.env | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/BroxtonPlatformPkg/BiosId.env 
b/Platform/BroxtonPlatformPkg/BiosId.env
index d7e8aa6841..350fac8253 100644
--- a/Platform/BroxtonPlatformPkg/BiosId.env
+++ b/Platform/BroxtonPlatformPkg/BiosId.env
@@ -31,5 +31,5 @@ BOARD_ID  = APLKRVP
 BOARD_REV = 3
 BUILD_TYPE= D
 VERSION_MAJOR = 0069
-VERSION_MINOR = 02
+VERSION_MINOR = 03
 BOARD_EXT = X64
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Add Memory test code.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../PlatformBootManagerLib/PlatformBootManager.c   | 23 +-
 .../PlatformBootManagerLib.inf |  1 +
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
index 7c7a98e2b9..6715d9073b 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1000,10 +1001,30 @@ PlatformBootManagerAfterConsole (
   VOID
   )
 {
-  EFI_BOOT_MODE LocalBootMode;
+  EFI_STATUSStatus;
+  EFI_BOOT_MODE LocalBootMode;
+  BOOLEAN   RequireSoftECCInit;
+  EFI_GENERIC_MEMORY_TEST_PROTOCOL  *GenMemoryTest;
   
   DEBUG ((EFI_D_INFO, "PlatformBootManagerAfterConsole\n"));
 
+  //
+  // Run memory test code at this point.
+  //
+  Status = gBS->LocateProtocol (
+  ,
+  NULL,
+  (VOID **) 
+  );
+
+  if (!EFI_ERROR (Status)) {
+Status = GenMemoryTest->MemoryTestInit (
+  GenMemoryTest,
+  IGNORE,
+  
+  );
+  } 
+
   //
   // Get current Boot Mode.
   //
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 8e429fbf9f..9f476a14d0 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -92,6 +92,7 @@
   gEfiFormBrowser2ProtocolGuid
   gExitPmAuthProtocolGuid
   gEfiGraphicsOutputProtocolGuid
+  gEfiGenericMemTestProtocolGuid
   
 [Guids]
   gEfiGlobalVariableGuid
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Remove UHCI and EHCI drivers.

[zwei4]

Remove UHCI and EHCI drivers because these USB controllers are not present on 
E3900 SoC.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 2 --
 1 file changed, 2 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf 
b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
index 80184c0526..6a538fb449 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
@@ -680,8 +680,6 @@ APRIORI DXE {
   # USB
   #
 !if $(USB_ENABLE) == TRUE  &&  $(USB_NATIVE_ENABLE) == TRUE
-  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
-  INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Fix VS2015 build failure.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: David Wei 
---
 .../PlatformBootManagerLib/PlatformBootOption.c| 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootOption.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootOption.c
index bed512a462..c77b20f686 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootOption.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootOption.c
@@ -24,9 +24,9 @@ EFI_EVENT  HotKeyEvent= NULL;
 UINTN  mUiAppOptionNumber;
 CHAR16 *TmpStr = L"Press [F2] key to enter BIOS Setup";
 
-EFI_GRAPHICS_OUTPUT_BLT_PIXEL Foreground;
-EFI_GRAPHICS_OUTPUT_BLT_PIXEL Background;
-EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
+EFI_GRAPHICS_OUTPUT_BLT_PIXEL mForeground;
+EFI_GRAPHICS_OUTPUT_BLT_PIXEL mBackground;
+EFI_GRAPHICS_OUTPUT_BLT_PIXEL mColor;
 
 EFI_GUID mUiFile = { 0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 
0xF4, 0x66, 0x23, 0x31 } };
 EFI_GUID mBootMenuFile = { 0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 
0x1B, 0x20, 0x39, 0xD1, 0x1D }};
@@ -432,16 +432,16 @@ PlatformBootManagerWaitCallback (
 
   TimeoutDefault = PcdGet16 (PcdPlatformBootTimeOut);
   if (TimeoutDefault == TimeoutRemain) {
-SetMem (, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
-SetMem (, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0);
-SetMem (, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
+SetMem (, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
+SetMem (, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0);
+SetMem (, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
   }
 
   PlatformBdsShowProgress (
-Foreground,
-Background,
+mForeground,
+mBackground,
 TmpStr,
-Color,
+mColor,
 ((TimeoutDefault - TimeoutRemain) * 100 / TimeoutDefault),
 0
 );
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Change BDS module.

[zwei4]

Change from BDS of IntelFrameworkModulePkg to BDS of MdeModulePkg.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/Library/PlatformBootManagerLib/PlatformBootManager.c  | 5 +
 Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc   | 9 -
 Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc   | 3 +++
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf  | 6 --
 4 files changed, 16 insertions(+), 7 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
index 3dffe72636..7c7a98e2b9 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -35,7 +35,6 @@
 #include 
 #include 
 
-#pragma optimize("g", off)
 
 #define TIMEOUT_COMMAND 10
 #define BIOS_COLOR_CODING_BAR_HEIGHT  40
@@ -635,8 +634,6 @@ UpdateDevicePath (
   return Return;
 }
 
-#pragma optimize("g", off)
-
 /**
   Check if current BootCurrent variable is internal shell boot option.
 
@@ -1047,6 +1044,6 @@ PlatformBootManagerAfterConsole (
   }
   
   if (IsNeedSortBootOption()) {
-EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, 
CompareBootOption);
+EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, 
(SORT_COMPARE)CompareBootOption);
   }
 }
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
index 3135d4dc69..c6313cdd5d 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
@@ -107,7 +107,7 @@
   GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
   }
 
-  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf {
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf {
 
   OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
   IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
@@ -116,6 +116,13 @@
   NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
   
NULL|$(PLATFORM_PACKAGE_COMMON)/Library/Tpm2DeviceLibPtp/Tpm2InstanceLibPtt.inf
   }
+  MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+
+  NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+  NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+  
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
 
   
$(PLATFORM_PACKAGE_COMMON)/SampleCode/IntelFsp2WrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
 
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc
index a4bc20973d..2320d2f9c6 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc
@@ -272,3 +272,6 @@
 

BltLib|$(PLATFORM_PACKAGE_COMMON)/Library/FrameBufferBltLib/FrameBufferBltLib.inf
 
+   UefiBootManagerLib | 
MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+   PlatformBootManagerLib | 
Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+   BootLogoLib | MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
\ No newline at end of file
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf 
b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
index 9af77d5901..80184c0526 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
@@ -527,7 +527,9 @@ APRIORI DXE {
   INF UefiCpuPkg/CpuDxe/CpuDxe.inf
   INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
 
-  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
 
 !if $(TOOL_CHAIN_TAG) != GCC5
   INF 
$(PLATFORM_PACKAGE_COMMON)/SampleCode/IntelFsp2WrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
@@ -752,7 +754,7 @@ APRIORI DXE {
   #
   # UEFI Shell
   #
-  FILE APPLICATION = 
PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) {
+  FILE APPLICATION = 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1 {
 SECTION PE32 = ShellBinPkg/UefiShell/$(IA32_X64_LC)/Shell.efi
   }
 
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Platform Boot Manager Library.

[zwei4]

Add library instance of PlatformBootManagerLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../PlatformBootManagerLib/PlatformBootManager.c   | 1052 
 .../PlatformBootManagerLib/PlatformBootManager.h   |  226 +
 .../PlatformBootManagerLib.inf |  109 ++
 .../PlatformBootManagerLib/PlatformBootOption.c|  738 ++
 .../Library/PlatformBootManagerLib/PlatformData.c  |  179 
 5 files changed, 2304 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootOption.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformData.c

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
new file mode 100644
index 0..3dffe7263
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -0,0 +1,1052 @@
+/** @file
+  This file include all platform action at BDS stage which can be customized 
by IBV/OEM.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformBootManager.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#pragma optimize("g", off)
+
+#define TIMEOUT_COMMAND 10
+#define BIOS_COLOR_CODING_BAR_HEIGHT  40
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_HII_HANDLE
gPlatformBdsLibStringPackHandle;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE mBootMode;
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GUID  *mLibTerminalType[] = {
+  ,
+  ,
+  ,
+  
+};
+
+//
+// Internal shell mode
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellModeColumn;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellModeRow;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellHorizontalResolution;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellVerticalResolution;
+
+CHAR16  *mConsoleVar[] = {L"ConIn", L"ConOut"};
+
+extern USB_CLASS_FORMAT_DEVICE_PATH mUsbClassKeyboardDevicePath;
+extern BOOLEAN  mAnyKeypressed;
+
+/**
+  The handle on the path we get might be not the display device.
+  We must check it.
+
+  @todo fix the parameters
+
+  @retval  TRUE PCI class type is VGA.
+  @retval  FALSEPCI class type isn't VGA.
+**/
+BOOLEAN
+IsVgaHandle (
+  IN EFI_HANDLE Handle
+)
+{
+  EFI_PCI_IO_PROTOCOL *PciIo;
+  PCI_TYPE00 Pci;
+  EFI_STATUS Status;
+
+  Status = gBS->HandleProtocol (
+  Handle,
+  ,
+  (VOID **));
+
+  if (!EFI_ERROR (Status)) {
+Status = PciIo->Pci.Read (
+  PciIo,
+  EfiPciIoWidthUint32,
+  0,
+  sizeof (Pci) / sizeof (UINT32),
+  );
+
+if (!EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "  PCI CLASS CODE= 0x%x\n", Pci.Hdr.ClassCode 
[2]));
+  DEBUG ((DEBUG_ERROR, "  PCI SUBCLASS CODE = 0x%x\n", Pci.Hdr.ClassCode 
[1]));
+
+  if (IS_PCI_VGA () || IS_PCI_OLD_VGA ()) {
+DEBUG ((DEBUG_ERROR, "  \nPCI VGA Device Found\n"));
+return TRUE;
+  }
+}
+  }
+  return FALSE;
+}
+
+/**
+  This function converts an input device structure to a Unicode string.
+
+  @param DevPath  A pointer to the device path structure.
+
+  @return A new allocated Unicode string that represents the device path.
+**/
+CHAR16 *
+DevicePathToStr (
+  IN EFI_DEVICE_PATH_PROTOCOL *DevPath
+  )
+{
+  EFI_STATUS   Status;
+  CHAR16   *ToText;
+  EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *DevPathToText;
+
+  if (DevPath == NULL) {
+return NULL;
+  }
+
+  Status = gBS->LocateProtocol (
+  ,
+  NULL,
+   

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] AX88179 UNDI driver.

[zwei4]

Add UNDI driver for AX88179 USB-to-LAN adapter.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf 
b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
index 6c377553f..9af77d590 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
@@ -702,10 +702,17 @@ APRIORI DXE {
   # LAN/Network
   #
 !if $(NETWORK_ENABLE) == TRUE
+  
+  FILE DRIVER = 51B24E4E-FDD2-4047-BE4D-131873A457B2 {
+SECTION PE32 = 
BroxtonPlatformPkg/Common/Binaries/UNDI/AX88179/AX88179_178A_UEFI_V2.7.0_X64.efi
+SECTION UI = "UNDI"
+  }
+
   FILE DRIVER = 2E561D56-4863-44F7-960D-EF2D7F2D35BB {
 SECTION PE32 = 
BroxtonPlatformPkg/Common/Binaries/UNDI/I210PcieUndiDxe/E7320X3.EFI
 SECTION UI = "UNDI"
   }
+
   INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
   INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
   INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Add control method power button.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/Acpi/AcpiTablesPCAT/Platform.asl   | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl
index 4674f70f2..49ddd10ff 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl
@@ -1,5 +1,5 @@
 /** @file
-  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -178,6 +178,8 @@ Method(_WAK,1,Serialized)
 {
   P8XH(1,0xAB) // Beginning of _WAK.
 
+  Notify(\_SB.PWRB,0x02)
+
   If (NEXP) {
 // Reinitialize the Native PCI Express after resume
 If (And(OSCC,0x02)) {
@@ -718,6 +720,21 @@ Scope(\_SB)
 }
   }//end scope
 
+  //
+  // Define a Control Method Power Button.
+  //
+  Device(PWRB)
+  {
+Name(_HID,EISAID("PNP0C0C"))
+
+// GPE16 = Waketime SCI.  
+Name(_PRW, Package() {16,4})
+  }
+
+  Device(SLPB)
+  {
+Name(_HID, EISAID("PNP0C0E"))
+  }
 } // end Scope(\_SB)
 
 Scope (\)
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Add UID for SueCreek LEDs.

[zwei4]

The _UID must be unique across all devices with a common _HID.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreekLeds.asl   | 2 ++
 1 file changed, 2 insertions(+)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreekLeds.asl
 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreekLeds.asl
index 2fcc45742..2f00f6795 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreekLeds.asl
+++ 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreekLeds.asl
@@ -15,6 +15,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 Scope(\_SB.PCI0.I2C5) {
   Device (LED0) {
 Name (_HID, "PCA9956")
+Name (_UID, 0)
 Name (_DDN, "SueCreekLed, CS0")
 Name (SBUF, ResourceTemplate () {
   I2cSerialBus (
@@ -42,6 +43,7 @@ Scope(\_SB.PCI0.I2C5) {
   }
   Device (LED1) {
 Name (_HID, "PCA9956")
+Name (_UID, 1)
 Name (_DDN, "SueCreekLed, CS0")
 Name (SBUF, ResourceTemplate () {
   I2cSerialBus (
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] IDTP9180 PMIC Power Sequence Configuration.

[zwei4]

Change Bit 2 (SUSPWRDNACKCFG) of Power Sequence Configuration register (offset 
0x2A) to 1.
If SUSPWRDNACKCFG is 0, SUSPWRDNACK signal is ignored. PMIC will not go to G3 
when SUSPWRDNACK goes high in S4 state.
If SUSPWRDNACKCFG is 1, PMIC responses to SUSPWRDNACK signal.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../AuroraGlacier/BoardInitDxe/BoardInitDxe.c  | 114 
 .../AuroraGlacier/BoardInitDxe/BoardInitDxe.inf|   1 +
 .../BensonGlacier/BoardInitDxe/BoardInitDxe.c  | 115 -
 .../BensonGlacier/BoardInitDxe/BoardInitDxe.inf|   1 +
 .../PlatformSettings/PlatformDxe/PlatformDxe.inf   |   2 +-
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf|   5 +
 Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc   |  15 ++-
 Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc|   6 +-
 .../BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h |   2 +-
 .../SouthCluster/Smbus/Dxe/PchSmbusEntry.c |   2 +
 10 files changed, 258 insertions(+), 5 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c
index e948594c8..f06a540eb 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c
@@ -15,6 +15,7 @@
 **/
 
 #include "BoardInitDxe.h"
+#include 
 
 GET_BOARD_NAME mAuroraGetBoardNamePtr = AuroraGetBoardName;
 
@@ -38,6 +39,111 @@ AuroraGetBoardName (
 }
 
 
+VOID
+EFIAPI
+AuroraProgramPmicPowerSequence (
+  EFI_EVENT  Event,
+  VOID   *Context
+  )
+{
+  EFI_STATUSStatus;
+  EFI_SMBUS_DEVICE_ADDRESS  SlaveAddress;
+  EFI_SMBUS_DEVICE_COMMAND  Command;
+  UINTN Length;
+  UINT8 BufferData[1];
+  EFI_SMBUS_HC_PROTOCOL *SmbusControllerProtocol;
+  
+  //
+  // Programe IDTP9810 PMIC.
+  //
+  
+  DEBUG ((EFI_D_INFO, "Programe PMIC. \n"));
+  
+  //
+  // Locate SMBus protocol
+  //
+  Status  = gBS->LocateProtocol (, NULL, (VOID 
**));
+  ASSERT_EFI_ERROR(Status);
+  
+  SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+  Command = 0x00; // Offset
+  Length  = 1;
+  
+  //
+  // Read one byte
+  //
+  Status = SmbusControllerProtocol->Execute ( 
+  SmbusControllerProtocol,
+  SlaveAddress,
+  Command,
+  EfiSmbusReadByte,
+  FALSE,
+  ,
+  BufferData
+  );
+  
+  
+  DEBUG ((EFI_D_INFO, "PMIC Vendor ID = %0x. \n", (UINT32) BufferData[0]));
+  
+
+  SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+  Command = 0x2A; // Offset
+  Length  = 1;
+  
+  //
+  // Read one byte
+  //
+  Status = SmbusControllerProtocol->Execute ( 
+  SmbusControllerProtocol,
+  SlaveAddress,
+  Command,
+  EfiSmbusReadByte,
+  FALSE,
+  ,
+  BufferData
+  );
+  
+  
+  DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration  Offset 0x2A 
PWRSEQCFG = %0x. \n", (UINT32) BufferData[0])); 
+
+  //
+  // Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG.
+  // 0 = SUSPWRDNACK signal is ignored. PMIC will not go to G3 when 
SUSPWRDNACK goes high in S4 state.
+  // 1 = PMIC responses to SUSPWRDNACK signal.
+  //
+  //
+  BufferData[0] = BufferData[0] | 0x04;
+  Status = SmbusControllerProtocol->Execute ( 
+  SmbusControllerProtocol,
+  SlaveAddress,
+  Command,
+  EfiSmbusWriteByte,
+  FALSE,
+  ,
+  BufferData
+  );
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration  Set Bit 2 
(SUSPWRDNACKCFG) of PWRSEQCFG. \n")); 
+
+
+  //
+  // Read one byte
+  //
+  Status = SmbusControllerProtocol->Execute ( 
+  SmbusControllerProtocol,
+  SlaveAddress,
+  Command,
+  EfiSmbusReadByte,
+  FALSE,
+  ,
+  BufferData
+  );
+  
+  
+  D

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] SMBus Host driver.

[zwei4]

Add Apollo Lake SMBus host controller DXE driver.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h | 358 +++
 .../SouthCluster/Smbus/Dxe/PchSmbusArp.c   | 673 +
 .../SouthCluster/Smbus/Dxe/PchSmbusDxe.inf |  63 ++
 .../SouthCluster/Smbus/Dxe/PchSmbusEntry.c | 155 +
 4 files changed, 1249 insertions(+)
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusArp.c
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusDxe.inf
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
new file mode 100644
index 0..5e226a80d
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
@@ -0,0 +1,358 @@
+/** @file
+  PCH SMBus Protocol.
+
+  Copyright (c) 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DXE_PCH_SMBUS_H
+#define _DXE_PCH_SMBUS_H
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// Definitions
+//
+
+///
+/// Max number of SMBus devices (7 bit address yields 128 combinations but 21 
of those are reserved)
+///
+#define MAX_SMBUS_DEVICES 107
+#define MICROSECOND 10
+#define MILLISECOND (1000 * MICROSECOND)
+#define ONESECOND   (1000 * MILLISECOND)
+
+///
+/// Private Data Structures
+///
+typedef struct _SMBUS_NOTIFY_FUNCTION_LIST_NODE {
+  UINT32Signature;
+  LIST_ENTRYLink;
+  EFI_SMBUS_DEVICE_ADDRESS  SlaveAddress;
+  UINTN Data;
+  EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction;
+} SMBUS_NOTIFY_FUNCTION_LIST_NODE;
+
+#define SMBUS_NOTIFY_FUNCTION_LIST_NODE_FROM_LINK(_node) \
+  CR ( \
+  _node, \
+  SMBUS_NOTIFY_FUNCTION_LIST_NODE, \
+  Link, \
+  PCH_SMBUS_PRIVATE_DATA_SIGNATURE \
+  )
+
+///
+/// Declare a local instance structure for this driver
+///
+typedef struct _SMBUS_INSTANCE {
+  UINTN Signature;
+  EFI_HANDLEHandle;
+
+  UINT32SmbusIoBase;
+  SMBUS_IO_READ SmbusIoRead;
+  SMBUS_IO_WRITESmbusIoWrite;
+  SMBUS_IO_DONE IoDone;
+
+  ///
+  /// Published interface
+  ///
+  EFI_SMBUS_HC_PROTOCOL SmbusController;
+
+  UINT8 DeviceMapEntries;
+  EFI_SMBUS_DEVICE_MAP  DeviceMap[MAX_SMBUS_DEVICES];
+
+  UINT8 PlatformNumRsvd;
+  CONST UINT8   *PlatformRsvdAddr;
+
+  LIST_ENTRYNotifyFunctionList;
+  EFI_EVENT NotificationEvent;
+
+} SMBUS_INSTANCE;
+
+//
+// Driver global data
+//
+SMBUS_INSTANCE  *mSmbusContext;
+
+//
+// Prototypes
+//
+
+/**
+  Execute an SMBUS operation
+
+  @param[in] This The protocol instance
+  @param[in] SlaveAddress The address of the SMBUS slave device
+  @param[in] Command  The SMBUS command
+  @param[in] OperationWhich SMBus protocol will be issued
+  @param[in] PecCheck If Packet Error Code Checking is to be used
+  @param[in, out] Length  Length of dta
+  @param[in, out] Buffer  Data buffer
+
+  @retval EFI_SUCCESS The SMBUS operation is successful
+  @retval Others  Something error occurred
+**/
+EFI_STATUS
+EFIAPI
+SmbusExecute (
+  IN  CONST EFI_SMBUS_HC_PROTOCOL   *This,
+  IN  EFI_SMBUS_DEVICE_ADDRESS  SlaveAddress,
+  IN  EFI_SMBUS_DEVICE_COMMAND  Command,
+  IN  EFI_SMBUS_OPERATION   Operation,
+  IN  BOOLEAN   PecCheck,
+  IN OUT  UINTN *Length,
+  IN OUT  VOID  *Buffer
+  );
+
+/**
+  SMBus DXE Module Entry Point.
+  
+  - Introduction
+The SMBus module is a DXE driver that provides a standard way to execute 
an SMBus command.
+
+  - @pre
+- @link SC_POLICY SC_POLICY_HOB @endlink
+  - This module uses the parameters in SmbusConfig for platform reserved 
(non ARP capable) addresses.
+
+  - @result
+The SMBus driver produces EFI_SMBUS_HC_PROTOCOL which is documented in the 
SMBus Host Controller
+Protocol Specification.
+
+  @param[in] ImageHandle  ImageHandle of this 

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] SMBus Library.

[zwei4]

Apollo Lake South Cluster SMBus executive code, which is common for PEI, DXE 
and SMM modules.

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
Cc: Mang Guo <mang@intel.com>
---
 .../PeiDxeSmmScSmbusCommonLib.inf  |  35 ++
 .../PeiDxeSmmScSmbusCommonLib/ScSmbusExec.c| 653 +
 2 files changed, 688 insertions(+)
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf
 create mode 100644 
Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/ScSmbusExec.c

diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf
 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf
new file mode 100644
index 0..2ca6549b8
--- /dev/null
+++ 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf
@@ -0,0 +1,35 @@
+## @file
+#  Apollo Lake South Cluster Smbus Common Lib.
+#
+#  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PeiDxeSmmPchSmbusCommonLib
+  FILE_GUID  = 490CEB45-F3A8-41CD-89CB-C47BF7F7A4B4
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ScSmbusCommonLib
+
+[Sources]
+  ScSmbusExec.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  BroxtonSiPkg/BroxtonSiPkg.dec
+  BroxtonSiPkg/BroxtonSiPrivate.dec
+
+[LibraryClasses]
+  IoLib
+  DebugLib
+  MmPciLib
diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/ScSmbusExec.c
 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/ScSmbusExec.c
new file mode 100644
index 0..2c5fe9b7b
--- /dev/null
+++ 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/ScSmbusExec.c
@@ -0,0 +1,653 @@
+/** @file
+  Apollo Lake South Cluster Smbus Executive Code (common PEI/DXE/SMM code).
+
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Get SMBUS IO Base address.
+
+  @param[in]  None
+
+  @retval UINT32  The SMBUS IO Base Address
+**/
+UINT32
+SmbusGetIoBase (
+  VOID
+  )
+{
+  UINT32  SmbusIoBase;
+
+  SmbusIoBase = MmioRead32 (
+ MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_SC,
+ PCI_DEVICE_NUMBER_SMBUS,
+ PCI_FUNCTION_NUMBER_SMBUS)
+ + R_SMBUS_BASE) & B_SMBUS_BASE_BAR;
+
+  ASSERT (SmbusIoBase != B_SMBUS_BASE_BAR && SmbusIoBase != 0);
+
+  return SmbusIoBase;
+}
+
+/**
+  This function provides a standard way to read PCH Smbus IO registers.
+
+  @param[in] Offset   Register offset from Smbus base IO address.
+
+  @retval UINT8   Returns data read from IO.
+**/
+UINT8
+EFIAPI
+SmbusIoRead (
+  IN  UINT8   Offset
+  )
+{
+  return IoRead8 (SmbusGetIoBase () + Offset);
+}
+
+/**
+  This function provides a standard way to write PCH Smbus IO registers.
+
+  @param[in] Offset   Register offset from Smbus base IO address.
+  @param[in] Data Data to write to register.
+
+**/
+VOID
+EFIAPI
+SmbusIoWrite (
+  IN  UINT8   Offset,
+  IN  UINT8   Data
+  )
+{
+
+  IoWrite8 (SmbusGetIoBase () + Offset, Data);
+  return;
+}
+
+/**
+  This function provides a standard way to check if a SMBus transaction has
+  completed.
+
+  @param[in] StsReg   Not used for input. On return, contains the
+  value of the SMBus status register.
+
+  @retval TRUETransaction is complete

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Fix Windows 10 S3 failure.

[zwei4]

The FSP-S preferred memory region, which is defined in FSP Integration Guide, 
must be reserved for BIOS S3 resume.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../PlatformPreMemPei/FvCallback.c | 29 +++---
 .../PlatformDsc/PcdsFixedAtBuild.dsc   |  2 ++
 2 files changed, 11 insertions(+), 20 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
index 6a2c9fd91..4a3a67574 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
@@ -269,7 +269,6 @@ ParseObbPayload (
   UINTNVariableSize;
   EFI_STATUS   Status;
   EFI_FIRMWARE_VOLUME_HEADER   *FvHeader;
-  EFI_FIRMWARE_VOLUME_HEADER   *FvHeaderS3;
   EFI_PLATFORM_INFO_HOB*PlatformInfo;
   EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariableServices;
   SYSTEM_CONFIGURATION SystemConfiguration;
@@ -298,13 +297,17 @@ ParseObbPayload (
   DEBUG ((EFI_D_INFO, "FSP-S Fsp Size = 0x%X\n", FspHeader->ImageSize));
 
   //
-  // Copy to FSP-S to preferred base
+  // Copy to FSP-S to preferred base. The preferred base is defined in FSP 
Integration Guide.
+  // This region must be reserved for BIOS S3 resume.
   //
+  BuildMemoryAllocationHob (
+(EFI_PHYSICAL_ADDRESS)FspSImageBase,
+(UINT64)FspHeader->ImageSize,
+EfiReservedMemoryType
+  );
   CopyMemSse4 ((VOID*) FspSImageBase, FvHeader, (UINT32) FvHeader->FvLength);
 
-  if (BootMode != BOOT_ON_S3_RESUME) {
-PcdSet32S (PcdFspsBaseAddress, (UINT32) FspSImageBase);
-  }
+  PcdSet32S (PcdFspsBaseAddress, (UINT32) FspSImageBase);
 
   while ((UINT32) FvHeader < PayloadTail) {
 if (FvHeader->Signature != EFI_FVH_SIGNATURE) {
@@ -319,21 +322,7 @@ ParseObbPayload (
 }
 DEBUG ((EFI_D_INFO, "Found Fv with GUID: %g\n", FvName));
 
-if (BootMode == BOOT_ON_S3_RESUME) {
-  //
-  // FspW requires both IBBR and FSP-S on S3 resume
-  // but only copy FSP-S, do not install it.
-  //
-  DEBUG ((DEBUG_INFO, "S3 Resume: Only looking for IBBR and FSP-S.\n"));
-  if (CompareGuid (FvName, ) || CompareGuid 
(FvName, )) {
-FvHeaderS3 = FvHeader;
-if (CompareGuid (FvName, )) {
-  PeiServicesInstallFvInfoPpi (NULL, FvHeaderS3, (UINT32) 
FvHeaderS3->FvLength, NULL, NULL);
-} else {
-  PcdSet32S (PcdFspsBaseAddress, (UINT32) FvHeaderS3);
-}
-  }
-} else if (CompareGuid (>FileSystemGuid, 
)) {
+if (CompareGuid (>FileSystemGuid, )) {
   DEBUG ((EFI_D_INFO, "NVStorage FV at 0x%x.\n", (UINT32) FvHeader));
   Status = PeiServicesLocatePpi (, 0, 
NULL, (VOID **) );
   if (EFI_ERROR (Status)) {
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFixedAtBuild.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFixedAtBuild.dsc
index b7cefdca0..6c26acaf5 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFixedAtBuild.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFixedAtBuild.dsc
@@ -83,4 +83,6 @@
 gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
   !endif
+  
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x3000
 
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Disable xDCI.

[zwei4]

Disable xDCI and assign USB3 Port 0 (OTG port) to xHCI.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi   | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
index f45d47a82..c6e9410ad 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -2411,8 +2411,8 @@ form formid = USB_OPTIONS_FORM_ID,
   oneof varid   = Setup.ScUsbOtg,
 prompt  = STRING_TOKEN(STR_USB_XDCI_PROMPT),
 help= STRING_TOKEN(STR_USB_XDCI_HELP),
-option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
-option text = STRING_TOKEN(STR_PCI_MODE_STRING), value = 1, flags = 
DEFAULT | MANUFACTURING | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_PCI_MODE_STRING), value = 1, flags = 
RESET_REQUIRED;
 //  option text = STRING_TOKEN(STR_ACPI_MODE_STRING), value = 2, flags = 
RESET_REQUIRED;
   endoneof;
 
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] DMIC NHLT Entry.

[zwei4]

Customize DMIC NHLT entry for boards.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/AuroraGlacier/BoardInitPostMem/BoardInit.c | 5 +
 .../Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf| 3 ++-
 .../Board/BensonGlacier/BoardInitPostMem/BoardInit.c | 7 ++-
 .../Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf| 3 ++-
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c  | 9 +++--
 .../Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf | 3 ++-
 .../Board/MinnowBoard3/BoardInitPostMem/BoardInit.c  | 7 ++-
 .../Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf | 3 ++-
 .../PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi | 6 +++---
 Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec | 8 ++--
 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScHda.c  | 6 +-
 .../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInitDxe.inf   | 4 +++-
 12 files changed, 49 insertions(+), 15 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
index 2f33bfe21..5ede1f114 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInit.c
@@ -144,6 +144,11 @@ AuroraGlacierPostMemInitCallback (
   PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 1);  // I2S2
   PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 1);   // I2S2
 
+  //
+  // DMIC
+  //
+  PcdSet8(NhltEndpointDmic, (UINT8) 
SystemConfiguration.ScHdAudioNhltEndpointDmic);
+
   //
   // Add init steps here
   //
diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
index f47cb4f28..ec30b262c 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -72,7 +72,8 @@
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId
-
+  gEfiBxtTokenSpaceGuid.NhltEndpointDmic
+  
 [Guids]
   gEfiPlatformInfoGuid
   gEfiAuthenticatedVariableGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index aabb350e8..deb36c610 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -1,7 +1,7 @@
 /** @file
   Board Init driver.
 
-  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -143,6 +143,11 @@ BensonGlacierPostMemInitCallback (
   PcdSet8(HdaEndpointI2sRenderSKPVirtualBusId, 1); // I2S2
   PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 1);  // I2S2
   PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 1);   // I2S2
+  
+  //
+  // DMIC
+  //
+  PcdSet8(NhltEndpointDmic, (UINT8) 
SystemConfiguration.ScHdAudioNhltEndpointDmic);
 
   //
   // Add init steps here
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
index c7499b564..53fa6756f 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -2,7 +2,7 @@
 #  Board detected module for Intel(R) Atom(TM) x5 Processor Series.
 #  It will detect the board ID.
 #
-#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
@@ -72,6 +72,7 @@
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId
   gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId
+  gEfiBxtTokenSpaceGuid.NhltEndpointDmic
 
 [Guids]
   gEfiPlatformInfoGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
index fdf2c7eaa..fdd6b4de6 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
+++ b/Pl

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 2/2] Change BIOS Version.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/BiosId.env | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/BroxtonPlatformPkg/BiosId.env 
b/Platform/BroxtonPlatformPkg/BiosId.env
index fc9d10eaa..ed144815c 100644
--- a/Platform/BroxtonPlatformPkg/BiosId.env
+++ b/Platform/BroxtonPlatformPkg/BiosId.env
@@ -31,5 +31,5 @@ BOARD_ID  = APLKRVP
 BOARD_REV = 3
 BUILD_TYPE= D
 VERSION_MAJOR = 0068
-VERSION_MINOR = 03
+VERSION_MINOR = 04
 BOARD_EXT = X64
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 1/2] FAB ID.

[zwei4]

Add code to detect FAB ID of Aurora Glacier.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/AuroraGlacier/BoardInitPreMem/BoardInit.c  | 16 +++-
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c
index bda774cb2..41d1c5af3 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c
@@ -73,15 +73,13 @@ AuroraGlacierPreMemInit (
 
   DEBUG ((EFI_D_INFO,  "This is Aurora Glacier board.\n"));
   
-  //
-  //Status = AuroraGetFabId (PeiServices, );
-  //if (FabId == 1) {
-  //  DEBUG ((EFI_D_INFO,  "This is Aurora Glacier FAB B.\n"));
-  //} else if (FabId == 0) {
-  //  DEBUG ((EFI_D_INFO,  "This is Aurora Glacier FAB A.\n"));
-  //}
-  //
-  FabId = 0;
+  
+  Status = AuroraGetFabId (PeiServices, );
+  if (FabId == 1) {
+DEBUG ((EFI_D_INFO,  "This is Aurora Glacier FAB B.\n"));
+  } else if (FabId == 0) {
+DEBUG ((EFI_D_INFO,  "This is Aurora Glacier FAB A.\n"));
+  }
   
   PcdSet8 (PcdBoardId, BoardId);
   PcdSet8 (PcdFabId, FabId);
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Fix License Header.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
Cc: michael.d.kin...@intel.com
Cc: mike...@intel.com
---
 .../Library/SerialPortLib/PlatformSerialPortLib.h  | 128 +++--
 .../Library/SerialPortLib/SerialPortLib.c  | 514 ++---
 Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h  | 146 +++---
 .../MonoStatusCode/PlatformStatusCode.h| 351 ++
 4 files changed, 523 insertions(+), 616 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h 
b/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
index e59ae9279..2cc7525b2 100644
--- a/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
+++ b/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
@@ -1,69 +1,59 @@
-/** @file
-  Header file of Serial port hardware definition.
-
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-   


-  This program and the accompanying materials are licensed and made available 
under

-  the terms and conditions of the BSD License that accompanies this 
distribution.  

-  The full text of the license may be found at 


-  http://opensource.org/licenses/bsd-license.php.  


-   


-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,


-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.

-   


-  This software and associated documentation
-  (if any) is furnished under a license and may only be used or
-  copied in accordance with the terms of the license.  Except as
-  permitted by such license, no part of this software or
-  documentation may be reproduced, stored in a retrieval system, or
-  transmitted in any form or by any means without the express written
-  consent of Intel Corporation.
-
-  Module Name:  PlatformSerialPortLib.h
-
-**/
-
-#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
-#define __PLATFORM_SERIAL_PORT_LIB_H_
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-//
-// UART Register Offsets
-//
-#define BAUD_LOW_OFFSET   0x00
-#define BAUD_HIGH_OFFSET  0x01
-#define IER_OFFSET0x01
-#define LCR_SHADOW_OFFSET 0x01
-#define FCR_SHADOW_OFFSET 0x02
-#define IR_CONTROL_OFFSET 0x02
-#define FCR_OFFSET0x02
-#define EIR_OFFSET0x02
-#define BSR_OFFSET0x03
-#define LCR_OFFSET0x03
-#define MCR_OFFSET0x04
-#define LSR_OFFSET0x05
-#define MSR_OFFSET0x06
-
-//
-// UART Register Bit Defines
-//
-#define LSR_TXRDY 0x20
-#define LSR_RXDA  0x01
-#define DLAB  0x01
-
-#define UART_DATA8
-#define UART_STOP1
-#define UART_PARITY  0
-#define UART_BREAK_SET  0
-
-VOID
-InitializeSio (
-  VOID
-  );
-
-#endif
+/** @file
+  Header file of Serial port hardware definition.
+
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+   

+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.  
+  The full text of the license may be found at 

+  http://opensource.org/licenses/bsd-license.php.  

+   

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+   

+**/
+
+#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
+#define __PLATFORM_SERIAL_PORT_LIB_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// UART Register Offsets
+//
+#define BAUD_LOW_OFFSET   0x00
+#define BAUD_HIGH_OFFSET  0x01
+#define IER_OFFSET0x01
+#define LCR_SHADOW_OFFSET 0x01
+#define FCR_SHADOW_OFFSET 0x02
+#define IR_CONTROL_OFFSET 0x02
+#define FCR_OFFSET0x02
+#define EIR_OFFSET0x02
+#define BSR_OFFSET0x03
+#define LCR_OFFSET0x03
+#define MCR_OFFSET0x04
+#define LSR_OFFSET0x05
+#define MSR_OFFSET0x06
+
+//
+// UART Register Bit Defines
+//
+#define LSR_TXRDY 0x20
+#define LSR_RXDA  0x01
+#define DLAB  0x01
+
+#define UART_DATA8
+#define UART_STOP1
+#define UART_PARITY  0
+#define UART_BREAK_SET  0
+
+VOID
+InitializeSio (
+  VOID
+  );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c 
b/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
index 2

[edk2] [Patch]Vlv2TbltDevicePkg:Fix License Header.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wei, David 
Cc: Kinney, Michael D 
Cc: Wu, Mike 
---
 .../Library/SerialPortLib/PlatformSerialPortLib.h  | 128 +++--
 .../Library/SerialPortLib/SerialPortLib.c  | 514 ++---
 Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h  | 146 +++---
 .../MonoStatusCode/PlatformStatusCode.h| 351 ++
 4 files changed, 523 insertions(+), 616 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h 
b/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
index e59ae9279f..8c9c9a810f 100644
--- a/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
+++ b/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
@@ -1,69 +1,59 @@
-/** @file
-  Header file of Serial port hardware definition.
-
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-   


-  This program and the accompanying materials are licensed and made available 
under

-  the terms and conditions of the BSD License that accompanies this 
distribution.  

-  The full text of the license may be found at 


-  http://opensource.org/licenses/bsd-license.php.  


-   


-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,


-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.

-   


-  This software and associated documentation
-  (if any) is furnished under a license and may only be used or
-  copied in accordance with the terms of the license.  Except as
-  permitted by such license, no part of this software or
-  documentation may be reproduced, stored in a retrieval system, or
-  transmitted in any form or by any means without the express written
-  consent of Intel Corporation.
-
-  Module Name:  PlatformSerialPortLib.h
-
-**/
-
-#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
-#define __PLATFORM_SERIAL_PORT_LIB_H_
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-//
-// UART Register Offsets
-//
-#define BAUD_LOW_OFFSET   0x00
-#define BAUD_HIGH_OFFSET  0x01
-#define IER_OFFSET0x01
-#define LCR_SHADOW_OFFSET 0x01
-#define FCR_SHADOW_OFFSET 0x02
-#define IR_CONTROL_OFFSET 0x02
-#define FCR_OFFSET0x02
-#define EIR_OFFSET0x02
-#define BSR_OFFSET0x03
-#define LCR_OFFSET0x03
-#define MCR_OFFSET0x04
-#define LSR_OFFSET0x05
-#define MSR_OFFSET0x06
-
-//
-// UART Register Bit Defines
-//
-#define LSR_TXRDY 0x20
-#define LSR_RXDA  0x01
-#define DLAB  0x01
-
-#define UART_DATA8
-#define UART_STOP1
-#define UART_PARITY  0
-#define UART_BREAK_SET  0
-
-VOID
-InitializeSio (
-  VOID
-  );
-
-#endif
+/** @file
+  Header file of Serial port hardware definition.
+
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+   

+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.  
+  The full text of the license may be found at 

+  http://opensource.org/licenses/bsd-license.php.  

+   

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
+#define __PLATFORM_SERIAL_PORT_LIB_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// UART Register Offsets
+//
+#define BAUD_LOW_OFFSET   0x00
+#define BAUD_HIGH_OFFSET  0x01
+#define IER_OFFSET0x01
+#define LCR_SHADOW_OFFSET 0x01
+#define FCR_SHADOW_OFFSET 0x02
+#define IR_CONTROL_OFFSET 0x02
+#define FCR_OFFSET0x02
+#define EIR_OFFSET0x02
+#define BSR_OFFSET0x03
+#define LCR_OFFSET0x03
+#define MCR_OFFSET0x04
+#define LSR_OFFSET0x05
+#define MSR_OFFSET0x06
+
+//
+// UART Register Bit Defines
+//
+#define LSR_TXRDY 0x20
+#define LSR_RXDA  0x01
+#define DLAB  0x01
+
+#define UART_DATA8
+#define UART_STOP1
+#define UART_PARITY  0
+#define UART_BREAK_SET  0
+
+VOID
+InitializeSio (
+  VOID
+  );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c 
b/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
index 21d5e8aec5..db27d4e027 100644
--- a/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
+++ 

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] I2S Audio Configure

[zwei4]

Customize I2S virtual bus ID for different boards.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../BensonGlacier/BoardInitPostMem/BoardGpios.c| 10 ---
 .../BensonGlacier/BoardInitPostMem/BoardGpios.h| 10 ---
 .../BensonGlacier/BoardInitPostMem/BoardInit.c |  9 ++
 .../BoardInitPostMem/BoardInitPostMem.inf  |  5 
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c|  9 ++
 .../LeafHill/BoardInitPostMem/BoardInitPostMem.inf |  5 
 .../MinnowBoard3/BoardInitPostMem/BoardGpios.c | 10 ---
 .../MinnowBoard3/BoardInitPostMem/BoardGpios.h | 10 ---
 .../MinnowBoard3/BoardInitPostMem/BoardInit.c  |  9 ++
 .../BoardInitPostMem/BoardInitPostMem.inf  |  5 
 .../PlatformSetupDxe/SouthClusterConfig.vfi|  4 +--
 Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec   | 12 
 .../Library/Private/DxeScHdaLib/DxeScHdaLib.inf|  5 
 .../Library/Private/DxeScHdaLib/ScHdaLib.c | 25 ++--
 .../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScHda.c   | 33 ++
 15 files changed, 102 insertions(+), 59 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c
index df11c8bbd..f7ae62114 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c
@@ -204,16 +204,6 @@ BensonMultiPlatformGpioProgram (
 GpioPadConfigTable (sizeof (mBenson_GpioInitData_W) / sizeof 
(mBenson_GpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
 GpioPadConfigTable (sizeof (mBenson_GpioInitData_SW) / sizeof 
(mBenson_GpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
 
-//
-// Note1: This BXT BIOS WA needs to be applied after PAD programming to 
overwrite the GPIO setting to take effect.
-// Note2: Enable TDO in BIOS SETUP as default for BXT Power-On only, need 
to set to AUTO prior to deliver to customer.
-// For BXT A0 Stepping only, to disable TDO GPIO to save power.
-//
-if (PlatformInfoHob->FABID == FAB2) {
-  DEBUG ((DEBUG_INFO, "FAB ID: FAB2\n"));
-  
GpioPadConfigTable(sizeof(mBenson_GpioInitData_FAB2)/sizeof(mBenson_GpioInitData_FAB2[0]),
 mBenson_GpioInitData_FAB2);
-}
-
 if (SystemConfiguration.TDO == 2) {  //Auto
   if (BxtA0 == BxtStepping()) {
 DEBUG ((DEBUG_INFO, " BxtA0 TDO disable\n" ));
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
index 5adc8e546..e4c1c2ee1 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
@@ -345,16 +345,6 @@ BXT_GPIO_PAD_INIT  mBenson_GpioInitData_Audio_SSP6 []=
   BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M0  , HI_Z  ,GPIO_D,   HI 
   ,   NA  ,  Wake_Disabled,  P_2K_H,   NA,NA,NA,  NA  ,  
GPIO_PADBAR+0x0028,  NORTHWEST),//Feature: Codec Power Down PD Net in Sch: 
SOC_CODEC_PD_N
 };
 
-BXT_GPIO_PAD_INIT  mBenson_GpioInitData_FAB2[] =
-{
-  //
-  //  Group Pin#:  pad_name,
PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,  Wake_Enabled 
,Term_H_L,Inverted, GPI_ROUT, IOSstae, IOSTerm, MMIO_Offset  ,Community
-  //
-  BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M0   ,GPI   ,GPIO_D,   NA 
   ,   Level   ,  Wake_Disabled, P_20K_L,   NA,IOAPIC,TxDRxE,NA,  
GPIO_PADBAR+0x0120,  NORTHWEST),//Feature:SSIC_WWAN_Wake
-  BXT_GPIO_PAD_CONF(L"GPIO_6",   M0   ,GPI   ,GPIO_D,   NA 
   ,   Level, Wake_Disabled, P_20K_L,   NA,IOAPIC,TxDRxE,NA,  
GPIO_PADBAR+0x0030,  NORTH),//Feature:DGPU Power OK
-  BXT_GPIO_PAD_CONF(L"GPIO_217 CNV_BRI_RSP", M0   ,GPO   ,GPIO_D,   LO 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,NA,NA,  
GPIO_PADBAR+0x0240,  NORTH),//Feature:DGPU_SEL
-};
-
 //
 // GPIO 191 is only used if EPI reworks are applied on the board. This GPIO 
switches between SD Card data (if set to 1) and EPI data (if set to 0).
 //
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index 74245de12..aabb350e8 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -135,6 +135,15 @@ BensonGlacierPostMemInitCallback (
   //
   PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) 
(SystemConfiguration.ScceMMCHostMaxSpeed));
 
+  //
+  // I2S NHLT Vi

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Enable HD audio.

[zwei4]

Enable HD audio on Intel reference board. 
(1) Enable HdAudioDspUaaCompliance.
(2) Move audio verb table to board specifc folder.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c|  7 
 .../LeafHill/BoardInitPostMem/BoardInitPostMem.inf |  5 ++-
 .../LeafHill/BoardInitPostMem}/HdaVerbTables.c | 38 ++---
 .../LeafHill/BoardInitPostMem/HdaVerbTables.h  | 38 +
 .../PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf|  2 +
 .../PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c| 11 ++---
 .../Library/PeiPolicyUpdateLib/HdaVerbTables.h | 30 --
 .../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf  |  1 -
 .../Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c | 48 --
 Platform/BroxtonPlatformPkg/PlatformPkg.dec|  5 +++
 10 files changed, 64 insertions(+), 121 deletions(-)
 rename Platform/BroxtonPlatformPkg/{Common/Library/PeiPolicyUpdateLib => 
Board/LeafHill/BoardInitPostMem}/HdaVerbTables.c (66%)
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/HdaVerbTables.h
 delete mode 100644 
Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/HdaVerbTables.h

diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
index 4bd93d167..ca49dfe0f 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
@@ -22,6 +22,7 @@
 #include 
 #include "BoardInit.h"
 #include "BoardInitMiscs.h"
+#include "HdaVerbTables.h"
 
 EFI_STATUS
 EFIAPI
@@ -135,6 +136,12 @@ LeafHillPostMemInitCallback (
   //
   PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) 
(SystemConfiguration.ScceMMCHostMaxSpeed));
 
+  //
+  // HDA audio verb table
+  //
+  PcdSet64 (PcdHdaVerbTablePtr, (UINT64) (UINTN) );
+  PcdSet8(HdaVerbTableEntryNum, 1);
+  
   //
   // Add init steps here
   //
diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
index 0f11b1c11..5154235f8 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
@@ -31,6 +31,7 @@
   PlatformInfoHob.c
   BoardGpios.c
   BoardGpios.h
+  HdaVerbTables.c
 
 [LibraryClasses]
   PeiServicesLib
@@ -64,7 +65,9 @@
   gPlatformModuleTokenSpaceGuid.PcdSueCreek
   gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState
   gPlatformModuleTokenSpaceGuid.PcdeMMCHostMaxSpeed
-
+  gPlatformModuleTokenSpaceGuid.PcdHdaVerbTablePtr
+  gPlatformModuleTokenSpaceGuid.HdaVerbTableEntryNum
+  
 [Guids]
   gEfiPlatformInfoGuid
   gEfiAuthenticatedVariableGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/HdaVerbTables.c 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/HdaVerbTables.c
similarity index 66%
rename from 
Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/HdaVerbTables.c
rename to 
Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/HdaVerbTables.c
index 6cd068e41..9a911fe2c 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/HdaVerbTables.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/HdaVerbTables.c
@@ -1,5 +1,7 @@
 /** @file
-  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+  HD Audio Verb Table.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -14,13 +16,6 @@
 #include "HdaVerbTables.h"
 
 HDAUDIO_VERB_TABLE HdaVerbTableAlc662 = {
-  //
-  // VerbTable: (Realtek ALC662)
-  // Revision ID = 0xff
-  // Codec Verb Table for IOTG CRB boards
-  // Codec Address: CAd value (0/1/2)
-  // Codec Vendor: 0x10EC0662
-  //
   {
 0x10EC0662, // Vendor ID / Device ID
 0xFF,   // Revision ID
@@ -28,31 +23,7 @@ HDAUDIO_VERB_TABLE HdaVerbTableAlc662 = {
 15 * 4  // Number of data DWORDs following the header.
   },
   {
-//
-// Realtek Semiconductor Corp.
-//
-// Realtek High Definition Audio Configuration - Version : 5.0.2.6
-// Realtek HD Audio Codec : ALC662-VD
-// PCI PnP ID : PCI\VEN_8086_2668_72708086
-// HDA Codec PnP ID : HDAUDIO\FUNC_01_10EC_0662_8086
-// The number of verb command block : 15
-//
-// NID 0x12 : 0x4013
-// NID 0x14 : 0x01014010
-// NID 0x15 : 0x01011012
-// NID 0x16 : 0x01016011
-// NID 0x18 : 0x01A19030
-// NID 0x19 : 0x02A19040
-// NID 0x1A : 0x0181303F
-// NID 0x1B : 0x0221401F
-

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] SATA LED.

[zwei4]

Enable SATA LED function on MinnowBoard3 Next pre-production board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.h| 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.h
 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.h
index 49340b10f..f51274f19 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.h
@@ -89,7 +89,7 @@ BXT_GPIO_PAD_INIT  mMinnow3Next_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_23",  M0   ,GPI   ,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_NONE ,NA   ,NA, NA   ,DisPuPd, 
GPIO_PADBAR+0x00B8, NORTH), // BOOT_SEL1#
   BXT_GPIO_PAD_CONF(L"GPIO_24",  M0   ,GPI   ,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_NONE ,NA   ,NA, NA   ,DisPuPd, 
GPIO_PADBAR+0x00C0, NORTH), // BOOT_SEL0#
   BXT_GPIO_PAD_CONF(L"GPIO_25",  M0   ,GPI   ,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_NONE ,NA   ,NA, NA   ,DisPuPd, 
GPIO_PADBAR+0x00C8, NORTH), // TEST#
-  BXT_GPIO_PAD_CONF(L"GPIO_26",  M0   ,GPO   ,  NA   ,  HI 
   ,   NA   , Wake_Disabled, P_NONE ,NA   ,NA, NA   ,DisPuPd, 
GPIO_PADBAR+0x00D0, NORTH), // SATA_LED#
+  BXT_GPIO_PAD_CONF(L"GPIO_26",  M5   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D0, NORTH), // SATA_LEDN
   BXT_GPIO_PAD_CONF(L"GPIO_27",  M0   ,GPI   ,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_NONE ,NA   ,NA, NA   ,DisPuPd, 
GPIO_PADBAR+0x00D8, NORTH), // NC
   BXT_GPIO_PAD_CONF(L"GPIO_28",  M0   ,GPO   ,  NA   ,  HI 
   ,   NA   , Wake_Disabled, P_NONE ,NA   ,NA, NA   ,DisPuPd, 
GPIO_PADBAR+0x00E0, NORTH), // USB2_EN
   BXT_GPIO_PAD_CONF(L"GPIO_29",  M0   ,GPO   ,  NA   ,  HI 
   ,   NA   , Wake_Disabled, P_NONE ,NA   ,NA, NA   ,DisPuPd, 
GPIO_PADBAR+0x00E8, NORTH), // USB_DRIVE_BUS_1V8
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Change Build Script

[zwei4]

Change GCC build script for Benson Glacier FAB B and
Minnowboard 3 Next pre-production board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>

---
 BuildBIOS.sh|  7 +++-
 Platform/BroxtonPlatformPkg/BuildBxtBios.sh | 54 +
 Platform/BroxtonPlatformPkg/BuildIFWI.sh| 11 --
 3 files changed, 62 insertions(+), 10 deletions(-)
 mode change 100644 => 100755 Platform/BroxtonPlatformPkg/BuildBxtBios.sh

diff --git a/BuildBIOS.sh b/BuildBIOS.sh
index 5ea0dd8..d679d2e 100755
--- a/BuildBIOS.sh
+++ b/BuildBIOS.sh
@@ -18,8 +18,9 @@ function Usage () {
   echo
   echo "Usage: BuildBios.sh Build_Flags [PlatformName]  Target_Flag"
   echo
-  echo "   Build_Flags: /MNMinnow3 Board (default: MN)"
+  echo "   Build_Flags: /MNMinnowBoard3 (default: MN)"
   echo "   Build_Flags: /BGBenson Glacier Board"
+  echo "   Build_Flags: /MXMinnowBoard3 Next"
   echo "   Build_Flags: /A Set FabId to A (default:  
FAB_B)"
   echo "   Build_Flags: /B Set FabId to B (default:  
FAB_B)"
   echo "   PlatformName [optional]: Broxton  "   
@@ -59,6 +60,10 @@ for (( i=1; i<=$#; ))
   BoardId=BG
   Build_Flags="$Build_Flags /BG"
   shift
+elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/MX" ]; then
+  BoardId=MX
+  Build_Flags="$Build_Flags /MX"
+  shift
 elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/B" ]; then
   FabId=B
   Build_Flags="$Build_Flags /B"
diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.sh 
b/Platform/BroxtonPlatformPkg/BuildBxtBios.sh
old mode 100644
new mode 100755
index d0b677f..cf02ceb
--- a/Platform/BroxtonPlatformPkg/BuildBxtBios.sh
+++ b/Platform/BroxtonPlatformPkg/BuildBxtBios.sh
@@ -104,6 +104,9 @@ for (( i=1; i<=$#; ))
 elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/BG" ]; then
   BoardId=BG
   shift
+elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/MX" ]; then
+  BoardId=MX
+  shift
 elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/B" ]; then
   FabId=B
   shift
@@ -132,10 +135,14 @@ sed -i '/^BUILD_TYPE/d' $WORKSPACE/Conf/BiosId.env
 if [ $BoardId == "MN" ]; then
   BOARD_ID=MNW3
   echo BOARD_ID = MINNOW3 >> $WORKSPACE/Conf/BiosId.env
+elif [ $BoardId == "MX" ]; then
+  BOARD_ID=MNXT
+  echo BOARD_ID = MINNEXT >> $WORKSPACE/Conf/BiosId.env
 else
   BOARD_ID=BEN1
   echo BOARD_ID = BENSONV >> $WORKSPACE/Conf/BiosId.env
 fi
+
 ENBDT_PF_BUILD=TRUE
 PLATFORM_NAME=BroxtonPlatformPkg
 PLATFORM_PACKAGE=Platform/BroxtonPlatformPkg  
@@ -176,8 +183,13 @@ else
 fi
 
 if [ $BoardId == "BG" ]; then
-  BOARD_REV=A
-  echo BOARD_REV = A >> $WORKSPACE/Conf/BiosId.env
+  if [ $FabId == "B" ]; then
+BOARD_REV=B
+echo BOARD_REV = B >> $WORKSPACE/Conf/BiosId.env
+  else
+BOARD_REV=A
+echo BOARD_REV = A >> $WORKSPACE/Conf/BiosId.env
+  fi
 fi
 
 if [ $BoardId == "MN" ]; then
@@ -190,6 +202,15 @@ if [ $BoardId == "MN" ]; then
   fi
 fi
 
+if [ $BoardId == "MX" ]; then
+  if [ $FabId == "B" ]; then
+BOARD_REV=B
+echo BOARD_REV = B >> $WORKSPACE/Conf/BiosId.env
+  else
+BOARD_REV=A
+echo BOARD_REV = A >> $WORKSPACE/Conf/BiosId.env
+  fi
+fi
 
 ##**
 ## Additional EDK Build Setup/Configuration
@@ -291,10 +312,17 @@ cp -f $BUILD_PATH/FV/FVIBBM.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Too
 cp -f $BUILD_PATH/FV/FVIBBL.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 
 if [ $BoardId == "BG" ]; then
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk1.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk2.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk3.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/GCC/NvStorage.Fv
 $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+  if [ $FabId == "B" ]; then
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_B/SpiChunk1.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGla

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Minnowboard3 Next Pre-production.

[zwei4]

Add code for Minnowboard3 Next pre-production board.
Build Command: BuildBios /vs13 /MX /A Broxton Release.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
CC: mike...@intel.com
CC: mang@intel.com
---
 BuildBIOS.bat  |  3 +-
 .../MinnowBoard3Next/BoardInitPreMem/BoardInit.c   |  1 -
 Platform/BroxtonPlatformPkg/BuildBxtBios.bat   | 17 ++-
 Platform/BroxtonPlatformPkg/BuildIFWI.bat  | 59 --
 .../LpssUartSerialDxe/LpssUartSerialDxe.inf|  2 +
 .../Common/Console/LpssUartSerialDxe/Serial.c  |  4 +-
 .../BaseFspWrapperPlatformLibSample.inf|  1 +
 .../FspPlatformInfoLibSample.c |  2 +-
 .../Common/Include/BoardFunctionsPei.h |  7 +++
 .../Common/Include/Guid/PlatformInfo.h |  1 +
 .../Common/Include/Guid/PlatformInfo_Aplk.h|  1 +
 .../Library/BaseSerialPortLib/BaseSerialPortLib.c  |  7 ++-
 .../BaseSerialPortLib/BaseSerialPortLib.inf|  2 +-
 .../BaseSerialPortLib/BaseSerialPortLibNoInit.inf  |  2 +-
 .../PlatformPreMemPei/BoardGpiosPreMem.c   | 25 +++--
 .../Common/Tools/Stitch/IFWIStitch_Simple.bat  |  9 
 .../PlatformDsc/Components.IA32.dsc|  2 +
 .../BroxtonPlatformPkg/PlatformDsc/Components.dsc  |  3 ++
 Platform/BroxtonPlatformPkg/PlatformPkg.dec|  7 +++
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf|  6 +++
 Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec   |  3 --
 .../PeiDxeSmmPchSerialIoUartLib.inf|  3 --
 22 files changed, 121 insertions(+), 46 deletions(-)

diff --git a/BuildBIOS.bat b/BuildBIOS.bat
index 7b2394f3b..2cec70f7c 100644
--- a/BuildBIOS.bat
+++ b/BuildBIOS.bat
@@ -56,7 +56,8 @@ echo/x64   Set Arch to X64  (default: X64)
 echo/IA32  Set Arch to IA32 (default: X64)
 echo/A Set FabId to A (default:  FAB_B)
 echo/B Set FabId to B (default:  FAB_B)
-echo/MNMinnow3 Board (default: MN)
+echo/MNMinnowBoard 3(default: MN)
+echo/MXMinnowBoard 3 Next
 echo/BGBenson Glacier Board
 echoPlatformName:  Broxton
 echoBuildTargets:  Release, Debug
diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
index 7df8fd1c0..a3a0cd857 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
@@ -68,7 +68,6 @@ MinnowBoard3NextPreMemInit (
  
  );
   if (!EFI_ERROR (Status)) {
- DEBUG ((EFI_D_INFO,  "Minnow Board 3 Next Pre Mem Init: Skip\n"));
 return EFI_SUCCESS;
   }
 
diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat 
b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
index e08f5d10b..ede285e38 100644
--- a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
+++ b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
@@ -177,7 +177,12 @@ if /i "%~1"=="/BG" (
 shift
 goto OptLoop
 )
-
+if /i "%~1"=="/MX" (
+set BoardId=MX
+echo.
+shift
+goto OptLoop
+)
 if /i "%~1"=="/m" (
 if defined NUMBER_OF_PROCESSORS (
 set /a build_threads=%NUMBER_OF_PROCESSORS%
@@ -202,6 +207,8 @@ if /i "%~1" == "%Minnow_RVP%" (
 set BOARD_ID=MINNOW3
   ) else if %BoardId%==BG (
 set BOARD_ID=BENSONV
+  ) else if %BoardId%==MX (
+set BOARD_ID=MINNEXT
   )
 set ENBDT_PF_BUILD=TRUE
 set PLATFORM_NAME=BroxtonPlatformPkg
@@ -270,6 +277,14 @@ if %BoardId%==MN (
   )
 )
 
+if %BoardId%==MX (
+  if %FabId%==B (
+echo BOARD_REV = B >> Conf\BiosId.env
+  ) else (
+echo BOARD_REV = A >> Conf\BiosId.env
+  )
+)
+
 :: Set the Build_Type, Version_Major, and Version_Minor environment variables
 find /v "#" Conf\BiosId.env > ver_strings
 for /f "tokens=1,3" %%i in (ver_strings) do set %%i=%%j
diff --git a/Platform/BroxtonPlatformPkg/BuildIFWI.bat 
b/Platform/BroxtonPlatformPkg/BuildIFWI.bat
index a27362ae0..556bd4abb 100644
--- a/Platform/BroxtonPlatformPkg/BuildIFWI.bat
+++ b/Platform/BroxtonPlatformPkg/BuildIFWI.bat
@@ -2,13 +2,13 @@
 SetLocal EnableDelayedExpansion EnableExtensions
 
 :: Assign initial values
-set thisscript=%0
+set thisscript=%0
 set exitCode=0
 set "Build_Flags= "
 set Arch=X64
 set SkipUsageFlag=FALSE
-set FabId=B
-set BoardId=MN
+set FabId=B
+set BoardId=MN
 set buildthread=
 set WORKSPACE=%CD%
 if %WORKSPACE:~-1%==\ (
@@ -82,29 +82,36 @@ if /i "%~1"=="/FspW" (
 goto OptLoop
 )
 if /i "%~1"=="/A" (
-set FabId=A
+set FabId=A
 set Build_Flags=%Build_Flags% /A
 shift
 goto OptLoop
 )
 if /i "%~1"=="/B" (
-set Fab

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 4/4] Board Specific Code.

[zwei4]

Add VBT for Minnowboard3 Next pre-production board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/MinnowBoard3Next/Vbt/VbtBxtMipi.bin| Bin 0 -> 5632 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/Vbt/VbtBxtMipi.bin

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/Vbt/VbtBxtMipi.bin 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/Vbt/VbtBxtMipi.bin
new file mode 100644
index 
..5907374b5ebdc09b27125d28a2f15036252d0ad8
GIT binary patch
literal 5632
zcmeHKU2GIp6h1T4{kt=>JDnCOOD%eFu}El^6WcD7qe7h1a8mRh4pw`CV?EVQ
ziwGTKNtzJMKA=HEw8j_>zBEyvj1eD<Btd+vAdJ?Gq?S<znGMr|JKCDJQH!FWfPKMH{J))QgUzj-b^bPgXKiD1U@JWX
zkHOj8o0kEi46{fmQ<Spc?x9$(uce4K^>z33#!BmAgD(yB_0v!wNc}r@#Cl@`T|==b
zZEfG|r#hZUYWMc^M(MV_ySifoRTM!Kw5Db2O4hEUw0uLUvbMBbDO-;%Rb>@b>o<y|
zZd0JSDHLq<w*_(H%`LPp*y?X>-PBau_$&>zG^5j$fxiBI13fRiI7EGc
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ztSkdAyz^PG;Q=AwrCkRN;7{=|wlT02s~XVEG%>0g&@uumzy}n28C6**R4lr%(gu`*
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zfx~3d5$-Z44Fu6du+a=waoG#wA-Yfzlz`sL@B<ge{b+cy(#Qur$wTczdgsa
ztVza#1CN1#hnRi-eNm)BM1!1%sJqBiX=4FhdM)DyJNlEx^~6>2L*jmvuV}q
zVBc~I-{dFm-~Z=xh@C^L7r>EvoK_HD>f0d%QCQ8q4VSo*34pN~dLY!b#wlRBcwGf%
zZX6TI*i*CJj<-q;GJt*t>0c$2)<>JZ7d<0OYI4yRx=+$kbu~E4dkX6-7+Bu3yBs6f
z>8l3({MSE1jZTk7PWtYVx9@$1U1QAOSk9em$;iys>;`RM84d6-*6;M*()Bno8{Ra+eP7OYQZ~nY^_2Q+A)7*vS7Xs=MPPNH1+Y+m8lt&
fc@$%OC27Rqm$pU5?Shv}n(@_pGXAZ>9zOXOhl)}z

literal 0
HcmV?d1

-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 2/4] Board Specific Code.

[zwei4]

Add BoardInitPostMem lib for Minnowboard3 Next pre-product board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../MinnowBoard3Next/BoardInitPostMem/BoardGpios.c | 251 +++
 .../MinnowBoard3Next/BoardInitPostMem/BoardGpios.h | 350 +
 .../MinnowBoard3Next/BoardInitPostMem/BoardInit.c  | 136 
 .../MinnowBoard3Next/BoardInitPostMem/BoardInit.h  |  30 ++
 .../BoardInitPostMem/BoardInitMiscs.c  | 180 +++
 .../BoardInitPostMem/BoardInitMiscs.h  | 127 
 .../BoardInitPostMem/BoardInitPostMem.inf  |  81 +
 .../BoardInitPostMem/PlatformInfoHob.c |  58 
 8 files changed, 1213 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardInit.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardInit.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardInitMiscs.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardInitMiscs.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardInitPostMem.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/PlatformInfoHob.c

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.c
 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.c
new file mode 100644
index 0..d89ee67ac
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPostMem/BoardGpios.c
@@ -0,0 +1,251 @@
+/** @file
+  Gpio setting for multiplatform.
+
+  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardGpios.h"
+#include 
+#include 
+#include 
+
+
+/**
+  Returns the Correct GPIO table for Mobile/Desktop respectively.
+  Before call it, make sure PlatformInfoHob->BoardId is get 
correctly.
+
+  @param[in] PeiServices General purpose services available to every 
PEIM.
+  @param[in] PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor 
specified.
+
+  @retvalEFI_SUCCESS The function completed successfully.
+  @retvalEFI_DEVICE_ERRORKSC fails to respond.
+
+**/
+EFI_STATUS
+Minnow3NextMultiPlatformGpioTableInit (
+  IN CONST EFI_PEI_SERVICES **PeiServices,
+  IN EFI_PLATFORM_INFO_HOB  *PlatformInfoHob
+  )
+{
+  DEBUG ((DEBUG_INFO, "Minnow3NextMultiPlatformGpioTableInit()...\n"));
+  DEBUG ((DEBUG_INFO, "PlatformInfoHob->BoardId: 0x%02X\n", 
PlatformInfoHob->BoardId));
+
+  //
+  // Select/modify the GPIO initialization data based on the Board ID.
+  //
+  switch (PlatformInfoHob->BoardId) {
+case BOARD_ID_LFH_CRB:
+case BOARD_ID_MINNOW:
+case BOARD_ID_MINNOW_NEXT:
+case BOARD_ID_BENSON:
+  PlatformInfoHob->PlatformGpioSetting_SW = 
_GpioInitData_SW[0];
+  PlatformInfoHob->PlatformGpioSetting_W  = 
_GpioInitData_W[0];
+  PlatformInfoHob->PlatformGpioSetting_NW = 
_GpioInitData_NW[0];
+  PlatformInfoHob->PlatformGpioSetting_N  = 
_GpioInitData_N[0];
+  break;
+default:
+  PlatformInfoHob->PlatformGpioSetting_SW = 
_GpioInitData_SW[0];
+  PlatformInfoHob->PlatformGpioSetting_W  = 
_GpioInitData_W[0];
+  PlatformInfoHob->PlatformGpioSetting_NW = 
_GpioInitData_NW[0];
+  PlatformInfoHob->PlatformGpioSetting_N  = 
_GpioInitData_N[0];
+  break;
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Set GPIO Lock for security.
+
+**/
+VOID
+Minnow3NextSetGpioPadCfgLock (
+  VOID
+  )
+{
+  UINT32 Data32;
+
+  Data32 = 0;
+
+  //
+  // JTAG
+  //
+  GpioLockPadCfg (N_TCK);
+  GpioLockPadCfg (N_TRST_B);
+  GpioLockPadCfg (N_TMS);
+  GpioLockPadCfg (N_TDI);
+  GpioLockPadCfg (N_TDO);
+
+  //
+  // Power
+  //
+  GpioLockPadCfg (NW_PMIC_THERMTRIP_B);
+  GpioLockPadCfg (NW_PROCHOT_B);
+
+  //
+  // Touch
+  //
+  GpioLockPadCfg (NW_GPIO_118);
+  GpioLockPadCfg (NW_GPIO_119);
+  GpioLockPadCfg (NW_GPIO_120);
+  GpioLockPadCfg (NW_GPIO_121);
+  GpioLockPadCfg (NW_GPIO_122);
+  GpioLockPadCfg (NW_GPIO_123);
+
+  //
+  // SPI
+  //
+  GpioLockPadCfg (NW_GPIO_97);
+  GpioLockP

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 3/4] Board Specific Code.

[zwei4]

Add BoardInitPreMem lib for Minnowboard3 Next pre-production board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../MinnowBoard3Next/BoardInitPreMem/BoardInit.c   | 190 +
 .../MinnowBoard3Next/BoardInitPreMem/BoardInit.h   |  29 ++
 .../BoardInitPreMem/BoardInitMiscs.c   | 433 +
 .../BoardInitPreMem/BoardInitMiscs.h   |  67 
 .../BoardInitPreMem/BoardInitPreMem.inf|  62 +++
 .../MinnowBoard3Next/BoardInitPreMem/PlatformId.c  | 231 +++
 .../MinnowBoard3Next/BoardInitPreMem/PlatformId.h  |  45 +++
 7 files changed, 1057 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitPreMem.inf
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.h

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
new file mode 100644
index 0..7df8fd1c0
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c
@@ -0,0 +1,190 @@
+/** @file
+  Board Init driver.
+
+  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "BoardInit.h"
+#include "PlatformId.h"
+#include "BoardInitMiscs.h"
+
+EFI_STATUS
+EFIAPI
+MinnowBoard3NextPreMemInit (
+  IN CONST EFI_PEI_SERVICES **PeiServices,
+  IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+  );
+
+static PEI_BOARD_PRE_MEM_INIT_PPI mMinnow3NextPreMemInitPpiInstance = {
+  MinnowBoard3NextPreMemInit
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPreMemInitPpi = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPreMemInitDonePpi = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  NULL
+};
+
+EFI_STATUS
+EFIAPI
+MinnowBoard3NextPreMemInit (
+  IN CONST EFI_PEI_SERVICES **PeiServices,
+  IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+  )
+{
+  EFI_STATUS   Status;
+  VOID *Instance;
+  UINT8BoardId;
+  UINT8FabId;
+
+  BoardId = 0;
+  FabId = 0;
+  Status = PeiServicesLocatePpi (
+ ,
+ 0,
+ NULL,
+ 
+ );
+  if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO,  "Minnow Board 3 Next Pre Mem Init: Skip\n"));
+return EFI_SUCCESS;
+  }
+
+  DEBUG ((EFI_D_INFO,  "Minnow Board 3 Next Pre Mem Init\n"));
+
+  //
+  // Pre Mem Board Init
+  //
+  Status = Minnow3NextGetEmbeddedBoardIdFabId (PeiServices, , );
+
+  if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) {
+
+return EFI_SUCCESS;
+  }
+  DEBUG ((EFI_D_INFO,  "This is MinnowBoard3 Next\n"));
+
+  PcdSet8 (PcdBoardId, BoardId);
+  PcdSet8 (PcdFabId,   FabId);
+  
+  //
+  //PcdSet8 (PcdSerialIoUartNumber, 0);
+  //
+  
+  //
+  // Set board specific function as dynamic PCD to be called by common 
platform code
+  //
+  PcdSet64 (PcdUpdateFspmUpdFunc,(UINT64) (UINTN) 
mMb3NUpdateFspmUpdPtr);
+  PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) 
mMb3NDramCreatePolicyDefaultsPtr);
+  PcdSet64 (PcdUpdatePcieConfigFunc, (UINT64) (UINTN) 
mMb3NUpdatePcieConfigPtr);
+
+  //
+  // Install a flag signalling a board is detected and pre-mem init is done
+  //
+  Status = PeiServicesInstallPpi ();
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function performs Board initialization in Pre-Memory.
+
+  @retval EFI_SUCCESS   The PPI is installed and initialized.
+  @retval EFI ERRORSThe PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES  No enough resoruces (such as out of 
memory).
+
+**/
+EFI_STATU

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 1/4] Board Specific Code.

[zwei4]

Add BoardInitDxe lib for Minnowboard3 Next pre-product board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../MinnowBoard3Next/BoardInitDxe/BoardInitDxe.c   | 68 ++
 .../MinnowBoard3Next/BoardInitDxe/BoardInitDxe.h   | 37 
 .../MinnowBoard3Next/BoardInitDxe/BoardInitDxe.inf | 52 +
 3 files changed, 157 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.c
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.h
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.inf

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.c
 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.c
new file mode 100644
index 0..a1c2c3952
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.c
@@ -0,0 +1,68 @@
+/** @file
+  Board specific functions in DXE phase to be set as dynamic PCD and consumed 
by
+  commmon platform code.
+
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitDxe.h"
+
+GET_BOARD_NAME mMb3NGetBoardNamePtr = Mb3NGetBoardName;
+
+CHAR16*
+EFIAPI
+Mb3NGetBoardName (
+  IN  UINT8   BoardId
+  )
+{
+  STATIC CHAR16  BoardName[40];
+
+  DEBUG ((EFI_D_INFO,  "BoardInitDxe: GetBoardName - Minnow Board v3 Next\n"));
+
+  UnicodeSPrint (BoardName, sizeof (BoardName), L"Minnow Board v3 Next 
(0x%02X)", BoardId);
+
+  if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) {
+return NULL;
+  } else {
+return BoardName;
+  }
+}
+
+
+/**
+  Set PCDs for board specific functions.
+
+  @param[in]  ImageHandle   ImageHandle of the loaded driver.
+  @param[in]  SystemTable   Pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS   The handlers were registered successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+Mb3NBoardInitDxeConstructor (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  UINT8   BoardId;
+
+  BoardId = PcdGet8 (PcdBoardId);
+  if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) {
+return EFI_SUCCESS;
+  }
+
+  PcdSet64 (PcdGetBoardNameFunc, (UINT64) mMb3NGetBoardNamePtr);
+
+  return EFI_SUCCESS;
+}
+
diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.h
 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.h
new file mode 100644
index 0..74407aca8
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.h
@@ -0,0 +1,37 @@
+/** @file
+  The internal header file includes the common header files, defines
+  internal structure and functions used by ImageVerificationLib.
+
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __MINNOW3_NEXT_BOARD_INIT_DXE_H__
+#define __MINNOW3_NEXT_BOARD_INIT_DXE_H__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+CHAR16*
+EFIAPI
+Mb3NGetBoardName (
+  IN  UINT8   BoardId
+  );
+
+#endif
diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.inf
 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.inf
new file mode 100644
index 0..0b385e9e7
--- /dev/null
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitDxe/BoardInitDxe.inf
@@ -0,0 +1,52 @@
+## @file
+#  Board specific functions in DXE phase to be set as dynamic PCD and consumed 
by
+#  commmon platform code.
+#
+#  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php.

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Linux Build Script Change.

[zwei4]

Add /B build option for Benson FAB B.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>

---
 Platform/BroxtonPlatformPkg/BuildBxtBios.sh | 24 ++--
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.sh 
b/Platform/BroxtonPlatformPkg/BuildBxtBios.sh
index d0b677f..d1a16e6 100644
--- a/Platform/BroxtonPlatformPkg/BuildBxtBios.sh
+++ b/Platform/BroxtonPlatformPkg/BuildBxtBios.sh
@@ -176,8 +176,13 @@ else
 fi
 
 if [ $BoardId == "BG" ]; then
-  BOARD_REV=A
-  echo BOARD_REV = A >> $WORKSPACE/Conf/BiosId.env
+  if [ $FabId == "B" ]; then
+BOARD_REV=B
+echo BOARD_REV = B >> $WORKSPACE/Conf/BiosId.env
+  else 
+BOARD_REV=A
+echo BOARD_REV = A >> $WORKSPACE/Conf/BiosId.env
+  fi
 fi
 
 if [ $BoardId == "MN" ]; then
@@ -291,10 +296,17 @@ cp -f $BUILD_PATH/FV/FVIBBM.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Too
 cp -f $BUILD_PATH/FV/FVIBBL.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 
 if [ $BoardId == "BG" ]; then
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk1.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk2.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk3.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
-  cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/GCC/NvStorage.Fv
 $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+  if [ $FabId == "B" ]; then
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_B/SpiChunk1.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_B/SpiChunk2.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_B/SpiChunk3.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_B/GCC/NvStorage.Fv
 $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+  else 
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk1.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk2.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/SpiChunk3.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/BensonGlacier/FAB_A/GCC/NvStorage.Fv
 $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+  fi
 fi
 
 if [ $BoardId == "MN" ]; then
-- 
2.7.4

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[edk2] [PATCH][edk2-platforms/devel-MinnowBoard3-UDK2017 1/2] Modify FCE tool to be Linux executable file.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/Common/Tools/FCE/BfmLib | Bin
 Platform/BroxtonPlatformPkg/Common/Tools/FCE/FCE| Bin
 2 files changed, 0 insertions(+), 0 deletions(-)
 mode change 100644 => 100755 
Platform/BroxtonPlatformPkg/Common/Tools/FCE/BfmLib
 mode change 100644 => 100755 Platform/BroxtonPlatformPkg/Common/Tools/FCE/FCE

diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/FCE/BfmLib 
b/Platform/BroxtonPlatformPkg/Common/Tools/FCE/BfmLib
old mode 100644
new mode 100755
diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/FCE/FCE 
b/Platform/BroxtonPlatformPkg/Common/Tools/FCE/FCE
old mode 100644
new mode 100755
-- 
2.7.4

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 2/2] GPIOs Change.

[zwei4]

GPIOs Change for FAB B. (FAB A does not use these GPIOs)

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/BensonGlacier/BoardInitPostMem/BoardGpios.h| 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
index 0278ea388..5adc8e546 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
@@ -92,8 +92,8 @@ BXT_GPIO_PAD_INIT  mBenson_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_26",  M0   ,GPIO  ,GPIO_D ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D0,  NORTH),//SATA_LEDN
   BXT_GPIO_PAD_CONF(L"GPIO_27",  M0   ,GPO   ,GPIO_D ,  HI 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D8,  NORTH),//Feature:DFUNet in Sch: NFC_DFU
   BXT_GPIO_PAD_CONF(L"GPIO_28",  M2   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00E0,  NORTH),//   Net in Sch: 
ISH_GPIO10
-  BXT_GPIO_PAD_CONF(L"GPIO_29",  M0   ,GPO   ,GPIO_D ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00E8,  NORTH),// SOC_M2_RST   Net in 
Sch: ISH_GPIO11
-  //BXT_GPIO_PAD_CONF(L"GPIO_30",  M1   ,NA,  NA   ,  
NA,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   
SAME, GPIO_PADBAR+0x00F0,  NORTH),// FAB ID  Net in 
Sch: ISH_GPIO12
+  BXT_GPIO_PAD_CONF(L"GPIO_29",  M0   ,GPO   ,GPIO_D ,  HI 
   ,   NA   , Wake_Disabled, P_NONE,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00E8,  NORTH),// SOC_M2_RST
+  //BXT_GPIO_PAD_CONF(L"GPIO_30",  M0   ,NA,  NA   ,  
NA,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   
SAME, GPIO_PADBAR+0x00F0,  NORTH),// FAB ID, Programmed by earlier FAB ID 
detection code.
   BXT_GPIO_PAD_CONF(L"GPIO_31",  M5   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00F8,  NORTH),//Feature: SUSCLK1
   BXT_GPIO_PAD_CONF(L"GPIO_32",  M5   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x0100,  NORTH),//   Net in Sch: SUSCLK2
   BXT_GPIO_PAD_CONF(L"GPIO_33",  M5   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x0108,  NORTH),//Feature: SUSCLK3
@@ -162,7 +162,7 @@ BXT_GPIO_PAD_INIT  mBenson_GpioInitData_NW [] =
   BXT_GPIO_PAD_CONF(L"GPIO_196 PANEL1_VDDEN",M0  , GPO   ,GPIO_D,  LO  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,NA, NA,  
GPIO_PADBAR+0x0048,  NORTHWEST),//DISP1_VDDEN
   BXT_GPIO_PAD_CONF(L"GPIO_197 PANEL1_BKLTEN",   M0  , GPO   ,GPIO_D,  LO  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,NA, NA,  
GPIO_PADBAR+0x0050,  NORTHWEST),//DISP1_BKLTEN
   BXT_GPIO_PAD_CONF(L"GPIO_198 PANEL1_BKLTCTL",  M1  , NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,Last_Value,   SAME,  
GPIO_PADBAR+0x0058,  NORTHWEST),//DISP1_BLTCTL
-  BXT_GPIO_PAD_CONF(L"GPIO_199 DBI_CSX", M2  , NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_20K_H,NA   ,NA  ,NA, NA,  
GPIO_PADBAR+0x0060,  NORTHWEST),//HDMI_HPD
+  BXT_GPIO_PAD_CONF(L"GPIO_199 DBI_CSX", M2  , NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled,  P_NONE,NA   ,NA  ,NA, NA,  
GPIO_PADBAR+0x0060,  NORTHWEST),//HDMI_HPD
   BXT_GPIO_PAD_CONF(L"GPIO_200 DBI_RESX",M2  , NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_20K_H,NA   ,NA  ,NA, NA,  
GPIO_PADBAR+0x0068,  NORTHWEST),//EDP_HPD
   BXT_GPIO_PAD_CONF(L"GPIO_201 GP_INTD_DSI_TE1", M1  , NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,D0RxDRx0I ,   SAME,  
GPIO_PADBAR+0x0070,  NORTHWEST),//DISP_INTD_TE1
   BXT_GPIO_PAD_CONF(L"GPIO_202 GP_INTD_DSI_TE2", M1  , NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,D0RxDRx0I ,   SAME,  
GPIO_PADBAR+0x0078,  NORTHWEST),//DISP_INTD_TE2
@@ -189,12 +189,12 @@ BXT_GPIO_PAD_INIT  mBenson_GpioIni

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 1/2] Fix GCC build failure.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 .../BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index 324baf9ad..28fc52922 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -59,7 +59,7 @@ BensonGlacierPostMemInitCallback (
   ZeroMem (, sizeof (SYSTEM_CONFIGURATION));
 
  (*PeiServices)->LocatePpi (
-PeiServices,
+(CONST EFI_PEI_SERVICES **)PeiServices,
 ,
 0,
 NULL,
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] SueCreek Bypass

[zwei4]

Add code in ACPI table for TI audio codec under I2C5.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../BensonGlacier/BoardInitPostMem/BoardInit.c |  33 +++-
 .../BoardInitPostMem/BoardInitPostMem.inf  |   1 +
 .../Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c |   4 +-
 .../Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf   |   1 +
 .../Common/Acpi/AcpiTablesPCAT/GloblNvs.asl|   1 +
 .../PlatformSsdt/Audio/AudioCodec10TI3100.asl  |  44 +
 .../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl   |   2 +
 .../Common/Include/Guid/SetupVariable.h|   3 +-
 .../PlatformSetupDxe/SouthClusterConfig.vfi|   7 
 .../PlatformSettings/PlatformSetupDxe/UqiList.uni  | Bin 126596 -> 126916 bytes
 .../PlatformSetupDxe/VfrStrings.uni| Bin 305486 -> 305886 bytes
 Platform/BroxtonPlatformPkg/PlatformPkg.dec|   3 +-
 .../NorthCluster/Include/Protocol/GlobalNvsArea.h  |   3 +-
 13 files changed, 96 insertions(+), 6 deletions(-)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec10TI3100.asl

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index 07246c155..324baf9ad 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -51,6 +51,29 @@ BensonGlacierPostMemInitCallback (
   UINT8ResetType;
   UINTNBufferSize;
   UINT8MaxPkgCState;
+  UINTNVariableSize;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariableServices;
+  SYSTEM_CONFIGURATION SystemConfiguration;
+
+  VariableSize = sizeof (SYSTEM_CONFIGURATION);
+  ZeroMem (, sizeof (SYSTEM_CONFIGURATION));
+
+ (*PeiServices)->LocatePpi (
+PeiServices,
+,
+0,
+NULL,
+(VOID **) 
+ );
+
+  VariableServices->GetVariable (
+  VariableServices,
+  PLATFORM_SETUP_VARIABLE_NAME,
+  ,
+  NULL,
+  ,
+  
+  );
 
   Status = PeiServicesLocatePpi (
  ,
@@ -91,7 +114,15 @@ BensonGlacierPostMemInitCallback (
   //
   // Set PcdSueCreek
   //
-  PcdSetBool (PcdSueCreek, TRUE);
+  if (SystemConfiguration.SueCreekBypass) {
+PcdSetBool (PcdSueCreek, FALSE);
+PcdSetBool (PcdTi3100AudioCodecEnable, TRUE);
+DEBUG ((EFI_D_INFO,  "Bypass SueCreek \n"));
+  } else {
+PcdSetBool (PcdSueCreek, TRUE);
+PcdSetBool (PcdTi3100AudioCodecEnable, FALSE); 
+DEBUG ((EFI_D_INFO,  "Use SueCreek \n"));
+  }
 
   //
   // Set PcdMaxPkgCState
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
index 55ec5b75f..e15e61293 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -65,6 +65,7 @@
   gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
   gPlatformModuleTokenSpaceGuid.PcdSueCreek
   gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState
+  gPlatformModuleTokenSpaceGuid.PcdTi3100AudioCodecEnable
 
 [Guids]
   gEfiPlatformInfoGuid
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
index d0c668ef5..c18753b61 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
@@ -1439,8 +1439,8 @@ AcpiPlatformEntryPoint (
 mGlobalNvsArea.Area->BatteryCapacity0   = 100;
 mGlobalNvsArea.Area->Mmio32Base = (MmioRead32 ((UINTN) 
PcdGet64 (PcdPciExpressBaseAddress) + 0xBC) & 0xFFF0);;
 mGlobalNvsArea.Area->Mmio32Length   = ACPI_MMIO_BASE_ADDRESS - 
mGlobalNvsArea.Area->Mmio32Base;
-mGlobalNvsArea.Area->SueCreekEnable   = 
PcdGetBool(PcdSueCreek);
-
+mGlobalNvsArea.Area->SueCreekEnable = PcdGetBool(PcdSueCreek);
+mGlobalNvsArea.Area->Ti3100AudioCodecEnable = 
PcdGetBool(PcdTi3100AudioCodecEnable );
 //
 // Initialize IGD state by checking if IGD Device 2 Function 0 is enabled 
in the chipset
 //
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPl

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Benson FAB B

[zwei4]

Add code for Benson Glacier FAB B.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 .../BensonGlacier/BoardInitPostMem/BoardGpios.h|   6 +-
 .../BensonGlacier/BoardInitPostMem/BoardInit.c |   2 -
 .../BensonGlacier/BoardInitPreMem/BoardInit.c  |  15 ++-
 .../BensonGlacier/BoardInitPreMem/PlatformId.c | 136 -
 .../BensonGlacier/BoardInitPreMem/PlatformId.h |  16 +--
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c|   2 -
 .../Board/LeafHill/BoardInitPreMem/BoardInit.c |   5 +-
 .../MinnowBoard3/BoardInitPostMem/BoardInit.c  |   2 -
 .../Board/MinnowBoard3/BoardInitPreMem/BoardInit.c |   6 +-
 Platform/BroxtonPlatformPkg/BuildBxtBios.bat   |   6 +-
 .../Common/Tools/Stitch/IFWIStitch_Simple.bat  |  12 +-
 11 files changed, 55 insertions(+), 153 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
index d72cd80c9..d5accbc17 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
@@ -90,10 +90,10 @@ BXT_GPIO_PAD_INIT  mBenson_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_24",  M0   ,GPO   ,GPIO_D ,  NA 
   ,   NA   , Wake_Disabled, P_20K_H,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00C0,  NORTH),//SATA_DEVSLP0
   BXT_GPIO_PAD_CONF(L"GPIO_25",  M0   ,GPO   ,GPIO_D ,  NA 
   ,   Level, Wake_Disabled, P_20K_H, Inverted,   SCI, NA   , NA, 
GPIO_PADBAR+0x00C8,  NORTH),//Feature:ODD MD/DA SCI  Net in Sch: 
SATA_ODD_DA_IN
   BXT_GPIO_PAD_CONF(L"GPIO_26",  M0   ,GPIO  ,GPIO_D ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D0,  NORTH),//SATA_LEDN
-  BXT_GPIO_PAD_CONF(L"GPIO_27",  M0   ,GPO   , GPIO_D,  HI 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D8,  NORTH),//Feature:DFUNet in Sch: NFC_DFU
+  BXT_GPIO_PAD_CONF(L"GPIO_27",  M0   ,GPO   ,GPIO_D ,  HI 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D8,  NORTH),//Feature:DFUNet in Sch: NFC_DFU
   BXT_GPIO_PAD_CONF(L"GPIO_28",  M2   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00E0,  NORTH),//   Net in Sch: 
ISH_GPIO10
-  BXT_GPIO_PAD_CONF(L"GPIO_29",  M2   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00E8,  NORTH),//   Net in Sch: 
ISH_GPIO11
-  BXT_GPIO_PAD_CONF(L"GPIO_30",  M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00F0,  NORTH),//   Net in Sch: 
ISH_GPIO12
+  BXT_GPIO_PAD_CONF(L"GPIO_29",  M0   ,GPO   ,GPIO_D ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00E8,  NORTH),// SOC_M2_RST   Net in 
Sch: ISH_GPIO11
+  //BXT_GPIO_PAD_CONF(L"GPIO_30",  M1   ,NA,  NA   ,  
NA,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   
SAME, GPIO_PADBAR+0x00F0,  NORTH),// FAB ID  Net in 
Sch: ISH_GPIO12
   BXT_GPIO_PAD_CONF(L"GPIO_31",  M5   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00F8,  NORTH),//Feature: SUSCLK1
   BXT_GPIO_PAD_CONF(L"GPIO_32",  M5   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x0100,  NORTH),//   Net in Sch: SUSCLK2
   BXT_GPIO_PAD_CONF(L"GPIO_33",  M5   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x0108,  NORTH),//Feature: SUSCLK3
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index ab11aaafd..07246c155 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -59,7 +59,6 @@ BensonGlacierPostMemInitCallback (
  
  );
   if (!EFI_ERROR

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] VBT table change

[zwei4]

Move VBT tables from common folder into board specific folders.

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
Cc: Loeppert, Anthony <anthony.loepp...@intel.com>
---
 .../BensonGlacier/BoardInitPostMem/BoardInit.c |   7 ++
 .../BoardInitPostMem/BoardInitPostMem.inf  |   2 +
 .../BensonGlacier}/Vbt/VbtBxtEdp.bin   | Bin
 .../BensonGlacier}/Vbt/VbtBxtMipi.bin  | Bin
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c|   7 ++
 .../LeafHill/BoardInitPostMem/BoardInitPostMem.inf |   2 +
 .../Board/LeafHill/Vbt/VbtBxtEdp.bin   | Bin 0 -> 5632 bytes
 .../Board/LeafHill/Vbt/VbtBxtMipi.bin  | Bin 0 -> 5632 bytes
 .../MinnowBoard3/BoardInitPostMem/BoardInit.c  |   7 ++
 .../BoardInitPostMem/BoardInitPostMem.inf  |   2 +
 .../Board/MinnowBoard3/Vbt/VbtBxtEdp.bin   | Bin 0 -> 5632 bytes
 .../Board/MinnowBoard3/Vbt/VbtBxtMipi.bin  | Bin 0 -> 5632 bytes
 .../PlatformGopPolicyDxe/PlatformGopPolicy.c   |  88 +
 .../PlatformGopPolicyDxe/PlatformGopPolicyDxe.inf  |   4 +-
 .../PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf|   6 +-
 .../PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c|   4 +-
 Platform/BroxtonPlatformPkg/PlatformPkg.dec|   7 +-
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf|  22 --
 18 files changed, 72 insertions(+), 86 deletions(-)
 rename Platform/BroxtonPlatformPkg/{Common/Binaries => 
Board/BensonGlacier}/Vbt/VbtBxtEdp.bin (100%)
 rename Platform/BroxtonPlatformPkg/{Common/Binaries => 
Board/BensonGlacier}/Vbt/VbtBxtMipi.bin (100%)
 create mode 100644 Platform/BroxtonPlatformPkg/Board/LeafHill/Vbt/VbtBxtEdp.bin
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/LeafHill/Vbt/VbtBxtMipi.bin
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3/Vbt/VbtBxtEdp.bin
 create mode 100644 
Platform/BroxtonPlatformPkg/Board/MinnowBoard3/Vbt/VbtBxtMipi.bin

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index a4f3414b4..8b21b50a7 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -49,6 +49,7 @@ BensonGlacierPostMemInitCallback (
   UINT8BoardId;
   UINT8FabId;
   UINT8ResetType;
+  UINTNBufferSize;
 
   Status = PeiServicesLocatePpi (
  ,
@@ -82,6 +83,12 @@ BensonGlacierPostMemInitCallback (
   ResetType = V_RST_CNT_HARDRESET;
   PcdSet8 (PcdResetType, (UINT8) ResetType);
 
+  //
+  // Board specific VBT table.
+  //
+  BufferSize = sizeof (EFI_GUID);
+  PcdSetPtr(PcdBoardVbtFileGuid, , (UINT8 
*));
+
   //
   // Add init steps here
   //
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
index 4ce6ab2db..c22bfadb5 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -62,6 +62,7 @@
   gPlatformModuleTokenSpaceGuid.PcdBoardId
   gPlatformModuleTokenSpaceGuid.PcdFabId
   gPlatformModuleTokenSpaceGuid.PcdResetType
+  gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
 
 [Guids]
   gEfiPlatformInfoGuid
@@ -73,6 +74,7 @@
   gEfiTpmDeviceInstanceTpm12Guid
   gEfiTpmDeviceInstanceTpm20DtpmGuid
   gTpmDeviceInstanceTpm20PttPtpGuid
+  gPeiBensonGlacierVbtGuid
 
 [Ppis]
   gBoardPostMemInitStartGuid
diff --git a/Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtEdp.bin 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/Vbt/VbtBxtEdp.bin
similarity index 100%
rename from Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtEdp.bin
rename to Platform/BroxtonPlatformPkg/Board/BensonGlacier/Vbt/VbtBxtEdp.bin
diff --git a/Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtMipi.bin 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/Vbt/VbtBxtMipi.bin
similarity index 100%
rename from Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtMipi.bin
rename to Platform/BroxtonPlatformPkg/Board/BensonGlacier/Vbt/VbtBxtMipi.bin
diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
index e591b1d1f..60fe1a31a 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
@@ -57,6 +57,7 @@ LeafHillPostMemInitCallback (
   UINT8BoardId;
   UINT8FabId;
   UINT8 

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Update Minor Version of BIOS ID.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/BiosId.env | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/BroxtonPlatformPkg/BiosId.env 
b/Platform/BroxtonPlatformPkg/BiosId.env
index 8de9eb87f..13b7d3be9 100644
--- a/Platform/BroxtonPlatformPkg/BiosId.env
+++ b/Platform/BroxtonPlatformPkg/BiosId.env
@@ -31,5 +31,5 @@ BOARD_ID  = APLKRVP
 BOARD_REV = 3
 BUILD_TYPE= D
 VERSION_MAJOR = 0066
-VERSION_MINOR = 02
+VERSION_MINOR = 03
 BOARD_EXT = X64
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 2/2] Update Minor Version of BIOS ID.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0

Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/BiosId.env | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/BroxtonPlatformPkg/BiosId.env 
b/Platform/BroxtonPlatformPkg/BiosId.env
index 3c1b1a489..8de9eb87f 100644
--- a/Platform/BroxtonPlatformPkg/BiosId.env
+++ b/Platform/BroxtonPlatformPkg/BiosId.env
@@ -31,5 +31,5 @@ BOARD_ID  = APLKRVP
 BOARD_REV = 3
 BUILD_TYPE= D
 VERSION_MAJOR = 0066
-VERSION_MINOR = 01
+VERSION_MINOR = 02
 BOARD_EXT = X64
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Calibrate PMIC IMON.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 .../PlatformPostMemPei/PlatformInit.c  | 49 ++
 .../PlatformSettings/PlatformSetupDxe/UnCore.vfi   |  6 +--
 .../BroxtonSiPkg/NorthCluster/Include/SaRegs.h |  8 +++-
 3 files changed, 59 insertions(+), 4 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
index bfed3bf1a..7d003e466 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
@@ -311,6 +311,53 @@ BXTPolicyInit (
   return EFI_SUCCESS;
 }
 
+VOID
+ConfigurePmicIMON (
+  VOID
+  )
+{
+  UINTN   PciD0F0RegBase = 0;
+  UINTN   MchBar = 0;
+  UINT32  Data;
+  UINT16  StallCount;
+  UINT64  PkgPwrSKU;
+
+  PciD0F0RegBase  = MmPciAddress (0,SA_MC_BUS,SA_MC_DEV,SA_MC_FUN,0);
+  MchBar  = MmioRead32 (PciD0F0RegBase + R_SA_MCHBAR_REG) &~BIT0;
+  PkgPwrSKU   = AsmReadMsr64 (MSR_PACKAGE_POWER_SKU);
+
+  StallCount = 0;
+  while (StallCount < 1000) {
+Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE); 
+if ((Data & BIT31) == BIT31) {
+  MicroSecondDelay (1);
+} else {
+  break;
+}
+StallCount++;
+  }
+  MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xfa0d04a4);
+  MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x811d);
+
+  StallCount = 0;
+  while (StallCount < 1000) {
+Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE);
+if ((Data & BIT31) == BIT31) {
+  MicroSecondDelay (1);
+} else {
+  break;
+}
+StallCount++;
+  }
+
+  if ((PkgPwrSKU & 0x07FFF) >= 0x0903){
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xe8330466);
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x801d);
+  } else { 
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xed3303b3);
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x801d);
+  }
+}
 
 /**
   Platform Init PEI module entry point
@@ -363,6 +410,8 @@ PlatformInitEntryPoint (
   }
 
   PWM_Fan_Start ();
+  
+  ConfigurePmicIMON();
 
   //
   // Initialize PlatformInfo HOB
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
index 32eea2005..f8b4b47ec 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
@@ -1,7 +1,7 @@
 // /** @file
 //  UnCore Setup formset.
 //
-//  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+//  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
 //
 //  This program and the accompanying materials
 //  are licensed and made available under the terms and conditions of the BSD 
License
@@ -104,8 +104,8 @@ form formid = UNCORE_FORM_ID,
   oneof varid = Setup.EnableRenderStandby,
prompt   = STRING_TOKEN(STR_VIDEO_RS2_PROMPT),
help = STRING_TOKEN(STR_VIDEO_RS2_HELP),
-   option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
-   option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
+   option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
+   option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
   endoneof;
 
   oneof varid= Setup.GTTSize,
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h
index 5dd844092..e985e75c4 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h
@@ -15,7 +15,7 @@
   Registers / bits of new devices introduced in a SA generation will be just 
named
   as "_SA_" without [generation_name] inserted.
 
-  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -59,6 +59,12 @@
 #define R_SA_MC_CAPID0_B   0xE8
 #define R_SA_MCHBAR_REG0x48
 
+//
+// IA-Punit Mailbox on MCH BAR 
+//
+#define R_BIOS_MAILBOX_DATA0x7080
+#define R_BIOS_MAILBOX_INTERFACE   0x7084
+
 //
 // Silicon Steppings
 //
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Calibrate PMIC IMON.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0

Signed-off-by: zwei4 <david@intel.com>
---
 .../PlatformPostMemPei/PlatformInit.c  | 76 ++
 .../PlatformSettings/PlatformSetupDxe/UnCore.vfi   |  6 +-
 .../BroxtonSiPkg/NorthCluster/Include/SaRegs.h |  8 ++-
 3 files changed, 86 insertions(+), 4 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
index bfed3bf1a..66b0e49f4 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c
@@ -311,6 +311,80 @@ BXTPolicyInit (
   return EFI_SUCCESS;
 }
 
+VOID
+ConfigurePmicIMON (
+  VOID
+  )
+{
+  UINTN   PciD0F0RegBase = 0;
+  UINTN   MchBar = 0;
+  UINT32  Data;
+  UINT16  StallCount;
+  UINT64  PkgPwrSKU;
+
+  PciD0F0RegBase  = MmPciAddress (0,SA_MC_BUS,SA_MC_DEV,SA_MC_FUN,0);
+  MchBar  = MmioRead32 (PciD0F0RegBase + R_SA_MCHBAR_REG) &~BIT0;
+  PkgPwrSKU   = AsmReadMsr64 (MSR_PACKAGE_POWER_SKU);
+
+  StallCount = 0;
+  while (StallCount < 1000) {
+Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE);
+if ((Data & BIT31) == BIT31) {
+  MicroSecondDelay (1); 
+} else {
+  break;
+}
+StallCount++;
+  }
+  MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xfa0d04a4);
+  MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x811d);
+
+  StallCount = 0;
+  while (StallCount < 1000) {
+Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE);
+if ((Data & BIT31) == BIT31) {
+  MicroSecondDelay (1);
+} else {
+  break;
+}
+StallCount++;
+  }
+
+  if ((PkgPwrSKU & 0x07FFF) >= 0x0903){
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xe8330466);
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x801d);
+  } else { 
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xed3303b3);
+MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x801d);
+  }
+
+}
 
 /**
   Platform Init PEI module entry point
@@ -363,6 +437,8 @@ PlatformInitEntryPoint (
   }
 
   PWM_Fan_Start ();
+  
+  ConfigurePmicIMON();
 
   //
   // Initialize PlatformInfo HOB
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
index 32eea2005..f8b4b47ec 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi
@@ -1,7 +1,7 @@
 // /** @file
 //  UnCore Setup formset.
 //
-//  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+//  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
 //
 //  This program and the accompanying materials
 //  are licensed and made available under the terms and conditions of the BSD 
License
@@ -104,8 +104,8 @@ form formid = UNCORE_FORM_ID,
   oneof varid = Setup.EnableRenderStandby,
prompt   = STRING_TOKEN(STR_VIDEO_RS2_PROMPT),
help = STRING_TOKEN(STR_VIDEO_RS2_HELP),
-   option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
-   option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
+   option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
+   option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
   endoneof;
 
   oneof varid= Setup.GTTSize,
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h 
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h
index 5dd844092..e985e75c4 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h
@@ -15,7 +15,7 @@
   Registers / bits of new devices introduced in a SA generation will be just 
named
   as "_SA_" without [generation_name] inserted.
 
-  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -59,6 +59,12 @@
 #define R_SA_MC_CAPID0_B   0xE8
 #define R_SA_MCHBAR_REG0x48
 
+//
+// IA-Punit Mailbox on MCH BAR 
+//
+#define R_BIOS_MAILBOX_DATA0x7080
+#define R_BIOS_MAILBOX_INTERFACE   0x7084
+
 //
 // Silicon Steppings
 //
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 2/2] BroxtonPlatformPkg: RTC initialize

[zwei4]

Force RTC century to 20 in case core driver has failed to
initialize it.

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/PlatformSettings/PlatformDxe/Platform.c |  5 +++
 .../PlatformSettings/PlatformDxe/PlatformDxe.h |  6 +++
 .../PlatformSettings/PlatformDxe/PlatformDxe.inf   |  1 +
 .../Common/PlatformSettings/PlatformDxe/Rtc.c  | 51 ++
 4 files changed, 63 insertions(+)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Rtc.c

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
index abe635d90..a6d251ded 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
@@ -390,6 +390,11 @@ ReadyToBootFunction (
 mPciLanInfo = NULL;
   }
 
+  //
+  // Set RTC century in case RTC core driver failed to initialize it.
+  //
+  AdjustRtcCentury ();
+
   return;
 }
 
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.h 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.h
index 1475c4cab..a27277bb7 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.h
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.h
@@ -235,6 +235,12 @@ InitSioPlatformPolicy (
   VOID
   );
 
+VOID
+EFIAPI
+AdjustRtcCentury (
+  VOID
+  );
+
 //
 // Global externs
 //
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
index 7516a1548..ee8fd5a68 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
@@ -33,6 +33,7 @@
   PciDevice.c
   IchTcoReset.c
   SensorVar.c
+  Rtc.c
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Rtc.c 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Rtc.c
new file mode 100644
index 0..4b6ab285e
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Rtc.c
@@ -0,0 +1,51 @@
+/** @file
+  Adjust Default System Time.
+  
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+   

+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.  
+  The full text of the license may be found at 

+  http://opensource.org/licenses/bsd-license.php.  

+   

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+   

+--*/
+
+#include 
+
+//
+// Date and time initial values.
+// They are used if the RTC values are invalid during driver initialization
+//
+#define RTC_INIT_SECOND 0
+#define RTC_INIT_MINUTE 0
+#define RTC_INIT_HOUR   0
+
+#define RTC_ADDRESS_CENTURY  50
+
+#define RTC_ADDRESS_REGISTER 0x70
+#define RTC_DATA_REGISTER0x71
+
+/**
+  Set RTC century to 20 in case RTC core driver failed to initialize it.
+
+**/
+VOID
+EFIAPI
+AdjustRtcCentury (
+  VOID
+  )
+{
+
+  UINT8  Century;
+
+  Century = 20;
+  Century = DecimalToBcd8 (20);
+  IoWrite8 (RTC_ADDRESS_REGISTER, (UINT8) (RTC_ADDRESS_CENTURY | (UINT8) 
(IoRead8 (PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
+  IoWrite8 (RTC_DATA_REGISTER, Century);
+  Century = IoRead8(RTC_DATA_REGISTER);
+
+  return;
+}
-- 
2.14.1.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 1/2] Clean up CMOS code.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 .../Library/BaseSerialPortLib/BaseSerialPortLib.c  | 69 +++---
 .../BaseSerialPortLib/BaseSerialPortLib.inf|  3 +-
 .../BaseSerialPortLib/BaseSerialPortLibNoInit.c| 46 ++-
 .../BaseSerialPortLib/BaseSerialPortLibNoInit.inf  |  3 +-
 .../Library/PlatformSecLib/Vtf0PlatformSecLib.inf  |  1 -
 .../Common/PlatformSettings/PlatformDxe/Platform.c | 25 
 .../PlatformSettings/PlatformDxe/PlatformDxe.inf   |  1 -
 .../PlatformDsc/LibraryClasses.IA32.PEI.dsc|  1 -
 .../PlatformDsc/LibraryClasses.dsc |  6 --
 .../PlatformDsc/PcdsFixedAtBuild.dsc   |  2 -
 10 files changed, 15 insertions(+), 142 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c
 
b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c
index 5fc9d8c71..2c63f9878 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c
@@ -1,7 +1,7 @@
 /** @file
   Serial I/O Port library functions with no library constructor/destructor.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -18,9 +18,7 @@
 #include 
 #include 
 #include 
-#include 
 #include 
-#include 
 #include 
 
 #ifdef TRACE_HUB_DEBUGLIB_USAGE
@@ -104,13 +102,12 @@ UARTInitialize (
   //
   // Calculate divisor for baud generator
   //
-  BaudRate = GetSerialPortBaudRate ();
+  BaudRate = PcdGet32 (PcdSerialBaudRate);
   if ((BaudRate == 0) || ((BaudRate % 9600) != 0)) {
 //
 // If Serail Baud Rate is not valid, set it to the default value
 //
 BaudRate = PcdGet32 (PcdSerialBaudRate);
-SetSerialPortBaudRate (BaudRate);
   }
   Divisor = MAX_BAUD_RATE / BaudRate;
 
@@ -174,23 +171,8 @@ SerialPortInitialize (
   VOID
   )
 {
-  UINT8  CmosStatusCodeFlags;
 
-  CmosStatusCodeFlags = GetDebugInterface ();
-  if ((!(CmosStatusCodeFlags & STATUS_CODE_CMOS_VALID)) || 
(CmosStatusCodeFlags & STATUS_CODE_CMOS_INVALID)) {
-CmosStatusCodeFlags = STATUS_CODE_USE_SERIALIO | STATUS_CODE_CMOS_VALID;
-SetDebugInterface (CmosStatusCodeFlags);
-  }
-  //
-  // no init for MEM
-  //
-
-  if (CmosStatusCodeFlags & STATUS_CODE_USE_SERIALIO) {
-PchSerialIoUartInit (PcdGet8 (PcdSerialIoUartNumber), TRUE, 115200, 3, 
FALSE);
-  }
-  //
-  // no init for TRACEHUB
-  //
+  PchSerialIoUartInit (PcdGet8 (PcdSerialIoUartNumber), TRUE, 115200, 3, 
FALSE);
 
   return RETURN_SUCCESS;
 }
@@ -307,19 +289,8 @@ SerialPortWrite (
   IN UINTN NumberOfBytes
   )
 {
-  UINT8CmosStatusCodeFlags;
 
-  CmosStatusCodeFlags = GetDebugInterface ();
-  if ((!(CmosStatusCodeFlags & STATUS_CODE_CMOS_VALID)) || 
(CmosStatusCodeFlags & STATUS_CODE_CMOS_INVALID)) {
-//
-// invalid cmos value, it means action was attempted before Init
-//
-return RETURN_NOT_READY;
-  }
-
-  if (CmosStatusCodeFlags & STATUS_CODE_USE_SERIALIO) {
-PchSerialIoUartOut (PcdGet8 (PcdSerialIoUartNumber), Buffer, 
NumberOfBytes);
-  }
+  PchSerialIoUartOut (PcdGet8 (PcdSerialIoUartNumber), Buffer, NumberOfBytes);
 
   return RETURN_SUCCESS;
 }
@@ -399,21 +370,9 @@ SerialPortRead (
   IN  UINTN NumberOfBytes
   )
 {
-  UINT8CmosStatusCodeFlags;
-
-  CmosStatusCodeFlags = GetDebugInterface ();
 
-  if ((!(CmosStatusCodeFlags & STATUS_CODE_CMOS_VALID)) || 
(CmosStatusCodeFlags & STATUS_CODE_CMOS_INVALID)) {
-//
-// invalid cmos value, it means action was attempted before Init
-//
-return RETURN_NOT_READY;
-  }
-
-
-  if (CmosStatusCodeFlags & STATUS_CODE_USE_SERIALIO) {
-PchSerialIoUartIn (PcdGet8 (PcdSerialIoUartNumber), Buffer, NumberOfBytes, 
FALSE);
-  }
+  PchSerialIoUartIn (PcdGet8 (PcdSerialIoUartNumber), Buffer, NumberOfBytes, 
FALSE);
+ 
   return RETURN_SUCCESS;
 }
 
@@ -475,23 +434,11 @@ SerialPortPoll (
   VOID
   )
 {
-  UINT8 CmosStatusCodeFlags;
-  BOOLEAN   Status;
-
-  CmosStatusCodeFlags = GetDebugInterface ();
-  if ((!(CmosStatusCodeFlags & STATUS_CODE_CMOS_VALID)) || 
(CmosStatusCodeFlags & STATUS_CODE_CMOS_INVALID)) {
 
-//
-// invalid cmos value, it means action was attempted before Init
-//
-return FALSE;
-  }
+  BOOLEAN   Status;
 
   Status = FALSE;
-
-  if (CmosStatusCodeFlags & STATUS_CODE_USE_SERIALIO) {
-Status |= PchSerialIoUartPoll (PcdGet8 (PcdSerialIoUartNumber));
-  }
+  Status |= PchSerialIoUartPoll (PcdGet8 (PcdSerialIoUartNumber));
 
   return Status;
 }
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.inf
 
b/Platfo

[edk2] [PATCH][edk2-platforms] Ubuntu boot

[zwei4]

From: xianhu2x 

Add Ubuntu boot loader file path into known OS loader list.

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: xianhu2x 
---
 .../Library/GenericBdsLib/BdsBoot.c| 26 ++
 Core/MdePkg/Include/Uefi/UefiSpec.h| 11 -
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c 
b/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
index d1da635f3..dec5d8cef 100644
--- a/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
+++ b/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
@@ -2384,6 +2384,21 @@ BdsLibBootViaBootOption (
   0,
   
   );
+  //
+  //Try UBUNTU boot loader
+  //
+  if (EFI_ERROR(Status)) {
+FilePath = FileDevicePath (Handle, 
EFI_REMOVABLE_MEDIA_FILE_NAME_UBUNTU);
+Status = gBS->LoadImage (
+TRUE,
+gImageHandle,
+FilePath,
+NULL,
+0,
+
+);
+  }
+   
 }
   }
 }
@@ -3721,6 +3736,17 @@ BdsLibGetBootableHandle (
  ,
  Hdr
  );
+  //
+  //Try UBUNTU boot loader
+  //
+  if (EFI_ERROR(Status)) {
+Status = BdsLibGetImageHeader (
+   SimpleFileSystemHandles[Index],
+   EFI_REMOVABLE_MEDIA_FILE_NAME_UBUNTU,
+   ,
+   Hdr
+   );
+  }
   if (!EFI_ERROR (Status) &&
 EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32->FileHeader.Machine) &&
 Hdr.Pe32->OptionalHeader.Subsystem == 
EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {
diff --git a/Core/MdePkg/Include/Uefi/UefiSpec.h 
b/Core/MdePkg/Include/Uefi/UefiSpec.h
index 57cb4e804..e5556952b 100644
--- a/Core/MdePkg/Include/Uefi/UefiSpec.h
+++ b/Core/MdePkg/Include/Uefi/UefiSpec.h
@@ -2166,11 +2166,12 @@ typedef struct {
 //
 // EFI File location to boot from on removable media devices
 //
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32L"\\EFI\\BOOT\\BOOTIA32.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64L"\\EFI\\BOOT\\BOOTIA64.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32   L"\\EFI\\BOOT\\BOOTIA32.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64   L"\\EFI\\BOOT\\BOOTIA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64L"\\EFI\\BOOT\\BOOTX64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARML"\\EFI\\BOOT\\BOOTARM.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_UBUNTU_X64 L"\\EFI\\UBUNTU\\GRUBX64.EFI"
 
 #if   defined (MDE_CPU_IA32)
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
-- 
2.14.1.windows.1

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[edk2] [PATCH] Add UBUNTU boot loader

[zwei4]

From: xianhu2x 

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: xianhu2x 
---
 .../Library/GenericBdsLib/BdsBoot.c| 26 ++
 Core/MdePkg/Include/Uefi/UefiSpec.h| 11 -
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c 
b/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
index d1da635f3..dec5d8cef 100644
--- a/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
+++ b/Core/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
@@ -2384,6 +2384,21 @@ BdsLibBootViaBootOption (
   0,
   
   );
+  //
+  //Try UBUNTU boot loader
+  //
+  if (EFI_ERROR(Status)) {
+FilePath = FileDevicePath (Handle, 
EFI_REMOVABLE_MEDIA_FILE_NAME_UBUNTU);
+Status = gBS->LoadImage (
+TRUE,
+gImageHandle,
+FilePath,
+NULL,
+0,
+
+);
+  }
+   
 }
   }
 }
@@ -3721,6 +3736,17 @@ BdsLibGetBootableHandle (
  ,
  Hdr
  );
+  //
+  //Try UBUNTU boot loader
+  //
+  if (EFI_ERROR(Status)) {
+Status = BdsLibGetImageHeader (
+   SimpleFileSystemHandles[Index],
+   EFI_REMOVABLE_MEDIA_FILE_NAME_UBUNTU,
+   ,
+   Hdr
+   );
+  }
   if (!EFI_ERROR (Status) &&
 EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32->FileHeader.Machine) &&
 Hdr.Pe32->OptionalHeader.Subsystem == 
EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {
diff --git a/Core/MdePkg/Include/Uefi/UefiSpec.h 
b/Core/MdePkg/Include/Uefi/UefiSpec.h
index 57cb4e804..e5556952b 100644
--- a/Core/MdePkg/Include/Uefi/UefiSpec.h
+++ b/Core/MdePkg/Include/Uefi/UefiSpec.h
@@ -2166,11 +2166,12 @@ typedef struct {
 //
 // EFI File location to boot from on removable media devices
 //
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32L"\\EFI\\BOOT\\BOOTIA32.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64L"\\EFI\\BOOT\\BOOTIA64.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32   L"\\EFI\\BOOT\\BOOTIA32.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64   L"\\EFI\\BOOT\\BOOTIA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64L"\\EFI\\BOOT\\BOOTX64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARML"\\EFI\\BOOT\\BOOTARM.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_UBUNTU_X64 L"\\EFI\\UBUNTU\\GRUBX64.EFI"
 
 #if   defined (MDE_CPU_IA32)
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
-- 
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[edk2] [Patch][edk2-platforms 2/2] Change reset type.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c
index 36ac0e3d0..2bac0a5e3 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Reset/RuntimeDxe/ScReset.c
@@ -296,7 +296,7 @@ IntelScResetSystem (
 
 case EfiResetCold:
   InitialData = V_RST_CNT_HARDSTARTSTATE;
-  OutputData  = V_RST_CNT_FULLRESET;
+  OutputData  = V_RST_CNT_HARDRESET;
   break;
 
 case EfiResetShutdown:
-- 
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[edk2] [Patch][edk2-platforms 1/2] Disable PCIe De-emphasis.

[zwei4]

Some PCIe device, such as Intel8265NGW/8260NGW WiFi device, disappears after 
reboot. PCIe root port De-emphasis has to be disabled to fix this issue.

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi   | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
index 35aeb34bf..1b0e93dd9 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -1236,8 +1236,8 @@ form formid   = PCIERP2_OPTIONS_FORM_ID,
 oneof varid   = Setup.PcieRootPortSelectableDeemphasis[OFFSET_1],
   prompt   = STRING_TOKEN (STR_PCH_PCIE_SD_PROMPT),
   help = STRING_TOKEN (STR_PCH_PCIE_SD_HELP),
-  option text = STRING_TOKEN(STR_DISABLE),  value = 0, flags = 
RESET_REQUIRED;
-  option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
+  option text = STRING_TOKEN(STR_DISABLE),  value = 0, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
+  option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = 
RESET_REQUIRED;
 endoneof;
   endif;
 endform; //End of PCIERP2_OPTIONS_FORM_ID
-- 
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[edk2] [Patch][edk2-platforms] Enable GT RC6.

[zwei4]

Remove code that disables GT RC6. This could allow GT to enter deep sleep when 
it is idle, so that more power could be saved for core to use.

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/BiosId.env |  2 +-
 .../Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c|  2 +-
 .../Common/PlatformSettings/PlatformDxe/Platform.c |  4 +---
 .../PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c   |  4 +---
 Platform/BroxtonPlatformPkg/DefineAtBuildMacros.dsc| 14 +++---
 5 files changed, 7 insertions(+), 19 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/BiosId.env 
b/Platform/BroxtonPlatformPkg/BiosId.env
index f8dfb3219..3c1b1a489 100644
--- a/Platform/BroxtonPlatformPkg/BiosId.env
+++ b/Platform/BroxtonPlatformPkg/BiosId.env
@@ -30,6 +30,6 @@
 BOARD_ID  = APLKRVP
 BOARD_REV = 3
 BUILD_TYPE= D
-VERSION_MAJOR = 0065
+VERSION_MAJOR = 0066
 VERSION_MINOR = 01
 BOARD_EXT = X64
diff --git 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
index 6abeb1d34..f124623ec 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
@@ -116,7 +116,7 @@ LhUpdateFspmUpd (
   FspUpdRgn->FspmConfig.MemoryDown  = 1;
   FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;
   FspUpdRgn->FspmConfig.DDR3LASR= 0;
-  FspUpdRgn->FspmConfig.MemorySizeLimit = 0x1800;
+  FspUpdRgn->FspmConfig.MemorySizeLimit = 0;
   FspUpdRgn->FspmConfig.DIMM0SPDAddress = 0;
   FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;
   FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
index e5e9c9319..7733dd0ac 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c
@@ -786,9 +786,7 @@ InitializePlatform (
   mSystemConfiguration.BoardId = PlatformInfoHob->BoardId;
 
   if (mSystemConfiguration.PlatformSettingEn == 0) {
-if (PlatformInfoHob->PmicVersion == 0) {
-  mSystemConfiguration.EnableRenderStandby = 0;
-}
+
 mSystemConfiguration.PlatformSettingEn = 1;
   }
 
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
index 06dffcdfb..7e3beb611 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.c
@@ -145,9 +145,7 @@ LoadPlatformDefaultValues (
 case BOARD_ID_LFH_CRB:
 case BOARD_ID_MINNOW:
 case BOARD_ID_BENSON:
-  if (Private->FakeNvData.PmicSetupDefault == 1) {
-Private->FakeNvData.EnableRenderStandby = FALSE;
-  }
+
   break;
 default:
   break;
diff --git a/Platform/BroxtonPlatformPkg/DefineAtBuildMacros.dsc 
b/Platform/BroxtonPlatformPkg/DefineAtBuildMacros.dsc
index e5ee4c1b4..0e29ef3be 100644
--- a/Platform/BroxtonPlatformPkg/DefineAtBuildMacros.dsc
+++ b/Platform/BroxtonPlatformPkg/DefineAtBuildMacros.dsc
@@ -1,11 +1,3 @@
-DEFINE ENBDT_PF_BUILD = TRUE
-DEFINE TABLET_PF_BUILD = FALSE
-DEFINE BYTI_PF_BUILD = FALSE
-DEFINE CSLE_ENABLE = FALSE
-DEFINE VP_BIOS_ENABLE = FALSE
-DEFINE SV_BIOS_ENABLE = FALSE
-DEFINE PPV_BIOS_ENABLE = FALSE
-DEFINE RVVP_BIOS_ENABLE = FALSE
-DEFINE RVV_BIOS_ENABLE = FALSE
-DEFINE SOURCE_DEBUG_ENABLE = FALSE
-DEFINE X64_CONFIG = TRUE
+DEFINE ENBDT_PF_BUILD  = TRUE  
+DEFINE APLK_SETUP_ENABLE_BUILD = TRUE 
+DEFINE X64_CONFIG  = TRUE  
-- 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Add Source Level Debug

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/BuildBios.sh   |  1 -
 .../FspmWrapperPeim/FspmWrapperPeim.inf|  3 ---
 .../PlatformDsc/Components.IA32.dsc|  2 ++
 .../BroxtonPlatformPkg/PlatformDsc/Defines.dsc |  6 +-
 .../PlatformDsc/LibraryClasses.DxeDriver.dsc   | 25 ++
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf|  4 ++--
 Platform/BroxtonPlatformPkg/PlatformPkgIA32.dsc| 19 +---
 Platform/BroxtonPlatformPkg/PlatformPkgX64.dsc | 19 +---
 Platform/BroxtonPlatformPkg/PlatformPkgX64Gcc.dsc  | 19 +---
 9 files changed, 33 insertions(+), 65 deletions(-)
 create mode 100644 
Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeDriver.dsc

diff --git a/Platform/BroxtonPlatformPkg/BuildBios.sh 
b/Platform/BroxtonPlatformPkg/BuildBios.sh
index 40d873e7a..3fa450b60 100644
--- a/Platform/BroxtonPlatformPkg/BuildBios.sh
+++ b/Platform/BroxtonPlatformPkg/BuildBios.sh
@@ -147,7 +147,6 @@ echo DEFINE SV_BIOS_ENABLE  = $SV_BIOS_ENABLE   >> 
$Build_Macros
 echo DEFINE PPV_BIOS_ENABLE = $PPV_BIOS_ENABLE  >> $Build_Macros
 echo DEFINE RVVP_BIOS_ENABLE= $RVVP_BIOS_ENABLE >> $Build_Macros
 echo DEFINE RVV_BIOS_ENABLE = $RVV_BIOS_ENABLE  >> $Build_Macros
-echo DEFINE SOURCE_DEBUG_ENABLE = $SrcDebug >> $Build_Macros
 
 if [ $Arch == "IA32" ]; then
   echo DEFINE X64_CONFIG = FALSE  >> $Build_Macros
diff --git 
a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
 
b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 334c8b02e..eeca8ac45 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -79,9 +79,6 @@
 
 [Sources]
   FspmWrapperPeim.c
-  ./../FspInitPei/SecMain.c
-  ./../FspInitPei/SecMain.h
-  ./../FspInitPei/FindPeiCore.c
 
 [Ppis]
   gTopOfTemporaryRamPpiGuid ## PRODUCES
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
index 1341e082b..f8900ea4b 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
@@ -17,6 +17,8 @@
 
   DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
   
PlatformSecLib|$(PLATFORM_PACKAGE_COMMON)/Library/PlatformSecLib/Vtf0PlatformSecLib.inf
+  
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x00
   gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x0
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
index 69641ced3..a2da30bf7 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
@@ -163,8 +163,4 @@
 DEFINE FSP_RAM_CODE_SIZE   = $(FSP_IBBM_SIZE)
 DEFINE CAR_REGION_SIZE = 0x10
 
-!if $(TARGET) == DEBUG
-  DEFINE SOURCE_DEBUG_ENABLE = TRUE
-!else 
-  DEFINE SOURCE_DEBUG_ENABLE = FALSE
-!endif
\ No newline at end of file
+DEFINE SOURCE_DEBUG_ENABLE = FALSE
diff --git 
a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeDriver.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeDriver.dsc
new file mode 100644
index 0..d9c91e668
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeDriver.dsc
@@ -0,0 +1,25 @@
+## @file
+#  Dxe Driver Library Classes Description.
+#
+#  Copyright (c) 2017, Intel Corporation. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+  !if $(PERFORMANCE_ENABLE) == TRUE
+PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
TimerLib|$(PLATFORM_PACKAGE_COMMON)/Library/PlatformTscTimerLib/DxeTscTimerLib.inf
+  !endif
+  
+  !if $(SOURCE_DEBUG_ENABLE) == TRUE
+DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+  !else
+DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Enable source level debug.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/BuildBios.bat |  2 +-
 .../PlatformDsc/Components.IA32.dsc   |  3 +++
 .../BroxtonPlatformPkg/PlatformDsc/Components.dsc |  4 
 Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc   |  5 +
 .../PlatformDsc/LibraryClasses.DxeCore.dsc|  6 ++
 .../PlatformDsc/LibraryClasses.DxeRuntimeDriver.dsc   |  6 ++
 .../PlatformDsc/LibraryClasses.DxeSmmDriver.dsc   |  2 ++
 .../PlatformDsc/LibraryClasses.IA32.PEI.dsc   |  6 +-
 .../PlatformDsc/LibraryClasses.SmmCore.dsc|  5 +
 .../BroxtonPlatformPkg/PlatformDsc/LibraryClasses.dsc | 19 ++-
 .../PlatformDsc/PcdsFixedAtBuild.dsc  |  8 +++-
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf   |  8 
 Platform/BroxtonPlatformPkg/PlatformPkgIA32.dsc   |  6 ++
 Platform/BroxtonPlatformPkg/PlatformPkgX64.dsc|  6 ++
 Platform/BroxtonPlatformPkg/PlatformPkgX64Gcc.dsc |  6 ++
 .../BroxtonSoC/BroxtonSiPkg/Library/GpioLib/GpioLib.c |  4 ++--
 .../BroxtonSiPkg/Txe/Library/HeciMsgLib/HeciMsgLib.c  |  4 ++--
 17 files changed, 80 insertions(+), 20 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/BuildBios.bat 
b/Platform/BroxtonPlatformPkg/BuildBios.bat
index 2ecc28d6b..7aca17650 100644
--- a/Platform/BroxtonPlatformPkg/BuildBios.bat
+++ b/Platform/BroxtonPlatformPkg/BuildBios.bat
@@ -204,7 +204,7 @@ copy /y nul %Build_Macros% >nul
 
 ::output platform specific build macros to DefineAtBuildMacros.dsc
 echo DEFINE ENBDT_PF_BUILD  = %ENBDT_PF_BUILD%  >> 
%Build_Macros%
-echo DEFINE SOURCE_DEBUG_ENABLE = %SrcDebug%>> 
%Build_Macros%
+
 echo DEFINE APLK_SETUP_ENABLE_BUILD = %APLK_SETUP_ENABLE_BUILD% >> 
%Build_Macros%
 
 if "%Arch%"=="IA32" (
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
index bfc45ff2f..1341e082b 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.IA32.dsc
@@ -201,3 +201,6 @@
   $(PLATFORM_PACKAGE_COMMON)/FpdtPei/FpdtPei.inf
 !endif
 
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf
+!endif
\ No newline at end of file
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
index 234c27708..04f616c36 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
@@ -32,6 +32,10 @@
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   }
 
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf
+!endif
+
   UefiCpuPkg/CpuDxe/CpuDxe.inf {
 
   CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
index 842acf308..69641ced3 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
@@ -163,3 +163,8 @@
 DEFINE FSP_RAM_CODE_SIZE   = $(FSP_IBBM_SIZE)
 DEFINE CAR_REGION_SIZE = 0x10
 
+!if $(TARGET) == DEBUG
+  DEFINE SOURCE_DEBUG_ENABLE = TRUE
+!else 
+  DEFINE SOURCE_DEBUG_ENABLE = FALSE
+!endif
\ No newline at end of file
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeCore.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeCore.dsc
index 5ae62d3dc..d60c900e7 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeCore.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeCore.dsc
@@ -30,4 +30,10 @@
 
TimerLib|$(PLATFORM_PACKAGE_COMMON)/Library/PlatformTscTimerLib/DxeTscTimerLib.inf
  !endif
   !endif
+ 
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!else
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
 
diff --git 
a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeRuntimeDriver.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeRuntimeDriver.dsc
index 75c07b151..9e13b6ff2 100644
--- 
a/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeRuntimeDriver.dsc
+++ 
b/Platform/BroxtonPlatformPkg/PlatformDsc/LibraryClasses.DxeRuntimeDriver.dsc
@@ -19,3 +19,9 @@
  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
   !endif
 
+  !if $(SOURCE_DEBUG_ENABLE) == TRUE
+DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+  !else
+DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  !endif
+
diff -

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] WIFI Pin Setting

[zwei4]

Configure GPIO pins of on-board WIFI.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h  | 4 ++--
 .../Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl   | 8 +++-
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
index 1bf848995..77d409026 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
@@ -73,7 +73,7 @@ BXT_GPIO_PAD_INIT  mMinnow3_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_7",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0038,  NORTH),//Mux with DISP1_TOUCH_INT_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_8",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0040,  NORTH),//Mux with DISP1_TOUCH_RST_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_9",   M1   ,NA,  NA,  
NA,   NA  , Wake_Disabled, P_20K_L,NA,   NA ,NA   , NA, 
GPIO_PADBAR+0x0048,  NORTH),//Feature: LB
-  BXT_GPIO_PAD_CONF(L"GPIO_10",  M0   ,GPO   , GPIO_D ,  
HI   ,   Level, Wake_Enabled , P_20K_L,NA, NA,   TxDRxE , NA, 
GPIO_PADBAR+0x0050,  NORTH),//Feature: LB 
+  BXT_GPIO_PAD_CONF(L"GPIO_10",  M0   ,GPO   , GPIO_D ,  
LO   ,   Level, Wake_Enabled , P_20K_L,NA, NA,   NA   , NA, 
GPIO_PADBAR+0x0050,  NORTH),//Feature: LB 
   BXT_GPIO_PAD_CONF(L"GPIO_11",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0058,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_12",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Enabled , P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0060,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_13",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0068,  NORTH),//Feature: LB
@@ -259,7 +259,7 @@ BXT_GPIO_PAD_INIT  mMinnow3_GpioInitData_W [] =
   BXT_GPIO_PAD_CONF(L"GPIO_151 ISH_GPIO_5",  M0   ,GPO   ,GPIO_D,   HI 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,  NA  ,  
GPIO_PADBAR+0x00A8,  WEST),//Feature: RF_KILL_WWAN   Net in Sch: 
NGFF_WWAN_RF_KILL_1P8_N
   BXT_GPIO_PAD_CONF(L"GPIO_152 ISH_GPIO_6",  M2   ,NA  ,   NA,  NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,  NA  ,  
GPIO_PADBAR+0x00B0,  WEST),//Feature: AVS_I2S5_SDI
   BXT_GPIO_PAD_CONF(L"GPIO_153 ISH_GPIO_7",  M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,  
GPIO_PADBAR+0x00B8,  WEST),
-  BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8",  M0   ,GPO   ,GPIO_D,   HI 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,  NA  ,  
GPIO_PADBAR+0x00C0,  WEST),//Feature: BT_Disable Net in Sch: 
BT_DISABLE2_1P8_N
+  BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8",  M0   ,GPO   ,GPIO_D,   LO 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,  NA  ,  
GPIO_PADBAR+0x00C0,  WEST),//Feature: BT_Disable Net in Sch: 
BT_DISABLE2_1P8_N
   BXT_GPIO_PAD_CONF(L"GPIO_155 ISH_GPIO_9",  M2   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,  
GPIO_PADBAR+0x00C8,  WEST),//CG2000 PDB: If PDB = 0: power-down; If PDB = 1: 
power-up, it is the same in ISH/LPSS mode
   BXT_GPIO_PAD_CONF(L"GPIO_209 PCIE_CLKREQ0_B",  M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_NONE,NA,NA, HizRx0I,  EnPd, 
GPIO_PADBAR+0x00D0,  WEST),
   BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B",  M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA, HizRx0I,  EnPd, 
GPIO_PADBAR+0x00D8,  WEST),
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl
 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl
index ed4b285ac..7d0fa4ba8 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl
+++ 
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl
@@ -12,9 +12,7 @@
 **/
 
 /*

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Multi board support.

[zwei4]

Cleanup libraries for multi boards.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../BensonGlacier/BoardInitDxe/BoardInitDxe.h  |  4 +-
 .../BensonGlacier/BoardInitPostMem/BoardGpios.c| 72 +--
 .../BensonGlacier/BoardInitPostMem/BoardGpios.h| 22 +++---
 .../BensonGlacier/BoardInitPostMem/BoardInit.c |  2 +-
 .../BensonGlacier/BoardInitPostMem/BoardInit.h |  6 +-
 .../BoardInitPostMem/BoardInitMiscs.c  | 24 +++
 .../BoardInitPostMem/BoardInitMiscs.h  | 18 ++---
 .../BoardInitPostMem/PlatformInfoHob.c |  4 +-
 .../BensonGlacier/BoardInitPreMem/BoardInit.c  |  6 +-
 .../BensonGlacier/BoardInitPreMem/BoardInit.h  |  6 +-
 .../BensonGlacier/BoardInitPreMem/BoardInitMiscs.h |  6 +-
 .../BensonGlacier/BoardInitPreMem/PlatformId.c |  8 +--
 .../BensonGlacier/BoardInitPreMem/PlatformId.h | 18 ++---
 .../Board/LeafHill/BoardInitDxe/BoardInitDxe.h |  4 +-
 .../Board/LeafHill/BoardInitPostMem/BoardGpios.c   | 80 +++---
 .../Board/LeafHill/BoardInitPostMem/BoardGpios.h   | 32 -
 .../Board/LeafHill/BoardInitPostMem/BoardInit.c|  2 +-
 .../Board/LeafHill/BoardInitPostMem/BoardInit.h|  6 +-
 .../LeafHill/BoardInitPostMem/BoardInitMiscs.c | 22 +++---
 .../LeafHill/BoardInitPostMem/BoardInitMiscs.h | 16 ++---
 .../LeafHill/BoardInitPostMem/PlatformInfoHob.c|  2 +-
 .../Board/LeafHill/BoardInitPreMem/BoardInit.c |  6 +-
 .../Board/LeafHill/BoardInitPreMem/BoardInit.h |  6 +-
 .../LeafHill/BoardInitPreMem/BoardInitMiscs.h  |  4 +-
 .../Board/LeafHill/BoardInitPreMem/PlatformId.c|  4 +-
 .../Board/LeafHill/BoardInitPreMem/PlatformId.h| 18 ++---
 .../Board/MinnowBoard3/BoardInitDxe/BoardInitDxe.h |  4 +-
 .../MinnowBoard3/BoardInitPostMem/BoardGpios.c | 70 +--
 .../MinnowBoard3/BoardInitPostMem/BoardGpios.h | 22 +++---
 .../MinnowBoard3/BoardInitPostMem/BoardInit.c  |  2 +-
 .../MinnowBoard3/BoardInitPostMem/BoardInit.h  |  6 +-
 .../MinnowBoard3/BoardInitPostMem/BoardInitMiscs.c | 22 +++---
 .../MinnowBoard3/BoardInitPostMem/BoardInitMiscs.h | 18 ++---
 .../BoardInitPostMem/PlatformInfoHob.c |  4 +-
 .../Board/MinnowBoard3/BoardInitPreMem/BoardInit.c |  8 +--
 .../Board/MinnowBoard3/BoardInitPreMem/BoardInit.h |  6 +-
 .../MinnowBoard3/BoardInitPreMem/BoardInitMiscs.h  |  6 +-
 .../MinnowBoard3/BoardInitPreMem/PlatformId.c  |  8 +--
 .../MinnowBoard3/BoardInitPreMem/PlatformId.h  | 20 +++---
 39 files changed, 297 insertions(+), 297 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.h 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.h
index e8f2aa3f0..e7ba1d255 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.h
@@ -14,8 +14,8 @@
 
 **/
 
-#ifndef __BOARD_INIT_DXE_H__
-#define __BOARD_INIT_DXE_H__
+#ifndef __BENSON_BOARD_INIT_DXE_H__
+#define __BENSON_BOARD_INIT_DXE_H__
 
 #include 
 #include 
diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c
index eef62d9fa..df11c8bbd 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.c
@@ -13,7 +13,7 @@
 
 **/
 
-#include 
+#include "BoardGpios.h"
 #include 
 #include 
 
@@ -30,12 +30,12 @@
 
 **/
 EFI_STATUS
-MultiPlatformGpioTableInit (
+BensonMultiPlatformGpioTableInit (
   IN CONST EFI_PEI_SERVICES **PeiServices,
   IN EFI_PLATFORM_INFO_HOB  *PlatformInfoHob
   )
 {
-  DEBUG ((DEBUG_INFO, "MultiPlatformGpioTableInit()...\n"));
+  DEBUG ((DEBUG_INFO, "BensonMultiPlatformGpioTableInit()...\n"));
   DEBUG ((DEBUG_INFO, "PlatformInfoHob->BoardId: 0x%02X\n", 
PlatformInfoHob->BoardId));
 
   //
@@ -45,16 +45,16 @@ MultiPlatformGpioTableInit (
 case BOARD_ID_LFH_CRB:
 case BOARD_ID_MINNOW:
 case BOARD_ID_BENSON:
-  PlatformInfoHob->PlatformGpioSetting_SW = _GpioInitData_SW[0];
-  PlatformInfoHob->PlatformGpioSetting_W = _GpioInitData_W[0];
-  PlatformInfoHob->PlatformGpioSetting_NW = _GpioInitData_NW[0];
-  PlatformInfoHob->PlatformGpioSetting_N = _GpioInitData_N[0];
+  PlatformInfoHob->PlatformGpioSetting_SW = _GpioInitData_SW[0];
+  PlatformInfoHob->PlatformGpioSetting_W = _GpioInitData_W[0];
+  PlatformInfoHob->PlatformGpioSetting_NW = _GpioInitData_NW[0];
+  PlatformInfoHob->PlatformGpioSetting_N = _GpioInitData_N[0];
   break;
 default:
-  PlatformInfoHob->PlatformGpioSetting_SW = _GpioInitData_SW[0];
-  PlatformInfoHob->Platform

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] LPDDR4 Configuration.

[zwei4]

Change LPDDR4 configuration for Benson Glacier.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../BensonGlacier/BoardInitPreMem/BoardInitMiscs.c | 34 +-
 1 file changed, 27 insertions(+), 7 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c
 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c
index bb1c9bfae..5424df06f 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c
+++ 
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c
@@ -83,13 +83,6 @@ BgUpdateFspmUpd (
 }
 
   }
-  //
-  // override RankEnable settings for Benson
-  //
-  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;
-  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1;
-  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 1;
-  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 1;
 
   DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
   Hob.Raw = GetFirstGuidHob ();
@@ -104,10 +97,37 @@ BgUpdateFspmUpd (
 ASSERT (FALSE);
   }
 
+  FspUpdRgn->FspmConfig.Package = 1;
+  FspUpdRgn->FspmConfig.Profile = 11;
+  FspUpdRgn->FspmConfig.MemoryDown  = 1;
+  FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;
+  FspUpdRgn->FspmConfig.DDR3LASR= 0;
+  FspUpdRgn->FspmConfig.MemorySizeLimit = 0x1800;
+  FspUpdRgn->FspmConfig.DIMM0SPDAddress = 0;
+  FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;
+  FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;
+  FspUpdRgn->FspmConfig.DDR3LASR= 0;
+
+  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;
+  FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 2;
   FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;
+  FspUpdRgn->FspmConfig.Ch0_Option   = 3;
+
+  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1;
+  FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 2;
   FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2;
+  FspUpdRgn->FspmConfig.Ch1_Option   = 3;
+
+  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 1;
+  FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 2;
   FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;
+  FspUpdRgn->FspmConfig.Ch2_Option   = 3;
+
+  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 1;
+  FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 2;
   FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;
+  FspUpdRgn->FspmConfig.Ch3_Option   = 3;
+
   return EFI_SUCCESS;
 }
 
-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] GPIO Change

[zwei4]

Change GPIO for buttons and UART.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
index 674617e84..193f347ec 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
@@ -80,16 +80,16 @@ BXT_GPIO_PAD_INIT  mBXT_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_14",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0070,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_15",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0078,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_16",  M0   ,GPI   ,  NA   ,  NA 
   ,   Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC,  HizRx0I ,DisPuPd, 
GPIO_PADBAR+0x0080,  NORTH),//Feature:SIM Card DetectNet in Sch: 
SIM_CON_CD1, falling edge trigger
-  BXT_GPIO_PAD_CONF(L"GPIO_17",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_H,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x0088,  NORTH),//Feature: LB
-  BXT_GPIO_PAD_CONF(L"GPIO_18",  M0   ,GPI   , NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_H,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x0090,  NORTH),//Feature: LB
-  BXT_GPIO_PAD_CONF(L"GPIO_19",  M0   ,GPI   , NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_H,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x0098,  NORTH),//Feature: LB
+  BXT_GPIO_PAD_CONF(L"GPIO_17",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_H,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x0088,  NORTH),//Feature: LB 
+  BXT_GPIO_PAD_CONF(L"GPIO_18",  M0   ,GPI   , GPIO_D,  NA 
   ,   Edge , Wake_Disabled,  P_NONE,NA   ,NA,TxDRxE, NA, 
GPIO_PADBAR+0x0090,  NORTH),
+  BXT_GPIO_PAD_CONF(L"GPIO_19",  M0   ,GPI   , GPIO_D,  NA 
   ,   Edge , Wake_Disabled,  P_NONE,NA   ,NA,TxDRxE, NA, 
GPIO_PADBAR+0x0098,  NORTH),
   BXT_GPIO_PAD_CONF(L"GPIO_20",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x00A0,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_21",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x00A8,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_23",  M0   ,GPO   , NA   ,   HI 
   ,   NA  ,  Wake_Disabled, P_20K_L,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x00B8,  NORTH),//Feature: LB USB Power in LFH
   BXT_GPIO_PAD_CONF(L"GPIO_24",  M5   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_H,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00C0,  NORTH),//SATA_DEVSLP0
   BXT_GPIO_PAD_CONF(L"GPIO_25",  M0   ,GPI   , ACPI_D,  NA 
   ,   Level, Wake_Disabled, P_20K_H, Inverted,   SCI, NA   , NA, 
GPIO_PADBAR+0x00C8,  NORTH),//Feature:ODD MD/DA SCI  Net in Sch: 
SATA_ODD_DA_IN
   BXT_GPIO_PAD_CONF(L"GPIO_26",  M5   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D0,  NORTH),//SATA_LEDN
-  BXT_GPIO_PAD_CONF(L"GPIO_27",  M0   ,GPI   ,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA, NA   , NA, 
GPIO_PADBAR+0x00D8,  NORTH),//Feature:DFUNet in Sch: NFC_DFU
+  BXT_GPIO_PAD_CONF(L"GPIO_27",  M0   ,GPI   , GPIO_D,  NA 
   ,   Edge , Wake_Disabled, P_NONE,   NA,NA,TxDRxE, NA, 
GPIO_PADBAR+0x00D8,  NORTH),  
   BXT_GPIO_PAD_CONF(L"GPIO_28",  M2   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00E0,  NORTH),//   Net in Sch: 
ISH_GPIO10
   BXT_GPIO_PAD_CONF(L"GPIO_29",  M2   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00E8,  NORTH),//   Net in Sch: 
ISH_GPIO11
   BXT_GPIO_PAD_CONF(L"GPIO_30

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 3/4]Setup Change.

[zwei4]

Change default values of several setup options.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/PlatformSettings/PlatformSetupDxe/CpuPower.vfi | 4 ++--
 .../Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/CpuPower.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/CpuPower.vfi
index fe6ba6814..5d5f305f8 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/CpuPower.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/CpuPower.vfi
@@ -40,8 +40,8 @@ form formid = CPU_PWR_CONFIGURATION_FORM_ID,
   oneof varid  = Setup.TurboModeEnable,
 prompt = STRING_TOKEN(STR_PROCESSOR_TURBO_MODE),
 help = STRING_TOKEN(STR_PROCESSOR_TURBO_MODE_HELP),
-option text = STRING_TOKEN(STR_DISABLE),  value = 0, flags = 
RESET_REQUIRED;
-option text = STRING_TOKEN(STR_ENABLE),   value = 1, flags = MANUFACTURING 
|DEFAULT | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_DISABLE),  value = 0, flags = MANUFACTURING 
|DEFAULT | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_ENABLE),   value = 1, flags = 
RESET_REQUIRED;
   endoneof;
   endif;
 
diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
index f2a09c236..9290c607c 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -3010,8 +3010,8 @@ form formid = HDAUDIO_OPTIONS_FORM_ID,
   oneof varid   = Setup.ScHdAudioIoBufferOwnership,
 prompt  = STRING_TOKEN(STR_HDA_IO_BUFF_PROMPT),
 help= STRING_TOKEN(STR_HDA_IO_BUFF_HELP),
-option text = STRING_TOKEN(STR_HDA_HDALINK), value = 0, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
-option text = STRING_TOKEN(STR_HDA_I2S), value = 3, flags = RESET_REQUIRED;
+option text = STRING_TOKEN(STR_HDA_HDALINK), value = 0, flags =  
RESET_REQUIRED;
+option text = STRING_TOKEN(STR_HDA_I2S), value = 3, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
   endoneof;
 
   oneof varid   = Setup.ScHdAudioBiosCfgLockDown,
-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 4/4]VBT change for HDMI.

[zwei4]

VBT change to support HDMI audio.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/Binaries/Vbt/VbtBxtMipi.bin| Bin 5632 -> 5632 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtMipi.bin 
b/Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtMipi.bin
index 
21a89410ed949fc862534f3480e1f7c7be2114c7..cc6f2e509af449b0f2eb8adf9536cb1bc6d17702
 100644
GIT binary patch
delta 59
zcmZqBY0#M<#k_>UU~(X%@J53IM*d3)3<3fSuQ(VO6c`v77$>i16o-oafr>G0zRIXA
F0syn14M6|^

delta 59
zcmZqBY0#M<#XNz*U~(X%@J53IM*eFF3<3fSuQ(VO6c`v7*e9=N6o-oafr@c#zRIXA
F0syf<4M6|^

-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 2/4]RTC configuration.

[zwei4]

Cleanup RTC initialization code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/Library/PlatformSecLib/PlatformSecLib.c| 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformSecLib/PlatformSecLib.c 
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformSecLib/PlatformSecLib.c
index e4bee35fb..98e18d4b5 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PlatformSecLib/PlatformSecLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PlatformSecLib/PlatformSecLib.c
@@ -1,7 +1,7 @@
 /** @file
   Null instance of Sec Platform Hook Lib.
 
-  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -43,12 +43,6 @@ PlatformSecLibConstructor (
 
   DefaultsRestored = FALSE;
 
-  //
-  // Perform a checksum computation and verify if the checksum is correct. If 
the checksum is incorrect
-  // initialize all the CMOS location to their default values and recalculate 
the checksum.
-  //
-  InitCmos (FALSE, );
-
   return EFI_SUCCESS;
 }
 
-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 1/4]GPIO configuration.

[zwei4]

Change GPIO configuration for LED and buttons.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h   | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
index 88044926d..674617e84 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
@@ -63,12 +63,12 @@ BXT_GPIO_PAD_INIT  mBXT_GpioInitData_N[] =
   //
   //  Group Pin#:  pad_name,
PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,  Wake_Enabled 
,Term_H_L,Inverted, GPI_ROUT, IOSstae, IOSTerm, MMIO_Offset  ,Community
   //
-  BXT_GPIO_PAD_CONF(L"GPIO_0",   M0   ,GPO   ,  NA   ,   
HI,   NA  , Wake_Disabled,  P_5K_L ,   NA,NA,NA,  NA  , 
   GPIO_PADBAR+0x,  NORTH),
-  BXT_GPIO_PAD_CONF(L"GPIO_1",   M0   ,GPO   ,  NA   ,   
HI,   NA  , Wake_Disabled,  P_5K_L ,   NA,NA,NA,  NA  , 
   GPIO_PADBAR+0x0008,  NORTH),
-  BXT_GPIO_PAD_CONF(L"GPIO_2",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0010,  NORTH),
-  BXT_GPIO_PAD_CONF(L"GPIO_3",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0018,  NORTH),
-  BXT_GPIO_PAD_CONF(L"GPIO_4",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0020,  NORTH),
-  BXT_GPIO_PAD_CONF(L"GPIO_5",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0028,  NORTH),//Mux with CSE_PG based on the SW3 switch
+  BXT_GPIO_PAD_CONF(L"GPIO_0",   M0   ,GPO   ,  NA   ,   
HI,   NA  , Wake_Disabled,  P_5K_L ,   NA,NA,   NA,  
NA, GPIO_PADBAR+0x,  NORTH),
+  BXT_GPIO_PAD_CONF(L"GPIO_1",   M0   ,GPO   ,  NA   ,   
HI,   NA  , Wake_Disabled,  P_5K_L ,   NA,NA,   NA,  
NA, GPIO_PADBAR+0x0008,  NORTH),
+  BXT_GPIO_PAD_CONF(L"GPIO_2",   M0   ,GPO   ,  NA   ,   
LO,   NA  , Wake_Disabled, P_20K_L,NA,NA,   NA,  
NA, GPIO_PADBAR+0x0010,  NORTH),
+  BXT_GPIO_PAD_CONF(L"GPIO_3",   M0   ,GPO   ,  NA   ,   
LO,   NA  , Wake_Disabled, P_20K_L,NA,NA,   NA,  
NA, GPIO_PADBAR+0x0018,  NORTH),
+  BXT_GPIO_PAD_CONF(L"GPIO_4",   M0   ,GPO   ,  NA   ,   
LO,   NA  , Wake_Disabled, P_20K_L,NA,NA,   NA,  
NA, GPIO_PADBAR+0x0020,  NORTH),
+  BXT_GPIO_PAD_CONF(L"GPIO_5",   M1   ,NA,  NA   ,  NA 
   ,NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0028,  NORTH),//Mux with CSE_PG based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_6",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0030,  NORTH),//Mux with DISP1_RST_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_7",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0038,  NORTH),//Mux with DISP1_TOUCH_INT_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_8",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0040,  NORTH),//Mux with DISP1_TOUCH_RST_N based on the SW3 switch
@@ -81,15 +81,15 @@ BXT_GPIO_PAD_INIT  mBXT_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_15",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0078,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_16",  M0   ,GPI   ,  NA   ,  NA 
   ,   Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC,  HizRx0I ,DisPuPd, 
GPIO_PADBAR+0x0080,  NORTH),//Feature:SIM Card DetectNet in Sch: 
SIM_CON_CD1, falling edge trigger
   BXT_GPIO_PAD_CONF(L"GPIO_17",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_H,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x0088,  NORTH),//Feature: LB
-  BXT_GPIO_PAD_CONF(L"GPIO_18",  M1   ,NA, 

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Set I2S pins.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h  | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
index 10ca9325b..88044926d 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
@@ -183,15 +183,15 @@ BXT_GPIO_PAD_INIT  mBXT_GpioInitData_NW [] =
   BXT_GPIO_PAD_CONF(L"PMIC_I2C_SDA", M1   ,NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_1K_H ,NA   ,NA  ,IOS_Masked,   SAME,  
GPIO_PADBAR+0x0108,  NORTHWEST),
   BXT_GPIO_PAD_CONF(L"GPIO_74 AVS_I2S1_MCLK",M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0110,  NORTHWEST),//Feature:AVS_I2S1_MCLK
   BXT_GPIO_PAD_CONF(L"GPIO_75 AVS_I2S1_BCLK",M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0118,  NORTHWEST),//Feature:AVS_I2S1_BCLK
-  BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M0   ,GPO   ,GPIO_D,  HI  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,NA, NA,  
GPIO_PADBAR+0x0120,  NORTHWEST),//Feature:Wake
-  BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M0   ,GPI   , NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0128,  NORTHWEST),//Feature:LPE Hdr
-  BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M0   ,GPI   , NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0130,  NORTHWEST),//Feature:LPE Hdr
+  BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M1   ,NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,NA, NA,  
GPIO_PADBAR+0x0120,  NORTHWEST),//Feature:Wake
+  BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0128,  NORTHWEST),//Feature:LPE Hdr
+  BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0130,  NORTHWEST),//Feature:LPE Hdr
   BXT_GPIO_PAD_CONF(L"GPIO_79 AVS_M_CLK_A1", M2   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,   
GPIO_PADBAR+0x0138,  NORTHWEST),
   BXT_GPIO_PAD_CONF(L"GPIO_80 AVS_M_CLK_B1", M2   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,   
GPIO_PADBAR+0x0140,  NORTHWEST),
   BXT_GPIO_PAD_CONF(L"GPIO_81 AVS_M_DATA_1", M2   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,TxDRxE,  EnPd,   
GPIO_PADBAR+0x0148,  NORTHWEST),
   BXT_GPIO_PAD_CONF(L"GPIO_82 AVS_M_CLK_AB2",M2   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,   
GPIO_PADBAR+0x0150,  NORTHWEST),
   BXT_GPIO_PAD_CONF(L"GPIO_83 AVS_M_DATA_2", M1   ,NA, NA   ,  NA  
   ,   NA  ,Wake_Disabled, P_20K_L,NA   ,NA  ,TxDRxE,   EnPd,  
GPIO_PADBAR+0x0158,  NORTHWEST),
-  BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK",M2   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0160,  NORTHWEST),//Spare signal, set to GPI.  Net in Sch:HDA_RSTB
+  BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK",M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,NA,NA,   
GPIO_PADBAR+0x0160,  NORTHWEST),//Spare signal, set to GPI.  Net in Sch:HDA_RSTB
   BXT_GPIO_PAD_CONF(L"GPIO_85 AVS_I2S2_BCLK",M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,   
GPIO_PADBAR+0x0168,  NORTHWEST),
   BXT_GPIO_PAD_CONF(L"GPIO_86 AVS_I2S2_WS_SYNC", M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,   
GPIO_PADBAR+0x0170,  NORTHWEST),
   BXT_GPIO_PAD_CONF(L"GPIO_87 AVS_I2S2_SDI", M1   ,NA, NA   ,   NA 
   ,   NA  ,  Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,  SAME,   
GPIO_PADBAR+0x0178,  NORTHWEST),
-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Add code for WIFI/BT

[zwei4]

Add code for LBEE5KL1DX WIFI & Blue Tooth on FAB B.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../MinnowBoard3/BoardInitPostMem/BoardGpios.h |  6 +--
 .../Common/Acpi/AcpiTablesPCAT/Platform.asl|  2 +-
 .../PlatformSsdt/Bluetooth/LBEE5KL1DX.asl  | 41 +++
 .../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl   |  6 +--
 .../PlatformSsdt/Wifi/LBEE5KL1DX.asl   | 59 ++
 5 files changed, 106 insertions(+), 8 deletions(-)
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/LBEE5KL1DX.asl
 create mode 100644 
Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl

diff --git 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
index 692fbf700..10ca9325b 100644
--- 
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
+++ 
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
@@ -72,8 +72,8 @@ BXT_GPIO_PAD_INIT  mBXT_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_6",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0030,  NORTH),//Mux with DISP1_RST_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_7",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0038,  NORTH),//Mux with DISP1_TOUCH_INT_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_8",   M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,   HizRx0I,   SAME, 
GPIO_PADBAR+0x0040,  NORTH),//Mux with DISP1_TOUCH_RST_N based on the SW3 switch
-  BXT_GPIO_PAD_CONF(L"GPIO_9",   M1   ,NA   ,  NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA,   NA ,NA   , NA, 
GPIO_PADBAR+0x0048,  NORTH),//Feature: LB
-  BXT_GPIO_PAD_CONF(L"GPIO_10",  M0   ,GPI   ,  NA   ,  NA 
   ,   Level, Wake_Enabled , P_20K_L, Inverted,IOAPIC,   TxDRxE , NA, 
GPIO_PADBAR+0x0050,  NORTH),//Feature: LB 
+  BXT_GPIO_PAD_CONF(L"GPIO_9",   M1   ,NA,  NA,  
NA,   NA  , Wake_Disabled, P_20K_L,NA,   NA ,NA   , NA, 
GPIO_PADBAR+0x0048,  NORTH),//Feature: LB
+  BXT_GPIO_PAD_CONF(L"GPIO_10",  M0   ,GPO   , GPIO_D ,  
HI   ,   Level, Wake_Enabled , P_20K_L,NA, NA,   TxDRxE , NA, 
GPIO_PADBAR+0x0050,  NORTH),//Feature: LB 
   BXT_GPIO_PAD_CONF(L"GPIO_11",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0058,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_12",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Enabled , P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0060,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_13",  M1   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA ,NA   , NA, 
GPIO_PADBAR+0x0068,  NORTH),//Feature: LB
@@ -95,7 +95,7 @@ BXT_GPIO_PAD_INIT  mBXT_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_30",  M1   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00F0,  NORTH),//   Net in Sch: 
ISH_GPIO12
   BXT_GPIO_PAD_CONF(L"GPIO_31",  M5   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x00F8,  NORTH),//Feature: SUSCLK1
   BXT_GPIO_PAD_CONF(L"GPIO_32",  M5   ,NA,  NA   ,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,   NA,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x0100,  NORTH),//   Net in Sch: SUSCLK2
-  BXT_GPIO_PAD_CONF(L"GPIO_33",  M5   ,NA, NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x0108,  NORTH),//Feature: SUSCLK3
+  BXT_GPIO_PAD_CONF(L"GPIO_33",  M0   ,GPIO  , NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA,IOS_Masked,   SAME, 
GPIO_PADBAR+0x0108,  NORTH),//Feature: SUSCLK3
   BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M0   ,GPIO  , NA,  NA 
   ,   NA   , Wake_Disabled, P_20K_L,NA   ,NA, NA   , NA, 
GPIO_PADBAR+0x0110,  NORTH),
   BXT_GPIO_PAD_CONF(L"GPIO_35 PWM1", M0   ,GPIO  , NA,  NA 
   ,   NA   , Wake_Disabled, P_5K_H 

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Change eMMC device path.

[zwei4]

Signed-off-by: zwei4 <david@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
---
 .../Sdio/Dxe/MMC/MmcMediaDeviceDxe/MediaDeviceDriver.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MediaDeviceDriver.c
 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MediaDeviceDriver.c
index 7f5bd1137..8a27d2563 100644
--- 
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MediaDeviceDriver.c
+++ 
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MediaDeviceDriver.c
@@ -425,15 +425,15 @@ MediaDeviceDriverAllPartitionNotPresent (
 
 STATIC
 struct {
-  DEVICE_LOGICAL_UNIT_DEVICE_PATH  LogicalUnit;
+  CONTROLLER_DEVICE_PATHLogicalUnit;
   EFI_DEVICE_PATH_PROTOCOL  End;
 } EmmcDevPathTemplate = {
   {
 {
-  MESSAGING_DEVICE_PATH,
-  MSG_DEVICE_LOGICAL_UNIT_DP,
+  HARDWARE_DEVICE_PATH,
+  HW_CONTROLLER_DP,
   {
-sizeof (DEVICE_LOGICAL_UNIT_DEVICE_PATH),
+sizeof (CONTROLLER_DEVICE_PATH),
 0
   },
 },
@@ -494,7 +494,7 @@ MediaDeviceDriverInstallBlockIo (
 Partition->Handle = NULL;
 Partition->CardData = CardData;
 
-EmmcDevPathTemplate.LogicalUnit.Lun = Loop;
+EmmcDevPathTemplate.LogicalUnit.ControllerNumber = Loop;
 Partition->DevPath =
   AppendDevicePath (
 MainPath,
-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Change PcdMinimalValidYear.

[zwei4]

Change PcdMinimalValidYear to 2017.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc 
b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
index 7efcdb425..06fd97be8 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc
@@ -159,7 +159,10 @@
 
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf {
+ 
+  gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2017 
+  }
   MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
 
   
$(PLATFORM_PACKAGE_COMMON)/PlatformSettings/PlatformSetupDxe/PlatformSetupDxe.inf
 {
-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] VBT table change.

[zwei4]

Disabling  “Onboard LSPCON for HDMI 2.0” in VBT table

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 .../Common/Binaries/Vbt/VbtBxtMipi.bin| Bin 5632 -> 5632 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtMipi.bin 
b/Platform/BroxtonPlatformPkg/Common/Binaries/Vbt/VbtBxtMipi.bin
index 
fcbb6bfb2d68903b0520e847ace6e1171124dcb4..21a89410ed949fc862534f3480e1f7c7be2114c7
 100644
GIT binary patch
delta 25
gcmZqBY0#M<#XNz*U~(X%@J54HMn-|n+Zeq>0A9xi{r~^~

delta 25
gcmZqBY0#M<#oWVSFgcJ>c%wlpBcsUXZH!(b0A7~{{r~^~

-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] GCC build script change.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 BuildBIOS.sh | 2 +-
 Platform/BroxtonPlatformPkg/BuildIFWI.sh | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/BuildBIOS.sh b/BuildBIOS.sh
index ff815e9fa..fb67f04c2 100755
--- a/BuildBIOS.sh
+++ b/BuildBIOS.sh
@@ -27,5 +27,5 @@ export 
PACKAGES_PATH=$WORKSPACE:$WORKSPACE/Core:$WORKSPACE/Silicon/:$WORKSPACE/P
 
 make -C BaseTools
 
-. ./Platform/BroxtonPlatformPkg/BuildIFWI.sh APLI $Target_Flag
+bash ./Platform/BroxtonPlatformPkg/BuildIFWI.sh APLI $Target_Flag
 
diff --git a/Platform/BroxtonPlatformPkg/BuildIFWI.sh 
b/Platform/BroxtonPlatformPkg/BuildIFWI.sh
index a319bd3ee..c21904f2c 100755
--- a/Platform/BroxtonPlatformPkg/BuildIFWI.sh
+++ b/Platform/BroxtonPlatformPkg/BuildIFWI.sh
@@ -160,7 +160,7 @@ fi
 ## Build BIOS
 echo "=="
 echo "Build_IFWI:  Calling BIOS build Script..."
-sh Platform/BroxtonPlatformPkg/BuildBios.sh $Build_Flags $Platform_Type 
$Build_Target
+bash Platform/BroxtonPlatformPkg/BuildBios.sh $Build_Flags $Platform_Type 
$Build_Target
 
 echo
 echo Finished Building Process.
-- 
2.11.0.windows.1

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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] GCC build support.

[zwei4]

Change code which is not compatible with GCC.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 BuildBIOS.sh   |  5 
 Core/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf |  3 ++-
 Platform/BroxtonPlatformPkg/BiosId.env |  1 +
 Platform/BroxtonPlatformPkg/BuildBios.sh   |  4 ++--
 Platform/BroxtonPlatformPkg/BuildIFWI.sh   |  3 ++-
 .../SmramSaveInfoHandlerSmm.c  |  1 +
 .../Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c |  1 +
 .../Common/Library/PlatformSecLib/Ia32/SecEntry.S  |  1 +
 .../PlatformPostMemPei/PlatformInit.c  |  3 +++
 .../PlatformPostMemPei/PlatformInit.h  |  1 +
 .../PlatformPreMemPei/PlatformInit.h   |  1 +
 .../Common/PlatformSmm/Platform.c  | 12 ++
 .../Common/PlatformSmm/SmmPlatform.h   | 15 +++-
 .../BroxtonPlatformPkg/DefineAtBuildMacros.dsc | 15 
 .../BroxtonPlatformPkg/PlatformDsc/Components.dsc  | 12 ++
 Platform/BroxtonPlatformPkg/PlatformPkg.fdf| 28 --
 .../SouthCluster/ScInit/Smm/ScInitSmm.h|  3 +++
 .../SouthCluster/ScInit/Smm/ScPcieSmm.c|  1 +
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmm.h   |  3 +++
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmmCore.c   |  2 ++
 .../ScSmiDispatcher/Smm/ScSmmPeriodicTimer.c   |  1 +
 .../BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c | 10 
 .../BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c  |  9 +++
 23 files changed, 113 insertions(+), 22 deletions(-)

diff --git a/BuildBIOS.sh b/BuildBIOS.sh
index 0dece1f77..ff815e9fa 100755
--- a/BuildBIOS.sh
+++ b/BuildBIOS.sh
@@ -11,6 +11,11 @@
 Target_Flag=Release
 if [ "$1" == "Debug" ]; then
   Target_Flag=Debug
+  shift
+fi
+if [ "$1" == "Release" ]; then
+  Target_Flag=Release
+  shift
 fi
 
 echo $Target_Flag
diff --git a/Core/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf 
b/Core/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
index 9751ba1f0..4dfd82951 100644
--- a/Core/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+++ b/Core/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  MP Initialize Library instance for DXE driver.
 #
-#  Copyright (c) 2016, Intel Corporation. All rights reserved.
+#  Copyright (c) 2017, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
@@ -56,6 +56,7 @@
   UefiCpuLib
   UefiBootServicesTableLib
   DebugAgentLib
+  SynchronizationLib
 
 [Protocols]
   gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES
diff --git a/Platform/BroxtonPlatformPkg/BiosId.env 
b/Platform/BroxtonPlatformPkg/BiosId.env
index 2bf5bada9..18b4e0190 100644
--- a/Platform/BroxtonPlatformPkg/BiosId.env
+++ b/Platform/BroxtonPlatformPkg/BiosId.env
@@ -33,3 +33,4 @@ OEM_ID = X64
 BUILD_TYPE= D
 VERSION_MAJOR = 0064
 VERSION_MINOR = 01
+BOARD_EXT = X64
diff --git a/Platform/BroxtonPlatformPkg/BuildBios.sh 
b/Platform/BroxtonPlatformPkg/BuildBios.sh
index cadffc70d..fb6ac670d 100644
--- a/Platform/BroxtonPlatformPkg/BuildBios.sh
+++ b/Platform/BroxtonPlatformPkg/BuildBios.sh
@@ -317,7 +317,7 @@ cat SpiChunk1.bin IBBL.Fv IBB.Fv SpiChunk2.bin OBB.Fv 
NvStorage.Fv SpiChunk3.bin
 popd
 
 echo
-echo SPI IFWI location: 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/$BIOS_Name"_GCC".bin
+echo Check if SPI IFWI image is generated at below location:
+echo 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/$BIOS_Name"_GCC".bin
 echo
-echo  The EDKII BIOS build has successfully completed. 

 echo
diff --git a/Platform/BroxtonPlatformPkg/BuildIFWI.sh 
b/Platform/BroxtonPlatformPkg/BuildIFWI.sh
index bf91b5c18..a319bd3ee 100755
--- a/Platform/BroxtonPlatformPkg/BuildIFWI.sh
+++ b/Platform/BroxtonPlatformPkg/BuildIFWI.sh
@@ -163,6 +163,7 @@ echo "Build_IFWI:  Calling BIOS build Script..."
 sh Platform/BroxtonPlatformPkg/BuildBios.sh $Build_Flags $Platform_Type 
$Build_Target
 
 echo
-echo Finished Building BIOS.
+echo Finished Building Process.
+echo
 
 
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/S3/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
 
b/Platform/BroxtonPlatformPkg/Common/Features/S3/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
index ef45fdb6b..40655c2f6 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Features/S3/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
+++ 
b/Platform/BroxtonPlatformPkg/Common/Features/S3/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
@@ -45,6 +45,7 @@ CPU_INFO_PROTOCOL *mCpuInfoProtocol;
 
 **/
 EFI_STATUS
+EFIAPI
 SmramSaveInfoHandler (
   IN  EFI_

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Update GenBiosId

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 Platform/BroxtonPlatformPkg/BuildBios.sh|  12 
 .../Common/Tools/GenBiosId/GenBiosId| Bin 12236 -> 36128 bytes
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/BuildBios.sh 
b/Platform/BroxtonPlatformPkg/BuildBios.sh
index 88ea12f8c..cadffc70d 100644
--- a/Platform/BroxtonPlatformPkg/BuildBios.sh
+++ b/Platform/BroxtonPlatformPkg/BuildBios.sh
@@ -271,10 +271,6 @@ cp -f 
$WORKSPACE/Silicon/BroxtonSoC/BroxtonFspPkg/ApolloLakeFspBinPkg/FspBin/FSP
 cp -f 
$WORKSPACE/Silicon/BroxtonSoC/BroxtonFspPkg/ApolloLakeFspBinPkg/FspBin/FSP_M.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 cp -f 
$WORKSPACE/Silicon/BroxtonSoC/BroxtonFspPkg/ApolloLakeFspBinPkg/FspBin/FSP_S.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 
-
-grep "_PCD_VALUE_" 
$BUILD_PATH/IA32/BroxtonPlatformPkg/PlatformPei/PlatformPei/DEBUG/AutoGen.h > 
FlashMap.h
-
-
 #echo "Running fce..."
 ## Extract Hii data from build and store in HiiDefaultData.txt
 #wine PlatformTools/FCE/FCE.exe read -i $BUILD_PATH/FV/SOC.fd > 
$BUILD_PATH/FV/HiiDefaultData.txt 1>>EDK2.log 2>&1
@@ -292,7 +288,7 @@ cp $BUILD_PATH/FV/SOC.fd $BUILD_PATH/FV/Bxt"$Arch".fd
 VERSION_MAJOR=$(grep '^VERSION_MAJOR' Conf/BiosId.env | cut -d ' ' -f 3 | cut 
-c 1-4)
 VERSION_MINOR=$(grep '^VERSION_MINOR' Conf/BiosId.env | cut -d ' ' -f 3 | cut 
-c 1-2)
 
BIOS_Name="$BOARD_ID""$SV_String""$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"
-cp -f $BUILD_PATH/FV/Bxt"$Arch".fd  
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/$BIOS_Name.ROM
+
 cp -f $BUILD_PATH/FV/FVOBB.Fv  
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 cp -f $BUILD_PATH/FV/FVOBBX.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 cp -f $BUILD_PATH/FV/FVIBBR.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
@@ -302,7 +298,7 @@ cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/B_Stepping/Spi
 cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/B_Stepping/SpiChunk2.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/B_Stepping/SpiChunk3.bin
  $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
 cp -f 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Binaries/IFWI/B_Stepping/GCC/NvStorage.Fv
 $WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
-cp FlashMap.h $WORKSPACE/$BIOS_Name.map
+
 
 
 #
@@ -316,12 +312,12 @@ cat FVIBBM.Fv FSP_M.Fv > IBB.Fv
 
 cat FSP_S.Fv FVIBBR.Fv FVOBB.Fv FVOBBX.Fv > OBB.Fv
 
-cat SpiChunk1.bin IBBL.Fv IBB.Fv SpiChunk2.bin OBB.Fv NvStorage.Fv 
SpiChunk3.bin > MINNOWV3.X64.0063.IFWI.SPI.bin
+cat SpiChunk1.bin IBBL.Fv IBB.Fv SpiChunk2.bin OBB.Fv NvStorage.Fv 
SpiChunk3.bin > $BIOS_Name"_GCC".bin
 
 popd
 
 echo
-echo SPI IFWI location: 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/MINNOWV3.X64.0063.IFWI.SPI.bin
+echo SPI IFWI location: 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/$BIOS_Name"_GCC".bin
 echo
 echo  The EDKII BIOS build has successfully completed. 

 echo
diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/GenBiosId/GenBiosId 
b/Platform/BroxtonPlatformPkg/Common/Tools/GenBiosId/GenBiosId
index 
ef1578f2bcb8922905e0693035245c4329809aa7..dc9f28554594043fb2e981e96601f2851d19bb91
 100755
GIT binary patch
literal 36128
zcmdUY3w%`7)$cwtd7L3(CLsX=NEjXwup}fr!%HV2feA*4knm7(@|uv;WG0=N@DR~x
zK#hpS*0!{@gxcC#TU)Aa1zI6KuF}@F=(W~rzfZmvYf`GkN0nMN_rLbp>&(f?1pD2u
zzx(^$4RiKdYp>T{`*B`-pWIYlxx%4of|EmBDhNB5?vo_rD8!*Ii7HyLa0#EdSWFcu
zpd{nxlO>cJ5a;KWYR+}V=R}@_U$Mg=6gzwp;QS(kEI4NmDJOgJ<Wr!L$0iym=R$ZT
zf#k^7j9iH#uayAj<H;eU?ZhOLS02edBF#{8Gn5?Xr<7xybN#4p^s83+5$>Z*
zl*wZ}CtgZbuf-Y(_KlY)a-Re^ztbQK$eFGyo(p9es(XrKsrqrQP%*o;
zrGCM@*{zNFtu3LB?fKh_7vwLPR}c*s%#rmb{lvR+b@6!kW=~P%YU
z`>zP0sxdfBii16A$Sy>!oE#8c1U1#5=ib5IQ8?0?Mc%R3RQ5hJNKR
z^s-^-mBY|u!_b?Cq2~=lKQIivb{P5(K=

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] GCC build script change.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 BuildBIOS.sh |  8 ++-
 Platform/BroxtonPlatformPkg/BuildBios.sh | 86 
 Platform/BroxtonPlatformPkg/BuildIFWI.sh |  4 +-
 3 files changed, 52 insertions(+), 46 deletions(-)

diff --git a/BuildBIOS.sh b/BuildBIOS.sh
index 49a9e1b12..0dece1f77 100755
--- a/BuildBIOS.sh
+++ b/BuildBIOS.sh
@@ -8,6 +8,12 @@
 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
+Target_Flag=Release
+if [ "$1" == "Debug" ]; then
+  Target_Flag=Debug
+fi
+
+echo $Target_Flag
 
 export WORKSPACE=`pwd`
 export 
PACKAGES_PATH=$WORKSPACE:$WORKSPACE/Core:$WORKSPACE/Silicon/:$WORKSPACE/Platform:$WORKSPACE/Platform/BroxtonPlatformPkg:$WORKSPACE/Silicon/BroxtonSoC:$WORKSPACE/Platform/BroxtonPlatformPkg/Common
@@ -16,5 +22,5 @@ export 
PACKAGES_PATH=$WORKSPACE:$WORKSPACE/Core:$WORKSPACE/Silicon/:$WORKSPACE/P
 
 make -C BaseTools
 
-./Platform/BroxtonPlatformPkg/BuildIFWI.sh APLI Release
+. ./Platform/BroxtonPlatformPkg/BuildIFWI.sh APLI $Target_Flag
 
diff --git a/Platform/BroxtonPlatformPkg/BuildBios.sh 
b/Platform/BroxtonPlatformPkg/BuildBios.sh
index 3963c887a..88ea12f8c 100644
--- a/Platform/BroxtonPlatformPkg/BuildBios.sh
+++ b/Platform/BroxtonPlatformPkg/BuildBios.sh
@@ -76,19 +76,9 @@ cp $WORKSPACE/BaseTools/Conf/tools_def.template 
$WORKSPACE/Conf/tools_def.txt
 cp $WORKSPACE/BaseTools/Conf/build_rule.template $WORKSPACE/Conf/build_rule.txt
 
 
-## Get gcc version to determine which tool_def.template to use.
-## If gcc version is 4.6 or before, use default. If not, use new one.
-GCCVERSION=$(gcc --version | grep 'gcc' | grep '[0-9]' | cut -d ' ' -f 4 | cut 
-d '.' -f 2)
-if (($GCCVERSION > 6)); then
-  echo "GCC version is 4.7 or after"
-  TOOL_CHAIN_TAG=GCC47
-else
-  echo "Type 'gcc --version' to check version"
-  echo "Please update GCC version to 4.7 or later"
-  ErrorExit
-fi
 
-#make -C BaseTools > /dev/null
+
+TOOL_CHAIN_TAG=GCC5
 
 ## Define platform specific environment variables.
 PLATFORM_NAME=BroxtonPlatformPkg
@@ -268,28 +258,32 @@ build $Build_Flags
 ##**
 ## Post Build processing and cleanup
 ##**
+
+#
+# FSP Rebase and Split
+#
+#   0xFEF7A000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = 
$(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + 
$(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE)
+pushd  $WORKSPACE/Silicon/BroxtonSoC/BroxtonFspPkg/ApolloLakeFspBinPkg/FspBin
+python $WORKSPACE/Core/IntelFsp2Pkg/Tools/SplitFspBin.py rebase -f 
ApolloLakeFsp.fd -c m -b 0xFEF7A000 -o ./ -n FSP.fd
+python $WORKSPACE/Core/IntelFsp2Pkg/Tools/SplitFspBin.py split -f FSP.fd -o ./ 
-n FSP.Fv
+popd
+cp -f 
$WORKSPACE/Silicon/BroxtonSoC/BroxtonFspPkg/ApolloLakeFspBinPkg/FspBin/FSP_T.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Silicon/BroxtonSoC/BroxtonFspPkg/ApolloLakeFspBinPkg/FspBin/FSP_M.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+cp -f 
$WORKSPACE/Silicon/BroxtonSoC/BroxtonFspPkg/ApolloLakeFspBinPkg/FspBin/FSP_S.Fv 
$WORKSPACE/Platform/BroxtonPlatformPkg/Common/Tools/Stitch
+
+
 grep "_PCD_VALUE_" 
$BUILD_PATH/IA32/BroxtonPlatformPkg/PlatformPei/PlatformPei/DEBUG/AutoGen.h > 
FlashMap.h
 
+
 #echo "Running fce..."
 ## Extract Hii data from build and store in HiiDefaultData.txt
 #wine PlatformTools/FCE/FCE.exe read -i $BUILD_PATH/FV/SOC.fd > 
$BUILD_PATH/FV/HiiDefaultData.txt 1>>EDK2.log 2>&1
 
 ## copy the Setup variable to the SetupDefault variable and save changes to 
BxtXXX.fd
 #wine PlatformTools/FCE/FCE.exe mirror -i $BUILD_PATH/FV/SOC.fd -o 
$BUILD_PATH/FV/Bxt"$Arch".fd Setup SetupDefault 1>>EDK2.log 2>&1
-echo "Skip FCE tool..."
+#echo "Skip FCE tool..."
 cp $BUILD_PATH/FV/SOC.fd $BUILD_PATH/FV/Bxt"$Arch".fd
 
-##echo Running KeyEnroll...
-## RestrictedBegin
-##if /i not "$Platform_Type" == "$eNB_RVP" (
-##   call $PLATFORM_PACKAGE/Restricted/Internal/Tools/KeyEnroll/KeyEnroll.bat  
$BUILD_PATH  $BUILD_PATH/FV/Vlv"$Arch".fd 1>>EDK2.log 2>&1
-##) else if /i "$Platform_Type" == "$eNB_RVP" (
-##   call 
$PLATFORM_PACKAGE/Restricted/Internal/Tools/KeyEnroll/BBAY-KeyEnroll.bat  
$BUILD_PATH  $BUILD_PATH/FV/Vlv"$Arch".fd 1>>EDK2.log 2>&1
-##)
-##   if %ERRORLEVEL% NEQ 0 goto BldFail
-## RestrictedEnd
-echo Skip "KeyEnroll tool..."
-
 ## Set the Board_Id, Build_Type, Version_Major, and Version_Minor environment 
variables
 ##find /v "#" Conf\BiosId.env > ver_strings
 ##for /f "tokens=1,

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] GCC build script change.

[zwei4]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david@intel.com>
---
 BuildBIOS.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/BuildBIOS.sh b/BuildBIOS.sh
index cc1cb783c..49a9e1b12 100755
--- a/BuildBIOS.sh
+++ b/BuildBIOS.sh
@@ -14,5 +14,7 @@ export 
PACKAGES_PATH=$WORKSPACE:$WORKSPACE/Core:$WORKSPACE/Silicon/:$WORKSPACE/P
 
 . edksetup.sh
 
+make -C BaseTools
+
 ./Platform/BroxtonPlatformPkg/BuildIFWI.sh APLI Release
 
-- 
2.11.0.windows.1

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