Re: [edk2] [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment

2016-09-06 Thread Mudusuru, Giri P 
Thanks Jeff for adding comments to refer the SDM naming.

Reviewed series of patches.

Reviewed-by: Giri P Mudusuru  

> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, September 6, 2016 4:39 AM
> To: edk2-devel@lists.01.org
> Cc: Kinney, Michael D ; Tian, Feng
> ; Mudusuru, Giri P 
> Subject: [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM
> in comment
> 
> Cc: Michael Kinney 
> Cc: Feng Tian 
> Cc: Giri P Mudusuru 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jeff Fan 
> ---
>  UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51
> 
>  1 file changed, 51 insertions(+)
> 
> diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> index 6695b69..75f2dce 100644
> --- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> +++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> @@ -41,6 +41,7 @@
> 
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
>@endcode
> +  @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
>  **/
>  #define MSR_XEON_PHI_SMI_COUNT   0x0034
> 
> @@ -85,6 +86,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
>AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_PLATFORM_INFO is defined as
> MSR_PLATFORM_INFO in SDM.
>  **/
>  #define MSR_XEON_PHI_PLATFORM_INFO   0x00CE
> 
> @@ -151,6 +153,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
>AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as
> MSR_PKG_CST_CONFIG_CONTROL in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL  0x00E2
> 
> @@ -208,6 +211,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
>AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as
> MSR_PMG_IO_CAPTURE_BASE in SDM.
>  **/
>  #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x00E4
> 
> @@ -261,6 +265,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
>AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_FEATURE_CONFIG is defined as
> MSR_FEATURE_CONFIG in SDM.
>  **/
>  #define MSR_XEON_PHI_FEATURE_CONFIG  0x013C
> 
> @@ -313,6 +318,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
>AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as
> IA32_MISC_ENABLE in SDM.
>  **/
>  #define MSR_XEON_PHI_IA32_MISC_ENABLE0x01A0
> 
> @@ -402,6 +408,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
>AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as
> MSR_TEMPERATURE_TARGET in SDM.
>  **/
>  #define MSR_XEON_PHI_TEMPERATURE_TARGET  0x01A2
> 
> @@ -450,6 +457,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
>AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
>@endcode
> +  @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0
> in SDM.
>  **/
>  #define MSR_XEON_PHI_OFFCORE_RSP_0   0x01A6
> 
> @@ -468,6 +476,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
>AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
>@endcode
> +  @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1
> in SDM.
>  **/
>  #define MSR_XEON_PHI_OFFCORE_RSP_1   0x01A7
> 
> @@ -488,6 +497,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
>AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as
> MSR_TURBO_RATIO_LIMIT in SDM.
>  **/
>  #define MSR_XEON_PHI_TURBO_RATIO_LIMIT   0x01AD
> 
> @@ -612,6 +622,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
>AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
>@endcode
> +  @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
>  **/
>  #define MSR_XEON_PHI_LBR_SELECT  0x01C8
> 
> @@ -630,6 +641,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
>AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
>@endcode
> +  @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as
> MSR_LASTBRANCH_TOS in SDM.
>  **/
>  #define MSR_XEON_PHI_LASTBRANCH_TOS  0x01C9
> 
> @@ -647,6

[edk2] [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment

2016-09-06 Thread Jeff Fan 
Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51 
 1 file changed, 51 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 6695b69..75f2dce 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
   @endcode
+  @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_XEON_PHI_SMI_COUNT   0x0034
 
@@ -85,6 +86,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_XEON_PHI_PLATFORM_INFO   0x00CE
 
@@ -151,6 +153,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL  0x00E2
 
@@ -208,6 +211,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE 
in SDM.
 **/
 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x00E4
 
@@ -261,6 +265,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_XEON_PHI_FEATURE_CONFIG  0x013C
 
@@ -313,6 +318,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_XEON_PHI_IA32_MISC_ENABLE0x01A0
 
@@ -402,6 +408,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET 
in SDM.
 **/
 #define MSR_XEON_PHI_TEMPERATURE_TARGET  0x01A2
 
@@ -450,6 +457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_XEON_PHI_OFFCORE_RSP_0   0x01A6
 
@@ -468,6 +476,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 **/
 #define MSR_XEON_PHI_OFFCORE_RSP_1   0x01A7
 
@@ -488,6 +497,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
   AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in 
SDM.
 **/
 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT   0x01AD
 
@@ -612,6 +622,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
   AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
   @endcode
+  @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_XEON_PHI_LBR_SELECT  0x01C8
 
@@ -630,6 +641,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_XEON_PHI_LASTBRANCH_TOS  0x01C9
 
@@ -647,6 +659,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
   @endcode
+  @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_XEON_PHI_LER_FROM_LIP0x01DD
 
@@ -664,6 +677,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
   @endcode
+  @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_XEON_PHI_LER_TO_LIP  0x01DE
 
@@ -682,6 +696,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as