Re: Insulation Distance Between Circuitboard Layers (Safety)
I read in !emc-pstc that Doug McKean dmck...@corp.auspex.com wrote (in 004b01c24f87$66393680$cb3e3...@corp.auspex.com) about 'Insulation Distance Between Circuitboard Layers (Safety)' on Thu, 29 Aug 2002: FR4 has a dielectric factor of about 4.7. That simply means it's 4.7 times stronger than air. Therefore, *in theory* 1KV should in theory break down (1/4.7) mm of FR4, or 0.21 mm of FR4. One would need to distinguish VERY carefully between 'dielectric factor' as you have defined it and 'dielectric constant', which is also about 5 for FR4, I believe, but means something quite different. -- Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk Interested in professional sound reinforcement and distribution? Then go to http://www.isce.org.uk PLEASE do NOT copy news posts to me by E-MAIL! --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
Re: Insulation Distance Between Circuitboard Layers (Safety)
Something's bothering me about this discussion. It's not what people have said that I disagree. Maybe it's to be put in the FWIW department, 1MV breaks down 1 meter of air @ STP. It then follows that 1KV breaks down 1 mm of air. So, that's 1mm AIR/1KV. FR4 has a dielectric factor of about 4.7. That simply means it's 4.7 times stronger than air. Therefore, *in theory* 1KV should in theory break down (1/4.7) mm of FR4, or 0.21 mm of FR4. So, that's 0.21mm FR4/1KV. Now the circuit you're working with, primary or TNV, ... will decide the highest amount of stress during test. If it's going to be 2KVDC, then it's 0.4 mm. If it's going to be 3KVDC, 0.6mm. If it's going to be 8KV with some ESD test, then it's 1.6mm. That's between layers. Wanna put a safety factor of x2 in? The 2KV changes to 0.8mm. The 3KV changes to 1.2mm. Etc ... Something to consider. That's strictly between layers. I'd personally use the air breakdown rule of 1mm/1KV for planes in proximity to vias. And I would always work this out by myself before looking up the standard. And *ALWAYS*, check the standard. Regards, Doug McKean --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
Re: Insulation Distance Between Circuitboard Layers (Safety)
In a former job, I prevailed on them to follow (mostly) a rule of 100 mils clearance between any inner OR outer layer conductor, and conducting objects directly exposed to ESD. This, after a helpful layout designer decided to improve things by adding internal ESD traces interlaced with power and ground. (Don't do that.) However, the problems I've seen with clearance to surge and power-cross were associated with clearance to *vias* (and inside relays - a different matter) on the surface. The epoxy and FR4 material inside were more than sufficient to insulate against 2500 volt surge test voltages, even with 5 mil thickness. I believe the thread you recall was with respect to double insulation IN TRANSFORMERS. To prevent warping, keep the stackup symmetrical. Each layer should be matched by one the same thickness, on the other side. You will also need to insure copper is pretty evenly distributed. Cortland --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
Re: Insulation Distance Between Circuitboard Layers (Safety)
In a message dated 8/28/2002, Chris Maxwell writes: Can anyone see any pinholes in my reasoning? Can anyone recall the thread regarding multiple layers of thin insulation? Hi Chris: Wow, you are really pushing the limits with your board design. I work with EN 60950, and the clause in the third edition that is relevant to your question is 2.10.5.3, Printed Boards. The default requirement is 0.4 mm insulation thickness, but there are alternative methods listed in Table 2M. For instance, you can use three layers of sheet insulating material including pre-preg. You can even use two layers if you run a routine production test for electric strength. I don't know how much of this is relevant to EN 61010-1, but hopefully the info on 60950 will be useful in pursuing this. Joe Randolph Telecom Design Consultant Randolph Telecom, Inc. 781-721-2848 http://www.randolph-telecom.com
