Re: [flashrom] Error Reading BIOS on Dell Optiplex 745

2010-01-08 Thread Anthony DeRosa
carldani,

Requested output below.  Invalid opcode?  The MX25L8005 datasheet says the
part supports opcode 0x03, read data.

-Anthony


ubu...@ubuntu:~/flashrom$ sudo ./flashrom -c MX25L8005 -V -r backup.bin

flashrom v0.9.1-r837
No coreboot table found.
Found chipset Intel ICH8/ICH8R, enabling flash write...
0xfff8/0xffb8 FWH IDSEL: 0x0
0xfff0/0xffb0 FWH IDSEL: 0x0
0xffe8/0xffa8 FWH IDSEL: 0x1
0xffe0/0xffa0 FWH IDSEL: 0x1
0xffd8/0xff98 FWH IDSEL: 0x2
0xffd0/0xff90 FWH IDSEL: 0x2
0xffc8/0xff88 FWH IDSEL: 0x3
0xffc0/0xff80 FWH IDSEL: 0x3
0xff70/0xff30 FWH IDSEL: 0x4
0xff60/0xff20 FWH IDSEL: 0x5
0xff50/0xff10 FWH IDSEL: 0x6
0xff40/0xff00 FWH IDSEL: 0x7
0xfff8/0xffb8 FWH decode enabled
0xfff0/0xffb0 FWH decode enabled
0xffe8/0xffa8 FWH decode disabled
0xffe0/0xffa0 FWH decode disabled
0xffd8/0xff98 FWH decode disabled
0xffd0/0xff90 FWH decode disabled
0xffc8/0xff88 FWH decode disabled
0xffc0/0xff80 FWH decode disabled
0xff70/0xff30 FWH decode disabled
0xff60/0xff20 FWH decode disabled
0xff50/0xff10 FWH decode disabled
0xff40/0xff00 FWH decode disabled
Maximum FWH chip size: 0x10 bytes
BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
tried to set 0xdc to 0x3 on ICH8/ICH8R failed (WARNING ONLY)

Root Complex Register Block address = 0xfeda8000
GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
Top Swap : not enabled
SPIBAR = 0xfeda8000 + 0x3020
0x04: 0xa000 (HSFS)
FLOCKDN 1, FDV 0, FDOPSS 1, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0
0x50: 0x0202 (FRAP)
BMWAG 0, BMRAG 0, BRWA 2, BRRA 2
0x54: 0x1fff (FREG0)
0x58: 0x1fff (FREG1)
0x5C: 0x1fff (FREG2)
0x60: 0x1fff (FREG3)
0x64: 0x (FREG4)
0x74: 0x (PR0)
0x78: 0x (PR1)
0x7C: 0x (PR2)
0x80: 0x (PR3)
0x84: 0x (PR4)
0x90: 0x00416004 (SSFS, SSFC)
0x94: 0x0606 (PREOP)
0x96: 0x4fc8 (OPTYPE)
0x98: 0x029fabab (OPMENU)
0x9C: 0x010502d8 (OPMENU+4)
0xA0: 0x (BBAR)
0xB0: 0x (FDOC)
WARNING: SPI Configuration Lockdown activated.
Generating OPCODES... done
SPI Read Configuration: prefetching disabled, caching enabled, FAILED!
This chipset supports the following protocols: FWH,SPI.
Calibrating delay loop... 504M loops per second, 100 myus = 197 us. OK.
Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x14.
probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Chip status register is 00
Chip status register: Status Register Write Disable (SRWD) is not set
Chip status register: Bit 6 is not set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Found chip Macronix MX25L8005 (1024 KB, SPI) at physical address
0xfff0.
===
This flash part has status UNTESTED for operations: ERASE
Please email a report to flashrom@flashrom.org if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested. Thanks for
your help!
===
Reading flash... Invalid OPCODE 0x03
done.



On Fri, Jan 8, 2010 at 4:22 AM, Carl-Daniel Hailfinger 
c-d.hailfinger.devel.2...@gmx.net wrote:

 Hi Anthony,

 On 07.01.2010 22:55, Anthony DeRosa wrote:
  The bios version I am currently using (2.6.2) is no longer available for
  download, but i happen to have a copy of it attached (raw ROM file).

 I have stripped the ROM image from your mail before it could reach the
 list because we don't have distribution rights for ROM images.


  Below is the rest of the info. you asked for.
 
 
  ubu...@ubuntu:~/flashrom$ sudo ./flashrom -r backup.bin
  flashrom v0.9.1-r837
  No coreboot table found.
  Found chipset Intel ICH8/ICH8R, enabling flash write... WARNING: SPI
  Configuration Lockdown activated.
  FAILED!
  This chipset supports the following protocols: FWH,SPI.
  Calibrating delay loop... OK.
  Found chip Macronix MX25L8005 (1024 KB, SPI) at physical address
 0xfff0.
  Reading flash... done.
  ubu...@ubuntu:~/flashrom$ hexdump backup.bin
  000        
  *
  010
 

 Ouch.


  dmidecode snippet (bonus!)
 
  Handle 0x, DMI type 0, 24 bytes
  BIOS Information
  Vendor: Dell Inc.
  Version: 2.6.2
  ROM Size: 1024 kB
  BIOS Revision: 2.6
 
 
 
 
  flashrom -V
 
  flashrom v0.9.1-r837
  No coreboot table found.
  Found chipset Intel ICH8/ICH8R, enabling flash write...
  0xfff8/0xffb8 FWH IDSEL: 0x0
  

Re: [flashrom] Error Reading BIOS on Dell Optiplex 745

2010-01-08 Thread Adrian Glaubitz
Hi Anthony,

On Fri, Jan 8, 2010 at 4:16 PM, Anthony DeRosa anth...@ransomed.us wrote:
 carldani,

 Requested output below.  Invalid opcode?  The MX25L8005 datasheet says the
 part supports opcode 0x03, read data.

IIRC the newer Dell OptiPlex series have a special way for flashing
the BIOS. You use a Dell-provided utility to copy the new BIOS image
into a special (non-volatile?) memory, then reboot the machine. Once
it reboots, it will automatically start to flash. The same technique
is used by IBM with most of their Thinkpad models, I don't know
whether this still applies to the more recent Lenovo models.

Btw: I think Dell also provides flash utilities for Linux (since they
ship machines with Ubuntu), but my memory might deceive me ;).


Adrian

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Re: [flashrom] Error Reading BIOS on Dell Optiplex 745

2010-01-08 Thread ron minnich
On Fri, Jan 8, 2010 at 8:32 AM, Adrian Glaubitz
adrian.glaub...@googlemail.com wrote:

 IIRC the newer Dell OptiPlex series have a special way for flashing
 the BIOS. You use a Dell-provided utility to copy the new BIOS image
 into a special (non-volatile?) memory, then reboot the machine. Once
 it reboots, it will automatically start to flash.

wow, how ... special. So you have no visibility into the reflash
process and no idea of its progress.

This is the default mode for many new BIOSes, I understand, since so
many of them are EFI at the core. It's not an improvement for the
customer, but it's what the vendors are going to provide. It's very
disappointing.

ron

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Re: [flashrom] Error Reading BIOS on Dell Optiplex 745

2010-01-08 Thread Carl-Daniel Hailfinger
On 08.01.2010 18:06, ron minnich wrote:
 On Fri, Jan 8, 2010 at 8:32 AM, Adrian Glaubitz wrote
 IIRC the newer Dell OptiPlex series have a special way for flashing
 the BIOS. You use a Dell-provided utility to copy the new BIOS image
 into a special (non-volatile?) memory, then reboot the machine. Once
 it reboots, it will automatically start to flash.
 

 wow, how ... special. So you have no visibility into the reflash
 process and no idea of its progress.
   

I think the special Dell stuff has existed for years. Back then, they
probably didn't know (or didn't care) about flashrom, and nowadays this
flashing procedure is actually a reliability advantage over the
alternative: Windows flashers. Flashing from a multitasking OS
(especially if not done as kernel driver) means there are no guarantees
whatsoever about timing, reliability, crash resistance and other stuff
you'd care about.
You can find boatloads of reports from people who bricked their machines
by flashing under Windows, and because people are too unskilled (or
unwilling) to run DOS based flashers, it all burns down to doing the
reflashing from the BIOS.


 This is the default mode for many new BIOSes, I understand, since so
 many of them are EFI at the core. It's not an improvement for the
 customer, but it's what the vendors are going to provide. It's very
 disappointing.
   

I think this is only somewhat related to EFI (first time you can easily
add executables to the BIOS). Most of it is about reliability concerns.
And if you look at vendors like Sun, it seems there is an unwillingness
to perform host-based flashing at all, instead they opt to run the
reflashing process from the Management Engine.

I see a flashrom driver for such Management Engines on the horizon
(unless they are not providing direct hardware access), but since I
don't own the hardware, this is pretty low priority for me.

Now if we could motivate at least one board vendor to ship (or offer for
download) flashrom CDs for reflashing their boards, we'd win big time.

Regards,
Carl-Daniel

-- 
Developer quote of the year:
We are juggling too many chainsaws and flaming arrows and tigers.


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Re: [flashrom] Error Reading BIOS on Dell Optiplex 745

2010-01-08 Thread Carl-Daniel Hailfinger
On 08.01.2010 16:16, Anthony DeRosa wrote:
 Requested output below.  Invalid opcode?  The MX25L8005 datasheet says the
 part supports opcode 0x03, read data.
   

As discussed on IRC, the READ opcode 0x03 is not supported by your
chipset configuration.


 ubu...@ubuntu:~/flashrom$ sudo ./flashrom -c MX25L8005 -V -r backup.bin

 flashrom v0.9.1-r837
 No coreboot table found.
 Found chipset Intel ICH8/ICH8R, enabling flash write...
 [...]
 BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
 GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
 FLOCKDN 1, FDV 0, FDOPSS 1, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0
 0x98: 0x029fabab (OPMENU)
 0x9C: 0x010502d8 (OPMENU+4)
 [...]
 WARNING: SPI Configuration Lockdown activated.
 Generating OPCODES... done
 SPI Read Configuration: prefetching disabled, caching enabled, FAILED!
 This chipset supports the following protocols: FWH,SPI.
 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x14.
 probe_spi_rdid_generic: id1 0xc2, id2 0x2014
 Chip status register is 00
 Chip status register: Status Register Write Disable (SRWD) is not set
 Chip status register: Bit 6 is not set
 Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
 Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
 Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
 Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
 Chip status register: Write Enable Latch (WEL) is not set
 Chip status register: Write In Progress (WIP/BUSY) is not set
 Found chip Macronix MX25L8005 (1024 KB, SPI) at physical address
 0xfff0.
 Reading flash... Invalid OPCODE 0x03
 done.
   

This is a bug, though. If we encounter an Invalid opcode error during
read, we should NOT write that file at all, and we should NOT report
success. Will fix.

Regards,
Carl-Daniel

-- 
Developer quote of the year:
We are juggling too many chainsaws and flaming arrows and tigers.


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Re: [flashrom] Error Reading BIOS on Dell Optiplex 745

2010-01-08 Thread Joerg Mayer
On Fri, Jan 08, 2010 at 09:06:52AM -0800, ron minnich wrote:
 On Fri, Jan 8, 2010 at 8:32 AM, Adrian Glaubitz
 adrian.glaub...@googlemail.com wrote:
 
  IIRC the newer Dell OptiPlex series have a special way for flashing
  the BIOS. You use a Dell-provided utility to copy the new BIOS image
  into a special (non-volatile?) memory, then reboot the machine. Once
  it reboots, it will automatically start to flash.
 
 wow, how ... special. So you have no visibility into the reflash
 process and no idea of its progress.
 
 This is the default mode for many new BIOSes, I understand, since so
 many of them are EFI at the core. It's not an improvement for the
 customer, but it's what the vendors are going to provide. It's very
 disappointing.

I see one very good reason to try this (apart from several negative ones):
Malware. If malware manages to program itself into the BIOS, then it will
control what the OS sees - and has possibility to thwart any and all
attempts at detecting/repairing such a program. If the BIOS only accepts
signed BIOS updates for reflashing, then this could prevent that kind
of malware.

 Ciao
 Joerg
-- 
Joerg Mayer   jma...@loplof.de
We are stuck with technology when what we really want is just stuff that
works. Some say that should read Microsoft instead of technology.

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Re: [flashrom] Error Reading BIOS on Dell Optiplex 745

2010-01-07 Thread Carl-Daniel Hailfinger
Hi Anthony,

On 07.01.2010 22:55, Anthony DeRosa wrote:
 The bios version I am currently using (2.6.2) is no longer available for
 download, but i happen to have a copy of it attached (raw ROM file).

I have stripped the ROM image from your mail before it could reach the
list because we don't have distribution rights for ROM images.


 Below is the rest of the info. you asked for.


 ubu...@ubuntu:~/flashrom$ sudo ./flashrom -r backup.bin
 flashrom v0.9.1-r837
 No coreboot table found.
 Found chipset Intel ICH8/ICH8R, enabling flash write... WARNING: SPI
 Configuration Lockdown activated.
 FAILED!
 This chipset supports the following protocols: FWH,SPI.
 Calibrating delay loop... OK.
 Found chip Macronix MX25L8005 (1024 KB, SPI) at physical address 0xfff0.
 Reading flash... done.
 ubu...@ubuntu:~/flashrom$ hexdump backup.bin
 000        
 *
 010
   

Ouch.


 dmidecode snippet (bonus!)

 Handle 0x, DMI type 0, 24 bytes
 BIOS Information
 Vendor: Dell Inc.
 Version: 2.6.2
 ROM Size: 1024 kB
 BIOS Revision: 2.6




 flashrom -V

 flashrom v0.9.1-r837
 No coreboot table found.
 Found chipset Intel ICH8/ICH8R, enabling flash write...
 0xfff8/0xffb8 FWH IDSEL: 0x0
 0xfff0/0xffb0 FWH IDSEL: 0x0
 0xffe8/0xffa8 FWH IDSEL: 0x1
 0xffe0/0xffa0 FWH IDSEL: 0x1
 0xffd8/0xff98 FWH IDSEL: 0x2
 0xffd0/0xff90 FWH IDSEL: 0x2
 0xffc8/0xff88 FWH IDSEL: 0x3
 0xffc0/0xff80 FWH IDSEL: 0x3
 0xff70/0xff30 FWH IDSEL: 0x4
 0xff60/0xff20 FWH IDSEL: 0x5
 0xff50/0xff10 FWH IDSEL: 0x6
 0xff40/0xff00 FWH IDSEL: 0x7
 0xfff8/0xffb8 FWH decode enabled
 0xfff0/0xffb0 FWH decode enabled
 0xffe8/0xffa8 FWH decode disabled
 0xffe0/0xffa0 FWH decode disabled
 0xffd8/0xff98 FWH decode disabled
 0xffd0/0xff90 FWH decode disabled
 0xffc8/0xff88 FWH decode disabled
 0xffc0/0xff80 FWH decode disabled
 0xff70/0xff30 FWH decode disabled
 0xff60/0xff20 FWH decode disabled
 0xff50/0xff10 FWH decode disabled
 0xff40/0xff00 FWH decode disabled
 Maximum FWH chip size: 0x10 bytes
 BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
 tried to set 0xdc to 0x3 on ICH8/ICH8R failed (WARNING ONLY)
   

OK, write to LPC flash is disabled. That's not good.

 Root Complex Register Block address = 0xfeda8000
 GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
   

Then again, your BIOS lives on SPI, so you do not care about LPC.

 Top Swap : not enabled
 SPIBAR = 0xfeda8000 + 0x3020
 0x04: 0xa000 (HSFS)
 FLOCKDN 1, FDV 0, FDOPSS 1, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0
   

FLOCKDN=1 is not that good and means we can't modify the opcodes in the
chipset.
FDV=0 is good.


 0x50: 0x0202 (FRAP)
 BMWAG 0, BMRAG 0, BRWA 2, BRRA 2
 0x54: 0x1fff (FREG0)
 0x58: 0x1fff (FREG1)
 0x5C: 0x1fff (FREG2)
 0x60: 0x1fff (FREG3)
 0x64: 0x (FREG4)
   

Totally weird region configuration.


 0x74: 0x (PR0)
 0x78: 0x (PR1)
 0x7C: 0x (PR2)
 0x80: 0x (PR3)
 0x84: 0x (PR4)
 0x90: 0x00422004 (SSFS, SSFC)
 0x94: 0x0606 (PREOP)
 0x96: 0x4fc8 (OPTYPE)
 0x98: 0x029fabab (OPMENU)
 0x9C: 0x010502d8 (OPMENU+4)
 0xA0: 0x (BBAR)
 0xB0: 0x (FDOC)
 WARNING: SPI Configuration Lockdown activated.
   

Good. flashrom detects the chipset lockdown.


 Generating OPCODES... done
 SPI Read Configuration: prefetching disabled, caching enabled, FAILED!
 This chipset supports the following protocols: FWH,SPI.
 Calibrating delay loop... 512M loops per second, 100 myus = 200 us. OK.
 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x14. 
 probe_spi_rdid_generic: id1 0xc2, id2 0x2014
 Chip status register is 00
 Chip status register: Status Register Write Disable (SRWD) is not set
 Chip status register: Bit 6 is not set
 Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
 Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
 Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
 Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
 Chip status register: Write Enable Latch (WEL) is not set
 Chip status register: Write In Progress (WIP/BUSY) is not set
 Found chip Macronix MX25L8005 (1024 KB, SPI) at physical address 0xfff0.
 No operations were specified.
   

Hm. can you run
flashrom -c MX25L8005 -V -r backup.bin
and mail us about the output? There should be at least one transaction
error or somesuch. We should NOT create a dump file on error. I have a
patch for that in the queue.

Regards,
Carl-Daniel

-- 
Developer quote of the year:
We are juggling too many chainsaws and flaming arrows and tigers.


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