subject:"Re\: \[flashrom\] When flashrom support Intel Purley platform Lewisburg PCH\?"

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-09-01 Thread David Hendricks

Hi Sandy,

I updated the flashrom code to better take into account differences with 
Lewisburg, including the number of FREG registers as you point out: 
https://review.coreboot.org/#/c/20922/


When you have a chance, please and try again (using -V). You can copy+paste 
your result here for convenience: https://paste.flashrom.org/.

Flashrom -- File upload serivce<https://paste.flashrom.org/>
paste.flashrom.org
Welcome to flashrom's file upload service Please post only 
flashrom/coreboot/seabios or other firmware related contents. Post a new paste 
You can either post text ...




From: flashrom <flashrom-boun...@flashrom.org> on behalf of Sandy Zhang 
<sanzh...@celestica.com>
Sent: Monday, August 14, 2017 4:36:00 AM
To: David Hendricks
Cc: flashrom@flashrom.org
Subject: Re: [flashrom] When flashrom support Intel Purley platform Lewisburg 
PCH?

Hi David,

Lewisburg PCH defines sixty SPI regions, but from the code in ichspi.c, I find 
it defines only 10 regions, is this the reason about only 10 regions was 
described in the log file?

code as below: (num_freg define the spi regions)

int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
{
...
...
...
/* Moving registers / bits */
if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
num_freg = 10;
num_pr = 6;
reg_pr0 = PCH100_REG_FPR0;
swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
swseq_data.reg_preop = PCH100_REG_PREOP;
swseq_data.reg_optype = PCH100_REG_OPTYPE;
swseq_data.reg_opmenu = PCH100_REG_OPMENU;
hwseq_data.addr_mask = PCH100_FADDR_FLA;
hwseq_data.only_4k = true;
hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
}

2017-08-14 14:23 GMT+08:00 David Hendricks 
<david.hendri...@gmail.com<mailto:david.hendri...@gmail.com>>:
On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang 
<sanzh...@celestica.com<mailto:sanzh...@celestica.com>> wrote:
Hi David,

I'm inline.

I don't see your responses. Did you intend to reply to my comments?


2017-08-14 9:17 GMT+08:00 David Hendricks 
<david.hendri...@gmail.com<mailto:david.hendri...@gmail.com>>:
Hi Sandy,

Responses in-line.

On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang 
<sanzh...@celestica.com<mailto:sanzh...@celestica.com>> wrote:
Hi David,

 Sorry, I have a doubt about the range outside, from the binary map, we can 
find the Spare 3 Region size is 0x00FF - 0xFF + 1 = 0x1, and the 
binary size map to this range is also 0x1, they are equal, why outside was 
happened? and can you tell me how to update the binary region's range defined 
in the flash description?

Start (hex)End (hex)Length (hex)Area Name
-----
...
...

00FF   00FF 0001Spare 3 Region
0100   01FF 0100BIOS Region

The Flash Region registers (BIOS_FREGn) define the boundaries of each region. I 
don't see where 0xa36000-0xff is covered:
0x54: 0x FREG0: Flash Descriptor region (0x-0x0fff) is 
read-write.
0x58: 0x1fff1000 FREG1: BIOS region (0x0100-0x01ff) is read-write.
0x5C: 0x0a250003 FREG2: Management Engine region (0x3000-0x00a25fff) is 
read-write.
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x1000-0x2fff) is 
read-write.
0x64: 0x7fff FREG4: Platform Data region is unused.
0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is read-write.
0x6C: 0x7fff FREG6: unknown region is unused.
0x70: 0x7fff FREG7: unknown region is unused.
0x74: 0x7fff FREG8: unknown region is unused.
0x78: 0x7fff FREG9: unknown region is unused.

You might also need to set permissions for the "BIOS" master (i.e. flashrom 
running on the CPU) via BRWA and BRRA in the FRACC register.

 In addition, from flash log file(please see attachment 
"Lewisburg_W25Q256.log"), it shows:
Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) 
mapped at physical address 0x.
 but, my flash chip is "Winbond flash chip", what do you think about this?

This is OK. Intel hardware sequencing is an "opaque" programmer interface since 
flashrom does not directly send NOR flash commands via a raw SPI interface. For 
hardware sequencing we use the FCYCLE field as our command interface to the SPI 
flash.




--

Best Regard!

Sandy Zhang ( 张立康)
BIOS Engineer
Global Design Service
Celestica(Shanghai) R Center, China
Mail: sanzh...@celestica.com<mailto:viter...@celestica.com>
Mobile: (+86)15965353952<tel:+86%20159%206535%203952>
Phone: (+86)021-61006028-7623




--

Best Regard!

Sandy Zhang ( 张立康)
BIOS Engineer
Global Design Service
Celestica(Shanghai) R Center, China
Mail: sanzh...@celestica.com<mailto:viter...@celestica.com>
Mobile: (+86)15965353952
Phone: (+86)021-61006028-7623
___
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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-14 Thread Sandy Zhang

Hi David,

Lewisburg PCH defines sixty SPI regions, but from the code in ichspi.c, I
find it defines only 10 regions, is this the reason about only 10 regions
was described in the log file?

code as below: (num_freg define the spi regions)

int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
{
...
...
...
/* Moving registers / bits */
if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
num_freg = 10;
num_pr = 6;
reg_pr0 = PCH100_REG_FPR0;
swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
swseq_data.reg_preop = PCH100_REG_PREOP;
swseq_data.reg_optype = PCH100_REG_OPTYPE;
swseq_data.reg_opmenu = PCH100_REG_OPMENU;
hwseq_data.addr_mask = PCH100_FADDR_FLA;
hwseq_data.only_4k = true;
hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
}

2017-08-14 14:23 GMT+08:00 David Hendricks :

> On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> I'm inline.
>>
>
> I don't see your responses. Did you intend to reply to my comments?
>
>
>>
>> 2017-08-14 9:17 GMT+08:00 David Hendricks :
>>
>>> Hi Sandy,
>>>
>>> Responses in-line.
>>>
>>> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang 
>>> wrote:
>>>
 Hi David,

  Sorry, I have a doubt about the range outside, from the binary
 map, we can find the Spare 3 Region size is 0x00FF - 0xFF + 1 =
 0x1, and the binary size map to this range is also 0x1, they are
 equal, why outside was happened? and can you tell me how to update the
 binary region's range defined in the flash description?

 Start (hex)End (hex)Length (hex)Area Name
 -----
 ...
 ...
 
 00FF   00FF 0001Spare 3 Region
 0100   01FF 0100BIOS Region

>>>
>>> The Flash Region registers (BIOS_FREGn) define the boundaries of each
>>> region. I don't see where 0xa36000-0xff is covered:
>>> 0x54: 0x FREG0: Flash Descriptor region (0x-0x0fff)
>>> is read-write.
>>> 0x58: 0x1fff1000 FREG1: BIOS region (0x0100-0x01ff) is
>>> read-write.
>>> 0x5C: 0x0a250003 FREG2: Management Engine region (0x3000-0x00a25fff)
>>> is read-write.
>>> 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x1000-0x2fff)
>>> is read-write.
>>> 0x64: 0x7fff FREG4: Platform Data region is unused.
>>> 0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is
>>> read-write.
>>> 0x6C: 0x7fff FREG6: unknown region is unused.
>>> 0x70: 0x7fff FREG7: unknown region is unused.
>>> 0x74: 0x7fff FREG8: unknown region is unused.
>>> 0x78: 0x7fff FREG9: unknown region is unused.
>>>
>>> You might also need to set permissions for the "BIOS" master (i.e.
>>> flashrom running on the CPU) via BRWA and BRRA in the FRACC register.
>>>
>>>  In addition, from flash log file(please see attachment
 "Lewisburg_W25Q256.log"), it shows:
 Found Programmer flash chip "Opaque flash chip" (32768 kB,
 Programmer-specific) mapped at physical address 0x.
  but, my flash chip is "Winbond flash chip", what do you think about
 this?

>>>
>>> This is OK. Intel hardware sequencing is an "opaque" programmer
>>> interface since flashrom does not directly send NOR flash commands via a
>>> raw SPI interface. For hardware sequencing we use the FCYCLE field as our
>>> command interface to the SPI flash.
>>>
>>>
>>
>>
>> --
>>
>> *Best Regard!*
>>
>> *Sandy Zhang (* 张立康*)*
>> *BIOS Engineer*
>> *Global Design Service*
>> *Celestica(Shanghai) R Center, China*
>> *Mail: sanzh...@celestica.com *
>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>> *Phone: (+86)021-61006028-7623*
>>
>
>


-- 

*Best Regard!*

*Sandy Zhang (* 张立康*)*
*BIOS Engineer*
*Global Design Service*
*Celestica(Shanghai) R Center, China*
*Mail: sanzh...@celestica.com *
*Mobile: (+86)15965353952*
*Phone: (+86)021-61006028-7623*
___
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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-14 Thread Sandy Zhang

Hi David,

About set permissions for the "BIOS" master via BRWA and BRRA in the FRACC
register, do you mean modify the below location by FITC.exe? if yes, I have
changed the "Host CPU/BIOS Write Access" & "Host CPU/BIOS Read Access"'s value
to 0x to enable all the sixty region's access, but the result has not
any change.



[image: 内嵌图片 2]

2017-08-14 14:23 GMT+08:00 David Hendricks :

> On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> I'm inline.
>>
>
> I don't see your responses. Did you intend to reply to my comments?
>
>
>>
>> 2017-08-14 9:17 GMT+08:00 David Hendricks :
>>
>>> Hi Sandy,
>>>
>>> Responses in-line.
>>>
>>> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang 
>>> wrote:
>>>
 Hi David,

  Sorry, I have a doubt about the range outside, from the binary
 map, we can find the Spare 3 Region size is 0x00FF - 0xFF + 1 =
 0x1, and the binary size map to this range is also 0x1, they are
 equal, why outside was happened? and can you tell me how to update the
 binary region's range defined in the flash description?

 Start (hex)End (hex)Length (hex)Area Name
 -----
 ...
 ...
 
 00FF   00FF 0001Spare 3 Region
 0100   01FF 0100BIOS Region

>>>
>>> The Flash Region registers (BIOS_FREGn) define the boundaries of each
>>> region. I don't see where 0xa36000-0xff is covered:
>>> 0x54: 0x FREG0: Flash Descriptor region (0x-0x0fff)
>>> is read-write.
>>> 0x58: 0x1fff1000 FREG1: BIOS region (0x0100-0x01ff) is
>>> read-write.
>>> 0x5C: 0x0a250003 FREG2: Management Engine region (0x3000-0x00a25fff)
>>> is read-write.
>>> 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x1000-0x2fff)
>>> is read-write.
>>> 0x64: 0x7fff FREG4: Platform Data region is unused.
>>> 0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is
>>> read-write.
>>> 0x6C: 0x7fff FREG6: unknown region is unused.
>>> 0x70: 0x7fff FREG7: unknown region is unused.
>>> 0x74: 0x7fff FREG8: unknown region is unused.
>>> 0x78: 0x7fff FREG9: unknown region is unused.
>>>
>>> You might also need to set permissions for the "BIOS" master (i.e.
>>> flashrom running on the CPU) via BRWA and BRRA in the FRACC register.
>>>
>>>  In addition, from flash log file(please see attachment
 "Lewisburg_W25Q256.log"), it shows:
 Found Programmer flash chip "Opaque flash chip" (32768 kB,
 Programmer-specific) mapped at physical address 0x.
  but, my flash chip is "Winbond flash chip", what do you think about
 this?

>>>
>>> This is OK. Intel hardware sequencing is an "opaque" programmer
>>> interface since flashrom does not directly send NOR flash commands via a
>>> raw SPI interface. For hardware sequencing we use the FCYCLE field as our
>>> command interface to the SPI flash.
>>>
>>>
>>
>>
>> --
>>
>> *Best Regard!*
>>
>> *Sandy Zhang (* 张立康*)*
>> *BIOS Engineer*
>> *Global Design Service*
>> *Celestica(Shanghai) R Center, China*
>> *Mail: sanzh...@celestica.com *
>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>> *Phone: (+86)021-61006028-7623*
>>
>
>


-- 

*Best Regard!*

*Sandy Zhang (* 张立康*)*
*BIOS Engineer*
*Global Design Service*
*Celestica(Shanghai) R Center, China*
*Mail: sanzh...@celestica.com *
*Mobile: (+86)15965353952*
*Phone: (+86)021-61006028-7623*
___
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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-14 Thread David Hendricks

On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang  wrote:

> Hi David,
>
> I'm inline.
>

I don't see your responses. Did you intend to reply to my comments?


>
> 2017-08-14 9:17 GMT+08:00 David Hendricks :
>
>> Hi Sandy,
>>
>> Responses in-line.
>>
>> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang 
>> wrote:
>>
>>> Hi David,
>>>
>>>  Sorry, I have a doubt about the range outside, from the binary map,
>>> we can find the Spare 3 Region size is 0x00FF - 0xFF + 1 = 0x1,
>>> and the binary size map to this range is also 0x1, they are equal, why
>>> outside was happened? and can you tell me how to update the binary region's
>>> range defined in the flash description?
>>>
>>> Start (hex)End (hex)Length (hex)Area Name
>>> -----
>>> ...
>>> ...
>>> 
>>> 00FF   00FF 0001Spare 3 Region
>>> 0100   01FF 0100BIOS Region
>>>
>>
>> The Flash Region registers (BIOS_FREGn) define the boundaries of each
>> region. I don't see where 0xa36000-0xff is covered:
>> 0x54: 0x FREG0: Flash Descriptor region (0x-0x0fff)
>> is read-write.
>> 0x58: 0x1fff1000 FREG1: BIOS region (0x0100-0x01ff) is read-write.
>> 0x5C: 0x0a250003 FREG2: Management Engine region (0x3000-0x00a25fff)
>> is read-write.
>> 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x1000-0x2fff)
>> is read-write.
>> 0x64: 0x7fff FREG4: Platform Data region is unused.
>> 0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is
>> read-write.
>> 0x6C: 0x7fff FREG6: unknown region is unused.
>> 0x70: 0x7fff FREG7: unknown region is unused.
>> 0x74: 0x7fff FREG8: unknown region is unused.
>> 0x78: 0x7fff FREG9: unknown region is unused.
>>
>> You might also need to set permissions for the "BIOS" master (i.e.
>> flashrom running on the CPU) via BRWA and BRRA in the FRACC register.
>>
>>  In addition, from flash log file(please see attachment
>>> "Lewisburg_W25Q256.log"), it shows:
>>> Found Programmer flash chip "Opaque flash chip" (32768 kB,
>>> Programmer-specific) mapped at physical address 0x.
>>>  but, my flash chip is "Winbond flash chip", what do you think about
>>> this?
>>>
>>
>> This is OK. Intel hardware sequencing is an "opaque" programmer interface
>> since flashrom does not directly send NOR flash commands via a raw SPI
>> interface. For hardware sequencing we use the FCYCLE field as our command
>> interface to the SPI flash.
>>
>>
>
>
> --
>
> *Best Regard!*
>
> *Sandy Zhang (* 张立康*)*
> *BIOS Engineer*
> *Global Design Service*
> *Celestica(Shanghai) R Center, China*
> *Mail: sanzh...@celestica.com *
> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
> *Phone: (+86)021-61006028-7623*
>
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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-13 Thread Sandy Zhang

Hi David,

I'm inline.

2017-08-14 9:17 GMT+08:00 David Hendricks :

> Hi Sandy,
>
> Responses in-line.
>
> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>>  Sorry, I have a doubt about the range outside, from the binary map,
>> we can find the Spare 3 Region size is 0x00FF - 0xFF + 1 = 0x1,
>> and the binary size map to this range is also 0x1, they are equal, why
>> outside was happened? and can you tell me how to update the binary region's
>> range defined in the flash description?
>>
>> Start (hex)End (hex)Length (hex)Area Name
>> -----
>> ...
>> ...
>> 
>> 00FF   00FF 0001Spare 3 Region
>> 0100   01FF 0100BIOS Region
>>
>
> The Flash Region registers (BIOS_FREGn) define the boundaries of each
> region. I don't see where 0xa36000-0xff is covered:
> 0x54: 0x FREG0: Flash Descriptor region (0x-0x0fff) is
> read-write.
> 0x58: 0x1fff1000 FREG1: BIOS region (0x0100-0x01ff) is read-write.
> 0x5C: 0x0a250003 FREG2: Management Engine region (0x3000-0x00a25fff)
> is read-write.
> 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x1000-0x2fff) is
> read-write.
> 0x64: 0x7fff FREG4: Platform Data region is unused.
> 0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is
> read-write.
> 0x6C: 0x7fff FREG6: unknown region is unused.
> 0x70: 0x7fff FREG7: unknown region is unused.
> 0x74: 0x7fff FREG8: unknown region is unused.
> 0x78: 0x7fff FREG9: unknown region is unused.
>
> You might also need to set permissions for the "BIOS" master (i.e.
> flashrom running on the CPU) via BRWA and BRRA in the FRACC register.
>
>  In addition, from flash log file(please see attachment
>> "Lewisburg_W25Q256.log"), it shows:
>> Found Programmer flash chip "Opaque flash chip" (32768 kB,
>> Programmer-specific) mapped at physical address 0x.
>>  but, my flash chip is "Winbond flash chip", what do you think about
>> this?
>>
>
> This is OK. Intel hardware sequencing is an "opaque" programmer interface
> since flashrom does not directly send NOR flash commands via a raw SPI
> interface. For hardware sequencing we use the FCYCLE field as our command
> interface to the SPI flash.
>
>


-- 

*Best Regard!*

*Sandy Zhang (* 张立康*)*
*BIOS Engineer*
*Global Design Service*
*Celestica(Shanghai) R Center, China*
*Mail: sanzh...@celestica.com *
*Mobile: (+86)15965353952*
*Phone: (+86)021-61006028-7623*
___
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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-13 Thread David Hendricks

Hi Sandy,

Responses in-line.

On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang  wrote:

> Hi David,
>
>  Sorry, I have a doubt about the range outside, from the binary map,
> we can find the Spare 3 Region size is 0x00FF - 0xFF + 1 = 0x1,
> and the binary size map to this range is also 0x1, they are equal, why
> outside was happened? and can you tell me how to update the binary region's
> range defined in the flash description?
>
> Start (hex)End (hex)Length (hex)Area Name
> -----
> ...
> ...
> 
> 00FF   00FF 0001Spare 3 Region
> 0100   01FF 0100BIOS Region
>

The Flash Region registers (BIOS_FREGn) define the boundaries of each
region. I don't see where 0xa36000-0xff is covered:
0x54: 0x FREG0: Flash Descriptor region (0x-0x0fff) is
read-write.
0x58: 0x1fff1000 FREG1: BIOS region (0x0100-0x01ff) is read-write.
0x5C: 0x0a250003 FREG2: Management Engine region (0x3000-0x00a25fff) is
read-write.
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x1000-0x2fff) is
read-write.
0x64: 0x7fff FREG4: Platform Data region is unused.
0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is
read-write.
0x6C: 0x7fff FREG6: unknown region is unused.
0x70: 0x7fff FREG7: unknown region is unused.
0x74: 0x7fff FREG8: unknown region is unused.
0x78: 0x7fff FREG9: unknown region is unused.

You might also need to set permissions for the "BIOS" master (i.e. flashrom
running on the CPU) via BRWA and BRRA in the FRACC register.

 In addition, from flash log file(please see attachment
> "Lewisburg_W25Q256.log"), it shows:
> Found Programmer flash chip "Opaque flash chip" (32768 kB,
> Programmer-specific) mapped at physical address 0x.
>  but, my flash chip is "Winbond flash chip", what do you think about this?
>

This is OK. Intel hardware sequencing is an "opaque" programmer interface
since flashrom does not directly send NOR flash commands via a raw SPI
interface. For hardware sequencing we use the FCYCLE field as our command
interface to the SPI flash.
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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-10 Thread David Hendricks

Hi Sandy,
That range is outside of what you have defined in your flash descriptor.
Can you update your flash descriptor to include it?

On Thu, Aug 10, 2017 at 4:43 AM, Sandy Zhang  wrote:

> Hi David,
>
> I have used your program to verify,  but it still can't flash, it prompts
> "Transaction error between offset 0x00ff and 0x00ff003f  (= 0x00ff003f
> + 63)"!
>
>
>
>
> 2017-08-10 15:29 GMT+08:00 David Hendricks :
>
>> Hi Sandy,
>> Recent Intel PCHs use hardware sequencing which abstracts a lot of
>> details about the chip. So we don't actually need flashrom to explicitly
>> support the W25Q256.
>>
>> Here is a tarball based on the latest sources from git:
>> https://drive.google.com/file/d/0Bz3WBh8gVeIuSlJYZ2c1bS1LdGc
>> /view?usp=sharing
>>
>> It has the following patches applied:
>> https://review.coreboot.org/#/c/20922/ : chispet_enable: Add PCI IDs for
>> C620-series PCHs
>> https://review.coreboot.org/#/c/20936/ : ich_descriptors: Modify limits
>> for C620/Lewisburg PCH
>> https://review.coreboot.org/#/c/20937/ : ich_descriptors: Fix off-by-one
>> error
>>
>> Let us know if it works for you.
>>
>>
>> On Wed, Aug 9, 2017 at 8:04 PM, Sandy Zhang 
>> wrote:
>>
>>> Hi David,
>>>
>>> I have get the package from the web, but I can't find the code about
>>> "25Q256" in flashchip.c, so, maybe this will lead to flash fail.
>>>
>>> 2017-08-09 15:11 GMT+08:00 Sandy Zhang :
>>>
 Hi David,

 Yes, My system's ISA/LPC vendor id and device id is 8086:a1c6,
 In fact, I can't access the clone https://review.coreboot.
 org/flashrom.git,  I attempt to add the patch to flashrom-0.9.9, but I
 found the difference is a bit big between these files, I'm very hard to add
 the patch completely, so, could you send the latest package to me to try
 this on my system?
 Thanks for your great help!






 2017-08-09 14:04 GMT+08:00 David Hendricks :

> Hi Sandy,
> What is the result of `lspci -nn | grep ISA` on your system? I
> uploaded a patch for Lewisburg PCI IDs here: https://review.coreboot.
> org/#/c/20922/
>
> I have tested Lewisburg PCH + W25Q256xxx and it seems to work. Let me
> know if you need any help applying the patch and testing it out on your
> system.
>
>
> On Tue, Aug 8, 2017 at 7:09 PM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> Do you know whether the configuration "Lewisburg PCH + W25Q256xxx
>> SPI" has been tested with the flashrom? thank you!
>>
>>
>>
>>
>>
>>
>> 2017-08-08 3:55 GMT+08:00 David Hendricks 
>> :
>>
>>> Hi Sandy,
>>> Correct - The PCH will not allow us to write anything to regions
>>> which are not defined in the flash descriptor. You could add those 
>>> regions
>>> to the "BIOS" region if you wish to update them from your host OS. The 
>>> SPI
>>> Programming Guide for your PCH (Lewisburg?) should also have info about
>>> additional regions which you may set up in the flash descriptor.
>>>
>>> "EW" means erase and write, "S" means skip (content does not need to
>>> change), "E" means erase only, "W" means write only
>>>
>>> On Mon, Aug 7, 2017 at 12:50 AM, Sandy Zhang >> > wrote:
>>>
 Hi David,

 It seems that the below 2 regions are "write denied":

 00A26000   00A35FFF 0001DER #1 Region
 00A36000   00FE 005BA00010 Gbe A Region

 By the way, can you tell me what is the other parament "EW", "S"
 and "E" meana? thank you!




 2017-08-07 13:02 GMT+08:00 David Hendricks <
 david.hendri...@gmail.com>:

> Hi Sandy,
> It might not have done what you expect. The error is because
> offsets 0xa26000-0xff are not defined in the flash descriptor, so 
> the
> PCH gives us an error when flashrom attempts to update it. ":WD" next 
> to
> the offsets in the log means "write denied".
>
> If you wish to update that region of the ROM then you must change
> your flash descriptor to include it and set the permissions to enable 
> read
> and write.
>
>
> On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang <
> sanzh...@celestica.com> wrote:
>
>> Hi David,
>>
>> Attachment is the log file when flash bios into Winbond 32MB SPI
>> rom,  could you help to check if it's updated sucessfully? thank you!
>>
>> 2017-08-05 10:45 GMT+08:00 Sandy Zhang :
>>
>>> Hi David,
>>>
>>> Thank you very much,

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-10 Thread Sandy Zhang

Hi David,

I have used your program to verify,  but it still can't flash, it prompts
"Transaction error between offset 0x00ff and 0x00ff003f  (= 0x00ff003f
+ 63)"!




2017-08-10 15:29 GMT+08:00 David Hendricks :

> Hi Sandy,
> Recent Intel PCHs use hardware sequencing which abstracts a lot of details
> about the chip. So we don't actually need flashrom to explicitly support
> the W25Q256.
>
> Here is a tarball based on the latest sources from git:
> https://drive.google.com/file/d/0Bz3WBh8gVeIuSlJYZ2c1bS1LdGc/
> view?usp=sharing
>
> It has the following patches applied:
> https://review.coreboot.org/#/c/20922/ : chispet_enable: Add PCI IDs for
> C620-series PCHs
> https://review.coreboot.org/#/c/20936/ : ich_descriptors: Modify limits
> for C620/Lewisburg PCH
> https://review.coreboot.org/#/c/20937/ : ich_descriptors: Fix off-by-one
> error
>
> Let us know if it works for you.
>
>
> On Wed, Aug 9, 2017 at 8:04 PM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> I have get the package from the web, but I can't find the code about
>> "25Q256" in flashchip.c, so, maybe this will lead to flash fail.
>>
>> 2017-08-09 15:11 GMT+08:00 Sandy Zhang :
>>
>>> Hi David,
>>>
>>> Yes, My system's ISA/LPC vendor id and device id is 8086:a1c6,
>>> In fact, I can't access the clone https://review.coreboot.
>>> org/flashrom.git,  I attempt to add the patch to flashrom-0.9.9, but I
>>> found the difference is a bit big between these files, I'm very hard to add
>>> the patch completely, so, could you send the latest package to me to try
>>> this on my system?
>>> Thanks for your great help!
>>>
>>>
>>>
>>>
>>>
>>>
>>> 2017-08-09 14:04 GMT+08:00 David Hendricks :
>>>
 Hi Sandy,
 What is the result of `lspci -nn | grep ISA` on your system? I uploaded
 a patch for Lewisburg PCI IDs here: https://review.coreboot.
 org/#/c/20922/

 I have tested Lewisburg PCH + W25Q256xxx and it seems to work. Let me
 know if you need any help applying the patch and testing it out on your
 system.


 On Tue, Aug 8, 2017 at 7:09 PM, Sandy Zhang 
 wrote:

> Hi David,
>
> Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI"
> has been tested with the flashrom? thank you!
>
>
>
>
>
>
> 2017-08-08 3:55 GMT+08:00 David Hendricks :
>
>> Hi Sandy,
>> Correct - The PCH will not allow us to write anything to regions
>> which are not defined in the flash descriptor. You could add those 
>> regions
>> to the "BIOS" region if you wish to update them from your host OS. The 
>> SPI
>> Programming Guide for your PCH (Lewisburg?) should also have info about
>> additional regions which you may set up in the flash descriptor.
>>
>> "EW" means erase and write, "S" means skip (content does not need to
>> change), "E" means erase only, "W" means write only
>>
>> On Mon, Aug 7, 2017 at 12:50 AM, Sandy Zhang 
>> wrote:
>>
>>> Hi David,
>>>
>>> It seems that the below 2 regions are "write denied":
>>>
>>> 00A26000   00A35FFF 0001DER #1 Region
>>> 00A36000   00FE 005BA00010 Gbe A Region
>>>
>>> By the way, can you tell me what is the other parament "EW", "S" and
>>> "E" meana? thank you!
>>>
>>>
>>>
>>>
>>> 2017-08-07 13:02 GMT+08:00 David Hendricks <
>>> david.hendri...@gmail.com>:
>>>
 Hi Sandy,
 It might not have done what you expect. The error is because
 offsets 0xa26000-0xff are not defined in the flash descriptor, so 
 the
 PCH gives us an error when flashrom attempts to update it. ":WD" next 
 to
 the offsets in the log means "write denied".

 If you wish to update that region of the ROM then you must change
 your flash descriptor to include it and set the permissions to enable 
 read
 and write.


 On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang  wrote:

> Hi David,
>
> Attachment is the log file when flash bios into Winbond 32MB SPI
> rom,  could you help to check if it's updated sucessfully? thank you!
>
> 2017-08-05 10:45 GMT+08:00 Sandy Zhang :
>
>> Hi David,
>>
>> Thank you very much, I will try to add the patch to flashrom-0.9.9,
>> As a BIOS engineer, it is a bit difficult for me to complete this.
>> Do you know when will make it into a release tarball?
>>
>>
>>
>> BR
>> Sandy
>>
>> 2017-08-05 0:05 GMT+08:00 David Hendricks <
>> david.hendri...@gmail.com>:
>>

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-10 Thread David Hendricks

Hi Sandy,
Recent Intel PCHs use hardware sequencing which abstracts a lot of details
about the chip. So we don't actually need flashrom to explicitly support
the W25Q256.

Here is a tarball based on the latest sources from git:
https://drive.google.com/file/d/0Bz3WBh8gVeIuSlJYZ2c1bS1LdGc/view?usp=sharing

It has the following patches applied:
https://review.coreboot.org/#/c/20922/ : chispet_enable: Add PCI IDs for
C620-series PCHs
https://review.coreboot.org/#/c/20936/ : ich_descriptors: Modify limits for
C620/Lewisburg PCH
https://review.coreboot.org/#/c/20937/ : ich_descriptors: Fix off-by-one
error

Let us know if it works for you.


On Wed, Aug 9, 2017 at 8:04 PM, Sandy Zhang  wrote:

> Hi David,
>
> I have get the package from the web, but I can't find the code about
> "25Q256" in flashchip.c, so, maybe this will lead to flash fail.
>
> 2017-08-09 15:11 GMT+08:00 Sandy Zhang :
>
>> Hi David,
>>
>> Yes, My system's ISA/LPC vendor id and device id is 8086:a1c6,
>> In fact, I can't access the clone https://review.coreboot.
>> org/flashrom.git,  I attempt to add the patch to flashrom-0.9.9, but I
>> found the difference is a bit big between these files, I'm very hard to add
>> the patch completely, so, could you send the latest package to me to try
>> this on my system?
>> Thanks for your great help!
>>
>>
>>
>>
>>
>>
>> 2017-08-09 14:04 GMT+08:00 David Hendricks :
>>
>>> Hi Sandy,
>>> What is the result of `lspci -nn | grep ISA` on your system? I uploaded
>>> a patch for Lewisburg PCI IDs here: https://review.coreboot.
>>> org/#/c/20922/
>>>
>>> I have tested Lewisburg PCH + W25Q256xxx and it seems to work. Let me
>>> know if you need any help applying the patch and testing it out on your
>>> system.
>>>
>>>
>>> On Tue, Aug 8, 2017 at 7:09 PM, Sandy Zhang 
>>> wrote:
>>>
 Hi David,

 Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI"
 has been tested with the flashrom? thank you!






 2017-08-08 3:55 GMT+08:00 David Hendricks :

> Hi Sandy,
> Correct - The PCH will not allow us to write anything to regions which
> are not defined in the flash descriptor. You could add those regions to 
> the
> "BIOS" region if you wish to update them from your host OS. The SPI
> Programming Guide for your PCH (Lewisburg?) should also have info about
> additional regions which you may set up in the flash descriptor.
>
> "EW" means erase and write, "S" means skip (content does not need to
> change), "E" means erase only, "W" means write only
>
> On Mon, Aug 7, 2017 at 12:50 AM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> It seems that the below 2 regions are "write denied":
>>
>> 00A26000   00A35FFF 0001DER #1 Region
>> 00A36000   00FE 005BA00010 Gbe A Region
>>
>> By the way, can you tell me what is the other parament "EW", "S" and
>> "E" meana? thank you!
>>
>>
>>
>>
>> 2017-08-07 13:02 GMT+08:00 David Hendricks > >:
>>
>>> Hi Sandy,
>>> It might not have done what you expect. The error is because offsets
>>> 0xa26000-0xff are not defined in the flash descriptor, so the PCH 
>>> gives
>>> us an error when flashrom attempts to update it. ":WD" next to the 
>>> offsets
>>> in the log means "write denied".
>>>
>>> If you wish to update that region of the ROM then you must change
>>> your flash descriptor to include it and set the permissions to enable 
>>> read
>>> and write.
>>>
>>>
>>> On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang 
>>> wrote:
>>>
 Hi David,

 Attachment is the log file when flash bios into Winbond 32MB SPI
 rom,  could you help to check if it's updated sucessfully? thank you!

 2017-08-05 10:45 GMT+08:00 Sandy Zhang :

> Hi David,
>
> Thank you very much, I will try to add the patch to flashrom-0.9.9,
> As a BIOS engineer, it is a bit difficult for me to complete this.
> Do you know when will make it into a release tarball?
>
>
>
> BR
> Sandy
>
> 2017-08-05 0:05 GMT+08:00 David Hendricks <
> david.hendri...@gmail.com>:
>
>> On Aug 3, 2017 11:51 PM, "Sandy Zhang" 
>> wrote:
>>
>>> Hi David,
>>>
>>> Thanks for your reply, can you tell me where to download the
>>> flash package like "flashrom-0.9.9.tar" which is downloaded from the
>>> address ''https://www.flashrom.org/Downloads;?  thank you!
>>>
>>
>> The Skylake

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-09 Thread Sandy Zhang

Hi David,

I have get the package from the web, but I can't find the code about
"25Q256" in flashchip.c, so, maybe this will lead to flash fail.

2017-08-09 15:11 GMT+08:00 Sandy Zhang :

> Hi David,
>
> Yes, My system's ISA/LPC vendor id and device id is 8086:a1c6,
> In fact, I can't access the clone https://review.coreboot.org/flashrom.git,
>  I attempt to add the patch to flashrom-0.9.9, but I found the difference
> is a bit big between these files, I'm very hard to add the
> patch completely, so, could you send the latest package to me to try this
> on my system?
> Thanks for your great help!
>
>
>
>
>
>
> 2017-08-09 14:04 GMT+08:00 David Hendricks :
>
>> Hi Sandy,
>> What is the result of `lspci -nn | grep ISA` on your system? I uploaded a
>> patch for Lewisburg PCI IDs here: https://review.coreboot.org/#/c/20922/
>>
>> I have tested Lewisburg PCH + W25Q256xxx and it seems to work. Let me
>> know if you need any help applying the patch and testing it out on your
>> system.
>>
>>
>> On Tue, Aug 8, 2017 at 7:09 PM, Sandy Zhang 
>> wrote:
>>
>>> Hi David,
>>>
>>> Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI"
>>> has been tested with the flashrom? thank you!
>>>
>>>
>>>
>>>
>>>
>>>
>>> 2017-08-08 3:55 GMT+08:00 David Hendricks :
>>>
 Hi Sandy,
 Correct - The PCH will not allow us to write anything to regions which
 are not defined in the flash descriptor. You could add those regions to the
 "BIOS" region if you wish to update them from your host OS. The SPI
 Programming Guide for your PCH (Lewisburg?) should also have info about
 additional regions which you may set up in the flash descriptor.

 "EW" means erase and write, "S" means skip (content does not need to
 change), "E" means erase only, "W" means write only

 On Mon, Aug 7, 2017 at 12:50 AM, Sandy Zhang 
 wrote:

> Hi David,
>
> It seems that the below 2 regions are "write denied":
>
> 00A26000   00A35FFF 0001DER #1 Region
> 00A36000   00FE 005BA00010 Gbe A Region
>
> By the way, can you tell me what is the other parament "EW", "S" and
> "E" meana? thank you!
>
>
>
>
> 2017-08-07 13:02 GMT+08:00 David Hendricks 
> :
>
>> Hi Sandy,
>> It might not have done what you expect. The error is because offsets
>> 0xa26000-0xff are not defined in the flash descriptor, so the PCH 
>> gives
>> us an error when flashrom attempts to update it. ":WD" next to the 
>> offsets
>> in the log means "write denied".
>>
>> If you wish to update that region of the ROM then you must change
>> your flash descriptor to include it and set the permissions to enable 
>> read
>> and write.
>>
>>
>> On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang 
>> wrote:
>>
>>> Hi David,
>>>
>>> Attachment is the log file when flash bios into Winbond 32MB SPI
>>> rom,  could you help to check if it's updated sucessfully? thank you!
>>>
>>> 2017-08-05 10:45 GMT+08:00 Sandy Zhang :
>>>
 Hi David,

 Thank you very much, I will try to add the patch to flashrom-0.9.9,
 As a BIOS engineer, it is a bit difficult for me to complete this.
 Do you know when will make it into a release tarball?



 BR
 Sandy

 2017-08-05 0:05 GMT+08:00 David Hendricks <
 david.hendri...@gmail.com>:

> On Aug 3, 2017 11:51 PM, "Sandy Zhang" 
> wrote:
>
>> Hi David,
>>
>> Thanks for your reply, can you tell me where to download the
>> flash package like "flashrom-0.9.9.tar" which is downloaded from the
>> address ''https://www.flashrom.org/Downloads;?  thank you!
>>
>
> The Skylake patches have not made it into a release tarball yet.
> Can you try using the git sources from https://review.coreboot.o
> rg/cgit/flashrom.git? E.g:
>
> git clone https://review.coreboot.org/flashrom.git
> git checkout origin/staging
> make
>
>
>>
>>
>>
>> BR
>> Sandy
>>
>> 2017-08-04 14:35 GMT+08:00 David Hendricks <
>> david.hendri...@gmail.com>:
>>
>>> Hi Sandy,
>>> Skylake support was recently merged:
>>> https://review.coreboot.org/18973
>>>
>>> However you may need to add your PCH PCI ID. What does `lspci
>>> -nn | grep LPC` show on your test system?
>>>
>>> And yes, a 32MB ROM should work fine.
>>>
>>> On Mon, Jul 31, 2017 at 4:11 AM,

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-09 Thread Sandy Zhang

Hi David,

Yes, My system's ISA/LPC vendor id and device id is 8086:a1c6,
In fact, I can't access the clone https://review.coreboot.org/flashrom.git,
 I attempt to add the patch to flashrom-0.9.9, but I found the difference
is a bit big between these files, I'm very hard to add the
patch completely, so, could you send the latest package to me to try this
on my system?
Thanks for your great help!






2017-08-09 14:04 GMT+08:00 David Hendricks :

> Hi Sandy,
> What is the result of `lspci -nn | grep ISA` on your system? I uploaded a
> patch for Lewisburg PCI IDs here: https://review.coreboot.org/#/c/20922/
>
> I have tested Lewisburg PCH + W25Q256xxx and it seems to work. Let me know
> if you need any help applying the patch and testing it out on your system.
>
>
> On Tue, Aug 8, 2017 at 7:09 PM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI"
>> has been tested with the flashrom? thank you!
>>
>>
>>
>>
>>
>>
>> 2017-08-08 3:55 GMT+08:00 David Hendricks :
>>
>>> Hi Sandy,
>>> Correct - The PCH will not allow us to write anything to regions which
>>> are not defined in the flash descriptor. You could add those regions to the
>>> "BIOS" region if you wish to update them from your host OS. The SPI
>>> Programming Guide for your PCH (Lewisburg?) should also have info about
>>> additional regions which you may set up in the flash descriptor.
>>>
>>> "EW" means erase and write, "S" means skip (content does not need to
>>> change), "E" means erase only, "W" means write only
>>>
>>> On Mon, Aug 7, 2017 at 12:50 AM, Sandy Zhang 
>>> wrote:
>>>
 Hi David,

 It seems that the below 2 regions are "write denied":

 00A26000   00A35FFF 0001DER #1 Region
 00A36000   00FE 005BA00010 Gbe A Region

 By the way, can you tell me what is the other parament "EW", "S" and
 "E" meana? thank you!




 2017-08-07 13:02 GMT+08:00 David Hendricks :

> Hi Sandy,
> It might not have done what you expect. The error is because offsets
> 0xa26000-0xff are not defined in the flash descriptor, so the PCH 
> gives
> us an error when flashrom attempts to update it. ":WD" next to the offsets
> in the log means "write denied".
>
> If you wish to update that region of the ROM then you must change your
> flash descriptor to include it and set the permissions to enable read and
> write.
>
>
> On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> Attachment is the log file when flash bios into Winbond 32MB SPI rom,
>>  could you help to check if it's updated sucessfully? thank you!
>>
>> 2017-08-05 10:45 GMT+08:00 Sandy Zhang :
>>
>>> Hi David,
>>>
>>> Thank you very much, I will try to add the patch to flashrom-0.9.9,
>>> As a BIOS engineer, it is a bit difficult for me to complete this.
>>> Do you know when will make it into a release tarball?
>>>
>>>
>>>
>>> BR
>>> Sandy
>>>
>>> 2017-08-05 0:05 GMT+08:00 David Hendricks >> >:
>>>
 On Aug 3, 2017 11:51 PM, "Sandy Zhang" 
 wrote:

> Hi David,
>
> Thanks for your reply, can you tell me where to download the flash
> package like "flashrom-0.9.9.tar" which is downloaded from the 
> address ''
> https://www.flashrom.org/Downloads;?  thank you!
>

 The Skylake patches have not made it into a release tarball yet.
 Can you try using the git sources from https://review.coreboot.o
 rg/cgit/flashrom.git? E.g:

 git clone https://review.coreboot.org/flashrom.git
 git checkout origin/staging
 make


>
>
>
> BR
> Sandy
>
> 2017-08-04 14:35 GMT+08:00 David Hendricks <
> david.hendri...@gmail.com>:
>
>> Hi Sandy,
>> Skylake support was recently merged:
>> https://review.coreboot.org/18973
>>
>> However you may need to add your PCH PCI ID. What does `lspci -nn
>> | grep LPC` show on your test system?
>>
>> And yes, a 32MB ROM should work fine.
>>
>> On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang <
>> sanzh...@celestica.com> wrote:
>>
>>> Hi,
>>>
>>> Can you tell me when flashrom support Intel Purley platform
>>> Lewisburg PCH?
>>> and if it can support flash 32 MB SPI rom?
>>>  I am eager to your reply as soon as possible, thank you very
>>> much!
>>>
>>>
>>>

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-09 Thread David Hendricks

Hi Sandy,
What is the result of `lspci -nn | grep ISA` on your system? I uploaded a
patch for Lewisburg PCI IDs here: https://review.coreboot.org/#/c/20922/

I have tested Lewisburg PCH + W25Q256xxx and it seems to work. Let me know
if you need any help applying the patch and testing it out on your system.


On Tue, Aug 8, 2017 at 7:09 PM, Sandy Zhang  wrote:

> Hi David,
>
> Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI" has
> been tested with the flashrom? thank you!
>
>
>
>
>
>
> 2017-08-08 3:55 GMT+08:00 David Hendricks :
>
>> Hi Sandy,
>> Correct - The PCH will not allow us to write anything to regions which
>> are not defined in the flash descriptor. You could add those regions to the
>> "BIOS" region if you wish to update them from your host OS. The SPI
>> Programming Guide for your PCH (Lewisburg?) should also have info about
>> additional regions which you may set up in the flash descriptor.
>>
>> "EW" means erase and write, "S" means skip (content does not need to
>> change), "E" means erase only, "W" means write only
>>
>> On Mon, Aug 7, 2017 at 12:50 AM, Sandy Zhang 
>> wrote:
>>
>>> Hi David,
>>>
>>> It seems that the below 2 regions are "write denied":
>>>
>>> 00A26000   00A35FFF 0001DER #1 Region
>>> 00A36000   00FE 005BA00010 Gbe A Region
>>>
>>> By the way, can you tell me what is the other parament "EW", "S" and "E"
>>> meana? thank you!
>>>
>>>
>>>
>>>
>>> 2017-08-07 13:02 GMT+08:00 David Hendricks :
>>>
 Hi Sandy,
 It might not have done what you expect. The error is because offsets
 0xa26000-0xff are not defined in the flash descriptor, so the PCH gives
 us an error when flashrom attempts to update it. ":WD" next to the offsets
 in the log means "write denied".

 If you wish to update that region of the ROM then you must change your
 flash descriptor to include it and set the permissions to enable read and
 write.


 On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang 
 wrote:

> Hi David,
>
> Attachment is the log file when flash bios into Winbond 32MB SPI rom,
>  could you help to check if it's updated sucessfully? thank you!
>
> 2017-08-05 10:45 GMT+08:00 Sandy Zhang :
>
>> Hi David,
>>
>> Thank you very much, I will try to add the patch to flashrom-0.9.9,
>> As a BIOS engineer, it is a bit difficult for me to complete this.
>> Do you know when will make it into a release tarball?
>>
>>
>>
>> BR
>> Sandy
>>
>> 2017-08-05 0:05 GMT+08:00 David Hendricks 
>> :
>>
>>> On Aug 3, 2017 11:51 PM, "Sandy Zhang" 
>>> wrote:
>>>
 Hi David,

 Thanks for your reply, can you tell me where to download the flash
 package like "flashrom-0.9.9.tar" which is downloaded from the address 
 ''
 https://www.flashrom.org/Downloads;?  thank you!

>>>
>>> The Skylake patches have not made it into a release tarball yet. Can
>>> you try using the git sources from https://review.coreboot.o
>>> rg/cgit/flashrom.git? E.g:
>>>
>>> git clone https://review.coreboot.org/flashrom.git
>>> git checkout origin/staging
>>> make
>>>
>>>



 BR
 Sandy

 2017-08-04 14:35 GMT+08:00 David Hendricks <
 david.hendri...@gmail.com>:

> Hi Sandy,
> Skylake support was recently merged:
> https://review.coreboot.org/18973
>
> However you may need to add your PCH PCI ID. What does `lspci -nn
> | grep LPC` show on your test system?
>
> And yes, a 32MB ROM should work fine.
>
> On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang <
> sanzh...@celestica.com> wrote:
>
>> Hi,
>>
>> Can you tell me when flashrom support Intel Purley platform
>> Lewisburg PCH?
>> and if it can support flash 32 MB SPI rom?
>>  I am eager to your reply as soon as possible, thank you very
>> much!
>>
>>
>> --
>>
>> *Best Regard!*
>>
>> *Sandy Zhang (* 张立康*)*
>> *BIOS Engineer*
>> *Global Design Service*
>> *Celestica(Shanghai) R Center, China*
>> *Mail: sanzh...@celestica.com *
>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>> *Phone: (+86)021-61006028-7623*
>>
>> ___
>> flashrom mailing list
>> flashrom@flashrom.org
>> https://mail.coreboot.org/mailman/listinfo/flashrom
>>
>
>


 --

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-08 Thread Sandy Zhang

Hi David,

Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI" has
been tested with the flashrom? thank you!






2017-08-08 3:55 GMT+08:00 David Hendricks :

> Hi Sandy,
> Correct - The PCH will not allow us to write anything to regions which are
> not defined in the flash descriptor. You could add those regions to the
> "BIOS" region if you wish to update them from your host OS. The SPI
> Programming Guide for your PCH (Lewisburg?) should also have info about
> additional regions which you may set up in the flash descriptor.
>
> "EW" means erase and write, "S" means skip (content does not need to
> change), "E" means erase only, "W" means write only
>
> On Mon, Aug 7, 2017 at 12:50 AM, Sandy Zhang 
> wrote:
>
>> Hi David,
>>
>> It seems that the below 2 regions are "write denied":
>>
>> 00A26000   00A35FFF 0001DER #1 Region
>> 00A36000   00FE 005BA00010 Gbe A Region
>>
>> By the way, can you tell me what is the other parament "EW", "S" and "E"
>> meana? thank you!
>>
>>
>>
>>
>> 2017-08-07 13:02 GMT+08:00 David Hendricks :
>>
>>> Hi Sandy,
>>> It might not have done what you expect. The error is because offsets
>>> 0xa26000-0xff are not defined in the flash descriptor, so the PCH gives
>>> us an error when flashrom attempts to update it. ":WD" next to the offsets
>>> in the log means "write denied".
>>>
>>> If you wish to update that region of the ROM then you must change your
>>> flash descriptor to include it and set the permissions to enable read and
>>> write.
>>>
>>>
>>> On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang 
>>> wrote:
>>>
 Hi David,

 Attachment is the log file when flash bios into Winbond 32MB SPI rom,
  could you help to check if it's updated sucessfully? thank you!

 2017-08-05 10:45 GMT+08:00 Sandy Zhang :

> Hi David,
>
> Thank you very much, I will try to add the patch to flashrom-0.9.9,
> As a BIOS engineer, it is a bit difficult for me to complete this.
> Do you know when will make it into a release tarball?
>
>
>
> BR
> Sandy
>
> 2017-08-05 0:05 GMT+08:00 David Hendricks :
>
>> On Aug 3, 2017 11:51 PM, "Sandy Zhang" 
>> wrote:
>>
>>> Hi David,
>>>
>>> Thanks for your reply, can you tell me where to download the flash
>>> package like "flashrom-0.9.9.tar" which is downloaded from the address 
>>> ''
>>> https://www.flashrom.org/Downloads;?  thank you!
>>>
>>
>> The Skylake patches have not made it into a release tarball yet. Can
>> you try using the git sources from https://review.coreboot.o
>> rg/cgit/flashrom.git? E.g:
>>
>> git clone https://review.coreboot.org/flashrom.git
>> git checkout origin/staging
>> make
>>
>>
>>>
>>>
>>>
>>> BR
>>> Sandy
>>>
>>> 2017-08-04 14:35 GMT+08:00 David Hendricks <
>>> david.hendri...@gmail.com>:
>>>
 Hi Sandy,
 Skylake support was recently merged: https://review.coreboot.org/18
 973

 However you may need to add your PCH PCI ID. What does `lspci -nn |
 grep LPC` show on your test system?

 And yes, a 32MB ROM should work fine.

 On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang <
 sanzh...@celestica.com> wrote:

> Hi,
>
> Can you tell me when flashrom support Intel Purley platform
> Lewisburg PCH?
> and if it can support flash 32 MB SPI rom?
>  I am eager to your reply as soon as possible, thank you very much!
>
>
> --
>
> *Best Regard!*
>
> *Sandy Zhang (* 张立康*)*
> *BIOS Engineer*
> *Global Design Service*
> *Celestica(Shanghai) R Center, China*
> *Mail: sanzh...@celestica.com *
> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
> *Phone: (+86)021-61006028-7623*
>
> ___
> flashrom mailing list
> flashrom@flashrom.org
> https://mail.coreboot.org/mailman/listinfo/flashrom
>


>>>
>>>
>>> --
>>>
>>> *Best Regard!*
>>>
>>> *Sandy Zhang (* 张立康*)*
>>> *BIOS Engineer*
>>> *Global Design Service*
>>> *Celestica(Shanghai) R Center, China*
>>> *Mail: sanzh...@celestica.com *
>>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>>> *Phone: (+86)021-61006028-7623*
>>>
>>
>
>
> --
>
> *Best Regard!*
>
> *Sandy Zhang (* 张立康*)*
> *BIOS Engineer*
> *Global Design Service*
> *Celestica(Shanghai) R Center, China*
> *Mail:

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-06 Thread David Hendricks

Hi Sandy,
It might not have done what you expect. The error is because offsets
0xa26000-0xff are not defined in the flash descriptor, so the PCH gives
us an error when flashrom attempts to update it. ":WD" next to the offsets
in the log means "write denied".

If you wish to update that region of the ROM then you must change your
flash descriptor to include it and set the permissions to enable read and
write.


On Sun, Aug 6, 2017 at 8:20 PM, Sandy Zhang  wrote:

> Hi David,
>
> Attachment is the log file when flash bios into Winbond 32MB SPI rom,
>  could you help to check if it's updated sucessfully? thank you!
>
> 2017-08-05 10:45 GMT+08:00 Sandy Zhang :
>
>> Hi David,
>>
>> Thank you very much, I will try to add the patch to flashrom-0.9.9, As a
>> BIOS engineer, it is a bit difficult for me to complete this.
>> Do you know when will make it into a release tarball?
>>
>>
>>
>> BR
>> Sandy
>>
>> 2017-08-05 0:05 GMT+08:00 David Hendricks :
>>
>>> On Aug 3, 2017 11:51 PM, "Sandy Zhang"  wrote:
>>>
 Hi David,

 Thanks for your reply, can you tell me where to download the flash
 package like "flashrom-0.9.9.tar" which is downloaded from the address ''
 https://www.flashrom.org/Downloads;?  thank you!

>>>
>>> The Skylake patches have not made it into a release tarball yet. Can you
>>> try using the git sources from https://review.coreboot.o
>>> rg/cgit/flashrom.git? E.g:
>>>
>>> git clone https://review.coreboot.org/flashrom.git
>>> git checkout origin/staging
>>> make
>>>
>>>



 BR
 Sandy

 2017-08-04 14:35 GMT+08:00 David Hendricks :

> Hi Sandy,
> Skylake support was recently merged: https://review.coreboot.org/18973
>
> However you may need to add your PCH PCI ID. What does `lspci -nn |
> grep LPC` show on your test system?
>
> And yes, a 32MB ROM should work fine.
>
> On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang 
> wrote:
>
>> Hi,
>>
>> Can you tell me when flashrom support Intel Purley platform Lewisburg
>> PCH?
>> and if it can support flash 32 MB SPI rom?
>>  I am eager to your reply as soon as possible, thank you very much!
>>
>>
>> --
>>
>> *Best Regard!*
>>
>> *Sandy Zhang (* 张立康*)*
>> *BIOS Engineer*
>> *Global Design Service*
>> *Celestica(Shanghai) R Center, China*
>> *Mail: sanzh...@celestica.com *
>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>> *Phone: (+86)021-61006028-7623*
>>
>> ___
>> flashrom mailing list
>> flashrom@flashrom.org
>> https://mail.coreboot.org/mailman/listinfo/flashrom
>>
>
>


 --

 *Best Regard!*

 *Sandy Zhang (* 张立康*)*
 *BIOS Engineer*
 *Global Design Service*
 *Celestica(Shanghai) R Center, China*
 *Mail: sanzh...@celestica.com *
 *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
 *Phone: (+86)021-61006028-7623*

>>>
>>
>>
>> --
>>
>> *Best Regard!*
>>
>> *Sandy Zhang (* 张立康*)*
>> *BIOS Engineer*
>> *Global Design Service*
>> *Celestica(Shanghai) R Center, China*
>> *Mail: sanzh...@celestica.com *
>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>> *Phone: (+86)021-61006028-7623*
>>
>
>
>
> --
>
> *Best Regard!*
>
> *Sandy Zhang (* 张立康*)*
> *BIOS Engineer*
> *Global Design Service*
> *Celestica(Shanghai) R Center, China*
> *Mail: sanzh...@celestica.com *
> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
> *Phone: (+86)021-61006028-7623*
>
___
flashrom mailing list
flashrom@flashrom.org
https://mail.coreboot.org/mailman/listinfo/flashrom

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-04 Thread Sandy Zhang

Hi David,

Thank you very much, I will try to add the patch to flashrom-0.9.9, As a
BIOS engineer, it is a bit difficult for me to complete this.
Do you know when will make it into a release tarball?



BR
Sandy

2017-08-05 0:05 GMT+08:00 David Hendricks :

> On Aug 3, 2017 11:51 PM, "Sandy Zhang"  wrote:
>
>> Hi David,
>>
>> Thanks for your reply, can you tell me where to download the flash
>> package like "flashrom-0.9.9.tar" which is downloaded from the address ''
>> https://www.flashrom.org/Downloads;?  thank you!
>>
>
> The Skylake patches have not made it into a release tarball yet. Can you
> try using the git sources from https://review.coreboot.
> org/cgit/flashrom.git? E.g:
>
> git clone https://review.coreboot.org/flashrom.git
> git checkout origin/staging
> make
>
>
>>
>>
>>
>> BR
>> Sandy
>>
>> 2017-08-04 14:35 GMT+08:00 David Hendricks :
>>
>>> Hi Sandy,
>>> Skylake support was recently merged: https://review.coreboot.org/18973
>>>
>>> However you may need to add your PCH PCI ID. What does `lspci -nn | grep
>>> LPC` show on your test system?
>>>
>>> And yes, a 32MB ROM should work fine.
>>>
>>> On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang 
>>> wrote:
>>>
 Hi,

 Can you tell me when flashrom support Intel Purley platform Lewisburg
 PCH?
 and if it can support flash 32 MB SPI rom?
  I am eager to your reply as soon as possible, thank you very much!


 --

 *Best Regard!*

 *Sandy Zhang (* 张立康*)*
 *BIOS Engineer*
 *Global Design Service*
 *Celestica(Shanghai) R Center, China*
 *Mail: sanzh...@celestica.com *
 *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
 *Phone: (+86)021-61006028-7623*

 ___
 flashrom mailing list
 flashrom@flashrom.org
 https://mail.coreboot.org/mailman/listinfo/flashrom

>>>
>>>
>>
>>
>> --
>>
>> *Best Regard!*
>>
>> *Sandy Zhang (* 张立康*)*
>> *BIOS Engineer*
>> *Global Design Service*
>> *Celestica(Shanghai) R Center, China*
>> *Mail: sanzh...@celestica.com *
>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>> *Phone: (+86)021-61006028-7623*
>>
>


-- 

*Best Regard!*

*Sandy Zhang (* 张立康*)*
*BIOS Engineer*
*Global Design Service*
*Celestica(Shanghai) R Center, China*
*Mail: sanzh...@celestica.com *
*Mobile: (+86)15965353952*
*Phone: (+86)021-61006028-7623*
___
flashrom mailing list
flashrom@flashrom.org
https://mail.coreboot.org/mailman/listinfo/flashrom

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-04 Thread David Hendricks

On Aug 3, 2017 11:51 PM, "Sandy Zhang"  wrote:

> Hi David,
>
> Thanks for your reply, can you tell me where to download the flash package
> like "flashrom-0.9.9.tar" which is downloaded from the address ''
> https://www.flashrom.org/Downloads;?  thank you!
>

The Skylake patches have not made it into a release tarball yet. Can you
try using the git sources from https://review.coreboot.org/cgit/flashrom.git?
E.g:

git clone https://review.coreboot.org/flashrom.git
git checkout origin/staging
make


>
>
>
> BR
> Sandy
>
> 2017-08-04 14:35 GMT+08:00 David Hendricks :
>
>> Hi Sandy,
>> Skylake support was recently merged: https://review.coreboot.org/18973
>>
>> However you may need to add your PCH PCI ID. What does `lspci -nn | grep
>> LPC` show on your test system?
>>
>> And yes, a 32MB ROM should work fine.
>>
>> On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang 
>> wrote:
>>
>>> Hi,
>>>
>>> Can you tell me when flashrom support Intel Purley platform Lewisburg
>>> PCH?
>>> and if it can support flash 32 MB SPI rom?
>>>  I am eager to your reply as soon as possible, thank you very much!
>>>
>>>
>>> --
>>>
>>> *Best Regard!*
>>>
>>> *Sandy Zhang (* 张立康*)*
>>> *BIOS Engineer*
>>> *Global Design Service*
>>> *Celestica(Shanghai) R Center, China*
>>> *Mail: sanzh...@celestica.com *
>>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>>> *Phone: (+86)021-61006028-7623*
>>>
>>> ___
>>> flashrom mailing list
>>> flashrom@flashrom.org
>>> https://mail.coreboot.org/mailman/listinfo/flashrom
>>>
>>
>>
>
>
> --
>
> *Best Regard!*
>
> *Sandy Zhang (* 张立康*)*
> *BIOS Engineer*
> *Global Design Service*
> *Celestica(Shanghai) R Center, China*
> *Mail: sanzh...@celestica.com *
> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
> *Phone: (+86)021-61006028-7623*
>
___
flashrom mailing list
flashrom@flashrom.org
https://mail.coreboot.org/mailman/listinfo/flashrom

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-04 Thread Sandy Zhang

Hi David,

Thanks for your reply, can you tell me where to download the flash package
like "flashrom-0.9.9.tar" which is downloaded from the address ''
https://www.flashrom.org/Downloads;?  thank you!




BR
Sandy

2017-08-04 14:35 GMT+08:00 David Hendricks :

> Hi Sandy,
> Skylake support was recently merged: https://review.coreboot.org/18973
>
> However you may need to add your PCH PCI ID. What does `lspci -nn | grep
> LPC` show on your test system?
>
> And yes, a 32MB ROM should work fine.
>
> On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang 
> wrote:
>
>> Hi,
>>
>> Can you tell me when flashrom support Intel Purley platform Lewisburg PCH?
>> and if it can support flash 32 MB SPI rom?
>>  I am eager to your reply as soon as possible, thank you very much!
>>
>>
>> --
>>
>> *Best Regard!*
>>
>> *Sandy Zhang (* 张立康*)*
>> *BIOS Engineer*
>> *Global Design Service*
>> *Celestica(Shanghai) R Center, China*
>> *Mail: sanzh...@celestica.com *
>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>> *Phone: (+86)021-61006028-7623*
>>
>> ___
>> flashrom mailing list
>> flashrom@flashrom.org
>> https://mail.coreboot.org/mailman/listinfo/flashrom
>>
>
>


-- 

*Best Regard!*

*Sandy Zhang (* 张立康*)*
*BIOS Engineer*
*Global Design Service*
*Celestica(Shanghai) R Center, China*
*Mail: sanzh...@celestica.com *
*Mobile: (+86)15965353952*
*Phone: (+86)021-61006028-7623*
___
flashrom mailing list
flashrom@flashrom.org
https://mail.coreboot.org/mailman/listinfo/flashrom

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

2017-08-04 Thread David Hendricks

Hi Sandy,
Skylake support was recently merged: https://review.coreboot.org/18973

However you may need to add your PCH PCI ID. What does `lspci -nn | grep
LPC` show on your test system?

And yes, a 32MB ROM should work fine.

On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang  wrote:

> Hi,
>
> Can you tell me when flashrom support Intel Purley platform Lewisburg PCH?
> and if it can support flash 32 MB SPI rom?
>  I am eager to your reply as soon as possible, thank you very much!
>
>
> --
>
> *Best Regard!*
>
> *Sandy Zhang (* 张立康*)*
> *BIOS Engineer*
> *Global Design Service*
> *Celestica(Shanghai) R Center, China*
> *Mail: sanzh...@celestica.com *
> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
> *Phone: (+86)021-61006028-7623*
>
> ___
> flashrom mailing list
> flashrom@flashrom.org
> https://mail.coreboot.org/mailman/listinfo/flashrom
>
___
flashrom mailing list
flashrom@flashrom.org
https://mail.coreboot.org/mailman/listinfo/flashrom

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

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