Re: [PATCH] Haswell Kernel Mode Setting
On Mon, Nov 11, 2013 at 03:39:06PM -0800, Xin Li wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 11/11/13 14:29, Neel Chauhan wrote: Sorry if I sent a similar patch before. It didn't get accepted so I am sending one now. Enjoy. What does didn't get accepted mean? :) Since this looks like a PCI-ID only change that do not affect other existing hardware, if it's not an explicit objection from a reviewer, I think it's Okay to just go ahead and commit the change after a reasonable timeout instead of waiting indefinitely. I very much doubt that this patch works. More, I believe that it was not tested at all. Talking about the trivially obvious things, the PGTT handling must be updated since page tables have different format comparing with Ivy, there are some changes to ring dispatching, and lot of changes in the display pipeline. All this is missing from the patch. Oh, and the Series 8 chipset PCH detection is missing. I probably should stop now. HSW support is much more than just adding the Ids, I am (slowly) starting the work on importing the Linux updates. pgpOMRklPLnpt.pgp Description: PGP signature
Re: [PATCH] Haswell Kernel Mode Setting
On 2013-11-12 03:29, Konstantin Belousov wrote: On Mon, Nov 11, 2013 at 03:39:06PM -0800, Xin Li wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 11/11/13 14:29, Neel Chauhan wrote: Sorry if I sent a similar patch before. It didn't get accepted so I am sending one now. Enjoy. What does didn't get accepted mean? :) Since this looks like a PCI-ID only change that do not affect other existing hardware, if it's not an explicit objection from a reviewer, I think it's Okay to just go ahead and commit the change after a reasonable timeout instead of waiting indefinitely. I very much doubt that this patch works. More, I believe that it was not tested at all. Talking about the trivially obvious things, the PGTT handling must be updated since page tables have different format comparing with Ivy, there are some changes to ring dispatching, and lot of changes in the display pipeline. All this is missing from the patch. Oh, and the Series 8 chipset PCH detection is missing. I probably should stop now. HSW support is much more than just adding the Ids, I am (slowly) starting the work on importing the Linux updates. Konstantin, Thanks for telling me. The reality is, I don't really know about the insides of the FreeBSD kernel, Linux, or drm. I just looked at a few files. I should really get a book about FreeBSD before trying to send patches again. And anyways, this patch is untested. I was in a rush to send it to the mailing list, hoping it would get accepted. Thanks, Neel ___ freebsd-current@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-current To unsubscribe, send any mail to freebsd-current-unsubscr...@freebsd.org
[PATCH] Haswell Kernel Mode Setting
Hello FreeBSD-CURRENT and FreeBSD-X11 mailing list(s),
I have a patch to add support for kernel mode setting on Intel
Haswell/4th generation Core i(3/5/7) chips. The patch is:
diff -u -r -N head/sys/dev/agp/agp_i810.c tree/sys/dev/agp/agp_i810.c
--- head/sys/dev/agp/agp_i810.c 2013-11-11 16:18:23.0 -0500
+++ tree/sys/dev/agp/agp_i810.c 2013-11-11 17:09:33.0 -0500
@@ -734,6 +734,41 @@
.name = IvyBridge server GT2 IG,
.driver = agp_i810_sb_driver
},
+{
+.devid = 0x04028086,
+.name = Haswell desktop GT1 IG,
+.driver = agp_i810_sb_driver
+},
+{
+.devid = 0x04128086,
+.name = Haswell desktop GT2 IG,
+.driver = agp_i810_sb_driver
+},
+{
+.devid = 0x04068086,
+.name = Haswell mobile GT1 IG,
+.driver = agp_i810_sb_driver
+},
+{
+.devid = 0x04168086,
+.name = Haswell mobile GT2 IG,
+.driver = agp_i810_sb_driver
+},
+{
+.devid = 0x040a8086,
+.name = Haswell server GT1 IG,
+.driver = agp_i810_sb_driver
+},
+{
+.devid = 0x041a8086,
+.name = Haswell server GT2 IG,
+.driver = agp_i810_sb_driver
+},
+{
+.devid = 0x0c168086,
+.name = Haswell SDV,
+.driver = agp_i810_sb_driver
+},
{
.devid = 0,
}
diff -u -r -N head/sys/dev/drm2/drm_pciids.h
tree/sys/dev/drm2/drm_pciids.h
--- head/sys/dev/drm2/drm_pciids.h 2013-11-11 16:17:33.0 -0500
+++ tree/sys/dev/drm2/drm_pciids.h 2013-11-11 17:09:37.0 -0500
@@ -48,6 +48,42 @@
{0x8086, 0x0162, CHIP_I9XX|CHIP_I915, Intel IvyBridge}, \
{0x8086, 0x0166, CHIP_I9XX|CHIP_I915, Intel IvyBridge (M)}, \
{0x8086, 0x016A, CHIP_I9XX|CHIP_I915, Intel IvyBridge (S)}, \
+ {0x8086, 0x0402, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0412, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0422, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0406, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0416, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0426, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x040A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x041A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x042A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0C02, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0C12, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0C22, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0C06, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0C16, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0C26, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0C0A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0C1A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0C2A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0A02, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0A12, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0A22, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0A06, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0A16, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0A26, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0A0A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0A1A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0A2A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0D12, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0D22, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0D32, CHIP_I9XX|CHIP_I915, Intel Haswell}, \
+ {0x8086, 0x0D16, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0D26, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0D36, CHIP_I9XX|CHIP_I915, Intel Haswell (M)}, \
+ {0x8086, 0x0D1A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0D2A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
+ {0x8086, 0x0D3A, CHIP_I9XX|CHIP_I915, Intel Haswell (S)}, \
{0x8086, 0x2562, CHIP_I8XX, Intel i845G GMCH}, \
{0x8086, 0x2572, CHIP_I8XX, Intel i865G GMCH}, \
{0x8086, 0x2582, CHIP_I9XX|CHIP_I915, Intel i915G}, \
diff -u -r -N head/sys/dev/drm2/i915/i915_drv.c
tree/sys/dev/drm2/i915/i915_drv.c
--- head/sys/dev/drm2/i915/i915_drv.c 2013-11-11 16:17:24.0
-0500
+++ tree/sys/dev/drm2/i915/i915_drv.c 2013-11-11 17:10:05.0
-0500
@@ -173,6 +173,22 @@
.has_llc = 1,
};
+static const struct intel_device_info
Re: [PATCH] Haswell Kernel Mode Setting
-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 11/11/13 14:29, Neel Chauhan wrote: Sorry if I sent a similar patch before. It didn't get accepted so I am sending one now. Enjoy. What does didn't get accepted mean? :) Since this looks like a PCI-ID only change that do not affect other existing hardware, if it's not an explicit objection from a reviewer, I think it's Okay to just go ahead and commit the change after a reasonable timeout instead of waiting indefinitely. Cheers, - -- Xin LI delp...@delphij.nethttps://www.delphij.net/ FreeBSD - The Power to Serve! Live free or die -BEGIN PGP SIGNATURE- iQIcBAEBCgAGBQJSgWqaAAoJEJW2GBstM+ns7pgP/iTu4VI4UYgj/nCmSblhVsjH kO+YPaBoXkO+3e7GQ+E6LKqnH3Byjvc8WZH6/fBA2qY9Kfjjte0gJIG8t7Fu34IQ SRiQaErRYUyXCHIIfgjrvRVIrk7bvwe70awnMVQOIktmzdJ4i6cxxEzsvsLqd5OY Argc77bBkSSa0w/QiWR04bG119u/WVyEhNnJ1XdYq3IzJqTb/fkOYAHm/JaWkhSy F8Vj2bxSr9fiKD36wb/kV5cFC4ZNP/SounurAhMTMaHfWAGJE/KuUy5aRP0bHzOY FwcpAAqIsuy13tBKXXsDNgETTJrbnSGQp7AM7BMZJXkX7kfX8SIfpmG0rjoJH02G V3SDdvMmS/x4sIrKmgwQsUT1MGNGdJtD0Xzx27ng0BVSItPKXkB1azxvRkfRE03N yyWX4C0IQg/U/UgkV3jwe+8LAezPXNRbnKD5QX165g+EnAkRmferAT1/kNnV1zV/ G7eU7x9TTml8fCi0g5Oid3smL+BiwGOkZA36r+Js+lQd5Pmkn3GUJw1qx3vNTWKz P6UHeRzSppez1aWx6NigvPH9qUz+HpaN4aWf+Zzl9MFbKcEohtzT8LaBCB/F1BdG pvGOXcCb+BeUy/IBW+Yx7zal5Ri7YIRIAb2hssqACVBOYwbVzMQidEWuSERMyNdo gMcNWZw+kXLE5wCklwm9 =zbWH -END PGP SIGNATURE- ___ freebsd-current@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-current To unsubscribe, send any mail to freebsd-current-unsubscr...@freebsd.org
