Re: wikipedia article

2006-06-13 Thread Johnny Billquist

That qualifies as the answer of the day.
My hat goes off to you. :-D

Johnny

Thor Lancelot Simon wrote:

On Mon, Jun 12, 2006 at 10:27:33PM -0700, Ted Mittelstaedt wrote:


What was the bit size of the CPU's originally used to write UNIX in Bell
Labs?



Rather large.  You can get all the details at
http://en.wikipedia.org/wiki/Magnetic_core.



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Re: wikipedia article

2006-06-13 Thread Johnny Billquist

Otto Moerbeek wrote:

On Mon, 12 Jun 2006, Ted Mittelstaedt wrote:



-Original Message-
From: John Nemeth [mailto:[EMAIL PROTECTED]
Sent: Monday, June 12, 2006 1:15 PM
To: Ted Mittelstaedt; Nikolas Britton; Ted Unangst
Cc: Hamorszky Balazs; misc@openbsd.org; freebsd-questions@freebsd.org;
[EMAIL PROTECTED]
Subject: RE: wikipedia article


On Nov 1,  6:11pm, Ted Mittelstaedt wrote:
}
} Prior to the release of the 80386 the Intel processors didn't have
} memory protection which was a requirement of any processor running
} the BSD kernel.

   This is not entirely true.  The 80286 had memory protection.
However, its memory protection was completely based on segments (i.e.
it could not do paging).


Oh, yeah, your right about that.  Me bad.



Also, it was only a 16 bit processor.


What was the bit size of the CPU's originally used to write UNIX in Bell
Labs?


The PDP-7 was/is an 18-bit machine.


What's more, iirc the MMU of the pdp11 isn't what we call a MMU today,
it could not even do paging.


You're wrong. You could easily do paging on a PDP-11, if you wanted to. 
The main reasons this wasn't done are two.
1) Each page is 8K. At the time, that was considered way too large pages 
for a demand page system.
2) The address space is only 64 per process, which means you only have 8 
pages. Not only is that perhaps a little little for meaningful paging 
(most programs tend to refer to all 8 pages most of the time). The main 
memory on a PDP-11 is furthermore 4 meg, so having a lot of processes 
full memory space in physical memory at the same time is not a problem.


The PDP-11 MMU is a beatiful MMU. Nothing like the crap Intel spits out. ;-)

Johnny

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Re: wikipedia article

2006-06-13 Thread Johnny Billquist

Marcus Watts wrote:

Various wrote:


From: Otto Moerbeek [EMAIL PROTECTED]
To: Ted Mittelstaedt [EMAIL PROTECTED]


...


What's more, iirc the MMU of the pdp11 isn't what we call a MMU today,
it could not even do paging.


The pdp-11 mmu could handle program relocation, segmentation (after
a fashion) and memory protection.  I'm not sure what more you
could expect from an mmu.  What you mean by paging is
probably demand paging, which means the ability to run a program
without requiring that it be entirely resident.  The key
feature you need for that is a guarantee that any instruction fault
caused by missing memory can be either restarted or continued.
In most architectures that's a question of cpu design not mmu.


True. But it's mostly a combination of MMU and CPU.
The MMU needs to either abort or trap the offending instruction, and the 
CPU needs to know how much side effects had been done so that they can 
be undone before a restart.


The PDP-11 MMU can either abort the instruction, or do a trap after the 
instruction completes. The CPU have a register telling of register 
modifications done, as well as the pre-fetch PC. In additions to this, 
the MMU have both an expansion direction, a modified bit, and an 
accessed bit. And that is in addition to the protection field and size 
field of the page (and the address relocation). So I can't really 
imagine anything that you cannot do with the PDP-11 MMU. Heck, there is 
even the funny bypass cache bit. Useful for multiprocessor systems...


Since the PDP-11 have a different page table for I- and D-space, you can 
even have execute-only pages.



In the case of the pdp-11 that's mostly a moot point.  The pdp-11 only
provides for mapping the 64k of memory space into into 8 segments
(addressable on 64-byte clicks) and there's just not much win to
demand paging 8 pages.  (actually 6 x 8 pages; there was kernel,
user, and supervisor mode,  each had separate instruction and data
spaces, but supervisor mode was rarely used in Unix environments, and
only a few large user mode programs ran using split I/D space.)


2.11BSD uses supervisor mode for the networking parts of the kernel. And 
the kernel is all I/D-space, and a bunch of programs are as well. The 
development is still contiuing. :-)



 For
what it's worth, though, I *think* it was possible to restart most
instructions on the /45 and /70, which were the big machines and the
primary target of most later pdp-11 work.


I don't think there is a single instruction that you can't restart.
Some small, older machines missed a few registers needed for proper 
restarts however, and on those things were a bit more of a gamble if you 
wanted to go that path.



 In fact, some use was made
of this feature -- automatic stack growth.  If you look through ancient
Unix source, you'll find interesting bits of kernel code that manage
this.

There's actually a cheesy way to do demand paging with microprocessors
that don't support demand paging (such as the original 68000--another
16 bit machine).  The way to do this is to run two processors in parallel
but skewed by one instruction.  If the first one does a bad memory fetch,
then the second one will not have fetched the instruction causing the
fault so contains restartable machine state.  Masscomp sold a machine
like this once.


Didn't the first Apollos do this?

Johnny

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Re: wikipedia article

2006-06-13 Thread Johnny Billquist

Per Fogelström wrote:

On Tuesday 13 June 2006 14:23, Rick Kelly wrote:


Johnny Billquist said:


There's actually a cheesy way to do demand paging with microprocessors
that don't support demand paging (such as the original 68000--another
16 bit machine).  The way to do this is to run two processors in
parallel but skewed by one instruction.  If the first one does a bad
memory fetch, then the second one will not have fetched the instruction
causing the fault so contains restartable machine state.  Masscomp sold
a machine like this once.


Didn't the first Apollos do this?


And also the Sun 1.



IIRC it was simpler than that. When the first cpu caused a 'miss' it was put
in wait and cpu 2 handled the pagein and then released cpu 1. Keeping the two
cpus synched, one instruction apart would have been too complicated if not
impossible...


Your idea will not work, as far as I can tell.
If the first CPU instruction execution causes a miss, the end result in 
the CPU will be pretty undefined, and you cannot restart. That's the 
whole point in why you'd have a second CPU shadowing the first one. So 
that you'd be able to restore the state as it were before the illegal 
memory access.
And that was the problem with the original 68000. On an illegal memory 
reference, you would not know what state the CPU was in before the 
instruction, so you could not back it up, and re-execute the instruction 
after a page fault.


Johnny

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Re: Editor for C C++ language

2005-10-22 Thread Johnny Billquist
On Sat, 22 Oct 2005, vittorio wrote:

 Working usually under kde I'm looking for something similar to the llc-win32
 program under ms-windows - that is a development environment where you can
 edit your c++ program, compile it, debug it step by step, and finally run it
 in a suitable window.
 I tried the nice editor kate which allows to compile the file only. No
 debugging, no running.
 Is  there anything of the kind of llc-win32?

emacs can do anything. Put it might not be graphical enough for your taste
if you come from Windows...

Johnny

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  ||  on a psychedelic trip
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