date:20171020

[Freedreno] [PATCH 8/9] drm/msm: Removed unused struct_mutex_task

2017-10-20 Thread Jordan Crouse

Recent changes to locking have rendered struct_mutex_task
unused.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_drv.h| 6 --
 drivers/gpu/drm/msm/msm_gem_submit.c | 2 --
 2 files changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 9853e3e..c46dc12 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -154,12 +154,6 @@ struct msm_drm_private {
struct shrinker shrinker;
 
struct msm_vblank_ctrl vblank_ctrl;
-
-   /* task holding struct_mutex.. currently only used in submit path
-* to detect and reject faults from copy_from_user() for submit
-* ioctl.
-*/
-   struct task_struct *struct_mutex_task;
 };
 
 struct msm_format {
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c 
b/drivers/gpu/drm/msm/msm_gem_submit.c
index 9e087cf..d68bfa6 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -449,7 +449,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
goto out_unlock;
}
}
-   priv->struct_mutex_task = current;
 
submit = submit_create(dev, gpu, queue, args->nr_bos, args->nr_cmds);
if (!submit) {
@@ -569,7 +568,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
 out_unlock:
if (ret && (out_fence_fd >= 0))
put_unused_fd(out_fence_fd);
-   priv->struct_mutex_task = NULL;
mutex_unlock(>struct_mutex);
return ret;
 }
-- 
1.9.1

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[Freedreno] [PATCH 9/9] drm/msm: dump a rd GPUADDR header for all buffers in the command

2017-10-20 Thread Jordan Crouse

Currently the rd dump avoids any buffers marked as WRITE under
the assumption that the contents are not interesting.  While it
is true that the contents are uninteresting we should still print
the iova and size for all buffers so that any listening replay
tools can correctly construct the submission.

Print the header for all buffers but only dump the contents for
buffers marked as READ.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_rd.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c
index 0366b80..4c858d8 100644
--- a/drivers/gpu/drm/msm/msm_rd.c
+++ b/drivers/gpu/drm/msm/msm_rd.c
@@ -268,10 +268,6 @@ static void snapshot_buf(struct msm_rd_state *rd,
struct msm_gem_object *obj = submit->bos[idx].obj;
const char *buf;
 
-   buf = msm_gem_get_vaddr(>base);
-   if (IS_ERR(buf))
-   return;
-
if (iova) {
buf += iova - submit->bos[idx].iova;
} else {
@@ -279,8 +275,21 @@ static void snapshot_buf(struct msm_rd_state *rd,
size = obj->base.size;
}
 
+   /*
+* Always write the GPUADDR header so can get a complete list of all the
+* buffers in the cmd
+*/
rd_write_section(rd, RD_GPUADDR,
(uint32_t[3]){ iova, size, iova >> 32 }, 12);
+
+   /* But only dump the contents of buffers marked READ */
+   if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ))
+   return;
+
+   buf = msm_gem_get_vaddr(>base);
+   if (IS_ERR(buf))
+   return;
+
rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
 
msm_gem_put_vaddr(>base);
@@ -309,17 +318,8 @@ void msm_rd_dump_submit(struct msm_gem_submit *submit)
 
rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4));
 
-   if (rd_full) {
-   for (i = 0; i < submit->nr_bos; i++) {
-   /* buffers that are written to probably don't start out
-* with anything interesting:
-*/
-   if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
-   continue;
-
-   snapshot_buf(rd, submit, i, 0, 0);
-   }
-   }
+   for (i = 0; rd_full && i < submit->nr_bos; i++)
+   snapshot_buf(rd, submit, i, 0, 0);
 
for (i = 0; i < submit->nr_cmds; i++) {
uint64_t iova = submit->cmd[i].iova;
-- 
1.9.1

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[Freedreno] [PATCH 3/9] drm/msm: Support multiple ringbuffers

2017-10-20 Thread Jordan Crouse

Add the infrastructure to support the idea of multiple ringbuffers.
Assign each ringbuffer an id and use that as an index for the various
ring specific operations.

The biggest delta is to support legacy fences. Each fence gets its own
sequence number but the legacy functions expect to use a unique integer.
To handle this we return a unique identifier for each submission but
map it to a specific ring/sequence under the covers. Newer users use
a dma_fence pointer anyway so they don't care about the actual sequence
ID or ring.

The actual mechanics for multiple ringbuffers are very target specific
so this code just allows for the possibility but still only defines
one ringbuffer for each target family.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   |   9 +-
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c   |   9 +-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c   |  54 ++-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h   |   2 +-
 drivers/gpu/drm/msm/adreno/a5xx_power.c |   6 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 137 ---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  20 ++--
 drivers/gpu/drm/msm/msm_drv.c   |  23 +++--
 drivers/gpu/drm/msm/msm_drv.h   |   8 +-
 drivers/gpu/drm/msm/msm_fence.c |   2 +-
 drivers/gpu/drm/msm/msm_fence.h |   2 +-
 drivers/gpu/drm/msm/msm_gem.h   |   4 +-
 drivers/gpu/drm/msm/msm_gem_submit.c|  12 ++-
 drivers/gpu/drm/msm/msm_gpu.c   | 163 ++--
 drivers/gpu/drm/msm/msm_gpu.h   |  42 
 drivers/gpu/drm/msm/msm_ringbuffer.c|  35 +--
 drivers/gpu/drm/msm/msm_ringbuffer.h|  20 +++-
 drivers/gpu/drm/msm/msm_submitqueue.c   |  27 +-
 include/uapi/drm/msm_drm.h  |   1 +
 19 files changed, 366 insertions(+), 210 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 789f7fb..4baef27 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -44,7 +44,7 @@
 
 static bool a3xx_me_init(struct msm_gpu *gpu)
 {
-   struct msm_ringbuffer *ring = gpu->rb;
+   struct msm_ringbuffer *ring = gpu->rb[0];
 
OUT_PKT3(ring, CP_ME_INIT, 17);
OUT_RING(ring, 0x03f7);
@@ -65,7 +65,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
OUT_RING(ring, 0x);
 
-   gpu->funcs->flush(gpu);
+   gpu->funcs->flush(gpu, ring);
return a3xx_idle(gpu);
 }
 
@@ -339,7 +339,7 @@ static void a3xx_destroy(struct msm_gpu *gpu)
 static bool a3xx_idle(struct msm_gpu *gpu)
 {
/* wait for ringbuffer to drain: */
-   if (!adreno_idle(gpu))
+   if (!adreno_idle(gpu, gpu->rb[0]))
return false;
 
/* then wait for GPU to finish: */
@@ -446,6 +446,7 @@ static void a3xx_dump(struct msm_gpu *gpu)
.recover = a3xx_recover,
.submit = adreno_submit,
.flush = adreno_flush,
+   .active_ring = adreno_active_ring,
.irq = a3xx_irq,
.destroy = a3xx_destroy,
 #ifdef CONFIG_DEBUG_FS
@@ -491,7 +492,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
adreno_gpu->registers = a3xx_registers;
adreno_gpu->reg_offsets = a3xx_register_offsets;
 
-   ret = adreno_gpu_init(dev, pdev, adreno_gpu, );
+   ret = adreno_gpu_init(dev, pdev, adreno_gpu, , 1);
if (ret)
goto fail;
 
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index f87c4312..8199a4b 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -116,7 +116,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
 
 static bool a4xx_me_init(struct msm_gpu *gpu)
 {
-   struct msm_ringbuffer *ring = gpu->rb;
+   struct msm_ringbuffer *ring = gpu->rb[0];
 
OUT_PKT3(ring, CP_ME_INIT, 17);
OUT_RING(ring, 0x03f7);
@@ -137,7 +137,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
OUT_RING(ring, 0x);
 
-   gpu->funcs->flush(gpu);
+   gpu->funcs->flush(gpu, ring);
return a4xx_idle(gpu);
 }
 
@@ -337,7 +337,7 @@ static void a4xx_destroy(struct msm_gpu *gpu)
 static bool a4xx_idle(struct msm_gpu *gpu)
 {
/* wait for ringbuffer to drain: */
-   if (!adreno_idle(gpu))
+   if (!adreno_idle(gpu, gpu->rb[0]))
return false;
 
/* then wait for GPU to finish: */
@@ -534,6 +534,7 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t 
*value)
.recover = a4xx_recover,
.submit = adreno_submit,
.flush = adreno_flush,
+   .active_ring = adreno_active_ring,
.irq = a4xx_irq,
.destroy = a4xx_destroy,
 #ifdef CONFIG_DEBUG_FS
@@ -573,7 +574,7 @@ struct msm_gpu

[Freedreno] [PATCH 2/9] drm/msm: Move memptrs to msm_gpu

2017-10-20 Thread Jordan Crouse

When we move to multiple ringbuffers we're going to store the data
in the memptrs on a per-ring basis. In order to prepare for that
move the current memptrs from the adreno namespace into msm_gpu.
This is way cleaner and immediately lets us kill off some sub
functions so there is much less cost later when we do move to
per-ring structs.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   |  1 -
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c   |  1 -
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c   |  8 ++---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 52 -
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 16 --
 drivers/gpu/drm/msm/msm_gpu.c   | 30 +--
 drivers/gpu/drm/msm/msm_gpu.h   | 17 +--
 7 files changed, 57 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 7791313..789f7fb 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -444,7 +444,6 @@ static void a3xx_dump(struct msm_gpu *gpu)
.pm_suspend = msm_gpu_pm_suspend,
.pm_resume = msm_gpu_pm_resume,
.recover = a3xx_recover,
-   .last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
.irq = a3xx_irq,
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 58341ef..f87c4312 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -532,7 +532,6 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t 
*value)
.pm_suspend = a4xx_pm_suspend,
.pm_resume = a4xx_pm_resume,
.recover = a4xx_recover,
-   .last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
.irq = a4xx_irq,
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 17c59d8..32a5b55 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -98,7 +98,6 @@ static int zap_shader_load_mdt(struct device *dev, const char 
*fwname)
 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx)
 {
-   struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct msm_drm_private *priv = gpu->dev->dev_private;
struct msm_ringbuffer *ring = gpu->rb;
unsigned int i, ibs = 0;
@@ -125,8 +124,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
 
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31));
-   OUT_RING(ring, lower_32_bits(rbmemptr(adreno_gpu, fence)));
-   OUT_RING(ring, upper_32_bits(rbmemptr(adreno_gpu, fence)));
+   OUT_RING(ring, lower_32_bits(rbmemptr(gpu, fence)));
+   OUT_RING(ring, upper_32_bits(rbmemptr(gpu, fence)));
OUT_RING(ring, submit->fence->seqno);
 
gpu->funcs->flush(gpu);
@@ -804,7 +803,7 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu)
struct msm_drm_private *priv = dev->dev_private;
 
dev_err(dev->dev, "gpu fault fence %x status %8.8X rb %4.4x/%4.4x ib1 
%16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
-   gpu->funcs->last_fence(gpu),
+   gpu->memptrs->fence,
gpu_read(gpu, REG_A5XX_RBBM_STATUS),
gpu_read(gpu, REG_A5XX_CP_RB_RPTR),
gpu_read(gpu, REG_A5XX_CP_RB_WPTR),
@@ -992,7 +991,6 @@ static void a5xx_show(struct msm_gpu *gpu, struct seq_file 
*m)
.pm_suspend = a5xx_pm_suspend,
.pm_resume = a5xx_pm_resume,
.recover = a5xx_recover,
-   .last_fence = adreno_last_fence,
.submit = a5xx_submit,
.flush = adreno_flush,
.irq = a5xx_irq,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index c8b4ac2..b9238ac 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -82,8 +82,8 @@ int adreno_hw_init(struct msm_gpu *gpu)
gpu->rb->cur = gpu->rb->start;
 
/* reset completed fence seqno: */
-   adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
-   adreno_gpu->memptrs->rptr  = 0;
+   gpu->memptrs->fence = gpu->fctx->completed_fence;
+   gpu->memptrs->rptr  = 0;
 
/* Setup REG_CP_RB_CNTL: */
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
@@ -98,8 +98,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
 
if (!adreno_is_a430(adreno_gpu)) {
adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
-   REG_ADRENO_CP_RB_RPTR_ADDR_HI,
-   rbmemptr(adreno_gpu, rptr));
+

[Freedreno] [PATCH 7/9] drm/msm: Implement preemption for A5XX targets

2017-10-20 Thread Jordan Crouse

Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/Makefile  |   1 +
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 176 -
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 107 ++-
 drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 305 ++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   |  14 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h   |   7 +-
 drivers/gpu/drm/msm/msm_drv.h |   2 +-
 drivers/gpu/drm/msm/msm_gpu.c |   5 +-
 drivers/gpu/drm/msm/msm_ringbuffer.c  |   1 +
 drivers/gpu/drm/msm/msm_ringbuffer.h  |   1 +
 10 files changed, 599 insertions(+), 20 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_preempt.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 3c234e7..d0b26dd 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -8,6 +8,7 @@ msm-y := \
adreno/a4xx_gpu.o \
adreno/a5xx_gpu.o \
adreno/a5xx_power.o \
+   adreno/a5xx_preempt.o \
hdmi/hdmi.o \
hdmi/hdmi_audio.o \
hdmi/hdmi_bridge.o \
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index b7b9f4f..a0f69b2 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -95,13 +95,65 @@ static int zap_shader_load_mdt(struct device *dev, const 
char *fwname)
return ret;
 }
 
+static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
+{
+   struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+   struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
+   uint32_t wptr;
+   unsigned long flags;
+
+   spin_lock_irqsave(>lock, flags);
+
+   /* Copy the shadow to the actual register */
+   ring->cur = ring->next;
+
+   /* Make sure to wrap wptr if we need to */
+   wptr = get_wptr(ring);
+
+   spin_unlock_irqrestore(>lock, flags);
+
+   /* Make sure everything is posted before making a decision */
+   mb();
+
+   /* Update HW if this is the current ring and we are not in preempt */
+   if (a5xx_gpu->cur_ring == ring && !a5xx_in_preempt(a5xx_gpu))
+   gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
+}
+
 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx)
 {
+   struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+   struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
struct msm_drm_private *priv = gpu->dev->dev_private;
struct msm_ringbuffer *ring = submit->ring;
unsigned int i, ibs = 0;
 
+   OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
+   OUT_RING(ring, 0x02);
+
+   /* Turn off protected mode to write to special registers */
+   OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
+   OUT_RING(ring, 0);
+
+   /* Set the save preemption record for the ring/command */
+   OUT_PKT4(ring, REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 2);
+   OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));
+   OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));
+
+   /* Turn back on protected mode */
+   OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
+   OUT_RING(ring, 1);
+
+   /* Enable local preemption for finegrain preemption */
+   OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
+   OUT_RING(ring, 0x02);
+
+   /* Allow CP_CONTEXT_SWITCH_YIELD packets in the IB2 */
+   OUT_PKT7(ring, CP_YIELD_ENABLE, 1);
+   OUT_RING(ring, 0x02);
+
+   /* Submit the commands */
for (i = 0; i < submit->nr_cmds; i++) {
switch (submit->cmd[i].type) {
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
@@ -119,16 +171,54 @@ static void a5xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
}
}
 
+   /*
+* Write the render mode to NULL (0) to indicate to the CP that the IBs
+* are done rendering - otherwise a lucky preemption would start
+* replaying from the last checkpoint
+*/
+   OUT_PKT7(ring, CP_SET_RENDER_MODE, 5);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+
+   /* Turn off IB level preemptions */
+   OUT_PKT7(ring, CP_YIELD_ENABLE, 1);
+   OUT_RING(ring, 0x01);
+
+   /* Write the fence to the scratch register */
OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1);
OUT_RING(ring, submit->seqno);
 
+   /*
+* Execute a CACHE_FLUSH_TS event. This will ensure that the
+* timestamp is written to the memory and then triggers the interrupt
+*/
OUT_PKT7(ring, CP_EVENT_WRITE, 4);

[Freedreno] [PATCH v2 0/9] drm/msm for 4.15 (resend)

2017-10-20 Thread Jordan Crouse

(Resending for more visibility)

Here are the refreshed submitqueue/ringbuffer/preemption changes for 4.15.
These are the original changes with bug fixes, improvements and suggestions
squashed in:
 
 - Moved SUBMITQUEUE_CLOSE param to a u32 instead of reusing the struct
 - Changed to use per-ring fence contexts
 - Squashed in Rob's change to the driver version
 - Squshed in fix for preemption race condition

These apply against drm-msm-next-2017-08-22 from ~robclark/linux.

Jordan Crouse (9):
  drm/msm: Add per-instance submit queues
  drm/msm: Move memptrs to msm_gpu
  drm/msm: Support multiple ringbuffers
  drm/msm: Add a parameter query for the number of ringbuffers
  drm/msm: Shadow current pointer in the ring until command is complete
  drm/msm: Make the value of RB_CNTL (almost) generic
  drm/msm: Implement preemption for A5XX targets
  drm/msm: Removed unused struct_mutex_task
  drm/msm: dump a rd GPUADDR header for all buffers in the command

 drivers/gpu/drm/msm/Makefile  |   4 +-
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c |  10 +-
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c |  10 +-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 222 +++---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 109 ++-
 drivers/gpu/drm/msm/adreno/a5xx_power.c   |   6 +-
 drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 305 ++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 183 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  43 ++---
 drivers/gpu/drm/msm/msm_drv.c |  71 ++-
 drivers/gpu/drm/msm/msm_drv.h |  28 +--
 drivers/gpu/drm/msm/msm_fence.c   |   2 +-
 drivers/gpu/drm/msm/msm_fence.h   |   2 +-
 drivers/gpu/drm/msm/msm_gem.h |   5 +-
 drivers/gpu/drm/msm/msm_gem_submit.c  |  26 ++-
 drivers/gpu/drm/msm/msm_gpu.c | 174 -
 drivers/gpu/drm/msm/msm_gpu.h |  51 +++--
 drivers/gpu/drm/msm/msm_rd.c  |  30 +--
 drivers/gpu/drm/msm/msm_ringbuffer.c  |  37 +++-
 drivers/gpu/drm/msm/msm_ringbuffer.h  |  33 +++-
 drivers/gpu/drm/msm/msm_submitqueue.c | 152 +++
 include/uapi/drm/msm_drm.h|  24 +++
 22 files changed, 1249 insertions(+), 278 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_preempt.c
 create mode 100644 drivers/gpu/drm/msm/msm_submitqueue.c

-- 
1.9.1

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[Freedreno] [PATCH 4/9] drm/msm: Add a parameter query for the number of ringbuffers

2017-10-20 Thread Jordan Crouse

In order to manage ringbuffer priority to its fullest userspace
should know how many ringbuffers it has to work with. Add a
parameter to return the number of active rings.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
 include/uapi/drm/msm_drm.h  | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index fad946946..cf91840 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -57,6 +57,9 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, 
uint64_t *value)
return ret;
}
return -EINVAL;
+   case MSM_PARAM_NR_RINGS:
+   *value = gpu->nr_rings;
+   return 0;
default:
DBG("%s: invalid param: %u", gpu->name, param);
return -EINVAL;
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 42fa781..6363d94 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -73,6 +73,7 @@ struct drm_msm_timespec {
 #define MSM_PARAM_MAX_FREQ   0x04
 #define MSM_PARAM_TIMESTAMP  0x05
 #define MSM_PARAM_GMEM_BASE  0x06
+#define MSM_PARAM_NR_RINGS   0x07
 
 struct drm_msm_param {
__u32 pipe;   /* in, MSM_PIPE_x */
-- 
1.9.1

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[Freedreno] [PATCH 6/9] drm/msm: Make the value of RB_CNTL (almost) generic

2017-10-20 Thread Jordan Crouse

We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to calculate it once and use
it everywhere.

The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++-
 drivers/gpu/drm/msm/msm_gpu.h   |  5 +
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 77eaa46..72f1132 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -21,7 +21,6 @@
 #include "msm_gem.h"
 #include "msm_mmu.h"
 
-#define RB_BLKSIZE 32
 
 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
 {
@@ -96,11 +95,14 @@ int adreno_hw_init(struct msm_gpu *gpu)
ring->memptrs->rptr = 0;
}
 
-   /* Setup REG_CP_RB_CNTL: */
+   /*
+* Setup REG_CP_RB_CNTL.  The same value is used across targets (with
+* the excpetion of A430 that disables the RPTR shadow) - the cacluation
+* for the ringbuffer size and block size is moved to msm_gpu.h for the
+* pre-processor to deal with and the A430 variant is ORed in here
+*/
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
-   /* size is log2(quad-words): */
-   AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) |
-   AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
+   MSM_GPU_RB_CNTL_DEFAULT |
(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
 
/* Setup ringbuffer address - use ringbuffer[0] for GPU init */
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 1be0317..e113d64 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -129,6 +129,11 @@ struct msm_gpu {
 
 /* It turns out that all targets use the same ringbuffer size */
 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
+#define MSM_GPU_RINGBUFFER_BLKSIZE 32
+
+#define MSM_GPU_RB_CNTL_DEFAULT \
+   (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
+   AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
 
 static inline bool msm_gpu_active(struct msm_gpu *gpu)
 {
-- 
1.9.1

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Re: [Freedreno] [PATCH] drm/msm/mdp5: restore cursor state when enabling crtc

2017-10-20 Thread Archit Taneja




On 10/20/2017 01:30 AM, Rob Clark wrote:

Since we enabled runtime PM, we cannot count on cursor registers to
retain their values.  This can result in situations where we think the
cursor is enabled when we enable the CRTC but it is trying to scan out
null (and the rest of cursor position/size is lost), resulting in faults
and generally angering the hw when coming out of DPMS with a cursor
enabled.

stable backport note: reverting 774e39ee3572 is also a suitable fix

Fixes: 774e39ee3572 drm/msm/mdp5: Set up runtime PM for MDSS
Signed-off-by: Rob Clark 
---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 100 +--
  1 file changed, 68 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 6aa3a688d9a4..db5c460ba593 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -61,12 +61,15 @@ struct mdp5_crtc {
  
  		/* current cursor being scanned out: */

struct drm_gem_object *scanout_bo;
+   uint64_t iova;
uint32_t width, height;
uint32_t x, y;
} cursor;
  };
  #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  
+static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc);

+
  static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  {
struct msm_drm_private *priv = crtc->dev->dev_private;
@@ -449,6 +452,21 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
  
  	pm_runtime_get_sync(dev);
  
+	/* Restore cursor state, as it might have been lost with suspend: */

+   if (mdp5_crtc->cursor.iova) {
+   unsigned long flags;
+
+   spin_lock_irqsave(_crtc->cursor.lock, flags);
+   mdp5_crtc_restore_cursor(crtc);
+   spin_unlock_irqrestore(_crtc->cursor.lock, flags);
+
+   mdp5_ctl_set_cursor(mdp5_cstate->ctl,
+   _cstate->pipeline, 0, true);
+   } else {
+   mdp5_ctl_set_cursor(mdp5_cstate->ctl,
+   _cstate->pipeline, 0, false);
+   }
+
/* Restore vblank irq handling after power is enabled */
drm_crtc_vblank_on(crtc);
  
@@ -729,6 +747,50 @@ static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)

mdp5_crtc->cursor.y);
  }
  
+static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)

+{
+   struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
+   struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+   struct mdp5_kms *mdp5_kms = get_kms(crtc);
+   const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
+   uint32_t blendcfg, stride;
+   uint32_t x, y, width, height;
+   uint32_t roi_w, roi_h;
+   int lm;
+
+   assert_spin_locked(_crtc->cursor.lock);
+
+   lm = mdp5_cstate->pipeline.mixer->lm;
+
+   x = mdp5_crtc->cursor.x;
+   y = mdp5_crtc->cursor.y;
+   width = mdp5_crtc->cursor.width;
+   height = mdp5_crtc->cursor.height;
+
+   stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB, 0);
+
+   get_roi(crtc, _w, _h);
+
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
+   MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB));
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
+   MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
+   MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
+   MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
+   MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
+   MDP5_LM_CURSOR_START_XY_Y_START(y) |
+   MDP5_LM_CURSOR_START_XY_X_START(x));
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
+   mdp5_crtc->cursor.iova);
+
+   blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
+   blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
+}
+
  static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
struct drm_file *file, uint32_t handle,
uint32_t width, uint32_t height)
@@ -741,13 +803,9 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
struct platform_device *pdev = mdp5_kms->pdev;
struct msm_kms *kms = _kms->base.base;
struct drm_gem_object *cursor_bo, *old_bo = NULL;
-   uint32_t blendcfg, stride;
-   uint64_t cursor_addr;
struct mdp5_ctl *ctl;
-   int ret, lm;
-   enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
+   int ret;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
-   uint32_t roi_w, roi_h;

Re: [Freedreno] [PATCH] drm/msm/mdp5: don't use autosuspend

2017-10-20 Thread Archit Taneja




On 10/20/2017 05:47 PM, Rob Clark wrote:

It's only likely to paper over bugs.  Unlike the gpu, where we want to
keep things alive a bit longer in expectation of the next frame's
submit, when the display is shut down we can power off immediately.


Acked-by: Archit Taneja 



Signed-off-by: Rob Clark 
---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c |  2 +-
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  6 +++---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  2 +-
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 10 +-
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  6 +++---
  5 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
index 60790df91bfa..1abc7f5c345c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
@@ -224,7 +224,7 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder 
*encoder,
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
   MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 0b6ace26d622..6aa3a688d9a4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -429,7 +429,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
mdp_irq_unregister(_kms->base, _crtc->pp_done);
  
  	mdp_irq_unregister(_kms->base, _crtc->err);

-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	mdp5_crtc->enabled = false;

  }
@@ -821,7 +821,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
crtc_flush(crtc, flush_mask);
  
  end:

-   pm_runtime_put_autosuspend(>dev);
+   pm_runtime_put_sync(>dev);
if (old_bo) {
drm_flip_work_queue(_crtc->unref_cursor_work, old_bo);
/* enable vblank to complete cursor work: */
@@ -867,7 +867,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int 
x, int y)
  
  	crtc_flush(crtc, flush_mask);
  
-	pm_runtime_put_autosuspend(_kms->pdev->dev);

+   pm_runtime_put_sync(_kms->pdev->dev);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
index 5b851380d3f2..36ad3cbe5f79 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -384,7 +384,7 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder 
*encoder,
  
  	mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
  
-	pm_runtime_put_autosuspend(dev);

+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index bb5deb00c899..280e368bc9bb 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -54,7 +54,7 @@ void mdp5_irq_preinstall(struct msm_kms *kms)
pm_runtime_get_sync(dev);
mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0x);
mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  }
  
  int mdp5_irq_postinstall(struct msm_kms *kms)

@@ -72,7 +72,7 @@ int mdp5_irq_postinstall(struct msm_kms *kms)
  
  	pm_runtime_get_sync(dev);

mdp_irq_register(mdp_kms, error_handler);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
@@ -84,7 +84,7 @@ void mdp5_irq_uninstall(struct msm_kms *kms)
  
  	pm_runtime_get_sync(dev);

mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  }
  
  irqreturn_t mdp5_irq(struct msm_kms *kms)

@@ -119,7 +119,7 @@ int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc 
*crtc)
pm_runtime_get_sync(dev);
mdp_update_vblank_mask(to_mdp_kms(kms),
mdp5_crtc_vblank(crtc), true);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
@@ -132,5 +132,5 @@ void mdp5_disable_vblank(struct msm_kms *kms, struct 
drm_crtc *crtc)
pm_runtime_get_sync(dev);
mdp_update_vblank_mask(to_mdp_kms(kms),
mdp5_crtc_vblank(crtc), false);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index c664eb1d47dc..ca8f20206b6c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -125,7 +125,7 @@ static void mdp5_complete_commit(struct msm_kms *kms,

[Freedreno] [PATCH] drm/msm/mdp5: don't use autosuspend

2017-10-20 Thread Rob Clark

It's only likely to paper over bugs.  Unlike the gpu, where we want to
keep things alive a bit longer in expectation of the next frame's
submit, when the display is shut down we can power off immediately.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c |  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  6 +++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 10 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  6 +++---
 5 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
index 60790df91bfa..1abc7f5c345c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
@@ -224,7 +224,7 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder 
*encoder,
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
   MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 
return 0;
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 0b6ace26d622..6aa3a688d9a4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -429,7 +429,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
mdp_irq_unregister(_kms->base, _crtc->pp_done);
 
mdp_irq_unregister(_kms->base, _crtc->err);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 
mdp5_crtc->enabled = false;
 }
@@ -821,7 +821,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
crtc_flush(crtc, flush_mask);
 
 end:
-   pm_runtime_put_autosuspend(>dev);
+   pm_runtime_put_sync(>dev);
if (old_bo) {
drm_flip_work_queue(_crtc->unref_cursor_work, old_bo);
/* enable vblank to complete cursor work: */
@@ -867,7 +867,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int 
x, int y)
 
crtc_flush(crtc, flush_mask);
 
-   pm_runtime_put_autosuspend(_kms->pdev->dev);
+   pm_runtime_put_sync(_kms->pdev->dev);
 
return 0;
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
index 5b851380d3f2..36ad3cbe5f79 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -384,7 +384,7 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder 
*encoder,
 
mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
 
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 
return 0;
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index bb5deb00c899..280e368bc9bb 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -54,7 +54,7 @@ void mdp5_irq_preinstall(struct msm_kms *kms)
pm_runtime_get_sync(dev);
mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0x);
mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 }
 
 int mdp5_irq_postinstall(struct msm_kms *kms)
@@ -72,7 +72,7 @@ int mdp5_irq_postinstall(struct msm_kms *kms)
 
pm_runtime_get_sync(dev);
mdp_irq_register(mdp_kms, error_handler);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 
return 0;
 }
@@ -84,7 +84,7 @@ void mdp5_irq_uninstall(struct msm_kms *kms)
 
pm_runtime_get_sync(dev);
mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 }
 
 irqreturn_t mdp5_irq(struct msm_kms *kms)
@@ -119,7 +119,7 @@ int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc 
*crtc)
pm_runtime_get_sync(dev);
mdp_update_vblank_mask(to_mdp_kms(kms),
mdp5_crtc_vblank(crtc), true);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 
return 0;
 }
@@ -132,5 +132,5 @@ void mdp5_disable_vblank(struct msm_kms *kms, struct 
drm_crtc *crtc)
pm_runtime_get_sync(dev);
mdp_update_vblank_mask(to_mdp_kms(kms),
mdp5_crtc_vblank(crtc), false);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index c664eb1d47dc..ca8f20206b6c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -125,7 +125,7 @@ static void mdp5_complete_commit(struct msm_kms *kms, 
struct drm_atomic_state *s
if (mdp5_kms->smp)

[Freedreno] [PATCH 8/9] drm/msm: Removed unused struct_mutex_task

[Freedreno] [PATCH 9/9] drm/msm: dump a rd GPUADDR header for all buffers in the command

[Freedreno] [PATCH 3/9] drm/msm: Support multiple ringbuffers

[Freedreno] [PATCH 2/9] drm/msm: Move memptrs to msm_gpu

[Freedreno] [PATCH 7/9] drm/msm: Implement preemption for A5XX targets

[Freedreno] [PATCH v2 0/9] drm/msm for 4.15 (resend)

[Freedreno] [PATCH 4/9] drm/msm: Add a parameter query for the number of ringbuffers

[Freedreno] [PATCH 6/9] drm/msm: Make the value of RB_CNTL (almost) generic

Re: [Freedreno] [PATCH] drm/msm/mdp5: restore cursor state when enabling crtc

Re: [Freedreno] [PATCH] drm/msm/mdp5: don't use autosuspend

[Freedreno] [PATCH] drm/msm/mdp5: don't use autosuspend

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