[Freedreno] [PATCH] drm/msm: Grab a vblank reference when waiting for commit_done

[Sean Paul]

From: Sean Paul 

Similar to the atomic helpers, we should enable vblank while we're
waiting for the commit to finish. DPU needs this, MDP5 seems to work
fine without it.

Signed-off-by: Sean Paul 
---
 drivers/gpu/drm/msm/msm_atomic.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index c1f1779c980f..2b7bb6e166d3 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -32,7 +32,12 @@ static void msm_atomic_wait_for_commit_done(struct 
drm_device *dev,
if (!new_crtc_state->active)
continue;
 
+   if (drm_crtc_vblank_get(crtc))
+   continue;
+
kms->funcs->wait_for_crtc_commit_done(kms, crtc);
+
+   drm_crtc_vblank_put(crtc);
}
 }
 
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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Re: [Freedreno] [PATCH] drm/msm: dpu: Add tracing around CTL_FLUSH

[Jeykumar Sankaran]

On 2018-10-03 11:36, Sean Paul wrote:

From: Sean Paul 

I found these tracepoints useful for debugging cursor/ctl, someone else
might find them useful too

Signed-off-by: Sean Paul 
---

Thanks for the patch!

Reviewed-by: Jeykumar Sankaran 


 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 26 
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h  | 47 ++
 2 files changed, 65 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index b394a1818c5d..3f50164ad30e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -15,6 +15,7 @@
 #include "dpu_hw_ctl.h"
 #include "dpu_dbg.h"
 #include "dpu_kms.h"
+#include "dpu_trace.h"

 #define   CTL_LAYER(lm) \
(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
@@ -72,24 +73,39 @@ static int _mixer_stages(const struct dpu_lm_cfg
*mixer, int count,
return stages;
 }

+static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl 
*ctx)

+{
+   struct dpu_hw_blk_reg_map *c = >hw;
+
+   return DPU_REG_READ(c, CTL_FLUSH);
+}
+
 static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
 {
+   trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask,
+
dpu_hw_ctl_get_flush_register(ctx));
DPU_REG_WRITE(>hw, CTL_START, 0x1);
 }

 static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
 {
+   trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
+
dpu_hw_ctl_get_flush_register(ctx));
DPU_REG_WRITE(>hw, CTL_PREPARE, 0x1);
 }

 static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl 
*ctx)

 {
+   trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
+dpu_hw_ctl_get_flush_register(ctx));
ctx->pending_flush_mask = 0x0;
 }

 static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl
*ctx,
u32 flushbits)
 {
+   trace_dpu_hw_ctl_update_pending_flush(flushbits,
+ ctx->pending_flush_mask);
ctx->pending_flush_mask |= flushbits;
 }

@@ -103,17 +119,11 @@ static u32 dpu_hw_ctl_get_pending_flush(struct
dpu_hw_ctl *ctx)

 static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
 {
-
+   trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
+dpu_hw_ctl_get_flush_register(ctx));
DPU_REG_WRITE(>hw, CTL_FLUSH, ctx->pending_flush_mask);
 }

-static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl 
*ctx)

-{
-   struct dpu_hw_blk_reg_map *c = >hw;
-
-   return DPU_REG_READ(c, CTL_FLUSH);
-}
-
 static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl
*ctx,
enum dpu_sspp sspp)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index e12c4cefb742..636b31b0d311 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -1004,6 +1004,53 @@ TRACE_EVENT(dpu_core_perf_update_clk,
  __entry->stop_req ? "true" : "false", __entry->clk_rate)
 );

+TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
+   TP_PROTO(u32 new_bits, u32 pending_mask),
+   TP_ARGS(new_bits, pending_mask),
+   TP_STRUCT__entry(
+   __field(u32,new_bits)
+   __field(u32,pending_mask)
+   ),
+   TP_fast_assign(
+   __entry->new_bits = new_bits;
+   __entry->pending_mask = pending_mask;
+   ),
+   TP_printk("new=%x existing=%x", __entry->new_bits,
+ __entry->pending_mask)
+);
+
+DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
+   TP_PROTO(u32 pending_mask, u32 ctl_flush),
+   TP_ARGS(pending_mask, ctl_flush),
+   TP_STRUCT__entry(
+   __field(u32,pending_mask)
+   __field(u32,ctl_flush   )
+   ),
+   TP_fast_assign(
+   __entry->pending_mask = pending_mask;
+   __entry->ctl_flush = ctl_flush;
+   ),
+   TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
+ __entry->ctl_flush)
+);
+DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
dpu_hw_ctl_clear_pending_flush,
+   TP_PROTO(u32 pending_mask, u32 ctl_flush),
+   TP_ARGS(pending_mask, ctl_flush)
+);
+DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
+dpu_hw_ctl_trigger_pending_flush,
+   TP_PROTO(u32 pending_mask, u32 ctl_flush),
+   TP_ARGS(pending_mask, ctl_flush)
+);
+DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
dpu_hw_ctl_trigger_prepare,
+   TP_PROTO(u32 pending_mask, u32 ctl_flush),
+   TP_ARGS(pending_mask, ctl_flush)
+);
+DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 
dpu_hw_ctl_trigger_start,

+   

Re: [Freedreno] [PATCH 1/2] drm/msm: dpu: Only check flush register against pending flushes

[Sean Paul]

On Tue, Oct 02, 2018 at 06:14:38PM -0700, Jeykumar Sankaran wrote:
> On 2018-10-01 13:29, Sean Paul wrote:
> > On Wed, Sep 26, 2018 at 11:51:35AM -0700, Jeykumar Sankaran wrote:
> > > On 2018-09-19 11:56, Sean Paul wrote:
> > > > From: Sean Paul 
> > > >
> > > > There exists a case where a flush of a plane/dma may have been
> > triggered
> > > > & started from an async commit. If that plane/dma is subsequently
> > > > disabled
> > > > by the next commit, the flush register will continue to hold the flush
> > > > bit for the disabled plane. Since the bit remains active,
> > > > pending_kickoff_cnt will never decrement and we'll miss frame_done
> > > > events.
> > > >
> > > I suppose this is the vblank in between the async commit and the next
> > commit
> > > (one where
> > > the plane is disabled).
> > > 
> > > If this vblank had consumed the flush bits, it means the HW
> > > has read the configuration and it should have cleared bits.
> > > 
> > > If you still see the flush bit active, it means the async commit has
> > missed
> > > the VBLANK boundary
> > > and the HW has not yet taken the cursor configuration. So you are not
> > > supposed to
> > > get frame_done event.
> > 
> > Right, we're not getting frame_done until the next frame comes in. The
> > issue is
> > that we get 2 commits in between vblanks, the first commit triggers the
> > cursor
> > for flush and the second one disables it. Unfortunately the first commit
> > has
> > already called CTL_START and made it impossible for the second commit to
> > clear
> > that flush bit (afaict).
> > 
> > The frame_done events seem to flow properly, only being triggered once
> > per
> > vblank and only when a non-async commit has happened.
> > 
> > So is there a way to clear the CTL_FLUSH register on subsequent commits?
> > I've
> > poked around some more and can't seem to figure it out.
> > 
> We shouldn't be explicitly clearing the FLUSH register. Uncleared flush bits
> generally indicates that the config is not programmed yet. What is the
> observation if there is no followup non-async commit? Are you seeing a hang
> or delay in frame_done? 

There's no problems if there is no followup. Perhaps the issue is better
illustrated with some tracing. The following are traces when chrome changes the
UI and hides the cursor at the same time.


182.607515: dpu_hw_ctl_clear_pending_flush: pending_mask=10200c1 CTL_FLUSH=0
182.607569: dpu_hw_ctl_update_pending_flush: new=1020041 existing=0
182.607581: dpu_hw_ctl_update_pending_flush: new=1020081 existing=1020041
182.607822: dpu_kms_commit: id=46
182.607867: dpu_hw_ctl_trigger_pending_flush: pending_mask=10200c1 CTL_FLUSH=0

This is a normal atomic commit where chrome is providing updates to both planes
(primary and cursor). We clear the pending flush mask, figure out which planes
need to be flushed and trigger the flush.


182.607999: dpu_hw_ctl_clear_pending_flush: pending_mask=10200c1 
CTL_FLUSH=10200c1
182.608042: dpu_hw_ctl_update_pending_flush: new=20041 existing=0
182.608054: dpu_hw_ctl_update_pending_flush: new=20081 existing=20041
182.608136: dpu_plane_disable: id:42 is_virtual:false multirect_mode:0
182.608222: dpu_kms_commit: id=46
182.608246: dpu_hw_ctl_trigger_pending_flush: pending_mask=200c1 
CTL_FLUSH=10200c1

This commit comes in asynchronously before vblank and disables the cursor. As
you can see, CTL_FLUSH is still set at 10200c1 from the previous commit when
we first clear the pending mask. The new mask drops bit 24 (DMA2) and writes
200c1 (the current value of pending_mask) to CTL_FLUSH.

182.609924: dpu_enc_phys_vid_vblank: mask=0, register=100   
  

When the vblank does come in, the hardware has flushed the visible planes, but
CTL_FLUSH still contains the bit for DMA2 since it was not flushed. The criteria
for frame_done is that the bitwise & of the CTL_FLUSH and pending_mask. Since
pending mask doesn't contain DMA1 and the flush register does, we don't get a
frame_done for the commit.


So there are 2 ways to solve this, afaict:

1- Clear CTL_FLUSH when we clear pending flush. AFAICT, there's no good way to
   do this, and it's inherently racy with vblank.
2- Ensure that the bits we care about in pending_flush_mask are cleared as a
   criteria for frame_done.

I'm certainly open to ideas if there's a better way, however I haven't found one
yet.

Sean

> Eventually, the next VBLANK should pick the
> configuration
> and wipe off the flush register and the vblank irq handler should trigger
> the event.
> 
> > > 
> > > Comments outside the scope of this patch: To support async and sync
> > updates
> > > on the same display commit thread, we should be adding more protection
> > to
> > > support
> > > concurrency scenarios to avoid more than one ctl flushes per VBLANK
> > period.
> > 
> > Yeah, certainly easier said than done. I'm not really sure how to
> > implement
> > that, tbh.
> > 
> > There's no way to know how many commits you'll have, and there's no way
> > to
> > delay 

Re: [Freedreno] [PATCH 2/2] drm/msm: dpu: Make legacy cursor updates asynchronous

[Sean Paul]

On Tue, Oct 02, 2018 at 06:19:52PM -0700, Jeykumar Sankaran wrote:
> On 2018-10-01 13:30, Sean Paul wrote:
> > On Wed, Sep 26, 2018 at 11:56:47AM -0700, Jeykumar Sankaran wrote:
> > > On 2018-09-19 11:56, Sean Paul wrote:
> > > > From: Sean Paul 
> > > >
> > > > This patch sprinkles a few async/legacy_cursor_update checks
> > > > through commit to ensure that cursor updates aren't blocked on vsync.
> > > > There are 2 main components to this, the first is that we don't want
> > to
> > > > wait_for_commit_done in msm_atomic  before returning from
> > > > atomic_complete.
> > > > The second is that in dpu we don't want to wait for frame_done events
> > > > when
> > > > updating the cursor.
> > > >
> > > > Signed-off-by: Sean Paul 
> > > > ---

/snip

> > > > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> > > > b/drivers/gpu/drm/msm/msm_atomic.c
> > > > index c1f1779c980f..7912130ce5ce 100644
> > > > --- a/drivers/gpu/drm/msm/msm_atomic.c
> > > > +++ b/drivers/gpu/drm/msm/msm_atomic.c
> > > > @@ -76,7 +76,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state
> > > > *state)
> > > > kms->funcs->commit(kms, state);
> > > > }
> > > >
> > > > -   msm_atomic_wait_for_commit_done(dev, state);
> > > > +   if (!state->legacy_cursor_update)
> > > I see state->async_update is updated after validation checks on the
> > async
> > > capabilities. Shouldn't we use
> > > that var instead of state->legacy_cursor_update?
> > > > +   msm_atomic_wait_for_commit_done(dev, state);
> > > >
> > > > kms->funcs->complete_commit(kms, state);
> > > 
> > > Do we need to introduce plane helpers atomic_async_update and
> > > atomic_async_check in DPU before supporting
> > > these wait skips? or are they irrelevant for this legacy async path?
> > 
> > I was trying to limit the scope of this to just cursor updates. I think
> > once/if
> > support is added for generic async it makes sense to change over to that
> > verbage.
> > 
> Since SDM845 doesnt support dedicated CURSOR stages, 

Well, it has CURSOR type planes, which unlocks the cursor ioctls, so it kind of
does :)

> I think the right
> way to add the cursor support should be to introduce the atomic async
> support
> in the driver and let the cursor frame update like regulary async commit.
> 
> I need to explore on the right way to fit that in.

It's as easy as implementing the async atomic hooks. If they're present, the
cursor path goes through them. Upgrading from legacy cursor to generic async is
pretty trivial in light of the other issues we're facing here.

Sean

> 
> Thanks,
> Jeykumar S.
> > Sean
> > 
> > > 
> > > --
> > > Jeykumar S
> 
> -- 
> Jeykumar S

-- 
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Re: [Freedreno] [PATCH 11/18] drm/msm: Use drm_atomic_helper_shutdown

[Ville Syrjälä]

On Wed, Oct 03, 2018 at 11:16:44AM +0200, Daniel Vetter wrote:
> drm_plane_helper_disable is a non-atomic drivers only function, and
> will blow up (since no one passes the locking context it needs).
> 
> Atomic drivers which want to quiescent their hw on unload should
> use drm_atomic_helper_shutdown() instead.

lgtm
Reviewed-by: Ville Syrjälä 

> 
> Signed-off-by: Daniel Vetter 
> Cc: Rob Clark 
> Cc: Rajesh Yadav 
> Cc: Chandan Uddaraju 
> Cc: Archit Taneja 
> Cc: Jeykumar Sankaran 
> Cc: Sean Paul 
> Cc: Maarten Lankhorst 
> Cc: Sinclair Yeh 
> Cc: "Ville Syrjälä" 
> Cc: Russell King 
> Cc: Gustavo Padovan 
> Cc: Arnd Bergmann 
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedreno@lists.freedesktop.org
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 2 --
>  drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 1 -
>  drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 1 -
>  drivers/gpu/drm/msm/msm_drv.c  | 1 +
>  4 files changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 015341e2dd4c..ec959f847d5f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1482,8 +1482,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
>  
>   mutex_destroy(>lock);
>  
> - drm_plane_helper_disable(plane, NULL);
> -
>   /* this will destroy the states as well */
>   drm_plane_cleanup(plane);
>  
> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c 
> b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> index 79ff653d8081..7a499731ce93 100644
> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> @@ -68,7 +68,6 @@ static void mdp4_plane_destroy(struct drm_plane *plane)
>  {
>   struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
>  
> - drm_plane_helper_disable(plane, NULL);
>   drm_plane_cleanup(plane);
>  
>   kfree(mdp4_plane);
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 
> b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> index 7d306c5acd09..d5e4f0de321a 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> @@ -46,7 +46,6 @@ static void mdp5_plane_destroy(struct drm_plane *plane)
>  {
>   struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
>  
> - drm_plane_helper_disable(plane, NULL);
>   drm_plane_cleanup(plane);
>  
>   kfree(mdp5_plane);
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index c1abad8a8612..69dbdba183fe 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -312,6 +312,7 @@ static int msm_drm_uninit(struct device *dev)
>   if (fbdev && priv->fbdev)
>   msm_fbdev_free(ddev);
>  #endif
> + drm_atomic_helper_shutdown(ddev);
>   drm_mode_config_cleanup(ddev);
>  
>   pm_runtime_get_sync(dev);
> -- 
> 2.19.0.rc2

-- 
Ville Syrjälä
Intel
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Re: [Freedreno] [PATCH 06/13] drm/msm: Use kzalloc for submit struct allocation

[Sharat Masetty]

On 10/1/2018 11:43 PM, Jordan Crouse wrote:

On Mon, Oct 01, 2018 at 06:01:38PM +0530, Sharat Masetty wrote:

This patch changes to kzalloc and avoids setting individual submit
struct fields to zero manually.


I don't think this one is worth it.  There are so many members in submit and so
few that get reset to 0 - I don't think the extra cycles are worth it in this
fast path.
The patch "drm/msm: Use the DRM common Scheduler" adds a few more fields 
to the bo struct, If not kzalloc, then I will have to run a loop or 
memset the bos area to 0 at least.



Signed-off-by: Sharat Masetty 
---
  drivers/gpu/drm/msm/msm_gem_submit.c | 7 +--
  1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c 
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a7c8cbc..7931c2a 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -41,24 +41,19 @@ static struct msm_gem_submit *submit_create(struct 
drm_device *dev,
if (sz > SIZE_MAX)
return NULL;
  
-	submit = kmalloc(sz, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);

+   submit = kzalloc(sz, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
if (!submit)
return NULL;
  
  	submit->dev = dev;

submit->gpu = gpu;
submit->ctx = ctx;
-   submit->hw_fence = NULL;
submit->out_fence_id = -1;
submit->pid = get_pid(task_pid(current));
submit->cmd = (void *)>bos[nr_bos];
submit->queue = queue;
submit->ring = gpu->rb[queue->prio];
  
-	/* initially, until copy_from_user() and bo lookup succeeds: */

-   submit->nr_bos = 0;
-   submit->nr_cmds = 0;
-
INIT_LIST_HEAD(>node);
INIT_LIST_HEAD(>bo_list);
ww_acquire_init(>ticket, _ww_class);
--
1.9.1





--
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Re: [Freedreno] [PATCH 09/13] drm/msm: Use the DRM common Scheduler

[Sharat Masetty]

Thanks for the review comments Jordan. I tried to answer a few queries.. 
please check.


On 10/2/2018 12:32 AM, Jordan Crouse wrote:

On Mon, Oct 01, 2018 at 06:01:41PM +0530, Sharat Masetty wrote:

This patch hooks up the DRM gpu scheduler to the msm DRM driver. The
most noticeable changes to the driver are as follows. The submit path is
split into two parts, in the user context the submit(job) is created and
added to one of the entity's scheduler run queue. The scheduler then
tries to drain the queue by submitting the jobs the hardware to act upon.
The submit job sits on the scheduler queue until all the dependent
fences are waited upon successfully.

We have one scheduler instance per ring. The submitqueues will host a
scheduler entity object. This entity will be mapped to the scheduler's
default runqueue. This should be good for now, but in future it is possible
to extend the API to allow for scheduling amongst the submitqueues on the
same ring.

With this patch the role of the struct_mutex lock has been greatly reduced in
scope in the submit path, evidently when actually putting the job on the
ringbuffer. This should enable us with increased parallelism in the
driver which should translate to better performance overall hopefully.

Signed-off-by: Sharat Masetty 
---
  drivers/gpu/drm/msm/Kconfig   |   1 +
  drivers/gpu/drm/msm/Makefile  |   3 +-
  drivers/gpu/drm/msm/msm_drv.h |   3 +-
  drivers/gpu/drm/msm/msm_gem.c |   8 +-
  drivers/gpu/drm/msm/msm_gem.h |   6 +
  drivers/gpu/drm/msm/msm_gem_submit.c  | 138 +--
  drivers/gpu/drm/msm/msm_gpu.c |  72 ++--
  drivers/gpu/drm/msm/msm_gpu.h |   2 +
  drivers/gpu/drm/msm/msm_ringbuffer.c  |   7 +
  drivers/gpu/drm/msm/msm_ringbuffer.h  |   3 +
  drivers/gpu/drm/msm/msm_sched.c   | 313 ++
  drivers/gpu/drm/msm/msm_sched.h   |  18 ++
  drivers/gpu/drm/msm/msm_submitqueue.c |  18 +-
  13 files changed, 507 insertions(+), 85 deletions(-)
  create mode 100644 drivers/gpu/drm/msm/msm_sched.c
  create mode 100644 drivers/gpu/drm/msm/msm_sched.h

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 38cbde9..0d01810 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -15,6 +15,7 @@ config DRM_MSM
select SND_SOC_HDMI_CODEC if SND_SOC
select SYNC_FILE
select PM_OPP
+   select DRM_SCHED
default y
help
  DRM/KMS driver for MSM/snapdragon.
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index cd40c05..71ed921 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -60,7 +60,8 @@ msm-y := \
msm_perf.o \
msm_rd.o \
msm_ringbuffer.o \
-   msm_submitqueue.o
+   msm_submitqueue.o \
+   msm_sched.o
  
  msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o
  
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h

index b2da1fb..e461a9c 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -213,8 +213,7 @@ struct drm_gem_object *msm_gem_prime_import_sg_table(struct 
drm_device *dev,
  int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
  int msm_gem_sync_object(struct drm_gem_object *obj,
struct msm_fence_context *fctx, bool exclusive);
-void msm_gem_move_to_active(struct drm_gem_object *obj,
-   struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
+void msm_gem_move_to_active(struct drm_gem_object *obj, struct msm_gpu *gpu);
  void msm_gem_move_to_inactive(struct drm_gem_object *obj);
  int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t 
*timeout);
  int msm_gem_cpu_fini(struct drm_gem_object *obj);
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index f583bb4..7a12f30 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -663,16 +663,12 @@ int msm_gem_sync_object(struct drm_gem_object *obj,
return 0;
  }
  
-void msm_gem_move_to_active(struct drm_gem_object *obj,

-   struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence)
+void msm_gem_move_to_active(struct drm_gem_object *obj, struct msm_gpu *gpu)
  {
struct msm_gem_object *msm_obj = to_msm_bo(obj);
WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED);
msm_obj->gpu = gpu;
-   if (exclusive)
-   reservation_object_add_excl_fence(msm_obj->resv, fence);
-   else
-   reservation_object_add_shared_fence(msm_obj->resv, fence);
+
list_del_init(_obj->mm_list);
list_add_tail(_obj->mm_list, >active_list);
  }
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index cae3aa5..8c6269f 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -20,6 +20,7 @@
  
  #include 

  #include 
+#include 
  #include "msm_drv.h"
  
  /* Additional 

[Freedreno] [PATCH 11/18] drm/msm: Use drm_atomic_helper_shutdown

[Daniel Vetter]

drm_plane_helper_disable is a non-atomic drivers only function, and
will blow up (since no one passes the locking context it needs).

Atomic drivers which want to quiescent their hw on unload should
use drm_atomic_helper_shutdown() instead.

Signed-off-by: Daniel Vetter 
Cc: Rob Clark 
Cc: Rajesh Yadav 
Cc: Chandan Uddaraju 
Cc: Archit Taneja 
Cc: Jeykumar Sankaran 
Cc: Sean Paul 
Cc: Maarten Lankhorst 
Cc: Sinclair Yeh 
Cc: "Ville Syrjälä" 
Cc: Russell King 
Cc: Gustavo Padovan 
Cc: Arnd Bergmann 
Cc: linux-arm-...@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 2 --
 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 1 -
 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 1 -
 drivers/gpu/drm/msm/msm_drv.c  | 1 +
 4 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 015341e2dd4c..ec959f847d5f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1482,8 +1482,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
 
mutex_destroy(>lock);
 
-   drm_plane_helper_disable(plane, NULL);
-
/* this will destroy the states as well */
drm_plane_cleanup(plane);
 
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index 79ff653d8081..7a499731ce93 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -68,7 +68,6 @@ static void mdp4_plane_destroy(struct drm_plane *plane)
 {
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
 
-   drm_plane_helper_disable(plane, NULL);
drm_plane_cleanup(plane);
 
kfree(mdp4_plane);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 7d306c5acd09..d5e4f0de321a 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -46,7 +46,6 @@ static void mdp5_plane_destroy(struct drm_plane *plane)
 {
struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
 
-   drm_plane_helper_disable(plane, NULL);
drm_plane_cleanup(plane);
 
kfree(mdp5_plane);
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index c1abad8a8612..69dbdba183fe 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -312,6 +312,7 @@ static int msm_drm_uninit(struct device *dev)
if (fbdev && priv->fbdev)
msm_fbdev_free(ddev);
 #endif
+   drm_atomic_helper_shutdown(ddev);
drm_mode_config_cleanup(ddev);
 
pm_runtime_get_sync(dev);
-- 
2.19.0.rc2

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