[Freedreno] [PATCH 25/25] drm/msm/dpu: maintain RM init check internally
Move and maintain RM initialization flag checks
from KMS to RM.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 3 +++
4 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fdc89a8..59ccc46 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -668,9 +668,7 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
}
}
- if (dpu_kms->rm_init)
- dpu_rm_destroy(_kms->rm);
- dpu_kms->rm_init = false;
+ dpu_rm_destroy(_kms->rm);
if (dpu_kms->catalog)
dpu_hw_catalog_deinit(dpu_kms->catalog);
@@ -1085,8 +1083,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto power_error;
}
- dpu_kms->rm_init = true;
-
dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
dpu_kms->catalog);
if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 66d4666..1fff795 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -140,7 +140,6 @@ struct dpu_kms {
bool suspend_block;
struct dpu_rm rm;
- bool rm_init;
struct dpu_hw_vbif *hw_vbif[VBIF_MAX];
struct dpu_hw_mdp *hw_mdp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 9a63128..3452fb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -65,6 +65,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
struct dpu_rm_hw_blk *hw_cur, *hw_nxt;
enum dpu_hw_blk_type type;
+ if (!rm->initialized)
+ return 0;
+
for (type = 0; type < DPU_HW_BLK_MAX; type++) {
list_for_each_entry_safe(hw_cur, hw_nxt, >hw_blks[type],
list) {
@@ -74,6 +77,8 @@ int dpu_rm_destroy(struct dpu_rm *rm)
}
}
+ rm->initialized = false;
+
return 0;
}
@@ -141,6 +146,11 @@ int dpu_rm_init(struct dpu_rm *rm,
return -EINVAL;
}
+ if (rm->initialized) {
+ DPU_DEBUG("RM is already initialized\n");
+ return 0;
+ }
+
/* Clear, setup lists */
memset(rm, 0, sizeof(*rm));
@@ -196,6 +206,8 @@ int dpu_rm_init(struct dpu_rm *rm,
}
}
+ rm->initialized = true;
+
return 0;
fail:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 9acbeba..74e5d58 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,9 +24,12 @@
* struct dpu_rm - DPU dynamic hardware resource manager
* @hw_blks: array of lists of hardware resources present in the system, one
* list per type of hardware block
+ * @initialized: True, when RM is initialized with hw block list.
+ * False, otherwise
*/
struct dpu_rm {
struct list_head hw_blks[DPU_HW_BLK_MAX];
+ bool initialized;
};
/**
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[Freedreno] [PATCH 14/25] drm/msm/dpu: remove enc_id tagging for hw blocks
RM was using encoder id's to tag HW block's to reserve
and retrieve later for display pipeline. Now
that all the reserved HW blocks for a display are
maintained in its crtc state, no retrieval is needed.
This patch cleans up RM of encoder id tagging.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 90 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 28 --
2 files changed, 36 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 303f1b3..a8461b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -21,9 +21,6 @@
#include "dpu_encoder.h"
#include "dpu_trace.h"
-#define RESERVED_BY_OTHER(h, r) \
- ((h)->enc_id && (h)->enc_id != r)
-
/**
* struct dpu_rm_requirements - Reservation requirements parameter bundle
* @topology: selected topology for the display
@@ -38,12 +35,13 @@ struct dpu_rm_requirements {
/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @list: List head for list of all hardware blocks tracking items
- * @enc_id:Encoder id to which this blk is binded
+ * @in_use: True, if the hw block is assigned to a display pipeline.
+ * False, otherwise
* @hw:Pointer to the hardware register access object for this
block
*/
struct dpu_rm_hw_blk {
struct list_head list;
- uint32_t enc_id;
+ bool in_use;
struct dpu_hw_blk *hw;
};
@@ -51,23 +49,19 @@ struct dpu_rm_hw_blk {
* struct dpu_rm_hw_iter - iterator for use with dpu_rm
* @hw: dpu_hw object requested, or NULL on failure
* @blk: dpu_rm internal block representation. Clients ignore. Used as
iterator.
- * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
* @type: Hardware Block Type client wishes to search for.
*/
struct dpu_rm_hw_iter {
struct dpu_hw_blk *hw;
struct dpu_rm_hw_blk *blk;
- uint32_t enc_id;
enum dpu_hw_blk_type type;
};
static void _dpu_rm_init_hw_iter(
struct dpu_rm_hw_iter *iter,
- uint32_t enc_id,
enum dpu_hw_blk_type type)
{
memset(iter, 0, sizeof(*iter));
- iter->enc_id = enc_id;
iter->type = type;
}
@@ -91,16 +85,12 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct
dpu_rm_hw_iter *i)
i->blk = list_prepare_entry(i->blk, blk_list, list);
list_for_each_entry_continue(i->blk, blk_list, list) {
- if (i->enc_id == i->blk->enc_id) {
+ if (!i->blk->in_use) {
i->hw = i->blk->hw;
- DPU_DEBUG("found type %d id %d for enc %d\n",
- i->type, i->blk->hw->id, i->enc_id);
return true;
}
}
- DPU_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
-
return false;
}
@@ -196,7 +186,6 @@ static int _dpu_rm_hw_blk_create(
}
blk->hw = hw;
- blk->enc_id = 0;
list_add_tail(>list, >hw_blks[type]);
return 0;
@@ -301,7 +290,6 @@ static bool _dpu_rm_needs_split_display(const struct
msm_display_topology *top)
* proposed use case requirements, incl. hardwired dependent blocks like
* pingpong
* @rm: dpu resource manager handle
- * @enc_id: encoder id requesting for allocation
* @reqs: proposed use case requirements
* @lm: proposed layer mixer, function checks if lm, and all other hardwired
* blocks connected to the lm (pp) is available and appropriate
@@ -313,7 +301,6 @@ static bool _dpu_rm_needs_split_display(const struct
msm_display_topology *top)
*/
static bool _dpu_rm_check_lm_and_get_connected_blks(
struct dpu_rm *rm,
- uint32_t enc_id,
struct dpu_rm_requirements *reqs,
struct dpu_rm_hw_blk *lm,
struct dpu_rm_hw_blk **pp,
@@ -339,13 +326,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
}
}
- /* Already reserved? */
- if (RESERVED_BY_OTHER(lm, enc_id)) {
- DPU_DEBUG("lm %d already reserved\n", lm_cfg->id);
- return false;
- }
-
- _dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_PINGPONG);
+ _dpu_rm_init_hw_iter(, DPU_HW_BLK_PINGPONG);
while (_dpu_rm_get_hw_locked(rm, )) {
if (iter.blk->hw->id == lm_cfg->pingpong) {
*pp = iter.blk;
@@ -358,16 +339,10 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
return false;
}
- if (RESERVED_BY_OTHER(*pp, enc_id)) {
- DPU_DEBUG("lm %d pp %d already reserved\n", lm->hw->id,
- (*pp)->hw->id);
- return false;
- }
-
return true;
}
-static int _dpu_rm_reserve_lms(struct
[Freedreno] [PATCH 17/25] drm/msm/dpu: remove RM HW block list iterator
Replacing with simpler linked list helper iterators.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 120 +
1 file changed, 46 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 1234991..a79456c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -45,49 +45,6 @@ struct dpu_rm_hw_blk {
struct dpu_hw_blk *hw;
};
-/**
- * struct dpu_rm_hw_iter - iterator for use with dpu_rm
- * @blk: dpu_rm internal block representation. Clients ignore. Used as
iterator.
- * @type: Hardware Block Type client wishes to search for.
- */
-struct dpu_rm_hw_iter {
- struct dpu_rm_hw_blk *blk;
- enum dpu_hw_blk_type type;
-};
-
-static void _dpu_rm_init_hw_iter(
- struct dpu_rm_hw_iter *iter,
- enum dpu_hw_blk_type type)
-{
- memset(iter, 0, sizeof(*iter));
- iter->type = type;
-}
-
-static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
-{
- struct list_head *blk_list;
-
- if (!rm || !i || i->type >= DPU_HW_BLK_MAX) {
- DPU_ERROR("invalid rm\n");
- return false;
- }
-
- blk_list = >hw_blks[i->type];
-
- if (i->blk && (>blk->list == blk_list)) {
- DPU_DEBUG("attempt resume iteration past last\n");
- return false;
- }
-
- i->blk = list_prepare_entry(i->blk, blk_list, list);
-
- list_for_each_entry_continue(i->blk, blk_list, list)
- if (!i->blk->in_use)
- return true;
-
- return false;
-}
-
static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
{
switch (type) {
@@ -301,7 +258,8 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
struct dpu_rm_hw_blk *primary_lm)
{
const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
- struct dpu_rm_hw_iter iter;
+ struct dpu_rm_hw_blk *iter;
+ struct list_head *blk_list = >hw_blks[DPU_HW_BLK_PINGPONG];
*pp = NULL;
@@ -320,10 +278,12 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
}
}
- _dpu_rm_init_hw_iter(, DPU_HW_BLK_PINGPONG);
- while (_dpu_rm_get_hw_locked(rm, )) {
- if (iter.blk->hw->id == lm_cfg->pingpong) {
- *pp = iter.blk;
+ list_for_each_entry(iter, blk_list, list) {
+ if (iter->in_use)
+ continue;
+
+ if (iter->hw->id == lm_cfg->pingpong) {
+ *pp = iter;
break;
}
}
@@ -343,7 +303,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
{
struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
struct dpu_rm_hw_blk *pp[MAX_BLOCKS];
- struct dpu_rm_hw_iter iter_i, iter_j;
+ struct dpu_rm_hw_blk *iter_i, *iter_j;
+ struct list_head *blk_list = >hw_blks[DPU_HW_BLK_LM];
int lm_count = 0;
int i, rc = 0;
@@ -353,14 +314,18 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
}
/* Find a primary mixer */
- _dpu_rm_init_hw_iter(_i, DPU_HW_BLK_LM);
- while (lm_count != reqs->topology.num_lm &&
- _dpu_rm_get_hw_locked(rm, _i)) {
+ list_for_each_entry(iter_i, blk_list, list) {
+ if (iter_i->in_use)
+ continue;
+
+ if (lm_count == reqs->topology.num_lm)
+ break;
+
memset(, 0, sizeof(lm));
memset(, 0, sizeof(pp));
lm_count = 0;
- lm[lm_count] = iter_i.blk;
+ lm[lm_count] = iter_i;
if (!_dpu_rm_check_lm_and_get_connected_blks(
rm, reqs, lm[lm_count],
@@ -370,19 +335,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
++lm_count;
/* Valid primary mixer found, find matching peers */
- _dpu_rm_init_hw_iter(_j, DPU_HW_BLK_LM);
+ list_for_each_entry(iter_j, blk_list, list) {
+ if (iter_j->in_use)
+ continue;
- while (lm_count != reqs->topology.num_lm &&
- _dpu_rm_get_hw_locked(rm, _j)) {
- if (iter_i.blk == iter_j.blk)
+ if (lm_count == reqs->topology.num_lm)
+ break;
+
+ if (iter_i == iter_j)
continue;
if (!_dpu_rm_check_lm_and_get_connected_blks(
- rm, reqs, iter_j.blk,
- [lm_count], iter_i.blk))
+ rm, reqs, iter_j,
+ [lm_count], iter_i))
[Freedreno] [PATCH 24/25] drm/msm/dpu: remove mutex locking for RM interfaces
Since HW reservations are happening through atomic_check
and all the display commits are catered by a single commit thread,
it is not necessary to protect the interfaces by a separate
mutex.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 24
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 --
2 files changed, 26 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 34e09aa..9a63128 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -74,8 +74,6 @@ int dpu_rm_destroy(struct dpu_rm *rm)
}
}
- mutex_destroy(>rm_lock);
-
return 0;
}
@@ -146,8 +144,6 @@ int dpu_rm_init(struct dpu_rm *rm,
/* Clear, setup lists */
memset(rm, 0, sizeof(*rm));
- mutex_init(>rm_lock);
-
for (type = 0; type < DPU_HW_BLK_MAX; type++)
INIT_LIST_HEAD(>hw_blks[type]);
@@ -473,11 +469,7 @@ void dpu_rm_crtc_release(struct dpu_rm *rm, struct
drm_crtc_state *crtc_state)
{
struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
- mutex_lock(>rm_lock);
-
_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
-
- mutex_unlock(>rm_lock);
}
void dpu_rm_encoder_release(struct dpu_rm *rm,
@@ -485,11 +477,7 @@ void dpu_rm_encoder_release(struct dpu_rm *rm,
{
struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
- mutex_lock(>rm_lock);
-
_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
-
- mutex_unlock(>rm_lock);
}
int dpu_rm_crtc_reserve(
@@ -506,8 +494,6 @@ int dpu_rm_crtc_reserve(
DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc_state->crtc->base.id);
- mutex_lock(>rm_lock);
-
ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
if (ret) {
DPU_ERROR("unable to find appropriate mixers\n");
@@ -520,15 +506,11 @@ int dpu_rm_crtc_reserve(
goto cleanup_on_fail;
}
- mutex_unlock(>rm_lock);
-
return ret;
cleanup_on_fail:
_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
- mutex_unlock(>rm_lock);
-
return ret;
}
@@ -547,8 +529,6 @@ int dpu_rm_encoder_reserve(
DRM_DEBUG_KMS("reserving hw for enc %d\n", enc->base.id);
- mutex_lock(>rm_lock);
-
dpu_encoder_get_hw_resources(enc, _res);
ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, _res);
@@ -557,14 +537,10 @@ int dpu_rm_encoder_reserve(
goto cleanup_on_fail;
}
- mutex_unlock(>rm_lock);
-
return ret;
cleanup_on_fail:
_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
- mutex_unlock(>rm_lock);
-
return ret;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 8676fa5..9acbeba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,11 +24,9 @@
* struct dpu_rm - DPU dynamic hardware resource manager
* @hw_blks: array of lists of hardware resources present in the system, one
* list per type of hardware block
- * @rm_lock: resource manager mutex
*/
struct dpu_rm {
struct list_head hw_blks[DPU_HW_BLK_MAX];
- struct mutex rm_lock;
};
/**
--
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[Freedreno] [PATCH 18/25] drm/msm/dpu: merge RM interface reservation helpers
we don't have enough reasons why the HW block looping's
cannot happen in the same function. So merge them.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 63 ++
1 file changed, 26 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index a79456c..bb59250 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -435,52 +435,39 @@ static int _dpu_rm_reserve_ctls(
return 0;
}
-static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
- struct dpu_rm *rm,
- uint32_t id,
- enum dpu_hw_blk_type type)
-{
- struct dpu_rm_hw_blk *iter;
- struct list_head *blk_list = >hw_blks[DPU_HW_BLK_INTF];
-
- /* Find the block entry in the rm, and note the reservation */
- list_for_each_entry(iter, blk_list, list) {
- if (iter->hw->id != id || iter->in_use)
- continue;
-
- trace_dpu_rm_reserve_intf(iter->hw->id, DPU_HW_BLK_INTF);
-
- break;
- }
-
- /* Shouldn't happen since intfs are fixed at probe */
- if (!iter) {
- DPU_ERROR("couldn't find type %d id %d\n", type, id);
- return NULL;
- }
-
- return iter;
-}
-
-static int _dpu_rm_reserve_intf_related_hw(
+static int _dpu_rm_reserve_intfs(
struct dpu_rm *rm,
struct dpu_crtc_state *dpu_cstate,
struct dpu_encoder_hw_resources *hw_res)
{
- struct dpu_rm_hw_blk *blk;
+ struct dpu_rm_hw_blk *iter;
+ struct list_head *blk_list = >hw_blks[DPU_HW_BLK_INTF];
int i, num_intfs = 0;
for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
+ struct dpu_rm_hw_blk *intf_blk = NULL;
+
if (hw_res->intfs[i] == INTF_MODE_NONE)
continue;
- blk = _dpu_rm_reserve_intf(rm, i + INTF_0,
- DPU_HW_BLK_INTF);
- if (!blk)
- return -ENAVAIL;
+ list_for_each_entry(iter, blk_list, list) {
+ if (iter->in_use)
+ continue;
+
+ if (iter->hw->id == (INTF_0 + i)) {
+ intf_blk = iter;
+ break;
+ }
+ }
+
+ if (!intf_blk)
+ return -EINVAL;
- blk->in_use = true;
- dpu_cstate->hw_intfs[num_intfs++] = to_dpu_hw_intf(blk->hw);
+ intf_blk->in_use = true;
+ dpu_cstate->hw_intfs[num_intfs++] =
+ to_dpu_hw_intf(intf_blk->hw);
+
+ trace_dpu_rm_reserve_intf(intf_blk->hw->id, DPU_HW_BLK_INTF);
}
dpu_cstate->num_intfs = num_intfs;
@@ -507,9 +494,11 @@ static int _dpu_rm_make_reservation(
return ret;
}
- ret = _dpu_rm_reserve_intf_related_hw(rm, dpu_cstate, >hw_res);
- if (ret)
+ ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, >hw_res);
+ if (ret) {
+ DPU_ERROR("unable to find appropriate INTF\n");
return ret;
+ }
return ret;
}
--
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[Freedreno] [PATCH 15/25] drm/msm/dpu: avoid redundant hw blk reference
Get rid of hw block pointer in RM iter as we can
access the same through dpu_hw_blk.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index a8461b8..3a92a3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -47,12 +47,10 @@ struct dpu_rm_hw_blk {
/**
* struct dpu_rm_hw_iter - iterator for use with dpu_rm
- * @hw: dpu_hw object requested, or NULL on failure
* @blk: dpu_rm internal block representation. Clients ignore. Used as
iterator.
* @type: Hardware Block Type client wishes to search for.
*/
struct dpu_rm_hw_iter {
- struct dpu_hw_blk *hw;
struct dpu_rm_hw_blk *blk;
enum dpu_hw_blk_type type;
};
@@ -74,7 +72,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct
dpu_rm_hw_iter *i)
return false;
}
- i->hw = NULL;
blk_list = >hw_blks[i->type];
if (i->blk && (>blk->list == blk_list)) {
@@ -84,12 +81,9 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct
dpu_rm_hw_iter *i)
i->blk = list_prepare_entry(i->blk, blk_list, list);
- list_for_each_entry_continue(i->blk, blk_list, list) {
- if (!i->blk->in_use) {
- i->hw = i->blk->hw;
+ list_for_each_entry_continue(i->blk, blk_list, list)
+ if (!i->blk->in_use)
return true;
- }
- }
return false;
}
--
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[Freedreno] [PATCH 12/25] drm/msm/dpu: remove mode_set_complete
This flag was introduced as a fix to notify modeset complete
when hw reservations were happening in both atomic_check
and atomic_commit paths. Now that we are reserving only in
atomic_check, we can get rid of this flag.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++
1 file changed, 3 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dd482ca..468b8fd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -167,7 +167,6 @@ enum dpu_enc_rc_states {
* clks and resources after IDLE_TIMEOUT time.
* @vsync_event_work: worker to handle vsync event for autorefresh
* @topology: topology of the display
- * @mode_set_complete: flag to indicate modeset completion
* @idle_timeout: idle timeout duration in milliseconds
*/
struct dpu_encoder_virt {
@@ -204,7 +203,6 @@ struct dpu_encoder_virt {
struct kthread_delayed_work delayed_off_work;
struct kthread_work vsync_event_work;
struct msm_display_topology topology;
- bool mode_set_complete;
u32 idle_timeout;
};
@@ -636,18 +634,9 @@ static int dpu_encoder_virt_atomic_check(
topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
- if (!ret) {
- /*
-* Avoid reserving resources when mode set is pending. Topology
-* info may not be available to complete reservation.
-*/
- if (drm_atomic_crtc_needs_modeset(crtc_state)
- && dpu_enc->mode_set_complete) {
- ret = dpu_rm_reserve(_kms->rm, drm_enc, crtc_state,
-topology, false);
- dpu_enc->mode_set_complete = false;
- }
- }
+ if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
+ ret = dpu_rm_reserve(_kms->rm, drm_enc, crtc_state,
+topology, false);
if (!ret)
drm_mode_set_crtcinfo(adj_mode, 0);
@@ -1060,8 +1049,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
phys->ops.mode_set(phys, mode, adj_mode);
}
}
-
- dpu_enc->mode_set_complete = true;
}
static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
--
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[Freedreno] [PATCH 20/25] drm/msm/dpu: refine layer mixer reservations
Validate layer mixer pairs for compatibility before retrieving
the connected pingpong blocks.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 61 ++
1 file changed, 17 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 85a0fe2..f794d13 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -235,61 +235,32 @@ static bool _dpu_rm_needs_split_display(const struct
dpu_crtc_state *dpu_cstate)
}
/**
- * _dpu_rm_check_lm_and_get_connected_blks - check if proposed layer mixer
meets
- * proposed use case requirements, incl. hardwired dependent blocks like
- * pingpong
+ * _dpu_rm_get_connected_pp - retrieve hardwired pingpong block
* @rm: dpu resource manager handle
* @lm: proposed layer mixer, function checks if lm, and all other hardwired
- * blocks connected to the lm (pp) is available and appropriate
- * @pp: output parameter, pingpong block attached to the layer mixer.
- * NULL if pp was not available, or not matching requirements.
- * @primary_lm: if non-null, this function check if lm is compatible primary_lm
- * as well as satisfying all other requirements
- * @Return: true if lm matches all requirements, false otherwise
+ * @Return: handle to ping pong rm block
*/
-static bool _dpu_rm_check_lm_and_get_connected_blks(
- struct dpu_rm *rm,
- struct dpu_rm_hw_blk *lm,
- struct dpu_rm_hw_blk **pp,
- struct dpu_rm_hw_blk *primary_lm)
+static struct dpu_rm_hw_blk *
+_dpu_rm_get_connected_pp(struct dpu_rm *rm, struct dpu_rm_hw_blk *lm)
{
const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
- struct dpu_rm_hw_blk *iter;
struct list_head *blk_list = >hw_blks[DPU_HW_BLK_PINGPONG];
-
- *pp = NULL;
-
- DPU_DEBUG("check lm %d pp %d\n",
- lm_cfg->id, lm_cfg->pingpong);
-
- /* Check if this layer mixer is a peer of the proposed primary LM */
- if (primary_lm) {
- const struct dpu_lm_cfg *prim_lm_cfg =
- to_dpu_hw_mixer(primary_lm->hw)->cap;
-
- if (!test_bit(lm_cfg->id, _lm_cfg->lm_pair_mask)) {
- DPU_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
- prim_lm_cfg->id);
- return false;
- }
- }
+ struct dpu_rm_hw_blk *iter, *pp = NULL;
list_for_each_entry(iter, blk_list, list) {
if (iter->in_use)
continue;
if (iter->hw->id == lm_cfg->pingpong) {
- *pp = iter;
+ pp = iter;
break;
}
}
- if (!*pp) {
- DPU_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
- return false;
- }
+ if (!pp)
+ DPU_ERROR("failed to get pp on lm %d\n", lm->hw->id);
- return true;
+ return pp;
}
static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
@@ -315,15 +286,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
lm_count = 0;
lm[lm_count] = iter_i;
-
- if (!_dpu_rm_check_lm_and_get_connected_blks(
- rm, lm[lm_count], [lm_count], NULL))
- continue;
+ pp[lm_count] = _dpu_rm_get_connected_pp(rm, iter_i);
++lm_count;
/* Valid primary mixer found, find matching peers */
list_for_each_entry(iter_j, blk_list, list) {
+ const struct dpu_lm_cfg *prim_lm_cfg =
+ to_dpu_hw_mixer(iter_i->hw)->cap;
+
if (iter_j->in_use)
continue;
@@ -333,11 +304,13 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
if (iter_i == iter_j)
continue;
- if (!_dpu_rm_check_lm_and_get_connected_blks(
- rm, iter_j, [lm_count], iter_i))
+ if (!test_bit(iter_j->hw->id,
+ _lm_cfg->lm_pair_mask))
continue;
lm[lm_count] = iter_j;
+ pp[lm_count] = _dpu_rm_get_connected_pp(rm, iter_j);
+
++lm_count;
}
}
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[Freedreno] [PATCH 19/25] drm/msm/dpu: remove msm_display_topology
msm_display_topology was used for providing HW block
layout of the pipeline for a specific display topology.
We already got rid of its usage from DSI driver. In DPU,
it was used to provide the details on HW blocks while
reserving resources. Since we can use the crtc state used
for storing the assigned HW blocks for providing the info,
we can conveniently get rid of this structure.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 --
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 82 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 4 +-
drivers/gpu/drm/msm/msm_drv.h | 12 -
4 files changed, 33 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dd17528..5d501c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -166,7 +166,6 @@ enum dpu_enc_rc_states {
* @delayed_off_work: delayed worker to schedule disabling of
* clks and resources after IDLE_TIMEOUT time.
* @vsync_event_work: worker to handle vsync event for autorefresh
- * @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
*/
struct dpu_encoder_virt {
@@ -202,7 +201,6 @@ struct dpu_encoder_virt {
enum dpu_enc_rc_states rc_state;
struct kthread_delayed_work delayed_off_work;
struct kthread_work vsync_event_work;
- struct msm_display_topology topology;
u32 idle_timeout;
};
@@ -557,25 +555,19 @@ static void _dpu_encoder_adjust_mode(struct drm_connector
*connector,
}
}
-static struct msm_display_topology dpu_encoder_get_topology(
+static void _dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
- struct dpu_kms *dpu_kms,
+ struct drm_crtc_state *crtc_state,
struct drm_display_mode *mode)
{
- struct msm_display_topology topology;
- int i, intf_count = 0;
-
- for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
- if (dpu_enc->phys_encs[i])
- intf_count++;
+ struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
/* User split topology for width > 1080 */
- topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
- topology.num_enc = 0;
- topology.num_intf = intf_count;
-
- return topology;
+ dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
+ dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
+ dpu_cstate->num_intfs = dpu_enc->num_phys_encs;
}
+
static int dpu_encoder_virt_atomic_check(
struct drm_encoder *drm_enc,
struct drm_crtc_state *crtc_state,
@@ -586,7 +578,6 @@ static int dpu_encoder_virt_atomic_check(
struct dpu_kms *dpu_kms;
const struct drm_display_mode *mode;
struct drm_display_mode *adj_mode;
- struct msm_display_topology topology;
int i = 0;
int ret = 0;
@@ -632,11 +623,9 @@ static int dpu_encoder_virt_atomic_check(
}
}
- topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
-
+ _dpu_encoder_get_topology(dpu_enc, crtc_state, adj_mode);
if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
- ret = dpu_rm_reserve(_kms->rm, drm_enc, crtc_state,
-topology);
+ ret = dpu_rm_reserve(_kms->rm, drm_enc, crtc_state);
if (!ret)
drm_mode_set_crtcinfo(adj_mode, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index bb59250..85a0fe2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -23,11 +23,9 @@
/**
* struct dpu_rm_requirements - Reservation requirements parameter bundle
- * @topology: selected topology for the display
* @hw_res: Hardware resources required as reported by the encoders
*/
struct dpu_rm_requirements {
- struct msm_display_topology topology;
struct dpu_encoder_hw_resources hw_res;
};
@@ -231,9 +229,9 @@ int dpu_rm_init(struct dpu_rm *rm,
return rc;
}
-static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
+static bool _dpu_rm_needs_split_display(const struct dpu_crtc_state
*dpu_cstate)
{
- return top->num_intf > 1;
+ return dpu_cstate->num_intfs > 1;
}
/**
@@ -241,7 +239,6 @@ static bool _dpu_rm_needs_split_display(const struct
msm_display_topology *top)
* proposed use case requirements, incl. hardwired dependent blocks like
* pingpong
* @rm: dpu resource manager handle
- * @reqs: proposed use case requirements
* @lm: proposed layer mixer, function checks if
[Freedreno] [PATCH 22/25] drm/msm/dpu: make crtc and encoder specific HW reservation
Instead of letting encoder make a centralized reservation for
all of its display DRM components, this path splits the
responsibility between CRTC and Encoder, each requesting
RM for the HW mapping of its own domain.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 31 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 69 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 36 +++
4 files changed, 119 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 0625f56..0536b8a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,6 +47,8 @@
#define LEFT_MIXER 0
#define RIGHT_MIXER 1
+#define MAX_VDISPLAY_SPLIT 1080
+
static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate,
struct drm_display_mode *mode)
{
@@ -448,6 +450,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
for (i = 0; i < cstate->num_mixers; i++) {
struct drm_rect *r = >lm_bounds[i];
+
r->x1 = crtc_split_width * i;
r->y1 = 0;
r->x2 = r->x1 + crtc_split_width;
@@ -885,6 +888,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_display_mode *mode;
struct drm_encoder *encoder;
struct msm_drm_private *priv;
+ struct dpu_kms *dpu_kms;
unsigned long flags;
if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
@@ -895,6 +899,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
cstate = to_dpu_crtc_state(crtc->state);
mode = >base.adjusted_mode;
priv = crtc->dev->dev_private;
+ dpu_kms = to_dpu_kms(priv->kms);
DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
@@ -953,6 +958,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
crtc->state->event = NULL;
spin_unlock_irqrestore(>dev->event_lock, flags);
}
+
+ dpu_rm_crtc_release(_kms->rm, crtc->state);
}
static void dpu_crtc_enable(struct drm_crtc *crtc,
@@ -1004,6 +1011,21 @@ struct plane_state {
u32 pipe_id;
};
+static void _dpu_crtc_get_topology(
+ struct drm_crtc_state *crtc_state,
+ struct drm_display_mode *mode)
+{
+ struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
+
+ dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
+
+ /**
+* encoder->atomic_check is invoked before crtc->atomic_check.
+* so dpu_cstate->num_intfs should have a non-zero value.
+*/
+ dpu_cstate->num_ctls = dpu_cstate->num_intfs;
+}
+
static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
@@ -1014,6 +1036,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
const struct drm_plane_state *pstate;
struct drm_plane *plane;
struct drm_display_mode *mode;
+ struct msm_drm_private *priv;
+ struct dpu_kms *dpu_kms;
int cnt = 0, rc = 0, mixer_width, i, z_pos;
@@ -1039,6 +1063,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
goto end;
}
+ priv = crtc->dev->dev_private;
+ dpu_kms = to_dpu_kms(priv->kms);
+
mode = >adjusted_mode;
DPU_DEBUG("%s: check", dpu_crtc->name);
@@ -1229,6 +1256,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
}
}
+ _dpu_crtc_get_topology(state, mode);
+ if (drm_atomic_crtc_needs_modeset(state))
+ rc = dpu_rm_crtc_reserve(_kms->rm, state);
+
end:
kfree(pstates);
return rc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5d501c8..ce66309 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -67,8 +67,6 @@
#define IDLE_SHORT_TIMEOUT 1
-#define MAX_VDISPLAY_SPLIT 1080
-
/**
* enum dpu_enc_rc_events - events for resource control state machine
* @DPU_ENC_RC_EVENT_KICKOFF:
@@ -557,14 +555,10 @@ static void _dpu_encoder_adjust_mode(struct drm_connector
*connector,
static void _dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
- struct drm_crtc_state *crtc_state,
- struct drm_display_mode *mode)
+ struct drm_crtc_state *crtc_state)
{
struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
- /* User split topology for width > 1080 */
- dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
- dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
[Freedreno] [PATCH 21/25] drm/msm/dpu: merge RM reservation helpers
We cleaned up RM reserve api's enough to get rid of
most of its unwanted checks and release handlers. To
improve further the readability of the function, merging
down the individual HW type allocators into one function.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 73 +++---
1 file changed, 24 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f794d13..5304597 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -22,15 +22,6 @@
#include "dpu_trace.h"
/**
- * struct dpu_rm_requirements - Reservation requirements parameter bundle
- * @hw_res: Hardware resources required as reported by the encoders
- */
-struct dpu_rm_requirements {
- struct dpu_encoder_hw_resources hw_res;
-};
-
-
-/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @list: List head for list of all hardware blocks tracking items
* @in_use: True, if the hw block is assigned to a display pipeline.
@@ -427,41 +418,6 @@ static int _dpu_rm_reserve_intfs(
return 0;
}
-static int _dpu_rm_make_reservation(
- struct dpu_rm *rm,
- struct dpu_crtc_state *dpu_cstate,
- struct dpu_rm_requirements *reqs)
-{
- int ret;
-
- ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
- if (ret) {
- DPU_ERROR("unable to find appropriate mixers\n");
- return ret;
- }
-
- ret = _dpu_rm_reserve_ctls(rm, dpu_cstate);
- if (ret) {
- DPU_ERROR("unable to find appropriate CTL\n");
- return ret;
- }
-
- ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, >hw_res);
- if (ret) {
- DPU_ERROR("unable to find appropriate INTF\n");
- return ret;
- }
-
- return ret;
-}
-
-static void _dpu_rm_populate_requirements(
- struct drm_encoder *enc,
- struct dpu_rm_requirements *reqs)
-{
- dpu_encoder_get_hw_resources(enc, >hw_res);
-}
-
static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
int id)
{
@@ -535,7 +491,7 @@ int dpu_rm_reserve(
struct drm_encoder *enc,
struct drm_crtc_state *crtc_state)
{
- struct dpu_rm_requirements reqs;
+ struct dpu_encoder_hw_resources hw_res;
struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
int ret;
@@ -548,14 +504,33 @@ int dpu_rm_reserve(
mutex_lock(>rm_lock);
- _dpu_rm_populate_requirements(enc, );
+ dpu_encoder_get_hw_resources(enc, _res);
- ret = _dpu_rm_make_reservation(rm, dpu_cstate, );
+ ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
if (ret) {
- DPU_ERROR("failed to reserve hw resources: %d\n", ret);
- _dpu_rm_release_reservation(rm, dpu_cstate);
+ DPU_ERROR("unable to find appropriate mixers\n");
+ goto cleanup_on_fail;
}
+ ret = _dpu_rm_reserve_ctls(rm, dpu_cstate);
+ if (ret) {
+ DPU_ERROR("unable to find appropriate CTL\n");
+ goto cleanup_on_fail;
+ }
+
+ ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, _res);
+ if (ret) {
+ DPU_ERROR("unable to find appropriate INTF\n");
+ goto cleanup_on_fail;
+ }
+
+ mutex_unlock(>rm_lock);
+
+ return ret;
+
+cleanup_on_fail:
+ _dpu_rm_release_reservation(rm, dpu_cstate);
+
mutex_unlock(>rm_lock);
return ret;
--
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[Freedreno] [PATCH 16/25] drm/msm/dpu: clean up test_only flag for RM reservation
Encoder uses test_only flag to differentiate RM reservations
invoked from atomic check and atomic_commit phases.
After reserving the HW blocks, if test_only was set, RM
releases the reservation. Retains them if not. Since we
got rid of RM reserve call from atomic_commit path, get rid
of this flag.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 13 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 4 +---
3 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 468b8fd0..dd17528 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -636,7 +636,7 @@ static int dpu_encoder_virt_atomic_check(
if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
ret = dpu_rm_reserve(_kms->rm, drm_enc, crtc_state,
-topology, false);
+topology);
if (!ret)
drm_mode_set_crtcinfo(adj_mode, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 3a92a3e..1234991 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -631,8 +631,7 @@ int dpu_rm_reserve(
struct dpu_rm *rm,
struct drm_encoder *enc,
struct drm_crtc_state *crtc_state,
- struct msm_display_topology topology,
- bool test_only)
+ struct msm_display_topology topology)
{
struct dpu_rm_requirements reqs;
struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
@@ -642,8 +641,8 @@ int dpu_rm_reserve(
if (!drm_atomic_crtc_needs_modeset(crtc_state))
return 0;
- DRM_DEBUG_KMS("reserving hw for enc %d crtc %d test_only %d\n",
- enc->base.id, crtc_state->crtc->base.id, test_only);
+ DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n",
+ enc->base.id, crtc_state->crtc->base.id);
mutex_lock(>rm_lock);
@@ -657,13 +656,7 @@ int dpu_rm_reserve(
if (ret) {
DPU_ERROR("failed to reserve hw resources: %d\n", ret);
_dpu_rm_release_reservation(rm, dpu_cstate);
- } else if (test_only) {
-/* test_only: test the reservation and then undo */
- DPU_DEBUG("test_only: discard test [enc: %d]\n",
- enc->base.id);
- _dpu_rm_release_reservation(rm, dpu_cstate);
}
-
end:
mutex_unlock(>rm_lock);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 7ac1553..415eeec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -63,14 +63,12 @@ int dpu_rm_init(struct dpu_rm *rm,
* @drm_enc: DRM Encoder handle
* @crtc_state: Proposed Atomic DRM CRTC State handle
* @topology: Pointer to topology info for the display
- * @test_only: Atomic-Test phase, discard results (unless property overrides)
* @Return: 0 on Success otherwise -ERROR
*/
int dpu_rm_reserve(struct dpu_rm *rm,
struct drm_encoder *drm_enc,
struct drm_crtc_state *crtc_state,
- struct msm_display_topology topology,
- bool test_only);
+ struct msm_display_topology topology);
/**
* dpu_rm_release - Given the encoder for the display chain, release any
--
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[Freedreno] [PATCH 10/25] drm/msm/dpu: maintain hw_mdp in kms
hw_mdp block is common for displays. No need
to reserve per display.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 20
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 10 --
3 files changed, 6 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 8309850..fdc89a8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -689,6 +689,10 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
devm_iounmap(_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
dpu_kms->vbif[VBIF_RT] = NULL;
+ if (dpu_kms->hw_mdp)
+ dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
+ dpu_kms->hw_mdp = NULL;
+
if (dpu_kms->mmio)
devm_iounmap(_kms->pdev->dev, dpu_kms->mmio);
dpu_kms->mmio = NULL;
@@ -1083,7 +1087,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
dpu_kms->rm_init = true;
- dpu_kms->hw_mdp = dpu_rm_get_mdp(_kms->rm);
+ dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
+dpu_kms->catalog);
if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) {
rc = PTR_ERR(dpu_kms->hw_mdp);
if (!dpu_kms->hw_mdp)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 24fc1c7..561120d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -63,11 +63,6 @@ struct dpu_rm_hw_iter {
enum dpu_hw_blk_type type;
};
-struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
-{
- return rm->hw_mdp;
-}
-
static void _dpu_rm_init_hw_iter(
struct dpu_rm_hw_iter *iter,
uint32_t enc_id,
@@ -151,9 +146,6 @@ int dpu_rm_destroy(struct dpu_rm *rm)
}
}
- dpu_hw_mdp_destroy(rm->hw_mdp);
- rm->hw_mdp = NULL;
-
mutex_destroy(>rm_lock);
return 0;
@@ -168,11 +160,8 @@ static int _dpu_rm_hw_blk_create(
void *hw_catalog_info)
{
struct dpu_rm_hw_blk *blk;
- struct dpu_hw_mdp *hw_mdp;
void *hw;
- hw_mdp = rm->hw_mdp;
-
switch (type) {
case DPU_HW_BLK_LM:
hw = dpu_hw_lm_init(id, mmio, cat);
@@ -236,15 +225,6 @@ int dpu_rm_init(struct dpu_rm *rm,
for (type = 0; type < DPU_HW_BLK_MAX; type++)
INIT_LIST_HEAD(>hw_blks[type]);
- /* Some of the sub-blocks require an mdptop to be created */
- rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat);
- if (IS_ERR_OR_NULL(rm->hw_mdp)) {
- rc = PTR_ERR(rm->hw_mdp);
- rm->hw_mdp = NULL;
- DPU_ERROR("failed: mdp hw not available\n");
- goto fail;
- }
-
/* Interrogate HW catalog and create tracking items for hw blocks */
for (i = 0; i < cat->mixer_count; i++) {
struct dpu_lm_cfg *lm = >mixer[i];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index c7e3b2b..7ac1553 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,13 +24,11 @@
* struct dpu_rm - DPU dynamic hardware resource manager
* @hw_blks: array of lists of hardware resources present in the system, one
* list per type of hardware block
- * @hw_mdp: hardware object for mdp_top
* @lm_max_width: cached layer mixer maximum width
* @rm_lock: resource manager mutex
*/
struct dpu_rm {
struct list_head hw_blks[DPU_HW_BLK_MAX];
- struct dpu_hw_mdp *hw_mdp;
uint32_t lm_max_width;
struct mutex rm_lock;
};
@@ -82,12 +80,4 @@ int dpu_rm_reserve(struct dpu_rm *rm,
* @Return: 0 on Success otherwise -ERROR
*/
void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
-
-/**
- * dpu_rm_get_mdp - Retrieve HW block for MDP TOP.
- * This is never reserved, and is usable by any display.
- * @rm: DPU Resource Manager handle
- * @Return: Pointer to hw block or NULL
- */
-struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm);
#endif /* __DPU_RM_H__ */
--
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[Freedreno] [PATCH 03/25] drm/msm/dpu: remove dev from RM
Not used. Remove from RM.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 7 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 6 +-
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0a683e6..8309850 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1075,8 +1075,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto power_error;
}
- rc = dpu_rm_init(_kms->rm, dpu_kms->catalog, dpu_kms->mmio,
- dpu_kms->dev);
+ rc = dpu_rm_init(_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
if (rc) {
DPU_ERROR("rm init failed: %d\n", rc);
goto power_error;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 36a929b..5ce89b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -224,13 +224,12 @@ static int _dpu_rm_hw_blk_create(
int dpu_rm_init(struct dpu_rm *rm,
struct dpu_mdss_cfg *cat,
- void __iomem *mmio,
- struct drm_device *dev)
+ void __iomem *mmio)
{
int rc, i;
enum dpu_hw_blk_type type;
- if (!rm || !cat || !mmio || !dev) {
+ if (!rm || !cat || !mmio) {
DPU_ERROR("invalid kms\n");
return -EINVAL;
}
@@ -243,8 +242,6 @@ int dpu_rm_init(struct dpu_rm *rm,
for (type = 0; type < DPU_HW_BLK_MAX; type++)
INIT_LIST_HEAD(>hw_blks[type]);
- rm->dev = dev;
-
/* Some of the sub-blocks require an mdptop to be created */
rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat);
if (IS_ERR_OR_NULL(rm->hw_mdp)) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 0dd3c21..f41fd19 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -22,7 +22,6 @@
/**
* struct dpu_rm - DPU dynamic hardware resource manager
- * @dev: device handle for event logging purposes
* @hw_blks: array of lists of hardware resources present in the system, one
* list per type of hardware block
* @hw_mdp: hardware object for mdp_top
@@ -30,7 +29,6 @@
* @rm_lock: resource manager mutex
*/
struct dpu_rm {
- struct drm_device *dev;
struct list_head hw_blks[DPU_HW_BLK_MAX];
struct dpu_hw_mdp *hw_mdp;
uint32_t lm_max_width;
@@ -63,13 +61,11 @@ struct dpu_rm_hw_iter {
* @rm: DPU Resource Manager handle
* @cat: Pointer to hardware catalog
* @mmio: mapped register io address of MDP
- * @dev: device handle for event logging purposes
* @Return: 0 on Success otherwise -ERROR
*/
int dpu_rm_init(struct dpu_rm *rm,
struct dpu_mdss_cfg *cat,
- void __iomem *mmio,
- struct drm_device *dev);
+ void __iomem *mmio);
/**
* dpu_rm_destroy - Free all memory allocated by dpu_rm_init
--
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[Freedreno] [PATCH 23/25] drm/msm/dpu: remove max_width from RM
Unused variable in the driver.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 --
2 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 901b1fc..34e09aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -166,18 +166,6 @@ int dpu_rm_init(struct dpu_rm *rm,
DPU_ERROR("failed: lm hw not available\n");
goto fail;
}
-
- if (!rm->lm_max_width) {
- rm->lm_max_width = lm->sblk->maxwidth;
- } else if (rm->lm_max_width != lm->sblk->maxwidth) {
- /*
-* Don't expect to have hw where lm max widths differ.
-* If found, take the min.
-*/
- DPU_ERROR("unsupported: lm maxwidth differs\n");
- if (rm->lm_max_width > lm->sblk->maxwidth)
- rm->lm_max_width = lm->sblk->maxwidth;
- }
}
for (i = 0; i < cat->pingpong_count; i++) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 0b1deb0..8676fa5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,12 +24,10 @@
* struct dpu_rm - DPU dynamic hardware resource manager
* @hw_blks: array of lists of hardware resources present in the system, one
* list per type of hardware block
- * @lm_max_width: cached layer mixer maximum width
* @rm_lock: resource manager mutex
*/
struct dpu_rm {
struct list_head hw_blks[DPU_HW_BLK_MAX];
- uint32_t lm_max_width;
struct mutex rm_lock;
};
--
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[Freedreno] [PATCH 04/25] drm/msm/dpu: clean up dpu_rm_check_property_topctl declaration
Definition was removed already. Clean up header declaration. Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index f41fd19..eb6a6ac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -136,12 +136,4 @@ void dpu_rm_init_hw_iter( * @Return: true on match found, false on no match found */ bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *iter); - -/** - * dpu_rm_check_property_topctl - validate property bitmask before it is set - * @val: user's proposed topology control bitmask - * @Return: 0 on success or error - */ -int dpu_rm_check_property_topctl(uint64_t val); - #endif /* __DPU_RM_H__ */ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 02/25] drm/msm/dpu: avoid tracking reservations in RM
RM was equipped with reservation tracking structure RSVP
to cache HW reservation of displays for certain clients
where atomic_checks (atomic commit with TEST_ONLY) for all
the displays are called before their respective atomic_commits.
Since DPU doesn't support the sequence anymore, clean up
the support from RM. Replace rsvp with the corresponding
encoder id to tag the HW blocks reserved.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 284 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 4 -
2 files changed, 43 insertions(+), 245 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index bdb1177..36a929b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -21,8 +21,8 @@
#include "dpu_encoder.h"
#include "dpu_trace.h"
-#define RESERVED_BY_OTHER(h, r) \
- ((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
+#define RESERVED_BY_OTHER(h, r) \
+ ((h)->enc_id && (h)->enc_id != r)
/**
* struct dpu_rm_requirements - Reservation requirements parameter bundle
@@ -34,85 +34,23 @@ struct dpu_rm_requirements {
struct dpu_encoder_hw_resources hw_res;
};
-/**
- * struct dpu_rm_rsvp - Use Case Reservation tagging structure
- * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
- * By using as a tag, rather than lists of pointers to HW blocks used
- * we can avoid some list management since we don't know how many blocks
- * of each type a given use case may require.
- * @list: List head for list of all reservations
- * @seq: Global RSVP sequence number for debugging, especially for
- * differentiating differenct allocations for same encoder.
- * @enc_id:Reservations are tracked by Encoder DRM object ID.
- * CRTCs may be connected to multiple Encoders.
- * An encoder or connector id identifies the display path.
- */
-struct dpu_rm_rsvp {
- struct list_head list;
- uint32_t seq;
- uint32_t enc_id;
-};
/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @list: List head for list of all hardware blocks tracking items
- * @rsvp: Pointer to use case reservation if reserved by a client
- * @rsvp_nxt: Temporary pointer used during reservation to the incoming
- * request. Will be swapped into rsvp if proposal is accepted
* @type: Type of hardware block this structure tracks
* @id:Hardware ID number, within it's own space, ie. LM_X
- * @catalog: Pointer to the hardware catalog entry for this block
+ * @enc_id:Encoder id to which this blk is binded
* @hw:Pointer to the hardware register access object for this
block
*/
struct dpu_rm_hw_blk {
struct list_head list;
- struct dpu_rm_rsvp *rsvp;
- struct dpu_rm_rsvp *rsvp_nxt;
enum dpu_hw_blk_type type;
uint32_t id;
+ uint32_t enc_id;
struct dpu_hw_blk *hw;
};
-/**
- * dpu_rm_dbg_rsvp_stage - enum of steps in making reservation for event
logging
- */
-enum dpu_rm_dbg_rsvp_stage {
- DPU_RM_STAGE_BEGIN,
- DPU_RM_STAGE_AFTER_CLEAR,
- DPU_RM_STAGE_AFTER_RSVPNEXT,
- DPU_RM_STAGE_FINAL
-};
-
-static void _dpu_rm_print_rsvps(
- struct dpu_rm *rm,
- enum dpu_rm_dbg_rsvp_stage stage)
-{
- struct dpu_rm_rsvp *rsvp;
- struct dpu_rm_hw_blk *blk;
- enum dpu_hw_blk_type type;
-
- DPU_DEBUG("%d\n", stage);
-
- list_for_each_entry(rsvp, >rsvps, list) {
- DRM_DEBUG_KMS("%d rsvp[s%ue%u]\n", stage, rsvp->seq,
- rsvp->enc_id);
- }
-
- for (type = 0; type < DPU_HW_BLK_MAX; type++) {
- list_for_each_entry(blk, >hw_blks[type], list) {
- if (!blk->rsvp && !blk->rsvp_nxt)
- continue;
-
- DRM_DEBUG_KMS("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
- (blk->rsvp) ? blk->rsvp->seq : 0,
- (blk->rsvp) ? blk->rsvp->enc_id : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
- blk->type, blk->id);
- }
- }
-}
-
struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
{
return rm->hw_mdp;
@@ -148,15 +86,13 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm,
struct dpu_rm_hw_iter *i)
i->blk = list_prepare_entry(i->blk, blk_list, list);
list_for_each_entry_continue(i->blk, blk_list, list) {
- struct dpu_rm_rsvp *rsvp = i->blk->rsvp;
-
if (i->blk->type != i->type) {
DPU_ERROR("found incorrect block type %d on %d list\n",
[Freedreno] [PATCH 06/25] drm/msm/dpu: clean up redundant hw type
struct dpu_hw_blk has hw block type info. Remove duplicate
type tracking in struct dpu_rm_hw_blk.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 5ce89b9..377def7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -38,14 +38,12 @@ struct dpu_rm_requirements {
/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @list: List head for list of all hardware blocks tracking items
- * @type: Type of hardware block this structure tracks
* @id:Hardware ID number, within it's own space, ie. LM_X
* @enc_id:Encoder id to which this blk is binded
* @hw:Pointer to the hardware register access object for this
block
*/
struct dpu_rm_hw_blk {
struct list_head list;
- enum dpu_hw_blk_type type;
uint32_t id;
uint32_t enc_id;
struct dpu_hw_blk *hw;
@@ -86,12 +84,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct
dpu_rm_hw_iter *i)
i->blk = list_prepare_entry(i->blk, blk_list, list);
list_for_each_entry_continue(i->blk, blk_list, list) {
- if (i->blk->type != i->type) {
- DPU_ERROR("found incorrect block type %d on %d list\n",
- i->blk->type, i->type);
- return false;
- }
-
if (i->enc_id == i->blk->enc_id) {
i->hw = i->blk->hw;
DPU_DEBUG("found type %d id %d for enc %d\n",
@@ -151,7 +143,7 @@ int dpu_rm_destroy(struct dpu_rm *rm)
list_for_each_entry_safe(hw_cur, hw_nxt, >hw_blks[type],
list) {
list_del(_cur->list);
- _dpu_rm_hw_destroy(hw_cur->type, hw_cur->hw);
+ _dpu_rm_hw_destroy(type, hw_cur->hw);
kfree(hw_cur);
}
}
@@ -213,7 +205,6 @@ static int _dpu_rm_hw_blk_create(
return -ENOMEM;
}
- blk->type = type;
blk->id = id;
blk->hw = hw;
blk->enc_id = 0;
@@ -458,7 +449,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t
enc_id,
lm[i]->enc_id = enc_id;
pp[i]->enc_id = enc_id;
- trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, enc_id,
+ trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
pp[i]->id);
}
@@ -510,7 +501,7 @@ static int _dpu_rm_reserve_ctls(
for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
ctls[i]->enc_id = enc_id;
- trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
+ trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
enc_id);
}
@@ -538,7 +529,7 @@ static int _dpu_rm_reserve_intf(
}
iter.blk->enc_id = enc_id;
- trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
+ trace_dpu_rm_reserve_intf(iter.blk->id, DPU_HW_BLK_INTF,
enc_id);
break;
}
--
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a Linux Foundation Collaborative Project
___
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[Freedreno] [PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing
Layer mixer/pingpong block counts and hw ctl block counts
will not be same for all the topologies (e.g. layer
mixer muxing to single interface)
Use the encoder's split_role info to retrieve the
respective control path for programming.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 96cdf06..d12f896 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+ int ctl_index;
if (phys) {
if (!dpu_enc->hw_pp[i]) {
@@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct
drm_encoder *drm_enc,
return;
}
- if (!hw_ctl[i]) {
+ ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1 : 0;
+
+ if (!hw_ctl[ctl_index]) {
DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
-"at idx: %d\n", i);
+"at idx: %d\n", ctl_index);
return;
}
phys->hw_pp = dpu_enc->hw_pp[i];
- phys->hw_ctl = hw_ctl[i];
+ phys->hw_ctl = hw_ctl[ctl_index];
phys->connector = conn->state->connector;
if (phys->ops.mode_set)
--
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a Linux Foundation Collaborative Project
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[Freedreno] [PATCH 05/25] drm/msm/dpu: remove encoder from crtc mixer struct
Not actively used. Clean up the crtc mixer struct.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d4530d6..4960641 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -461,8 +461,6 @@ static void _dpu_crtc_setup_mixer_for_encoder(
return;
}
- mixer->encoder = enc;
-
cstate->num_mixers++;
DPU_DEBUG("setup mixer %d: lm %d\n",
i, mixer->hw_lm->idx - LM_0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 3723b48..75fdd3c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -84,14 +84,12 @@ struct dpu_crtc_smmu_state_data {
* struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
* @hw_lm: LM HW Driver context
* @lm_ctl:CTL Path HW driver context
- * @encoder: Encoder attached to this lm & ctl
* @mixer_op_mode: mixer blending operation mode
* @flush_mask:mixer flush mask for ctl, mixer and pipe
*/
struct dpu_crtc_mixer {
struct dpu_hw_mixer *hw_lm;
struct dpu_hw_ctl *lm_ctl;
- struct drm_encoder *encoder;
u32 mixer_op_mode;
u32 flush_mask;
};
--
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a Linux Foundation Collaborative Project
___
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[Freedreno] [PATCH 13/25] drm/msm/dpu: make RM iterator hw type specific
Usage of hw block iterators are only RM internal. Instead
of using generic void pointers for HW blocks, use dpu
specific structure. It helps us to get rid of duplicate
hw block id's maintained in RM wrapper.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 561120d..303f1b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -38,13 +38,11 @@ struct dpu_rm_requirements {
/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @list: List head for list of all hardware blocks tracking items
- * @id:Hardware ID number, within it's own space, ie. LM_X
* @enc_id:Encoder id to which this blk is binded
* @hw:Pointer to the hardware register access object for this
block
*/
struct dpu_rm_hw_blk {
struct list_head list;
- uint32_t id;
uint32_t enc_id;
struct dpu_hw_blk *hw;
};
@@ -57,7 +55,7 @@ struct dpu_rm_hw_blk {
* @type: Hardware Block Type client wishes to search for.
*/
struct dpu_rm_hw_iter {
- void *hw;
+ struct dpu_hw_blk *hw;
struct dpu_rm_hw_blk *blk;
uint32_t enc_id;
enum dpu_hw_blk_type type;
@@ -96,7 +94,7 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct
dpu_rm_hw_iter *i)
if (i->enc_id == i->blk->enc_id) {
i->hw = i->blk->hw;
DPU_DEBUG("found type %d id %d for enc %d\n",
- i->type, i->blk->id, i->enc_id);
+ i->type, i->blk->hw->id, i->enc_id);
return true;
}
}
@@ -197,7 +195,6 @@ static int _dpu_rm_hw_blk_create(
return -ENOMEM;
}
- blk->id = id;
blk->hw = hw;
blk->enc_id = 0;
list_add_tail(>list, >hw_blks[type]);
@@ -350,7 +347,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
_dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_PINGPONG);
while (_dpu_rm_get_hw_locked(rm, )) {
- if (iter.blk->id == lm_cfg->pingpong) {
+ if (iter.blk->hw->id == lm_cfg->pingpong) {
*pp = iter.blk;
break;
}
@@ -362,8 +359,8 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
}
if (RESERVED_BY_OTHER(*pp, enc_id)) {
- DPU_DEBUG("lm %d pp %d already reserved\n", lm->id,
- (*pp)->id);
+ DPU_DEBUG("lm %d pp %d already reserved\n", lm->hw->id,
+ (*pp)->hw->id);
return false;
}
@@ -436,8 +433,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t
enc_id,
dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
dpu_cstate->mixers[i].hw_pp = to_dpu_hw_pingpong(pp[i]->hw);
- trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
-pp[i]->id);
+ trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM, enc_id,
+pp[i]->hw->id);
}
dpu_cstate->num_mixers = lm_count;
@@ -474,13 +471,13 @@ static int _dpu_rm_reserve_ctls(
has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
- DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
+ DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->hw->id, features);
if (needs_split_display != has_split_display)
continue;
ctls[i] = iter.blk;
- DPU_DEBUG("ctl %d match\n", iter.blk->id);
+ DPU_DEBUG("ctl %d match\n", iter.blk->hw->id);
if (++i == num_ctls)
break;
@@ -493,7 +490,7 @@ static int _dpu_rm_reserve_ctls(
ctls[i]->enc_id = enc_id;
dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
- trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
+ trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL,
enc_id);
}
@@ -513,7 +510,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
/* Find the block entry in the rm, and note the reservation */
_dpu_rm_init_hw_iter(, 0, type);
while (_dpu_rm_get_hw_locked(rm, )) {
- if (iter.blk->id != id)
+ if (iter.blk->hw->id != id)
continue;
if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
@@ -522,7 +519,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
}
iter.blk->enc_id = enc_id;
-
[Freedreno] [PATCH 09/25] drm/msm/dpu: make RM iterator static
HW blocks reserved for a display are stored in crtc state.
No one outside RM is interested in using these API's for
HW block list iterations.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 37 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 46 --
2 files changed, 20 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 619b596..24fc1c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -49,12 +49,26 @@ struct dpu_rm_hw_blk {
struct dpu_hw_blk *hw;
};
+/**
+ * struct dpu_rm_hw_iter - iterator for use with dpu_rm
+ * @hw: dpu_hw object requested, or NULL on failure
+ * @blk: dpu_rm internal block representation. Clients ignore. Used as
iterator.
+ * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
+ * @type: Hardware Block Type client wishes to search for.
+ */
+struct dpu_rm_hw_iter {
+ void *hw;
+ struct dpu_rm_hw_blk *blk;
+ uint32_t enc_id;
+ enum dpu_hw_blk_type type;
+};
+
struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
{
return rm->hw_mdp;
}
-void dpu_rm_init_hw_iter(
+static void _dpu_rm_init_hw_iter(
struct dpu_rm_hw_iter *iter,
uint32_t enc_id,
enum dpu_hw_blk_type type)
@@ -97,17 +111,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct
dpu_rm_hw_iter *i)
return false;
}
-bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
-{
- bool ret;
-
- mutex_lock(>rm_lock);
- ret = _dpu_rm_get_hw_locked(rm, i);
- mutex_unlock(>rm_lock);
-
- return ret;
-}
-
static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
{
switch (type) {
@@ -365,7 +368,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
return false;
}
- dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_PINGPONG);
+ _dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_PINGPONG);
while (_dpu_rm_get_hw_locked(rm, )) {
if (iter.blk->id == lm_cfg->pingpong) {
*pp = iter.blk;
@@ -404,7 +407,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t
enc_id,
}
/* Find a primary mixer */
- dpu_rm_init_hw_iter(_i, 0, DPU_HW_BLK_LM);
+ _dpu_rm_init_hw_iter(_i, 0, DPU_HW_BLK_LM);
while (lm_count != reqs->topology.num_lm &&
_dpu_rm_get_hw_locked(rm, _i)) {
memset(, 0, sizeof(lm));
@@ -421,7 +424,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t
enc_id,
++lm_count;
/* Valid primary mixer found, find matching peers */
- dpu_rm_init_hw_iter(_j, 0, DPU_HW_BLK_LM);
+ _dpu_rm_init_hw_iter(_j, 0, DPU_HW_BLK_LM);
while (lm_count != reqs->topology.num_lm &&
_dpu_rm_get_hw_locked(rm, _j)) {
@@ -480,7 +483,7 @@ static int _dpu_rm_reserve_ctls(
needs_split_display = _dpu_rm_needs_split_display(top);
- dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_CTL);
+ _dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_CTL);
while (_dpu_rm_get_hw_locked(rm, )) {
const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
unsigned long features = ctl->caps->features;
@@ -528,7 +531,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
struct dpu_rm_hw_iter iter;
/* Find the block entry in the rm, and note the reservation */
- dpu_rm_init_hw_iter(, 0, type);
+ _dpu_rm_init_hw_iter(, 0, type);
while (_dpu_rm_get_hw_locked(rm, )) {
if (iter.blk->id != id)
continue;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index e48e8f2..c7e3b2b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -36,26 +36,6 @@ struct dpu_rm {
};
/**
- * struct dpu_rm_hw_blk - resource manager internal structure
- * forward declaration for single iterator definition without void pointer
- */
-struct dpu_rm_hw_blk;
-
-/**
- * struct dpu_rm_hw_iter - iterator for use with dpu_rm
- * @hw: dpu_hw object requested, or NULL on failure
- * @blk: dpu_rm internal block representation. Clients ignore. Used as
iterator.
- * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
- * @type: Hardware Block Type client wishes to search for.
- */
-struct dpu_rm_hw_iter {
- void *hw;
- struct dpu_rm_hw_blk *blk;
- uint32_t enc_id;
- enum dpu_hw_blk_type type;
-};
-
-/**
* dpu_rm_init - Read hardware catalog and create reservation tracking objects
* for all HW blocks.
* @rm: DPU Resource Manager handle
@@ -110,30 +90,4 @@ int dpu_rm_reserve(struct dpu_rm *rm,
*
[Freedreno] [PATCH 00/25] reserve RM resources in CRTC state
Submitting series of patches to clean up DPU resource manager (RM) of complicated hw iterations, redundant data maintenence and eventually modifying the DPU to reserve display HW blocks only in atomic check and caching the assigned HW blocks in atomic CRTC state. Thanks, Jeykumar S. Jeykumar Sankaran (25): drm/msm/dpu: fix hw ctl retrieval for mixer muxing drm/msm/dpu: avoid tracking reservations in RM drm/msm/dpu: remove dev from RM drm/msm/dpu: clean up dpu_rm_check_property_topctl declaration drm/msm/dpu: remove encoder from crtc mixer struct drm/msm/dpu: clean up redundant hw type drm/msm/dpu: reserve using crtc state drm/msm/dpu: release reservation using crtc state drm/msm/dpu: make RM iterator static drm/msm/dpu: maintain hw_mdp in kms drm/msm/dpu: remove reserve in encoder mode_set drm/msm/dpu: remove mode_set_complete drm/msm/dpu: make RM iterator hw type specific drm/msm/dpu: remove enc_id tagging for hw blocks drm/msm/dpu: avoid redundant hw blk reference drm/msm/dpu: clean up test_only flag for RM reservation drm/msm/dpu: remove RM HW block list iterator drm/msm/dpu: merge RM interface reservation helpers drm/msm/dpu: remove msm_display_topology drm/msm/dpu: refine layer mixer reservations drm/msm/dpu: merge RM reservation helpers drm/msm/dpu: make crtc and encoder specific HW reservation drm/msm/dpu: remove max_width from RM drm/msm/dpu: remove mutex locking for RM interfaces drm/msm/dpu: maintain RM init check internally drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 98 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 96 +-- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 20 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 728 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 107 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 28 +- drivers/gpu/drm/msm/msm_drv.h | 12 - 10 files changed, 322 insertions(+), 800 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 07/25] drm/msm/dpu: reserve using crtc state
DPU maintained reservation lists to cache assigned
HW blocks for the display and a retrieval mechanism for
the individual DRM components to query their respective
HW blocks.
This patch uses the sub-classed CRTC state to store
and track HW blocks assigned for different components
of the display pipeline. It helps the driver:
- to get rid of unwanted store and retrieval RM API's
- to preserve HW resources assigned in atomic_check
through atomic swap/duplicate.
Separate patch is submitted to remove resource
reservation in atomic_commit path.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 65 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 14 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 28 +++---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 20 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 58 ---
5 files changed, 72 insertions(+), 113 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4960641..0625f56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -421,69 +421,20 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
trace_dpu_crtc_complete_commit(DRMID(crtc));
}
-static void _dpu_crtc_setup_mixer_for_encoder(
- struct drm_crtc *crtc,
- struct drm_encoder *enc)
+static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
{
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
- struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
- struct dpu_rm *rm = _kms->rm;
struct dpu_crtc_mixer *mixer;
- struct dpu_hw_ctl *last_valid_ctl = NULL;
- int i;
- struct dpu_rm_hw_iter lm_iter, ctl_iter;
-
- dpu_rm_init_hw_iter(_iter, enc->base.id, DPU_HW_BLK_LM);
- dpu_rm_init_hw_iter(_iter, enc->base.id, DPU_HW_BLK_CTL);
+ int i, ctl_index;
/* Set up all the mixers and ctls reserved by this encoder */
- for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
+ for (i = 0; i < cstate->num_mixers; i++) {
mixer = >mixers[i];
- if (!dpu_rm_get_hw(rm, _iter))
- break;
- mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw;
-
/* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
- if (!dpu_rm_get_hw(rm, _iter)) {
- DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
- mixer->hw_lm->idx - LM_0);
- mixer->lm_ctl = last_valid_ctl;
- } else {
- mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
- last_valid_ctl = mixer->lm_ctl;
- }
-
- /* Shouldn't happen, mixers are always >= ctls */
- if (!mixer->lm_ctl) {
- DPU_ERROR("no valid ctls found for lm %d\n",
- mixer->hw_lm->idx - LM_0);
- return;
- }
-
- cstate->num_mixers++;
- DPU_DEBUG("setup mixer %d: lm %d\n",
- i, mixer->hw_lm->idx - LM_0);
- DPU_DEBUG("setup mixer %d: ctl %d\n",
- i, mixer->lm_ctl->idx - CTL_0);
- }
-}
-
-static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
-{
- struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
- struct drm_encoder *enc;
-
- mutex_lock(_crtc->crtc_lock);
- /* Check for mixers on all encoders attached to this crtc */
- list_for_each_entry(enc, >dev->mode_config.encoder_list, head) {
- if (enc->crtc != crtc)
- continue;
-
- _dpu_crtc_setup_mixer_for_encoder(crtc, enc);
+ ctl_index = min(i, cstate->num_ctls - 1);
+ mixer->lm_ctl = cstate->hw_ctls[ctl_index];
}
-
- mutex_unlock(_crtc->crtc_lock);
}
static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
@@ -536,10 +487,8 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
dev = crtc->dev;
smmu_state = _crtc->smmu_state;
- if (!cstate->num_mixers) {
- _dpu_crtc_setup_mixers(crtc);
- _dpu_crtc_setup_lm_bounds(crtc, crtc->state);
- }
+ _dpu_crtc_setup_mixers(crtc);
+ _dpu_crtc_setup_lm_bounds(crtc, crtc->state);
if (dpu_crtc->event) {
WARN_ON(dpu_crtc->event);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 75fdd3c..17aaad7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -84,12 +84,14 @@ struct dpu_crtc_smmu_state_data {
* struct dpu_crtc_mixer: stores the map for each virtual
[Freedreno] [PATCH 08/25] drm/msm/dpu: release reservation using crtc state
Use the hw block pointers stored in crtc state to
release them back to RM resource pool. This change
is made to uncouple RM reservation from encoder_id.
Separate change is submitted to clean up RM of
encoder id tagging.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 69 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 6 +--
3 files changed, 60 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 17dbbc3..a8fd14e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1223,7 +1223,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder
*drm_enc)
DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
- dpu_rm_release(_kms->rm, drm_enc);
+ dpu_rm_release(_kms->rm, drm_enc->crtc->state);
}
static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 5703b11..619b596 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -625,27 +625,70 @@ static int _dpu_rm_populate_requirements(
return 0;
}
-static void _dpu_rm_release_reservation(struct dpu_rm *rm, uint32_t enc_id)
+static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
+ int id)
{
struct dpu_rm_hw_blk *blk;
- enum dpu_hw_blk_type type;
- for (type = 0; type < DPU_HW_BLK_MAX; type++) {
- list_for_each_entry(blk, >hw_blks[type], list) {
- if (blk->enc_id == enc_id) {
- blk->enc_id = 0;
- DPU_DEBUG("rel enc %d %d %d\n", enc_id,
- blk->type, blk->id);
- }
+ list_for_each_entry(blk, >hw_blks[type], list) {
+ if (blk->hw->id == id) {
+ blk->enc_id = 0;
+ return 0;
}
}
+
+ DRM_DEBUG_KMS("failed to find hw id(%d) of type(%d) for releasing\n",
+ id, type);
+
+ return -EINVAL;
}
-void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc)
+static void _dpu_rm_release_reservation(struct dpu_rm *rm,
+ struct dpu_crtc_state *dpu_cstate)
{
+ int i;
+
+ for (i = 0; i < dpu_cstate->num_mixers; i++) {
+ struct dpu_crtc_mixer *mixer = _cstate->mixers[i];
+
+ if (!mixer->hw_lm)
+ continue;
+
+ if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_LM,
+ mixer->hw_lm->base.id))
+ mixer->hw_lm = NULL;
+
+ if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_PINGPONG,
+ mixer->hw_pp->base.id))
+ mixer->hw_pp = NULL;
+ }
+
+ for (i = 0; i < dpu_cstate->num_ctls; i++) {
+ if (!dpu_cstate->hw_ctls[i])
+ continue;
+
+ if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_CTL,
+ dpu_cstate->hw_ctls[i]->base.id))
+ dpu_cstate->hw_ctls[i] = NULL;
+ }
+
+ for (i = 0; i < dpu_cstate->num_intfs; i++) {
+ if (!dpu_cstate->hw_intfs[i])
+ continue;
+
+ if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_INTF,
+ dpu_cstate->hw_intfs[i]->base.id))
+ dpu_cstate->hw_intfs[i] = NULL;
+ }
+}
+
+void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
+{
+ struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
+
mutex_lock(>rm_lock);
- _dpu_rm_release_reservation(rm, enc->base.id);
+ _dpu_rm_release_reservation(rm, dpu_cstate);
mutex_unlock(>rm_lock);
}
@@ -679,12 +722,12 @@ int dpu_rm_reserve(
ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, );
if (ret) {
DPU_ERROR("failed to reserve hw resources: %d\n", ret);
- _dpu_rm_release_reservation(rm, enc->base.id);
+ _dpu_rm_release_reservation(rm, dpu_cstate);
} else if (test_only) {
/* test_only: test the reservation and then undo */
DPU_DEBUG("test_only: discard test [enc: %d]\n",
enc->base.id);
- _dpu_rm_release_reservation(rm, enc->base.id);
+ _dpu_rm_release_reservation(rm, dpu_cstate);
}
end:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index eb6a6ac..e48e8f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++
Re: [Freedreno] [PATCH] drm/msm: Grab a vblank reference when waiting for commit_done
On 2018-10-03 13:22, Sean Paul wrote: From: Sean Paul Similar to the atomic helpers, we should enable vblank while we're waiting for the commit to finish. DPU needs this, MDP5 seems to work fine without it. Signed-off-by: Sean Paul --- As such I dont see any issue with this patch but I have a question overall on chrome vblank handling. For a video mode panel, we will keep the HW resources enabled (including vsync related clocks) till device is suspended. The vblank_get and vblank_put are only controlling the register/deregister of the vblank IRQ callback which send the events to the userspace and anything pending on vsync completion. Does the chrome userspace turn ON/OFF the vblank using vblank_ctrl IOCTL Or does it guarantee it to be? If so, is this patch just more of a safety check to make sure that vsync events remain ON till the frame is done? Because HW wise it should be and this shouldnt be needed. drivers/gpu/drm/msm/msm_atomic.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index c1f1779c980f..2b7bb6e166d3 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -32,7 +32,12 @@ static void msm_atomic_wait_for_commit_done(struct drm_device *dev, if (!new_crtc_state->active) continue; + if (drm_crtc_vblank_get(crtc)) + continue; + kms->funcs->wait_for_crtc_commit_done(kms, crtc); + + drm_crtc_vblank_put(crtc); } } ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3] drm/msm: validate display and event threads
While creating display and event threads per crtc, validate
them before setting their priorities.
changes in v2:
- use dev_warn (Abhinav Kumar)
changes in v3:
- fix compilation error
Change-Id: I1dda805286df981c0f0e2b26507d089d3a21ff6c
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/msm_drv.c | 49 ++-
1 file changed, 16 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 4904d0d..ab1b0a9 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -553,17 +553,18 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
kthread_run(kthread_worker_fn,
>disp_thread[i].worker,
"crtc_commit:%d", priv->disp_thread[i].crtc_id);
- ret = sched_setscheduler(priv->disp_thread[i].thread,
- SCHED_FIFO, );
- if (ret)
- pr_warn("display thread priority update failed: %d\n",
- ret);
-
if (IS_ERR(priv->disp_thread[i].thread)) {
dev_err(dev, "failed to create crtc_commit kthread\n");
priv->disp_thread[i].thread = NULL;
+ goto err_msm_uninit;
}
+ ret = sched_setscheduler(priv->disp_thread[i].thread,
+SCHED_FIFO, );
+ if (ret)
+ dev_warn(dev, "display thread priority update failed:
%d\n",
+ ret);
+
/* initialize event thread */
priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
kthread_init_worker(>event_thread[i].worker);
@@ -572,6 +573,12 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
kthread_run(kthread_worker_fn,
>event_thread[i].worker,
"crtc_event:%d", priv->event_thread[i].crtc_id);
+ if (IS_ERR(priv->event_thread[i].thread)) {
+ dev_err(dev, "failed to create crtc_event kthread\n");
+ priv->event_thread[i].thread = NULL;
+ goto err_msm_uninit;
+ }
+
/**
* event thread should also run at same priority as disp_thread
* because it is handling frame_done events. A lower priority
@@ -580,34 +587,10 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
* failure at crtc commit level.
*/
ret = sched_setscheduler(priv->event_thread[i].thread,
- SCHED_FIFO, );
+SCHED_FIFO, );
if (ret)
- pr_warn("display event thread priority update failed:
%d\n",
- ret);
-
- if (IS_ERR(priv->event_thread[i].thread)) {
- dev_err(dev, "failed to create crtc_event kthread\n");
- priv->event_thread[i].thread = NULL;
- }
-
- if ((!priv->disp_thread[i].thread) ||
- !priv->event_thread[i].thread) {
- /* clean up previously created threads if any */
- for ( ; i >= 0; i--) {
- if (priv->disp_thread[i].thread) {
- kthread_stop(
- priv->disp_thread[i].thread);
- priv->disp_thread[i].thread = NULL;
- }
-
- if (priv->event_thread[i].thread) {
- kthread_stop(
- priv->event_thread[i].thread);
- priv->event_thread[i].thread = NULL;
- }
- }
- goto err_msm_uninit;
- }
+ dev_warn(dev, "display event thread priority update
failed:%d\n",
+ ret);
}
ret = drm_vblank_init(ddev, priv->num_crtcs);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2] drm/msm: validate display and event threads
While creating display and event threads per crtc, validate
them before setting their priorities.
changes in v2:
- use dev_warn (Abhinav Kumar)
Change-Id: I1dda805286df981c0f0e2b26507d089d3a21ff6c
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/msm_drv.c | 49 ++-
1 file changed, 16 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 4904d0d..9df4047 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -553,17 +553,18 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
kthread_run(kthread_worker_fn,
>disp_thread[i].worker,
"crtc_commit:%d", priv->disp_thread[i].crtc_id);
- ret = sched_setscheduler(priv->disp_thread[i].thread,
- SCHED_FIFO, );
- if (ret)
- pr_warn("display thread priority update failed: %d\n",
- ret);
-
if (IS_ERR(priv->disp_thread[i].thread)) {
dev_err(dev, "failed to create crtc_commit kthread\n");
priv->disp_thread[i].thread = NULL;
+ goto err_msm_uninit;
}
+ ret = sched_setscheduler(priv->disp_thread[i].thread,
+SCHED_FIFO, );
+ if (ret)
+ dev_warn("display thread priority update failed: %d\n",
+ ret);
+
/* initialize event thread */
priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
kthread_init_worker(>event_thread[i].worker);
@@ -572,6 +573,12 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
kthread_run(kthread_worker_fn,
>event_thread[i].worker,
"crtc_event:%d", priv->event_thread[i].crtc_id);
+ if (IS_ERR(priv->event_thread[i].thread)) {
+ dev_err(dev, "failed to create crtc_event kthread\n");
+ priv->event_thread[i].thread = NULL;
+ goto err_msm_uninit;
+ }
+
/**
* event thread should also run at same priority as disp_thread
* because it is handling frame_done events. A lower priority
@@ -580,34 +587,10 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
* failure at crtc commit level.
*/
ret = sched_setscheduler(priv->event_thread[i].thread,
- SCHED_FIFO, );
+SCHED_FIFO, );
if (ret)
- pr_warn("display event thread priority update failed:
%d\n",
- ret);
-
- if (IS_ERR(priv->event_thread[i].thread)) {
- dev_err(dev, "failed to create crtc_event kthread\n");
- priv->event_thread[i].thread = NULL;
- }
-
- if ((!priv->disp_thread[i].thread) ||
- !priv->event_thread[i].thread) {
- /* clean up previously created threads if any */
- for ( ; i >= 0; i--) {
- if (priv->disp_thread[i].thread) {
- kthread_stop(
- priv->disp_thread[i].thread);
- priv->disp_thread[i].thread = NULL;
- }
-
- if (priv->event_thread[i].thread) {
- kthread_stop(
- priv->event_thread[i].thread);
- priv->event_thread[i].thread = NULL;
- }
- }
- goto err_msm_uninit;
- }
+ dev_warn("display event thread priority update
failed:%d\n",
+ ret);
}
ret = drm_vblank_init(ddev, priv->num_crtcs);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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Re: [Freedreno] [PATCH 5/6] drm/msm: dpu: Remove empty/useless labels
On 2018-10-08 15:24, Jeykumar Sankaran wrote:
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
I noticed an empty label while driving by and decided to use
coccinelle to see if there were any more. Here's the spatch and the
invocation:
---
@@
identifier lbl;
expression E;
@@
- goto lbl;
+ return E;
...
- lbl:
return E;
@@
identifier lbl;
@@
- goto lbl;
+ return;
...
- lbl:
- return;
---
spatch --allow-inconsistent-paths --sp-file file.spatch --dir
drivers/gpu/drm/msm/disp/dpu1 --in-place
---
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 5 ++---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 15
++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 4 +---
7 files changed, 20 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 41c5191f9056..affc9738e2b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -68,7 +68,7 @@ static bool
_dpu_core_video_mode_intf_connected(struct
drm_crtc *crtc)
bool intf_connected = false;
if (!crtc)
- goto end;
+ return intf_connected;
This can be further cleaned up by removing this intermediate var.
Nevermind. Just checked patch 6/6.
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if ((dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO)
&&
@@ -76,11 +76,10 @@ static bool
_dpu_core_video_mode_intf_connected(struct
drm_crtc *crtc)
DPU_DEBUG("video interface connected crtc:%d\n",
tmp_crtc->base.id);
intf_connected = true;
- goto end;
+ return intf_connected;
}
}
-end:
return intf_connected;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index c30ae05b3349..24a98f4e1f44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -496,14 +496,11 @@ static void dpu_encoder_phys_cmd_enable_helper(
_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
- goto skip_flush;
+ return;
ctl = phys_enc->hw_ctl;
ctl->ops.get_bitmask_intf(ctl, _mask, phys_enc->intf_idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
-
-skip_flush:
- return;
}
static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys
*phys_enc)
@@ -797,7 +794,7 @@ struct dpu_encoder_phys
*dpu_encoder_phys_cmd_init(
if (!cmd_enc) {
ret = -ENOMEM;
DPU_ERROR("failed to allocate\n");
- goto fail;
+ return ERR_PTR(ret);
}
phys_enc = _enc->base;
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
@@ -855,6 +852,5 @@ struct dpu_encoder_phys
*dpu_encoder_phys_cmd_init(
return phys_enc;
-fail:
return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index bfcd165e96df..0aa9b8e1ae70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -921,7 +921,7 @@ static int _dpu_format_populate_addrs_ubwc(
+ layout->plane_size[2] + layout->plane_size[3];
if (!meta)
- goto done;
+ return 0;
/* configure Y metadata plane */
layout->plane_addr[2] = base_addr;
@@ -952,12 +952,11 @@ static int _dpu_format_populate_addrs_ubwc(
layout->plane_addr[1] = 0;
if (!meta)
- goto done;
+ return 0;
layout->plane_addr[2] = base_addr;
layout->plane_addr[3] = 0;
}
-done:
return 0;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index cc3a623903f4..52fca13da176 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -177,7 +177,7 @@ static u32 dpu_hw_pp_get_line_count(struct
dpu_hw_pingpong *pp)
height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0x;
if (height < init)
- goto line_count_exit;
+ return line;
line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0x;
@@ -186,7 +186,6 @@ static u32
Re: [Freedreno] [PATCH 4/6] drm/msm: dpu: Remove 'inline' from several functions
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
Per chapter 15 of coding-style, removing 'inline' keyword from
functions
that are larger than a typical macro. In a couple of cases I've
simplified the function and kept the inline.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 16 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 6 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 12 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 ++---
.../gpu/drm/msm/disp/dpu1/msm_media_info.h| 24 +--
9 files changed, 30 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index a8f2dd7a37c7..5ff23f00582b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -53,7 +53,7 @@ static inline int _dpu_crtc_get_mixer_width(struct
dpu_crtc_state *cstate,
return mode->hdisplay / cstate->num_mixers;
}
-static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
+static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
{
struct msm_drm_private *priv;
@@ -70,7 +70,7 @@ static inline struct dpu_kms
*_dpu_crtc_get_kms(struct
drm_crtc *crtc)
return to_dpu_kms(priv->kms);
}
-static inline int _dpu_crtc_power_enable(struct dpu_crtc *dpu_crtc,
bool
enable)
+static int _dpu_crtc_power_enable(struct dpu_crtc *dpu_crtc, bool
enable)
{
struct drm_crtc *crtc;
struct msm_drm_private *priv;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 3723b4830335..cc18eca8f527 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -266,13 +266,7 @@ static inline int dpu_crtc_get_mixer_height(struct
dpu_crtc *dpu_crtc,
*/
static inline int dpu_crtc_frame_pending(struct drm_crtc *crtc)
{
- struct dpu_crtc *dpu_crtc;
-
- if (!crtc)
- return -EINVAL;
-
- dpu_crtc = to_dpu_crtc(crtc);
- return atomic_read(_crtc->frame_pending);
+ return crtc ? atomic_read(_dpu_crtc(crtc)->frame_pending) :
-EINVAL;
}
/**
@@ -329,13 +323,7 @@ enum dpu_intf_mode dpu_crtc_get_intf_mode(struct
drm_crtc *crtc);
static inline enum dpu_crtc_client_type dpu_crtc_get_client_type(
struct drm_crtc *crtc)
{
- struct dpu_crtc_state *cstate =
- crtc ? to_dpu_crtc_state(crtc->state) : NULL;
-
- if (!cstate)
- return NRT_CLIENT;
-
- return RT_CLIENT;
+ return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
}
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1f7f3c2e09c2..79a6c6b7350b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1376,7 +1376,7 @@ static void dpu_encoder_off_work(struct
kthread_work
*work)
* phys: Pointer to physical encoder structure
* extra_flush_bits: Additional bit mask to include in flush trigger
*/
-static inline void _dpu_encoder_trigger_flush(struct drm_encoder
*drm_enc,
+static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
{
struct dpu_hw_ctl *ctl;
@@ -1419,7 +1419,7 @@ static inline void
_dpu_encoder_trigger_flush(struct
drm_encoder *drm_enc,
* _dpu_encoder_trigger_start - trigger start for a physical encoder
* phys: Pointer to physical encoder structure
*/
-static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys
*phys)
+static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
{
if (!phys) {
DPU_ERROR("invalid argument(s)\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 283a2491f3e3..b3c68c4fcc8e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -110,7 +110,7 @@ static void drm_mode_to_intf_timing_params(
*/
}
-static inline u32 get_horizontal_total(const struct intf_timing_params
*timing)
+static u32 get_horizontal_total(const struct intf_timing_params
*timing)
{
u32 active = timing->xres;
u32 inactive =
@@ -119,7 +119,7 @@ static inline u32 get_horizontal_total(const struct
intf_timing_params *timing)
return active + inactive;
}
-static inline u32 get_vertical_total(const struct intf_timing_params
*timing)
+static u32 get_vertical_total(const struct intf_timing_params
Re: [Freedreno] [PATCH 2/6] drm/msm: dpu: Remove unused functions from msm_media_info.h
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
These functions aren't used anywhere, remove them.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
.../gpu/drm/msm/disp/dpu1/msm_media_info.h| 171 --
1 file changed, 171 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
b/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
index 4f12e5c534c8..1a35dfb4a4e5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
@@ -813,18 +813,6 @@ enum color_fmts {
#define COLOR_FMT_P010_UBWCCOLOR_FMT_P010_UBWC
#define COLOR_FMT_P010 COLOR_FMT_P010
-static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height)
-{
- (void)height;
- (void)width;
-
- /*
-* In the future, calculate the size based on the w/h but just
-* hardcode it for now since 16K satisfies all current usecases.
-*/
- return 16 * 1024;
-}
-
/*
* Function arguments:
* @color_fmt
@@ -1214,163 +1202,4 @@ static inline unsigned int
VENUS_RGB_META_SCANLINES(int color_fmt, int height)
return rgb_meta_scanlines;
}
-/*
- * Function arguments:
- * @color_fmt
- * @width
- * Progressive: width
- * Interlaced: width
- * @height
- * Progressive: height
- * Interlaced: height
- */
-static inline unsigned int VENUS_BUFFER_SIZE(
- int color_fmt, int width, int height)
-{
- const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width,
height);
- unsigned int uv_alignment = 0, size = 0;
- unsigned int y_plane, uv_plane, y_stride,
- uv_stride, y_sclines, uv_sclines;
- unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0;
- unsigned int y_meta_stride = 0, y_meta_scanlines = 0;
- unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0;
- unsigned int y_meta_plane = 0, uv_meta_plane = 0;
- unsigned int rgb_stride = 0, rgb_scanlines = 0;
- unsigned int rgb_plane = 0, rgb_ubwc_plane = 0, rgb_meta_plane =
0;
- unsigned int rgb_meta_stride = 0, rgb_meta_scanlines = 0;
-
- if (!width || !height)
- goto invalid_input;
-
- y_stride = VENUS_Y_STRIDE(color_fmt, width);
- uv_stride = VENUS_UV_STRIDE(color_fmt, width);
- y_sclines = VENUS_Y_SCANLINES(color_fmt, height);
- uv_sclines = VENUS_UV_SCANLINES(color_fmt, height);
- rgb_stride = VENUS_RGB_STRIDE(color_fmt, width);
- rgb_scanlines = VENUS_RGB_SCANLINES(color_fmt, height);
-
- switch (color_fmt) {
- case COLOR_FMT_NV21:
- case COLOR_FMT_NV12:
- case COLOR_FMT_P010:
- uv_alignment = 4096;
- y_plane = y_stride * y_sclines;
- uv_plane = uv_stride * uv_sclines + uv_alignment;
- size = y_plane + uv_plane +
- MSM_MEDIA_MAX(extra_size, 8 * y_stride);
- size = MSM_MEDIA_ALIGN(size, 4096);
- break;
- case COLOR_FMT_NV12_MVTB:
- uv_alignment = 4096;
- y_plane = y_stride * y_sclines;
- uv_plane = uv_stride * uv_sclines + uv_alignment;
- size = y_plane + uv_plane;
- size = 2 * size + extra_size;
- size = MSM_MEDIA_ALIGN(size, 4096);
- break;
- case COLOR_FMT_NV12_UBWC:
- y_sclines = VENUS_Y_SCANLINES(color_fmt, (height+1)>>1);
- y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines,
4096);
- uv_sclines = VENUS_UV_SCANLINES(color_fmt, (height+1)>>1);
- uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines,
4096);
- y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width);
- y_meta_scanlines =
- VENUS_Y_META_SCANLINES(color_fmt, (height+1)>>1);
- y_meta_plane = MSM_MEDIA_ALIGN(
- y_meta_stride * y_meta_scanlines, 4096);
- uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width);
- uv_meta_scanlines =
- VENUS_UV_META_SCANLINES(color_fmt, (height+1)>>1);
- uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride *
- uv_meta_scanlines, 4096);
-
- size = (y_ubwc_plane + uv_ubwc_plane + y_meta_plane +
- uv_meta_plane)*2 +
- MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride);
- size = MSM_MEDIA_ALIGN(size, 4096);
- break;
- case COLOR_FMT_NV12_BPP10_UBWC:
- y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines,
4096);
- uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines,
4096);
- y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width);
- y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt,
height);
- y_meta_plane = MSM_MEDIA_ALIGN(
- y_meta_stride * y_meta_scanlines, 4096);
Re: [Freedreno] [PATCH 6/6] drm/msm: dpu: Clean up _dpu_core_video_mode_intf_connected()
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
Local variable is not needed and condition can't be hit.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index affc9738e2b5..22e84b3d7f98 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -65,22 +65,17 @@ static bool _dpu_core_perf_crtc_is_power_on(struct
drm_crtc *crtc)
static bool _dpu_core_video_mode_intf_connected(struct drm_crtc *crtc)
{
struct drm_crtc *tmp_crtc;
- bool intf_connected = false;
-
- if (!crtc)
- return intf_connected;
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if ((dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO)
&&
_dpu_core_perf_crtc_is_power_on(tmp_crtc))
{
DPU_DEBUG("video interface connected crtc:%d\n",
tmp_crtc->base.id);
- intf_connected = true;
- return intf_connected;
+ return true;
}
}
- return intf_connected;
+ return false;
}
static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
--
Jeykumar S
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 1/6] drm/msm: Remove dpu_encoder_phys_ops->hw_reset()
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
We call out of the virt encoder into phys only to call back into the
virt for hw reset. So remove the indirection and just call the virt
function directly.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 -
4 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 8f6880db5c99..7842b66fbe2e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1509,7 +1509,7 @@ static int dpu_encoder_helper_wait_event_timeout(
return rc;
}
-void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
+static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys
*phys_enc)
{
struct dpu_encoder_virt *dpu_enc;
struct dpu_hw_ctl *ctl;
@@ -1805,9 +1805,7 @@ void dpu_encoder_prepare_for_kickoff(struct
drm_encoder *drm_enc,
if (needs_hw_reset) {
trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- phys = dpu_enc->phys_encs[i];
- if (phys && phys->ops.hw_reset)
- phys->ops.hw_reset(phys);
+
dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
}
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 964efcc757a4..3a67bb9f9d9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -114,8 +114,6 @@ struct dpu_encoder_virt_ops {
* @handle_post_kickoff: Do any work necessary post-kickoff work
* @trigger_start: Process start event on physical encoder
* @needs_single_flush:Whether encoder slaves need to be
flushed
- * @hw_reset: Issue HW recovery such as CTL reset and
clear
- * DPU_ENC_ERR_NEEDS_HW_RESET state
* @irq_control: Handler to enable/disable all the encoder
IRQs
* @prepare_idle_pc: phys encoder can update the vsync_enable
status
* on idle power collapse prepare
@@ -151,7 +149,6 @@ struct dpu_encoder_phys_ops {
void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
- void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
void (*restore)(struct dpu_encoder_phys *phys);
@@ -342,15 +339,6 @@ struct dpu_encoder_phys
*dpu_encoder_phys_cmd_init(
*/
void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys
*phys_enc);
-/**
- * dpu_encoder_helper_hw_reset - issue ctl hw reset
- * This helper function may be optionally specified by physical
- * encoders if they require ctl hw reset. If state is currently
- * DPU_ENC_ERR_NEEDS_HW_RESET, it is set back to DPU_ENC_ENABLED.
- * @phys_enc: Pointer to physical encoder structure
- */
-void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc);
-
static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
struct dpu_encoder_phys *phys_enc)
{
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b2d7f0ded24c..c30ae05b3349 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -776,7 +776,6 @@ static void dpu_encoder_phys_cmd_init_ops(
ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
- ops->hw_reset = dpu_encoder_helper_hw_reset;
ops->irq_control = dpu_encoder_phys_cmd_irq_control;
ops->restore = dpu_encoder_phys_cmd_enable_helper;
ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 84de385a9f62..283a2491f3e3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -766,7 +766,6 @@ static void dpu_encoder_phys_vid_init_ops(struct
dpu_encoder_phys_ops *ops)
ops->prepare_for_kickoff =
Re: [Freedreno] [PATCH 5/6] drm/msm: dpu: Remove empty/useless labels
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
I noticed an empty label while driving by and decided to use
coccinelle to see if there were any more. Here's the spatch and the
invocation:
---
@@
identifier lbl;
expression E;
@@
- goto lbl;
+ return E;
...
- lbl:
return E;
@@
identifier lbl;
@@
- goto lbl;
+ return;
...
- lbl:
- return;
---
spatch --allow-inconsistent-paths --sp-file file.spatch --dir
drivers/gpu/drm/msm/disp/dpu1 --in-place
---
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 5 ++---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 15 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 4 +---
7 files changed, 20 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 41c5191f9056..affc9738e2b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -68,7 +68,7 @@ static bool
_dpu_core_video_mode_intf_connected(struct
drm_crtc *crtc)
bool intf_connected = false;
if (!crtc)
- goto end;
+ return intf_connected;
This can be further cleaned up by removing this intermediate var.
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if ((dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO)
&&
@@ -76,11 +76,10 @@ static bool
_dpu_core_video_mode_intf_connected(struct
drm_crtc *crtc)
DPU_DEBUG("video interface connected crtc:%d\n",
tmp_crtc->base.id);
intf_connected = true;
- goto end;
+ return intf_connected;
}
}
-end:
return intf_connected;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index c30ae05b3349..24a98f4e1f44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -496,14 +496,11 @@ static void dpu_encoder_phys_cmd_enable_helper(
_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
- goto skip_flush;
+ return;
ctl = phys_enc->hw_ctl;
ctl->ops.get_bitmask_intf(ctl, _mask, phys_enc->intf_idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
-
-skip_flush:
- return;
}
static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys
*phys_enc)
@@ -797,7 +794,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
if (!cmd_enc) {
ret = -ENOMEM;
DPU_ERROR("failed to allocate\n");
- goto fail;
+ return ERR_PTR(ret);
}
phys_enc = _enc->base;
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
@@ -855,6 +852,5 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
return phys_enc;
-fail:
return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index bfcd165e96df..0aa9b8e1ae70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -921,7 +921,7 @@ static int _dpu_format_populate_addrs_ubwc(
+ layout->plane_size[2] + layout->plane_size[3];
if (!meta)
- goto done;
+ return 0;
/* configure Y metadata plane */
layout->plane_addr[2] = base_addr;
@@ -952,12 +952,11 @@ static int _dpu_format_populate_addrs_ubwc(
layout->plane_addr[1] = 0;
if (!meta)
- goto done;
+ return 0;
layout->plane_addr[2] = base_addr;
layout->plane_addr[3] = 0;
}
-done:
return 0;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index cc3a623903f4..52fca13da176 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -177,7 +177,7 @@ static u32 dpu_hw_pp_get_line_count(struct
dpu_hw_pingpong *pp)
height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0x;
if (height < init)
- goto line_count_exit;
+ return line;
line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0x;
@@ -186,7 +186,6 @@ static u32 dpu_hw_pp_get_line_count(struct
dpu_hw_pingpong *pp)
else
line -= init;
-line_count_exit:
return line;
[Freedreno] [PATCH 2/2] drm/msm: a6xx: Fix improper u64 division
From: Sean Paul
This patch uses the proper do_div() macro to perform u64 division and
guards against overflow if the result is too large for the unsigned long
return type
Fixes: a2c3c0a54d4c drm/msm/a6xx: Add devfreq support for a6xx
Cc: Sharat Masetty
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index cdc3d59a659d..631257c297fd 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -761,18 +761,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
- u64 busy_cycles;
- unsigned long busy_time;
+ u64 busy_cycles, busy_time;
busy_cycles = gmu_read64(_gpu->gmu,
REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
- busy_time = ((busy_cycles - gpu->devfreq.busy_cycles) * 10) / 192;
+ busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
+ do_div(busy_time, 192);
gpu->devfreq.busy_cycles = busy_cycles;
- return busy_time;
+ if (WARN_ON(busy_time > ~0LU))
+ return ~0LU;
+
+ return (unsigned long)busy_time;
}
static const struct adreno_gpu_funcs funcs = {
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH 1/2] drm/msm: a5xx: Remove unneeded parens
From: Sean Paul A small fixup I posted with my v2 patch [1] that was dropped. [1]- https://lists.freedesktop.org/archives/freedreno/2018-October/003647.html Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index eabe9252ae1e..48b5304f460c 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1443,8 +1443,8 @@ static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu) busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO, REG_A5XX_RBBM_PERFCTR_RBBM_0_HI); - busy_time = (busy_cycles - gpu->devfreq.busy_cycles); - do_div(busy_time, (clk_get_rate(gpu->core_clk) / 100)); + busy_time = busy_cycles - gpu->devfreq.busy_cycles; + do_div(busy_time, clk_get_rate(gpu->core_clk) / 100); gpu->devfreq.busy_cycles = busy_cycles; -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v3 4/4] drm/msm/dpu: Replace dpu_crtc_reset by atomic helper
On Fri, Oct 05, 2018 at 05:04:03PM -0400, Bruce Wang wrote:
> Since we removed all suspend logic from the crtc code (see patch 3/4),
> dpu_crtc_reset does the same things as drm_atomic_helper_crtc_reset, so let's
> just replace it with a call to the atomic helper.
>
> v3: added patch to patchset
>
> Signed-off-by: Bruce Wang
Alllright!
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 39 +---
> 1 file changed, 1 insertion(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index ac604055a824..c5ba753d441c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -844,43 +844,6 @@ static struct drm_crtc_state
> *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
> return >base;
> }
>
> -/**
> - * dpu_crtc_reset - reset hook for CRTCs
> - * Resets the atomic state for @crtc by freeing the state pointer (which
> might
> - * be NULL, e.g. at driver load time) and allocating a new empty state
> object.
> - * @crtc: Pointer to drm crtc structure
> - */
> -static void dpu_crtc_reset(struct drm_crtc *crtc)
> -{
> - struct dpu_crtc *dpu_crtc;
> - struct dpu_crtc_state *cstate;
> -
> - if (!crtc) {
> - DPU_ERROR("invalid crtc\n");
> - return;
> - }
> -
> - /* revert suspend actions, if necessary */
> - if (dpu_kms_is_suspend_state(crtc->dev))
> - _dpu_crtc_set_suspend(crtc, false);
> -
> - /* remove previous state, if present */
> - if (crtc->state) {
> - dpu_crtc_destroy_state(crtc, crtc->state);
> - crtc->state = 0;
> - }
> -
> - dpu_crtc = to_dpu_crtc(crtc);
> - cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
> - if (!cstate) {
> - DPU_ERROR("failed to allocate state\n");
> - return;
> - }
> -
> - cstate->base.crtc = crtc;
> - crtc->state = >base;
> -}
> -
> static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
> {
> struct drm_crtc *crtc = arg;
> @@ -1499,7 +1462,7 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = {
> .set_config = drm_atomic_helper_set_config,
> .destroy = dpu_crtc_destroy,
> .page_flip = drm_atomic_helper_page_flip,
> - .reset = dpu_crtc_reset,
> + .reset = drm_atomic_helper_crtc_reset,
> .atomic_duplicate_state = dpu_crtc_duplicate_state,
> .atomic_destroy_state = dpu_crtc_destroy_state,
> .late_register = dpu_crtc_late_register,
> --
> 2.19.0.605.g01d371f741-goog
>
--
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Re: [Freedreno] [PATCH v3 3/4] drm/msm/dpu: Remove suspend state tracking from crtc
On Fri, Oct 05, 2018 at 05:04:02PM -0400, Bruce Wang wrote:
> Since drm core's modeset locks serialize atomic commits, we don't need to
> track whether or not we're in a suspended state from inside the crtc for
> dpu_crtc_enable/disable. This patch removes the suspend logic from the crtc
> and
> removes the relevant tracing from dpu_trace. Since we removed all calls
> to dpu_kms_is_suspend_state, we can remove that function and the
> suspend_state field of dpu_kms as well.
>
> v2: added patch to patchset
> v3: reworded commit body and moved deletion of dpu_kms_is_suspend_state and
> suspend_state to this patch
>
> Signed-off-by: Bruce Wang
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 48 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 16
> drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 15 +--
> 4 files changed, 6 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index d4530d60767b..ac604055a824 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -815,35 +815,6 @@ static void _dpu_crtc_vblank_enable_no_lock(
> }
> }
>
> -/**
> - * _dpu_crtc_set_suspend - notify crtc of suspend enable/disable
> - * @crtc: Pointer to drm crtc object
> - * @enable: true to enable suspend, false to indicate resume
> - */
> -static void _dpu_crtc_set_suspend(struct drm_crtc *crtc, bool enable)
> -{
> - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> -
> - DRM_DEBUG_KMS("crtc%d suspend = %d\n", crtc->base.id, enable);
> -
> - mutex_lock(_crtc->crtc_lock);
> -
> - /*
> - * If the vblank is enabled, release a power reference on suspend
> - * and take it back during resume (if it is still enabled).
> - */
> - trace_dpu_crtc_set_suspend(DRMID(_crtc->base), enable, dpu_crtc);
> - if (dpu_crtc->suspend == enable)
> - DPU_DEBUG("crtc%d suspend already set to %d, ignoring update\n",
> - crtc->base.id, enable);
> - else if (dpu_crtc->enabled && dpu_crtc->vblank_requested) {
> - _dpu_crtc_vblank_enable_no_lock(dpu_crtc, !enable);
> - }
> -
> - dpu_crtc->suspend = enable;
> - mutex_unlock(_crtc->crtc_lock);
> -}
> -
> /**
> * dpu_crtc_duplicate_state - state duplicate hook
> * @crtc: Pointer to drm crtc structure
> @@ -951,9 +922,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>
> DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
>
> - if (dpu_kms_is_suspend_state(crtc->dev))
> - _dpu_crtc_set_suspend(crtc, true);
> -
> /* Disable/save vblank irq handling */
> drm_crtc_vblank_off(crtc);
>
> @@ -966,8 +934,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
> atomic_read(_crtc->frame_pending));
>
> trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
> - if (dpu_crtc->enabled && !dpu_crtc->suspend &&
> - dpu_crtc->vblank_requested) {
> + if (dpu_crtc->enabled && dpu_crtc->vblank_requested) {
> _dpu_crtc_vblank_enable_no_lock(dpu_crtc, false);
> }
> dpu_crtc->enabled = false;
> @@ -1033,8 +1000,7 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
>
> mutex_lock(_crtc->crtc_lock);
> trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
> - if (!dpu_crtc->enabled && !dpu_crtc->suspend &&
> - dpu_crtc->vblank_requested) {
> + if (!dpu_crtc->enabled && dpu_crtc->vblank_requested) {
> _dpu_crtc_vblank_enable_no_lock(dpu_crtc, true);
> }
> dpu_crtc->enabled = true;
> @@ -1289,17 +1255,11 @@ static int dpu_crtc_atomic_check(struct drm_crtc
> *crtc,
>
> int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
> {
> - struct dpu_crtc *dpu_crtc;
> -
> - if (!crtc) {
> - DPU_ERROR("invalid crtc\n");
> - return -EINVAL;
> - }
> - dpu_crtc = to_dpu_crtc(crtc);
> + struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
>
> mutex_lock(_crtc->crtc_lock);
> trace_dpu_crtc_vblank(DRMID(_crtc->base), en, dpu_crtc);
> - if (dpu_crtc->enabled && !dpu_crtc->suspend) {
> + if (dpu_crtc->enabled) {
> _dpu_crtc_vblank_enable_no_lock(dpu_crtc, en);
> }
> dpu_crtc->vblank_requested = en;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 3723b4830335..7dc181aabb4d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -133,7 +133,6 @@ struct dpu_crtc_frame_event {
> * @play_count: frame count between crtc enable and disable
> * @vblank_cb_time : ktime at vblank count reset
> * @vblank_requested : whether the user has requested vblank events
> - * @suspend : whether
Re: [Freedreno] [PATCH v3 2/4] drm/msm: Cut dpu_kms hooks from msm_pm_suspend/resume
On Fri, Oct 05, 2018 at 05:04:01PM -0400, Bruce Wang wrote:
> Removes the traces of the non-atomic helper calls in
> msm_pm_suspend/resume since we just deleted those functions (see patch
> 1). Also removes the drm_kms_helper_poll_disable/enable calls, since
> the DRM_CONNECTOR_POLL_CONNECT flag is never set so periodic polling
> doesn't happen anyways.
>
> v2: reorganized patch order
> v3: made error checks less severe
>
> Signed-off-by: Bruce Wang
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/msm/msm_drv.c | 27 ---
> drivers/gpu/drm/msm/msm_kms.h | 3 ---
> 2 files changed, 12 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index 4904d0d41409..f5cd7f6ce4f8 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -1069,18 +1069,15 @@ static int msm_pm_suspend(struct device *dev)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct msm_drm_private *priv = ddev->dev_private;
> - struct msm_kms *kms = priv->kms;
> -
> - /* TODO: Use atomic helper suspend/resume */
> - if (kms && kms->funcs && kms->funcs->pm_suspend)
> - return kms->funcs->pm_suspend(dev);
>
> - drm_kms_helper_poll_disable(ddev);
> + if (WARN_ON(priv->pm_state))
> + drm_atomic_state_put(priv->pm_state);
>
> priv->pm_state = drm_atomic_helper_suspend(ddev);
> if (IS_ERR(priv->pm_state)) {
> - drm_kms_helper_poll_enable(ddev);
> - return PTR_ERR(priv->pm_state);
> + int ret = PTR_ERR(priv->pm_state);
> + DRM_ERROR("Failed to suspend dpu, %d\n", ret);
> + return ret;
> }
>
> return 0;
> @@ -1090,16 +1087,16 @@ static int msm_pm_resume(struct device *dev)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct msm_drm_private *priv = ddev->dev_private;
> - struct msm_kms *kms = priv->kms;
> + int ret;
>
> - /* TODO: Use atomic helper suspend/resume */
> - if (kms && kms->funcs && kms->funcs->pm_resume)
> - return kms->funcs->pm_resume(dev);
> + if (WARN_ON(!priv->pm_state))
> + return -ENOENT;
>
> - drm_atomic_helper_resume(ddev, priv->pm_state);
> - drm_kms_helper_poll_enable(ddev);
> + ret = drm_atomic_helper_resume(ddev, priv->pm_state);
> + if (!ret)
> + priv->pm_state = NULL;
>
> - return 0;
> + return ret;
> }
> #endif
>
> diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
> index fd88cebb6adb..2b81b43a4bab 100644
> --- a/drivers/gpu/drm/msm/msm_kms.h
> +++ b/drivers/gpu/drm/msm/msm_kms.h
> @@ -67,9 +67,6 @@ struct msm_kms_funcs {
> void (*set_encoder_mode)(struct msm_kms *kms,
>struct drm_encoder *encoder,
>bool cmd_mode);
> - /* pm suspend/resume hooks */
> - int (*pm_suspend)(struct device *dev);
> - int (*pm_resume)(struct device *dev);
> /* cleanup: */
> void (*destroy)(struct msm_kms *kms);
> #ifdef CONFIG_DEBUG_FS
> --
> 2.19.0.605.g01d371f741-goog
>
--
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Re: [Freedreno] [PATCH 2/3] drm/msm/dpu: Integrate interconnect API in MDSS
On Mon, Oct 08, 2018 at 02:57:29PM +0530, Sravanthi Kollukuduru wrote:
> The interconnect framework is designed to provide a
> standard kernel interface to control the settings of
> the interconnects on a SoC.
>
> The interconnect API uses a consumer/provider-based model,
> where the providers are the interconnect buses and the
> consumers could be various drivers.
>
> MDSS is one of the interconnect consumers which uses the
> interconnect APIs to get the path between endpoints and
> set its bandwidth/latency/QoS requirements for the given
> interconnected path.
>
> Signed-off-by: Sravanthi Kollukuduru
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 56
> +---
> 1 file changed, 52 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> index 2235ef8129f4..8391e5c1e559 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> @@ -4,10 +4,12 @@
> */
>
> #include "dpu_kms.h"
> +#include
>
> #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
>
> #define HW_INTR_STATUS 0x0010
> +#define MAX_AXI_PORT_COUNT 3
>
> struct dpu_mdss {
> struct msm_mdss base;
> @@ -16,8 +18,36 @@ struct dpu_mdss {
> u32 hwversion;
> struct dss_module_power mp;
> struct dpu_irq_controller irq_controller;
> + struct icc_path *path[MAX_AXI_PORT_COUNT];
> + u32 num_paths;
> };
>
> +static int dpu_mdss_parse_data_bus_icc_path(
> + struct drm_device *dev, struct dpu_mdss *dpu_mdss)
> +{
> + struct icc_path *path0 = of_icc_get(dev->dev, "port0");
> + struct icc_path *path1 = of_icc_get(dev->dev, "port1");
> + int total_num_paths = 0;
> +
> + if (IS_ERR(path0))
> + return PTR_ERR(path0);
> +
> + dpu_mdss->path[0] = path0;
> + total_num_paths = 1;
> +
> + if (!IS_ERR(path1)) {
> + dpu_mdss->path[1] = path1;
> + total_num_paths++;
> + }
> +
> + if (total_num_paths > MAX_AXI_PORT_COUNT)
> + return -EINVAL;
Since you are using fixed names you know that by design this isn't possible.
> + dpu_mdss->num_paths = total_num_paths;
> +
> + return 0;
> +}
> +
> static irqreturn_t dpu_mdss_irq(int irq, void *arg)
> {
> struct dpu_mdss *dpu_mdss = arg;
> @@ -127,7 +157,12 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
> {
> struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
> struct dss_module_power *mp = _mdss->mp;
> - int ret;
> + int ret, i;
> + u64 ab = (dpu_mdss->num_paths) ? 68/dpu_mdss->num_paths : 0;
> + u64 ib = 68;
> +
> + for (i = 0; i < dpu_mdss->num_paths; i++)
> + icc_set(dpu_mdss->path[i], ab, ib);
>
> ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
> if (ret)
> @@ -140,12 +175,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss)
> {
> struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
> struct dss_module_power *mp = _mdss->mp;
> - int ret;
> + int ret, i;
>
> ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
> if (ret)
> DPU_ERROR("clock disable failed, ret:%d\n", ret);
>
> + for (i = 0; i < dpu_mdss->num_paths; i++)
> + icc_set(dpu_mdss->path[i], 0, 0);
> +
> return ret;
> }
>
> @@ -155,6 +193,7 @@ static void dpu_mdss_destroy(struct drm_device *dev)
> struct msm_drm_private *priv = dev->dev_private;
> struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
> struct dss_module_power *mp = _mdss->mp;
> + int i;
>
> _dpu_mdss_irq_domain_fini(dpu_mdss);
>
> @@ -163,6 +202,9 @@ static void dpu_mdss_destroy(struct drm_device *dev)
> msm_dss_put_clk(mp->clk_config, mp->num_clk);
> devm_kfree(>dev, mp->clk_config);
>
> + for (i = 0; i < dpu_mdss->num_paths; i++)
> + icc_put(dpu_mdss->path[i]);
> +
> if (dpu_mdss->mmio)
> devm_iounmap(>dev, dpu_mdss->mmio);
> dpu_mdss->mmio = NULL;
> @@ -203,6 +245,12 @@ int dpu_mdss_init(struct drm_device *dev)
> }
> dpu_mdss->mmio_len = resource_size(res);
>
> + ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
> + if (ret) {
> + DPU_ERROR("failed to parse icc path, ret=%d\n", ret);
Depending on the ordering between DPU and interconnect, this might return
-EPROBE_DEFER for a few times before working. You should skip printing
an error message on -EPROBE_DEFER so it doesn't spam the log.
> + return ret;
> + }
> +
> mp = _mdss->mp;
> ret = msm_dss_parse_clock(pdev, mp);
> if (ret) {
> @@ -224,14 +272,14 @@ int dpu_mdss_init(struct drm_device *dev)
> goto irq_error;
> }
>
> + priv->mdss = _mdss->base;
> +
This seems like it might have snuck in from a different patch?
>
Re: [Freedreno] [v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC)
On Mon, Oct 08, 2018 at 07:29:03PM +0530, Sharat Masetty wrote:
>
>
> On 10/5/2018 8:37 PM, Jordan Crouse wrote:
> >On Fri, Oct 05, 2018 at 06:38:35PM +0530, Sharat Masetty wrote:
> >>The last level system cache can be partitioned to 32 different slices
> >>of which GPU has two slices preallocated. One slice is used for caching GPU
> >>buffers and the other slice is used for caching the GPU SMMU pagetables.
> >>This patch talks to the core system cache driver to acquire the slice
> >>handles,
> >>configure the SCID's to those slices and activates and deactivates the
> >>slices
> >>upon GPU power collapse and restore.
> >>
> >>Some support from the IOMMU driver is also needed to make use of the
> >>system cache. IOMMU_SYS_CACHE is a buffer protection flag which enables
> >>caching GPU data buffers in the system cache with memory attributes such
> >>as outer cacheable, read-allocate, write-allocate for buffers. The GPU
> >>then has the ability to override a few cacheability parameters which it
> >>does to override write-allocate to write-no-allocate as the GPU hardware
> >>does not benefit much from it.
> >>
> >>Similarly DOMAIN_ATTR_USE_SYS_CACHE is another domain level attribute
> >>used by the IOMMU driver to set the right attributes to cache the hardware
> >>pagetables into the system cache.
> >>
> >>Signed-off-by: Sharat Masetty
> >>---
> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 159
> >> +-
> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++
> >> drivers/gpu/drm/msm/msm_iommu.c | 13 +++
> >> drivers/gpu/drm/msm/msm_mmu.h | 3 +
> >> 4 files changed, 183 insertions(+), 1 deletion(-)
> >>
> >>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>index 177dbfc..1790dde 100644
> >>--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>@@ -8,6 +8,7 @@
> >> #include "a6xx_gmu.xml.h"
> >> #include
> >>+#include
> >> static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
> >> {
> >>@@ -674,6 +675,151 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> >>~0
> >> };
> >>+#define A6XX_LLC_NUM_GPU_SCIDS 5
> >>+#define A6XX_GPU_LLC_SCID_NUM_BITS 5
> >>+
> >>+#define A6XX_GPU_LLC_SCID_MASK \
> >>+ ((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1)
> >>+
> >>+#define A6XX_GPUHTW_LLC_SCID_SHIFT 25
> >>+#define A6XX_GPUHTW_LLC_SCID_MASK \
> >>+ (((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)
> >>+
> >>+static inline void a6xx_gpu_cx_rmw(struct a6xx_llc *llc,
> >>+ u32 reg, u32 mask, u32 or)
> >>+{
> >>+ msm_rmw(llc->mmio + (reg << 2), mask, or);
> >>+}
> >>+
> >>+static void a6xx_llc_deactivate(struct msm_gpu *gpu)
> >>+{
> >>+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> >>+ struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> >>+ struct a6xx_llc *llc = _gpu->llc;
> >>+
> >>+ llcc_slice_deactivate(llc->gpu_llc_slice);
> >>+ llcc_slice_deactivate(llc->gpuhtw_llc_slice);
> >>+}
> >>+
> >>+static void a6xx_llc_activate(struct msm_gpu *gpu)
> >>+{
> >>+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> >>+ struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> >>+ struct a6xx_llc *llc = _gpu->llc;
> >>+
> >>+ if (!llc->mmio)
> >>+ return;
> >>+
> >>+ /*
> >>+* If the LLCC_GPU slice activated, program the sub-cache ID for all
> >>+* GPU blocks
> >>+*/
> >>+ if (!llcc_slice_activate(llc->gpu_llc_slice))
> >>+ a6xx_gpu_cx_rmw(llc,
> >>+ REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,
> >>+ A6XX_GPU_LLC_SCID_MASK,
> >>+ (llc->cntl1_regval &
> >>+A6XX_GPU_LLC_SCID_MASK));
> >>+
> >>+ /*
> >>+* If the LLCC_GPUHTW slice activated, program the sub-cache ID for the
> >>+* GPU pagetables
> >>+*/
> >>+ if (!llcc_slice_activate(llc->gpuhtw_llc_slice))
> >>+ a6xx_gpu_cx_rmw(llc,
> >>+ REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,
> >>+ A6XX_GPUHTW_LLC_SCID_MASK,
> >>+ (llc->cntl1_regval &
> >>+A6XX_GPUHTW_LLC_SCID_MASK));
> >>+
> >>+ /* Program cacheability overrides */
> >>+ a6xx_gpu_cx_rmw(llc, REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF,
> >>+ llc->cntl0_regval);
> >>+}
> >>+
> >>+void a6xx_llc_slices_destroy(struct a6xx_llc *llc)
> >>+{
> >>+ if (llc->mmio) {
> >>+ iounmap(llc->mmio);
> >>+ llc->mmio = NULL;
> >>+ }
> >>+
> >>+ llcc_slice_putd(llc->gpu_llc_slice);
> >>+ llc->gpu_llc_slice = NULL;
> >
> >I don't think these need to be put back to NULL - we shouldn't touch them
> >again
> >after this point.
> >
> >>+
> >>+ llcc_slice_putd(llc->gpuhtw_llc_slice);
> >>+ llc->gpuhtw_llc_slice = NULL;
> >>+}
> >>+
> >>+static int a6xx_llc_slices_init(struct platform_device
Re: [Freedreno] [v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC)
On 10/5/2018 8:37 PM, Jordan Crouse wrote:
On Fri, Oct 05, 2018 at 06:38:35PM +0530, Sharat Masetty wrote:
The last level system cache can be partitioned to 32 different slices
of which GPU has two slices preallocated. One slice is used for caching GPU
buffers and the other slice is used for caching the GPU SMMU pagetables.
This patch talks to the core system cache driver to acquire the slice handles,
configure the SCID's to those slices and activates and deactivates the slices
upon GPU power collapse and restore.
Some support from the IOMMU driver is also needed to make use of the
system cache. IOMMU_SYS_CACHE is a buffer protection flag which enables
caching GPU data buffers in the system cache with memory attributes such
as outer cacheable, read-allocate, write-allocate for buffers. The GPU
then has the ability to override a few cacheability parameters which it
does to override write-allocate to write-no-allocate as the GPU hardware
does not benefit much from it.
Similarly DOMAIN_ATTR_USE_SYS_CACHE is another domain level attribute
used by the IOMMU driver to set the right attributes to cache the hardware
pagetables into the system cache.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 159 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++
drivers/gpu/drm/msm/msm_iommu.c | 13 +++
drivers/gpu/drm/msm/msm_mmu.h | 3 +
4 files changed, 183 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 177dbfc..1790dde 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -8,6 +8,7 @@
#include "a6xx_gmu.xml.h"
#include
+#include
static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
{
@@ -674,6 +675,151 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
~0
};
+#define A6XX_LLC_NUM_GPU_SCIDS 5
+#define A6XX_GPU_LLC_SCID_NUM_BITS 5
+
+#define A6XX_GPU_LLC_SCID_MASK \
+ ((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1)
+
+#define A6XX_GPUHTW_LLC_SCID_SHIFT 25
+#define A6XX_GPUHTW_LLC_SCID_MASK \
+ (((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)
+
+static inline void a6xx_gpu_cx_rmw(struct a6xx_llc *llc,
+ u32 reg, u32 mask, u32 or)
+{
+ msm_rmw(llc->mmio + (reg << 2), mask, or);
+}
+
+static void a6xx_llc_deactivate(struct msm_gpu *gpu)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+ struct a6xx_llc *llc = _gpu->llc;
+
+ llcc_slice_deactivate(llc->gpu_llc_slice);
+ llcc_slice_deactivate(llc->gpuhtw_llc_slice);
+}
+
+static void a6xx_llc_activate(struct msm_gpu *gpu)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+ struct a6xx_llc *llc = _gpu->llc;
+
+ if (!llc->mmio)
+ return;
+
+ /*
+* If the LLCC_GPU slice activated, program the sub-cache ID for all
+* GPU blocks
+*/
+ if (!llcc_slice_activate(llc->gpu_llc_slice))
+ a6xx_gpu_cx_rmw(llc,
+ REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,
+ A6XX_GPU_LLC_SCID_MASK,
+ (llc->cntl1_regval &
+A6XX_GPU_LLC_SCID_MASK));
+
+ /*
+* If the LLCC_GPUHTW slice activated, program the sub-cache ID for the
+* GPU pagetables
+*/
+ if (!llcc_slice_activate(llc->gpuhtw_llc_slice))
+ a6xx_gpu_cx_rmw(llc,
+ REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,
+ A6XX_GPUHTW_LLC_SCID_MASK,
+ (llc->cntl1_regval &
+A6XX_GPUHTW_LLC_SCID_MASK));
+
+ /* Program cacheability overrides */
+ a6xx_gpu_cx_rmw(llc, REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF,
+ llc->cntl0_regval);
+}
+
+void a6xx_llc_slices_destroy(struct a6xx_llc *llc)
+{
+ if (llc->mmio) {
+ iounmap(llc->mmio);
+ llc->mmio = NULL;
+ }
+
+ llcc_slice_putd(llc->gpu_llc_slice);
+ llc->gpu_llc_slice = NULL;
I don't think these need to be put back to NULL - we shouldn't touch them again
after this point.
+
+ llcc_slice_putd(llc->gpuhtw_llc_slice);
+ llc->gpuhtw_llc_slice = NULL;
+}
+
+static int a6xx_llc_slices_init(struct platform_device *pdev,
+ struct a6xx_llc *llc)
+{
+ int i;
+
+ /* Map registers */
+ llc->mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
+ if (IS_ERR(llc->mmio)) {
+ llc->mmio = NULL;
+ return -1;
Return a valid error code here even if we don't care what it is. -ENODEV maybe.
And in fact, if we don't care what it is (LLCC is very
Re: [Freedreno] [v2 4/7] drm/msm/adreno: Add registers in the GPU CX domain
On 10/5/2018 8:31 PM, Jordan Crouse wrote: On Fri, Oct 05, 2018 at 06:38:32PM +0530, Sharat Masetty wrote: Add the registers needed for configuring the system cache slice info and other parameters in the GPU. This would conflict with msm-next or at least with the latest update from the rnndb. It is good to have this out here for people to prototype but we need to do a better job of keeping rnndb up to date so please send out a update for that as soon as you can - it is a pretty easy thing for Rob to generate and push new headers if we know that the database is good. Jordan Okay, got it. rnndb patch is @https://patchwork.freedesktop.org/patch/255356/. Added Rob to this thread too. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 2206765..2645b8f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1780,5 +1780,8 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A6XX_PDC_GPU_SEQ_MEM_00x +#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0 0x0001 + +#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1 0x0002 #endif /* A6XX_XML */ -- 1.9.1 -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] rnndb: Add additional a6xx registers in gpu CX
Add a few additional registers in the CX domain needed to implement system cache support for a6xx. --- rnndb/adreno/a6xx.xml | 5 + 1 file changed, 5 insertions(+) diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml index b2bd64b..78ba1ce 100644 --- a/rnndb/adreno/a6xx.xml +++ b/rnndb/adreno/a6xx.xml @@ -2963,4 +2963,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> + + + + + -- 1.9.1 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 3/3] dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845
Add interconnect properties such as interconnect provider specifier , the edge source and destination ports which are required by the interconnect API to configure interconnect path for MDSS. Signed-off-by: Sravanthi Kollukuduru --- Documentation/devicetree/bindings/display/msm/dpu.txt | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index ad2e8830324e..abd4d99b5030 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -28,6 +28,11 @@ Required properties: - #address-cells: number of address cells for the MDSS children. Should be 1. - #size-cells: Should be 1. - ranges: parent bus address space is the same as the child bus address space. +- interconnects : pairs of phandles and interconnect provider specifier to + denote the edge source and destination ports of the interconnect path. +- interconnect-names : list of interconnect path name strings sorted in the + same order as the interconnects property. Consumers drivers will use + interconnect-names to match interconnect paths with interconnect specifiers. Optional properties: - assigned-clocks: list of clock specifiers for clocks needing rate assignment @@ -86,6 +91,9 @@ Example: interrupt-controller; #interrupt-cells = <1>; + interconnects = < 38 512>; + interconnect-names = "port0"; + iommus = <_iommu 0>; #address-cells = <2>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 0/3] Use interconnect API in MDSS on SDM845
The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the appropriate power/performance profile. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth requirements for the given interconnected path. Subsequently, there is a clean up patch to remove all the references of the DPU custom bus scaling. There is corresponding DT patch with the source and destination ports defined for display driver which will be sent separately. Sravanthi Kollukuduru (3): drm/msm/dpu: clean up references of DPU custom bus scaling drm/msm/dpu: Integrate interconnect API in MDSS dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845 .../devicetree/bindings/display/msm/dpu.txt| 8 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 157 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 56 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 21 +-- 8 files changed, 143 insertions(+), 219 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
