Re: [Freedreno] [PATCH] drm/msm/mdp5: enable autocommit
Hi Jeffrey,
On Wed, Nov 13, 2019 at 06:23:34AM -0500, Brian Masney wrote:
> On Tue, Nov 12, 2019 at 08:38:27AM -0700, Jeffrey Hugo wrote:
> > On Tue, Nov 12, 2019 at 3:49 AM Brian Masney wrote:
> > >
> > > Since the introduction of commit 2d99ced787e3 ("drm/msm: async commit
> > > support"), command-mode panels began throwing the following errors:
> > >
> > > msm fd90.mdss: pp done time out, lm=0
> > >
> > > Let's fix this by enabling the autorefresh feature that's available in
> > > the MDP starting at version 1.0. This will cause the MDP to
> > > automatically send a frame to the panel every time the panel invokes
> > > the TE signal, which will trigger the PP_DONE IRQ. This requires not
> > > sending a START signal for command-mode panels.
> > >
> > > This fixes the error and gives us a counter for command-mode panels that
> > > we can use to implement async commit support for the MDP5 in a follow up
> > > patch.
> > >
> > > Signed-off-by: Brian Masney
> > > Suggested-by: Jeffrey Hugo
> > > ---
> > > drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 15 ++-
> > > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c | 9 +
> > > 2 files changed, 15 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
> > > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
> > > index 05cc04f729d6..539348cb6331 100644
> > > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
> > > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
> > > @@ -456,6 +456,7 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc
> > > *crtc,
> > > {
> > > struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
> > > struct mdp5_crtc_state *mdp5_cstate =
> > > to_mdp5_crtc_state(crtc->state);
> > > + struct mdp5_pipeline *pipeline = _cstate->pipeline;
> > > struct mdp5_kms *mdp5_kms = get_kms(crtc);
> > > struct device *dev = _kms->pdev->dev;
> > >
> > > @@ -493,9 +494,21 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc
> > > *crtc,
> > >
> > > mdp_irq_register(_kms->base, _crtc->err);
> > >
> > > - if (mdp5_cstate->cmd_mode)
> > > + if (mdp5_cstate->cmd_mode) {
> > > mdp_irq_register(_kms->base, _crtc->pp_done);
> > >
> > > + /*
> > > +* Enable autorefresh so we get regular ping/pong IRQs.
> > > +* - Bit 31 is the enable bit
> > > +* - Bits 0-15 represent the frame count, specifically
> > > how many
> > > +* TE events before the MDP sends a frame.
> > > +*/
> > > + mdp5_write(mdp5_kms,
> > > +
> > > REG_MDP5_PP_AUTOREFRESH_CONFIG(pipeline->mixer->pp),
> > > + BIT(31) | BIT(0));
> > > + crtc_flush_all(crtc);
> > > + }
> > > +
> > > mdp5_crtc->enabled = true;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
> > > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
> > > index 030279d7b64b..aee295abada3 100644
> > > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
> > > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
> > > @@ -187,14 +187,7 @@ static bool start_signal_needed(struct mdp5_ctl *ctl,
> > > if (!ctl->encoder_enabled)
> > > return false;
> > >
> > > - switch (intf->type) {
> > > - case INTF_WB:
> > > - return true;
> > > - case INTF_DSI:
> > > - return intf->mode == MDP5_INTF_DSI_MODE_COMMAND;
> > > - default:
> > > - return false;
> > > - }
> > > + return intf->type == INTF_WB;
> > > }
> >
> > I don't think this fully works.
> >
> > The whole "flush" thing exists because the configuration is double
> > buffered. You write to the flush register to tell the hardware to
> > pickup the new configuration, but it doesn't do that automatically.
> > It only picks up the new config on the next "vsync". When you have a
> > video mode panel, you have the timing engine running, which drives
> > that. With a command mode panel, you have either the start signal, or
> > the auto refresh to do the same, but you have a bit of a chicken and
> > egg situation where if you are programming the hardware from scratch,
> > autorefresh isn't already enabled to then pickup the config to enable
> > autorefresh. In this case, you'll need a single start to kick
> > everything off. However, if say the bootloader already configured
> > things and has autorefresh running, then you need to not do that start
> > because you'll overload the DSI like you saw.
>
> As part of my testing for this work, I added a log statement to
> mdp5_crtc_pp_done_irq() and it shows that a PP_IRQ comes in consistently
> every ~0.0166 seconds, which is about 60 HZ. Without this change, plus
> the 3 commits I mentioned in an earlier email related to the async
> commit support, the PP IRQs come in at a variety of times: between every
> ~0.0140 and ~0.2224
Re: [Freedreno] [PATCH v1] drm/msm: add support for 2.4.1 DSI version for sc7180 soc
On Thu, Nov 28, 2019 at 11:05 PM Harigovindan P wrote:
>
> Changes in v1:
> -Modify commit text to indicate DSI version and SOC detail(Jeffrey
> Hugo).
> -Splitting visionox panel driver code out into a
> different patch(set), since panel drivers are merged into
> drm-next via a different tree(Rob Clark).
>
> Signed-off-by: Harigovindan P
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 21 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index b7b7c1a..7b967dd 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -133,6 +133,10 @@ static const char * const dsi_sdm845_bus_clk_names[] = {
> "iface", "bus",
> };
>
> +static const char * const dsi_sc7180_bus_clk_names[] = {
> + "iface", "bus",
> +};
> +
> static const struct msm_dsi_config sdm845_dsi_cfg = {
> .io_offset = DSI_6G_REG_SHIFT,
> .reg_cfg = {
> @@ -147,6 +151,20 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
> .num_dsi = 2,
> };
>
> +static const struct msm_dsi_config sc7180_dsi_cfg = {
> + .io_offset = DSI_6G_REG_SHIFT,
> + .reg_cfg = {
> + .num = 1,
> + .regs = {
> + {"vdda", 21800, 4 },/* 1.2 V */
> + },
> + },
> + .bus_clk_names = dsi_sc7180_bus_clk_names,
> + .num_bus_clks = ARRAY_SIZE(dsi_sc7180_bus_clk_names),
> + .io_start = { 0xae94000 },
> + .num_dsi = 1,
> +};
> +
> const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
> .link_clk_enable = dsi_link_clk_enable_v2,
> .link_clk_disable = dsi_link_clk_disable_v2,
> @@ -201,6 +219,9 @@ static const struct msm_dsi_cfg_handler
> dsi_cfg_handlers[] = {
> _dsi_cfg, _dsi_6g_v2_host_ops},
> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
> _dsi_cfg, _dsi_6g_v2_host_ops},
> + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
> + _dsi_cfg, _dsi_6g_v2_host_ops},
> +
> };
>
> const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> index e2b7a7d..9919536 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> @@ -19,6 +19,7 @@
> #define MSM_DSI_6G_VER_MINOR_V1_4_10x10040001
> #define MSM_DSI_6G_VER_MINOR_V2_2_00x2000
> #define MSM_DSI_6G_VER_MINOR_V2_2_10x20020001
> +#define MSM_DSI_6G_VER_MINOR_V2_4_10x20040001
>
> #define MSM_DSI_V2_VER_MINOR_8064 0x0
>
> --
> 2.7.4
>
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Re: [Freedreno] [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support
On Mon, Dec 2, 2019 at 5:48 AM Chandan Uddaraju wrote:
>
> Add the needed displayPort files to enable DP driver
> on msm target.
>
> "dp_display" module is the main module that calls into
> other sub-modules. "dp_drm" file represents the interface
> between DRM framework and DP driver.
>
> changes in v2:
> -- Update copyright markings on all relevant files.
> -- Change pr_err() to DRM_ERROR()
> -- Use APIs directly instead of function pointers.
> -- Use drm_display_mode structure to store link parameters in the driver.
> -- Use macros for register definitions instead of hardcoded values.
> -- Replace writel_relaxed/readl_relaxed with writel/readl
>and remove memory barriers.
> -- Remove unnecessary NULL checks.
> -- Use drm helper functions for dpcd read/write.
> -- Use DRM_DEBUG_DP for debug msgs.
>
> changes in V3:
> -- Removed changes in dpu_io_util.[ch]
> -- Added locking around "is_connected" flag and removed atomic_set()
> -- Removed the argument validation checks in all the static functions
>except initialization functions and few API calls across msm/dp files
> -- Removed hardcoded values for register reads/writes
> -- Removed vreg related generic structures.
> -- Added return values where ever necessary.
> -- Updated dp_ctrl_on function.
> -- Calling the ctrl specific catalog functions directly instead of
>function pointers.
> -- Added seperate change that adds standard value in drm_dp_helper file.
> -- Added separate change in this list that is used to initialize
>displayport in DPU driver.
> -- Added change to use drm_dp_get_adjust_request_voltage() function.
>
> Signed-off-by: Chandan Uddaraju
> ---
[snip]
> +
> +void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
> + u32 rate, u32 stream_rate_khz,
> + bool fixed_nvid)
> +{
> + u32 pixel_m, pixel_n;
> + u32 mvid, nvid;
> + u64 mvid_calc;
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> +
> + if (fixed_nvid) {
> + nvid = DP_LINK_CONSTANT_N_VALUE;
> + DRM_DEBUG_DP("use fixed NVID=0x%x\n", nvid);
> +
> + /*
> +* For intermediate results, use 64 bit arithmetic to avoid
> +* loss of precision.
> +*/
> + mvid_calc = (u64) stream_rate_khz * nvid;
> + mvid_calc = div_u64(mvid_calc, rate);
> +
> + /*
> +* truncate back to 32 bits as this final divided value will
> +* always be within the range of a 32 bit unsigned int.
> +*/
> + mvid = (u32) mvid_calc;
> + DRM_DEBUG_DP("link rate=%dkbps, stream_rate_khz=%uKhz",
> + rate, stream_rate_khz);
> + } else {
> + pixel_m = dp_read_cc(catalog, MMSS_DP_PIXEL_M);
> + pixel_n = dp_read_cc(catalog, MMSS_DP_PIXEL_N);
Can we just calculate m/n from the rate instead. That gets rid of
having to ioremap() the dispcc region, which is really ugly.
BR,
-R
> + DRM_DEBUG_DP("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m,
> pixel_n);
> +
> + mvid = (pixel_m & 0x) * 5;
> + nvid = (0x & (~pixel_n)) + (pixel_m & 0x);
> +
> + DRM_DEBUG_DP("rate = %d\n", rate);
> +
> + switch (drm_dp_link_rate_to_bw_code(rate)) {
> + case DP_LINK_BW_5_4:
> + nvid *= 2;
> + break;
> + case DP_LINK_BW_8_1:
> + nvid *= 3;
> + break;
> + default:
> + break;
> + }
> + }
> +
> + DRM_DEBUG_DP("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
> + dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid);
> + dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid);
> +}
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Re: [Freedreno] [PATCH] rnndb: Add GBIF registers for a6xx GPU
On Thu, Nov 28, 2019 at 11:41 PM Sharat Masetty wrote: > > Add GBIF register definitions required to implement a618 > GPU revision > > Signed-off-by: Sharat Masetty thanks, I've pushed the xml to envytools BR, -R > --- > rnndb/adreno/a6xx.xml | 26 ++ > 1 file changed, 26 insertions(+) > > diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml > index 747f071..2d2063a 100644 > --- a/rnndb/adreno/a6xx.xml > +++ b/rnndb/adreno/a6xx.xml > @@ -1748,6 +1748,32 @@ to upconvert to 32b float internally? > > > > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > > > > -- > 1.9.1 > ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support
On Mon, Dec 2, 2019 at 5:48 AM Chandan Uddaraju wrote: > > Add the needed displayPort files to enable DP driver > on msm target. > > "dp_display" module is the main module that calls into > other sub-modules. "dp_drm" file represents the interface > between DRM framework and DP driver. > > changes in v2: > -- Update copyright markings on all relevant files. > -- Change pr_err() to DRM_ERROR() > -- Use APIs directly instead of function pointers. > -- Use drm_display_mode structure to store link parameters in the driver. > -- Use macros for register definitions instead of hardcoded values. > -- Replace writel_relaxed/readl_relaxed with writel/readl >and remove memory barriers. > -- Remove unnecessary NULL checks. > -- Use drm helper functions for dpcd read/write. > -- Use DRM_DEBUG_DP for debug msgs. > > changes in V3: > -- Removed changes in dpu_io_util.[ch] > -- Added locking around "is_connected" flag and removed atomic_set() > -- Removed the argument validation checks in all the static functions >except initialization functions and few API calls across msm/dp files > -- Removed hardcoded values for register reads/writes > -- Removed vreg related generic structures. > -- Added return values where ever necessary. > -- Updated dp_ctrl_on function. > -- Calling the ctrl specific catalog functions directly instead of >function pointers. > -- Added seperate change that adds standard value in drm_dp_helper file. > -- Added separate change in this list that is used to initialize >displayport in DPU driver. > -- Added change to use drm_dp_get_adjust_request_voltage() function. > > Signed-off-by: Chandan Uddaraju > --- [snip] > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index f96e142..29ac7d3 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -967,6 +967,9 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder > *drm_enc, > > trace_dpu_enc_mode_set(DRMID(drm_enc)); > > + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) > + msm_dp_display_mode_set(priv->dp, drm_enc, mode, adj_mode); > + for better or for worse, DSI and HDMI backends create an internal drm_bridge object to avoid all of these shunts over from the encoder. We might be still the only driver to do this, but IMHO it is better than making each encoder know about each backend, so we might as well stick with that. (same goes for the other 'if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS)'s) BR, -R > list_for_each_entry(conn_iter, connector_list, head) > if (conn_iter->encoder == drm_enc) > conn = conn_iter; ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [DPU PATCH v3 0/5] List of patches for DP drivers on SnapDragon
On Mon, Dec 2, 2019 at 5:47 AM Chandan Uddaraju wrote: > > These patches are to enable DisplayPort driver on SanpDragon. > > These patches have dependency on clock driver changes that > provide DP clock support. This looks like just a functional/runtime dependency? Ie. it would only be the corresponding dt nodes that have compile time dependency on the clock driver? (vidcc, I assume?) BR, -R > > Changes in V2: > Core Dp driver: > -- Update copyright markings on all relevant files. > -- Change pr_err() to DRM_ERROR() > -- Use APIs directly instead of function pointers. > -- Use drm_display_mode structure to store link parameters in the driver. > -- Use macros for register definitions instead of hardcoded values in > dp_catalog.c file. > -- Replace writel_relaxed/readl_relaxed with writel/readl and remove > memory barriers. > -- Remove unnecessary NULL checks. > -- Use drm helper functions for dpcd read/write. > -- Use DRM_DEBUG_DP for debug msgs. > DP PLL driver: > -- Update copyright markings on all relevant files. > -- Use DRM_DEBUG_DP for debug msgs. > > Changes in V3: > Core Dp Driver: > -- Removed changes in dpu_io_util.[ch] > -- Added locking around "is_connected" flag and removed atomic_set() > -- Removed the argument validation checks in all the static functions >except initialization functions and few API calls across msm/dp files > -- Removed hardcoded values for register reads/writes > -- Removed vreg related generic structures. > -- Added return values where ever necessary. > -- Updated dp_ctrl_on function. > -- Calling the ctrl specific catalog functions directly instead of >function pointers. > -- Added seperate change that adds standard value in drm_dp_helper file. > -- Added separate change in this list that is used to initialize >displayport in DPU driver. > -- Added change to use drm_dp_get_adjust_request_voltage() function. > > > Chandan Uddaraju (4): > dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon > 845 > drm: add constant N value in helper file > drm/msm/dp: add displayPort driver support > drm/msm/dp: add support for DP PLL driver > > Jeykumar Sankaran (1): > drm/msm/dpu: add display port support in DPU > > .../devicetree/bindings/display/msm/dp.txt | 249 +++ > .../devicetree/bindings/display/msm/dpu.txt| 16 +- > drivers/gpu/drm/i915/display/intel_display.c |2 +- > drivers/gpu/drm/msm/Kconfig| 22 + > drivers/gpu/drm/msm/Makefile | 17 + > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 28 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 65 +- > drivers/gpu/drm/msm/dp/dp_aux.c| 548 +++ > drivers/gpu/drm/msm/dp/dp_aux.h| 37 + > drivers/gpu/drm/msm/dp/dp_catalog.c| 841 +++ > drivers/gpu/drm/msm/dp/dp_catalog.h| 84 ++ > drivers/gpu/drm/msm/dp/dp_ctrl.c | 1590 > > drivers/gpu/drm/msm/dp/dp_ctrl.h | 34 + > drivers/gpu/drm/msm/dp/dp_display.c| 997 > drivers/gpu/drm/msm/dp/dp_display.h| 32 + > drivers/gpu/drm/msm/dp/dp_drm.c| 173 +++ > drivers/gpu/drm/msm/dp/dp_drm.h| 20 + > drivers/gpu/drm/msm/dp/dp_extcon.c | 216 +++ > drivers/gpu/drm/msm/dp/dp_extcon.h | 84 ++ > drivers/gpu/drm/msm/dp/dp_link.c | 1185 +++ > drivers/gpu/drm/msm/dp/dp_link.h | 132 ++ > drivers/gpu/drm/msm/dp/dp_panel.c | 450 ++ > drivers/gpu/drm/msm/dp/dp_panel.h | 92 ++ > drivers/gpu/drm/msm/dp/dp_parser.c | 496 ++ > drivers/gpu/drm/msm/dp/dp_parser.h | 226 +++ > drivers/gpu/drm/msm/dp/dp_power.c | 558 +++ > drivers/gpu/drm/msm/dp/dp_power.h | 51 + > drivers/gpu/drm/msm/dp/dp_reg.h| 488 ++ > drivers/gpu/drm/msm/dp/pll/dp_pll.c| 135 ++ > drivers/gpu/drm/msm/dp/pll/dp_pll.h| 57 + > drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c | 401 + > drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h | 86 ++ > drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c | 494 ++ > drivers/gpu/drm/msm/msm_drv.c |2 + > drivers/gpu/drm/msm/msm_drv.h | 42 + > include/drm/drm_dp_helper.h|1 + > 36 files changed, 9931 insertions(+), 20 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt > create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.c > create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.h > create mode 100644
Re: [Freedreno] [DPU PATCH v3 2/5] drm: add constant N value in helper file
On Mon, 02 Dec 2019, Chandan Uddaraju wrote:
> The constant N value (0x8000) is used by multiple DP
> drivers. Define this value in header file and use this
> in the existing i915 display driver.
>
> Signed-off-by: Chandan Uddaraju
Reviewed-by: Jani Nikula
and ack for merging via drm-misc or whichever tree you find suitable.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> include/drm/drm_dp_helper.h | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ce05e80..1a4ccfd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7496,7 +7496,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
>* which the devices expect also in synchronous clock mode.
>*/
> if (constant_n)
> - *ret_n = 0x8000;
> + *ret_n = DP_LINK_CONSTANT_N_VALUE;
> else
> *ret_n = min_t(unsigned int, roundup_pow_of_two(n),
> DATA_LINK_N_MAX);
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8364502..69b8251 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1357,6 +1357,7 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
> * DisplayPort link
> */
> #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
> +#define DP_LINK_CONSTANT_N_VALUE 0x8000
>
> struct drm_dp_link {
> unsigned char revision;
--
Jani Nikula, Intel Open Source Graphics Center
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[Freedreno] [DPU PATCH v3 4/5] drm/msm/dp: add support for DP PLL driver
Add the needed DP PLL specific files to support
display port interface on msm targets.
The DP driver calls the DP PLL driver registration.
The DP driver sets the link and pixel clock sources.
Changes in v2:
-- Update copyright markings on all relevant files.
-- Use DRM_DEBUG_DP for debug msgs.
Signed-off-by: Chandan Uddaraju
---
drivers/gpu/drm/msm/Kconfig | 13 +
drivers/gpu/drm/msm/Makefile | 4 +
drivers/gpu/drm/msm/dp/dp_display.c | 48 +++
drivers/gpu/drm/msm/dp/dp_display.h | 3 +
drivers/gpu/drm/msm/dp/dp_parser.h| 4 +
drivers/gpu/drm/msm/dp/dp_power.h | 1 -
drivers/gpu/drm/msm/dp/pll/dp_pll.c | 135 +++
drivers/gpu/drm/msm/dp/pll/dp_pll.h | 57 +++
drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c | 401 +
drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h | 86 +
drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c | 494 ++
11 files changed, 1245 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.c
create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.h
create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h
create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 7946cb1..e73ad23 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -66,6 +66,19 @@ config DRM_MSM_DP
display support is enabled through this config option. It can
be primary or secondary display on device.
+config DRM_MSM_DP_PLL
+ bool "Enable DP PLL driver in MSM DRM"
+ depends on DRM_MSM_DP && COMMON_CLK
+ help
+ Choose this option to enable DP PLL driver which provides DP
+ source clocks under common clock framework.
+
+config DRM_MSM_DP_10NM_PLL
+ bool "Enable DP 10nm PLL driver in MSM DRM (used by SDM845)"
+ depends on DRM_MSM_DP_PLL
+ help
+ Choose this option if DP PLL on SDM845 is used on the platform.
+
config DRM_MSM_DSI
bool "Enable DSI support in MSM DRM driver"
depends on DRM_MSM
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 5939f41..3ba0c8b 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -140,4 +140,8 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o
endif
+msm-$(CONFIG_DRM_MSM_DP_PLL)+= dp/pll/dp_pll.o
+msm-$(CONFIG_DRM_MSM_DP_10NM_PLL)+= dp/pll/dp_pll_10nm.o \
+ dp/pll/dp_pll_10nm_util.o
+
obj-$(CONFIG_DRM_MSM) += msm.o
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index a893542..b57a8c1 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -61,6 +61,48 @@ struct dp_display_private {
{}
};
+static int dp_get_pll(struct dp_display_private *dp_priv)
+{
+ struct platform_device *pdev = NULL;
+ struct platform_device *pll_pdev;
+ struct device_node *pll_node;
+ struct dp_parser *dp_parser = NULL;
+
+ if (!dp_priv) {
+ DRM_ERROR("Invalid Arguments\n");
+ return -EINVAL;
+ }
+
+ pdev = dp_priv->pdev;
+ dp_parser = dp_priv->parser;
+
+ if (!dp_parser) {
+ DRM_DEV_ERROR(>dev, "%s: Parser not initialized\n",
__func__);
+ return -EINVAL;
+ }
+
+ pll_node = of_parse_phandle(pdev->dev.of_node, "pll-node", 0);
+ if (!pll_node) {
+ DRM_DEV_ERROR(>dev, "%s: cannot find pll device\n",
__func__);
+ return -ENXIO;
+ }
+
+ pll_pdev = of_find_device_by_node(pll_node);
+ if (pll_pdev)
+ dp_parser->pll = platform_get_drvdata(pll_pdev);
+
+ of_node_put(pll_node);
+
+ if (!pll_pdev || !dp_parser->pll) {
+ DRM_DEV_ERROR(>dev, "%s: pll driver is not ready\n",
__func__);
+ return -EPROBE_DEFER;
+ }
+
+ dp_parser->pll_dev = get_device(_pdev->dev);
+
+ return 0;
+}
+
static irqreturn_t dp_display_irq(int irq, void *dev_id)
{
struct dp_display_private *dp = dev_id;
@@ -114,6 +156,10 @@ static int dp_display_bind(struct device *dev, struct
device *master,
goto end;
}
+ rc = dp_get_pll(dp);
+ if (rc)
+ goto end;
+
rc = dp_aux_register(dp->aux);
if (rc) {
DRM_ERROR("DRM DP AUX register failed\n");
@@ -812,6 +858,7 @@ int __init msm_dp_register(void)
{
int ret;
+ msm_dp_pll_driver_register();
ret = platform_driver_register(_display_driver);
if (ret) {
DRM_ERROR("driver register failed");
@@ -823,6 +870,7 @@ int __init msm_dp_register(void)
void __exit
[Freedreno] [DPU PATCH v3 0/5] List of patches for DP drivers on SnapDragon
These patches are to enable DisplayPort driver on SanpDragon. These patches have dependency on clock driver changes that provide DP clock support. Changes in V2: Core Dp driver: -- Update copyright markings on all relevant files. -- Change pr_err() to DRM_ERROR() -- Use APIs directly instead of function pointers. -- Use drm_display_mode structure to store link parameters in the driver. -- Use macros for register definitions instead of hardcoded values in dp_catalog.c file. -- Replace writel_relaxed/readl_relaxed with writel/readl and remove memory barriers. -- Remove unnecessary NULL checks. -- Use drm helper functions for dpcd read/write. -- Use DRM_DEBUG_DP for debug msgs. DP PLL driver: -- Update copyright markings on all relevant files. -- Use DRM_DEBUG_DP for debug msgs. Changes in V3: Core Dp Driver: -- Removed changes in dpu_io_util.[ch] -- Added locking around "is_connected" flag and removed atomic_set() -- Removed the argument validation checks in all the static functions except initialization functions and few API calls across msm/dp files -- Removed hardcoded values for register reads/writes -- Removed vreg related generic structures. -- Added return values where ever necessary. -- Updated dp_ctrl_on function. -- Calling the ctrl specific catalog functions directly instead of function pointers. -- Added seperate change that adds standard value in drm_dp_helper file. -- Added separate change in this list that is used to initialize displayport in DPU driver. -- Added change to use drm_dp_get_adjust_request_voltage() function. Chandan Uddaraju (4): dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845 drm: add constant N value in helper file drm/msm/dp: add displayPort driver support drm/msm/dp: add support for DP PLL driver Jeykumar Sankaran (1): drm/msm/dpu: add display port support in DPU .../devicetree/bindings/display/msm/dp.txt | 249 +++ .../devicetree/bindings/display/msm/dpu.txt| 16 +- drivers/gpu/drm/i915/display/intel_display.c |2 +- drivers/gpu/drm/msm/Kconfig| 22 + drivers/gpu/drm/msm/Makefile | 17 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 28 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 65 +- drivers/gpu/drm/msm/dp/dp_aux.c| 548 +++ drivers/gpu/drm/msm/dp/dp_aux.h| 37 + drivers/gpu/drm/msm/dp/dp_catalog.c| 841 +++ drivers/gpu/drm/msm/dp/dp_catalog.h| 84 ++ drivers/gpu/drm/msm/dp/dp_ctrl.c | 1590 drivers/gpu/drm/msm/dp/dp_ctrl.h | 34 + drivers/gpu/drm/msm/dp/dp_display.c| 997 drivers/gpu/drm/msm/dp/dp_display.h| 32 + drivers/gpu/drm/msm/dp/dp_drm.c| 173 +++ drivers/gpu/drm/msm/dp/dp_drm.h| 20 + drivers/gpu/drm/msm/dp/dp_extcon.c | 216 +++ drivers/gpu/drm/msm/dp/dp_extcon.h | 84 ++ drivers/gpu/drm/msm/dp/dp_link.c | 1185 +++ drivers/gpu/drm/msm/dp/dp_link.h | 132 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 450 ++ drivers/gpu/drm/msm/dp/dp_panel.h | 92 ++ drivers/gpu/drm/msm/dp/dp_parser.c | 496 ++ drivers/gpu/drm/msm/dp/dp_parser.h | 226 +++ drivers/gpu/drm/msm/dp/dp_power.c | 558 +++ drivers/gpu/drm/msm/dp/dp_power.h | 51 + drivers/gpu/drm/msm/dp/dp_reg.h| 488 ++ drivers/gpu/drm/msm/dp/pll/dp_pll.c| 135 ++ drivers/gpu/drm/msm/dp/pll/dp_pll.h| 57 + drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c | 401 + drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h | 86 ++ drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c | 494 ++ drivers/gpu/drm/msm/msm_drv.c |2 + drivers/gpu/drm/msm/msm_drv.h | 42 + include/drm/drm_dp_helper.h|1 + 36 files changed, 9931 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.c create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.h create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.c create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.h create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.c create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.h create mode 100644 drivers/gpu/drm/msm/dp/dp_display.c create mode 100644 drivers/gpu/drm/msm/dp/dp_display.h create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.c create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.h create mode 100644
[Freedreno] [DPU PATCH v3 2/5] drm: add constant N value in helper file
The constant N value (0x8000) is used by multiple DP
drivers. Define this value in header file and use this
in the existing i915 display driver.
Signed-off-by: Chandan Uddaraju
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
include/drm/drm_dp_helper.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ce05e80..1a4ccfd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7496,7 +7496,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
* which the devices expect also in synchronous clock mode.
*/
if (constant_n)
- *ret_n = 0x8000;
+ *ret_n = DP_LINK_CONSTANT_N_VALUE;
else
*ret_n = min_t(unsigned int, roundup_pow_of_two(n),
DATA_LINK_N_MAX);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8364502..69b8251 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1357,6 +1357,7 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
* DisplayPort link
*/
#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
+#define DP_LINK_CONSTANT_N_VALUE 0x8000
struct drm_dp_link {
unsigned char revision;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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[Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845
Add bindings for Snapdragon 845 DisplayPort and display-port PLL driver. Changes in V2: Provide details about sel-gpio Signed-off-by: Chandan Uddaraju --- .../devicetree/bindings/display/msm/dp.txt | 249 + .../devicetree/bindings/display/msm/dpu.txt| 16 +- 2 files changed, 261 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt diff --git a/Documentation/devicetree/bindings/display/msm/dp.txt b/Documentation/devicetree/bindings/display/msm/dp.txt new file mode 100644 index 000..38be36d --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dp.txt @@ -0,0 +1,249 @@ +Qualcomm Technologies, Inc. +DP is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. +DP Controller: Required properties: +- compatible: Should be "qcom,dp-display". +- reg: Base address and length of DP hardware's memory mapped regions. +- cell-index: Specifies the controller instance. +- reg-names:A list of strings that name the list of regs. + "dp_ahb" - DP controller memory region. + "dp_aux" - DP AUX memory region. + "dp_link" - DP link layer memory region. + "dp_p0" - DP pixel clock domain memory region. + "dp_phy" - DP PHY memory region. + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. + "dp_mmss_cc" - Display Clock Control memory region. + "qfprom_physical" - QFPROM Phys memory region. + "dp_pll" - USB3 DP combo PLL memory region. + "usb3_dp_com" - USB3 DP PHY combo memory region. + "hdcp_physical" - DP HDCP memory region. +- interrupt-parent phandle to the interrupt parent device node. +- interrupts: The interrupt signal from the DP block. +- clocks: Clocks required for Display Port operation. See [1] for details on clock bindings. +- clock-names: Names of the clocks corresponding to handles. Following clocks are required: + "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", + "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". +- pll-node:phandle to DP PLL node. +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. +- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg6-settings: Specifies the DP AUX
[Freedreno] [DPU PATCH v3 5/5] drm/msm/dpu: add display port support in DPU
From: Jeykumar Sankaran
Add display port support in DPU by creating hooks
for DP encoder enumeration and encoder mode
initialization.
This change is based on the SDM845 Display port
driver changes[1].
changes in v2:
- rebase on [2] (Sean Paul)
- remove unwanted error checks and
switch cases (Jordan Crouse)
[1] https://lwn.net/Articles/768265/
[2] https://lkml.org/lkml/2018/11/17/87
changes in V3:
-- Moved this change as part of the DP driver changes.
-- Addressed compilation issues on the latest code base.
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Chandan Uddaraju
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 65 -
2 files changed, 58 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 29ac7d3..f82d990 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2037,7 +2037,7 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
{
int ret = 0;
int i = 0;
- enum dpu_intf_type intf_type;
+ enum dpu_intf_type intf_type = INTF_NONE;
struct dpu_enc_phys_init_params phys_params;
if (!dpu_enc) {
@@ -2059,9 +2059,9 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
case DRM_MODE_ENCODER_DSI:
intf_type = INTF_DSI;
break;
- default:
- DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
- return -EINVAL;
+ case DRM_MODE_ENCODER_TMDS:
+ intf_type = INTF_DP;
+ break;
}
WARN_ON(disp_info->num_of_h_tiles < 1);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 6c92f0f..d5c290c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -421,6 +421,33 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
return rc;
}
+static int _dpu_kms_initialize_displayport(struct drm_device *dev,
+ struct msm_drm_private *priv,
+ struct dpu_kms *dpu_kms)
+{
+ struct drm_encoder *encoder = NULL;
+ int rc = 0;
+
+ if (!priv->dp)
+ return rc;
+
+ encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
+ if (IS_ERR(encoder)) {
+ DPU_ERROR("encoder init failed for dsi display\n");
+ return PTR_ERR(encoder);;
+ }
+
+ rc = msm_dp_modeset_init(priv->dp, dev, encoder);
+ if (rc) {
+ DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
+ drm_encoder_cleanup(encoder);
+ return rc;
+ }
+
+ priv->encoders[priv->num_encoders++] = encoder;
+ return rc;
+}
+
/**
* _dpu_kms_setup_displays - create encoders, bridges and connectors
* for underlying displays
@@ -433,12 +460,21 @@ static int _dpu_kms_setup_displays(struct drm_device *dev,
struct msm_drm_private *priv,
struct dpu_kms *dpu_kms)
{
- /**
-* Extend this function to initialize other
-* types of displays
-*/
+ int rc = 0;
+
+ rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
+ if (rc) {
+ DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
+ return rc;
+ }
- return _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
+ rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
+ if (rc) {
+ DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
+ return rc;
+ }
+
+ return rc;
}
static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms)
@@ -626,13 +662,20 @@ static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE :
MSM_DISPLAY_CAP_VID_MODE;
- /* TODO: No support for DSI swap */
- for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
- if (priv->dsi[i]) {
- info.h_tile_instance[info.num_of_h_tiles] = i;
- info.num_of_h_tiles++;
+ switch (info.intf_type) {
+ case DRM_MODE_ENCODER_DSI:
+ /* TODO: No support for DSI swap */
+ for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+ if (priv->dsi[i]) {
+ info.h_tile_instance[info.num_of_h_tiles] = i;
+ info.num_of_h_tiles++;
+ }
}
- }
+ break;
+ case DRM_MODE_ENCODER_TMDS:
+ info.num_of_h_tiles = 1;
+ break;
+ };
rc
