Re: [Freedreno] [PATCH v2 0/4] msm/gpu/a6xx: use the DMA-API for GMU memory allocations
On Thu, Feb 20, 2020 at 10:27 AM Jordan Crouse wrote: > When CONFIG_INIT_ON_ALLOC_DEFAULT_ON the GMU memory allocator runs afoul of > cache coherency issues because it is mapped as write-combine without clearing > the cache after it was zeroed. > > Rather than duplicate the hacky workaround we use in the GEM allocator for the > same reason it turns out that we don't need to have a bespoke memory allocator > for the GMU anyway. It uses a flat, global address space and there are only > two relatively minor allocations anyway. In short, this is essentially what > the > DMA API was created for so replace a bunch of memory management code with two > calls to allocate and free DMA memory and we're fine. > > The only wrinkle is that the memory allocations need to be in a very specific > location in the GMU virtual address space so in order to get the iova > allocator > to do the right thing we need to specify the dma-ranges property in the device > tree for the GMU node. Since we've not yet converted the GMU bindings over to > YAML two patches quickly turn into four but at the end of it we have at least > one bindings file converted to YAML and 99 less lines of code to worry about. > > v2: Fix the example bindings for dma-ranges - the third item is the size > Pass false to of_dma_configure so that it fails probe if the DMA region is not > set up. This set still works for me as well. Thanks so much! Tested-by: John Stultz thanks -john ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH] dt-bindings: arm-smmu: update the list of clocks
On Thu, Feb 20, 2020 at 01:42:22PM +0530, Sharat Masetty wrote: > This patch adds a clock definition needed for powering on the GPU TBUs > and the GPU TCU. > > Signed-off-by: Sharat Masetty > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 6515dbe..235c0df 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -28,6 +28,7 @@ properties: >- enum: >- qcom,msm8996-smmu-v2 >- qcom,msm8998-smmu-v2 > + - qcom,sc7180-smmu-v2 The addition of the compatible string isn't (directly) related with $subject, this should be done in a separate patch. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH] dt-bindings: arm-smmu: update the list of clocks
On Thu, 20 Feb 2020 13:42:22 +0530, Sharat Masetty wrote: > This patch adds a clock definition needed for powering on the GPU TBUs > and the GPU TCU. > > Signed-off-by: Sharat Masetty > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ > 1 file changed, 3 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/iommu/arm,smmu.example.dt.yaml: iommu@d0: clock-names: ['bus', 'iface'] is too short /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/iommu/arm,smmu.example.dt.yaml: iommu@d0: clocks: [[4294967295, 123], [4294967295, 124]] is too short See https://patchwork.ozlabs.org/patch/1241297 Please check and re-submit. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH] drm/msm/a6xx: Fix CP_MEMPOOL state name
On Thu, Feb 20, 2020 at 10:00:09AM -0800, Rob Clark wrote:
> From: Rob Clark
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> index 68cccfa2870a..bbbec8d26870 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> @@ -370,7 +370,7 @@ static const struct a6xx_indexed_registers {
> };
>
> static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
> - "CP_MEMPOOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
> + "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
> REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060,
> };
>
> --
> 2.24.1
>
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[Freedreno] [PATCH v2 1/4] dt-bindings: display: msm: Convert GMU bindings to YAML
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 --
.../devicetree/bindings/display/msm/gmu.yaml | 130 +
2 files changed, 130 insertions(+), 116 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt
b/Documentation/devicetree/bindings/display/msm/gmu.txt
deleted file mode 100644
index bf9c7a2..000
--- a/Documentation/devicetree/bindings/display/msm/gmu.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-Qualcomm adreno/snapdragon GMU (Graphics management unit)
-
-The GMU is a programmable power controller for the GPU. the CPU controls the
-GMU which in turn handles power controls for the GPU.
-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
- Note that you need to list the less specific "qcom,adreno-gmu"
- for generic matches and the more specific identifier to identify
- the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
- * "gmu"
- * "gmu_pdc"
- * "gmu_pdc_seg"
-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
- * "hfi"
- * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
- * "gmu"
- * "cxo"
- * "axi"
- * "mnoc"
-- power-domains: should be:
- <_gpucc GPU_CX_GDSC>
- <_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
-
-Example:
-
-/ {
- ...
-
- gmu: gmu@506a000 {
- compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
-
- reg = <0x506a000 0x3>,
- <0xb28 0x1>,
- <0xb48 0x1>;
- reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
-
- interrupts = ,
-;
- interrupt-names = "hfi", "gmu";
-
- clocks = < GPU_CC_CX_GMU_CLK>,
- < GPU_CC_CXO_CLK>,
- < GCC_DDRSS_GPU_AXI_CLK>,
- < GCC_GPU_MEMNOC_GFX_CLK>;
- clock-names = "gmu", "cxo", "axi", "memnoc";
-
- power-domains = < GPU_CX_GDSC>,
- < GPU_GX_GDSC>;
- power-domain-names = "cx", "gx";
-
- iommus = <_smmu 5>;
-
- operating-points-v2 = <_opp_table>;
- };
-};
-
-a3xx example with OCMEM support:
-
-/ {
- ...
-
- gpu: adreno@fdb0 {
- compatible = "qcom,adreno-330.2",
-"qcom,adreno";
- reg = <0xfdb0 0x1>;
- reg-names = "kgsl_3d0_reg_memory";
- interrupts = ;
- interrupt-names = "kgsl_3d0_irq";
- clock-names = "core",
- "iface",
- "mem_iface";
- clocks = < OXILI_GFX3D_CLK>,
-< OXILICX_AHB_CLK>,
-< OXILICX_AXI_CLK>;
- sram = <_sram>;
- power-domains = < OXILICX_GDSC>;
- operating-points-v2 = <_opp_table>;
- iommus = <_iommu 0>;
- };
-
- ocmem@fdd0 {
- compatible = "qcom,msm8974-ocmem";
-
- reg = <0xfdd0 0x2000>,
- <0xfec0 0x18>;
- reg-names = "ctrl",
-"mem";
-
- clocks = < RPM_SMD_OCMEMGX_CLK>,
-< OCMEMCX_OCMEMNOC_CLK>;
- clock-names = "core",
- "iface";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- gmu_sram: gmu-sram@0 {
- reg = <0x0 0x10>;
- ranges = <0 0 0xfec0 0x10>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
new file mode 100644
index 000..776ff92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
+%YAML 1.2
+---
+
+$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#;
+$schema:
[Freedreno] [PATCH v2 4/4] drm/msm/a6xx: Use the DMA API for GMU memory objects
The GMU has very few memory allocations and uses a flat memory space so
there is no good reason to go out of our way to bypass the DMA APIs which
were basically designed for this exact scenario.
v2: Pass force_dma false to of_dma_configure to require that the DMA
region be set up and return error from of_dma_configure to fail probe.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 112 +++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +-
2 files changed, 11 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 983afea..c36b38b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2,6 +2,7 @@
/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
#include
+#include
#include
#include
#include
@@ -895,21 +896,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo)
{
- int count, i;
- u64 iova;
-
if (IS_ERR_OR_NULL(bo))
return;
- count = bo->size >> PAGE_SHIFT;
- iova = bo->iova;
-
- for (i = 0; i < count; i++, iova += PAGE_SIZE) {
- iommu_unmap(gmu->domain, iova, PAGE_SIZE);
- __free_pages(bo->pages[i], 0);
- }
-
- kfree(bo->pages);
+ dma_free_attrs(gmu->dev, bo->size, bo->virt, bo->iova, bo->attrs);
kfree(bo);
}
@@ -917,94 +907,23 @@ static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct
a6xx_gmu *gmu,
size_t size)
{
struct a6xx_gmu_bo *bo;
- int ret, count, i;
bo = kzalloc(sizeof(*bo), GFP_KERNEL);
if (!bo)
return ERR_PTR(-ENOMEM);
bo->size = PAGE_ALIGN(size);
+ bo->attrs = DMA_ATTR_WRITE_COMBINE;
- count = bo->size >> PAGE_SHIFT;
+ bo->virt = dma_alloc_attrs(gmu->dev, bo->size, >iova, GFP_KERNEL,
+ bo->attrs);
- bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
- if (!bo->pages) {
+ if (!bo->virt) {
kfree(bo);
return ERR_PTR(-ENOMEM);
}
- for (i = 0; i < count; i++) {
- bo->pages[i] = alloc_page(GFP_KERNEL);
- if (!bo->pages[i])
- goto err;
- }
-
- bo->iova = gmu->uncached_iova_base;
-
- for (i = 0; i < count; i++) {
- ret = iommu_map(gmu->domain,
- bo->iova + (PAGE_SIZE * i),
- page_to_phys(bo->pages[i]), PAGE_SIZE,
- IOMMU_READ | IOMMU_WRITE);
-
- if (ret) {
- DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer
object\n");
-
- for (i = i - 1 ; i >= 0; i--)
- iommu_unmap(gmu->domain,
- bo->iova + (PAGE_SIZE * i),
- PAGE_SIZE);
-
- goto err;
- }
- }
-
- bo->virt = vmap(bo->pages, count, VM_IOREMAP,
- pgprot_writecombine(PAGE_KERNEL));
- if (!bo->virt)
- goto err;
-
- /* Align future IOVA addresses on 1MB boundaries */
- gmu->uncached_iova_base += ALIGN(size, SZ_1M);
-
return bo;
-
-err:
- for (i = 0; i < count; i++) {
- if (bo->pages[i])
- __free_pages(bo->pages[i], 0);
- }
-
- kfree(bo->pages);
- kfree(bo);
-
- return ERR_PTR(-ENOMEM);
-}
-
-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
-{
- int ret;
-
- /*
-* The GMU address space is hardcoded to treat the range
-* 0x6000 - 0x8000 as un-cached memory. All buffers shared
-* between the GMU and the CPU will live in this space
-*/
- gmu->uncached_iova_base = 0x6000;
-
-
- gmu->domain = iommu_domain_alloc(_bus_type);
- if (!gmu->domain)
- return -ENODEV;
-
- ret = iommu_attach_device(gmu->domain, gmu->dev);
-
- if (ret) {
- iommu_domain_free(gmu->domain);
- gmu->domain = NULL;
- }
-
- return ret;
}
/* Return the 'arc-level' for the given frequency */
@@ -1264,10 +1183,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
a6xx_gmu_memory_free(gmu, gmu->hfi);
- iommu_detach_device(gmu->domain, gmu->dev);
-
- iommu_domain_free(gmu->domain);
-
free_irq(gmu->gmu_irq, gmu);
free_irq(gmu->hfi_irq, gmu);
@@ -1288,7 +1203,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
device_node *node)
gmu->dev = >dev;
- of_dma_configure(gmu->dev, node, true);
+ /* Pass force_dma false to require the DT to set the dma region */
+ ret = of_dma_configure(gmu->dev, node, false);
+ if (ret)
+
[Freedreno] [PATCH v2 2/4] dt-bindings: display: msm: Add required dma-range property
The GMU node now requires a specific dma-range property so that the driver can use the DMA API to do the few memory allocations required by the GMU. This sets the IOMMU iova allocator to match the 'uncached' part of the GMU virtual address space. v2: Fix the dma-ranges tag. The third pair should be the size. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 776ff92..d11a073 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -83,6 +83,13 @@ properties: Phandle to the OPP table for the available GMU frequencies. Refer to ../../opp/opp.txt for more information. + dma-ranges: +$ref: /schemas/types.yaml#/definitions/uint32-array +description: + Describe the dma-address range for the device. This should always + describe the range between 0x6000 and 0x8000 which represents + the uncached region of the GMU address space. + required: - compatible - reg @@ -95,6 +102,7 @@ required: - power-domain-names - iommus - operating-points-v2 + - dma-ranges examples: - | @@ -127,4 +135,6 @@ examples: iommus = <_smmu 5>; operating-points-v2 = <_opp_table>; + +dma-ranges = <0 0x6000 0 0x6000 0 0x2000>; }; -- 2.7.4 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 0/4] msm/gpu/a6xx: use the DMA-API for GMU memory allocations
When CONFIG_INIT_ON_ALLOC_DEFAULT_ON the GMU memory allocator runs afoul of cache coherency issues because it is mapped as write-combine without clearing the cache after it was zeroed. Rather than duplicate the hacky workaround we use in the GEM allocator for the same reason it turns out that we don't need to have a bespoke memory allocator for the GMU anyway. It uses a flat, global address space and there are only two relatively minor allocations anyway. In short, this is essentially what the DMA API was created for so replace a bunch of memory management code with two calls to allocate and free DMA memory and we're fine. The only wrinkle is that the memory allocations need to be in a very specific location in the GMU virtual address space so in order to get the iova allocator to do the right thing we need to specify the dma-ranges property in the device tree for the GMU node. Since we've not yet converted the GMU bindings over to YAML two patches quickly turn into four but at the end of it we have at least one bindings file converted to YAML and 99 less lines of code to worry about. v2: Fix the example bindings for dma-ranges - the third item is the size Pass false to of_dma_configure so that it fails probe if the DMA region is not set up. Jordan Crouse (4): dt-bindings: display: msm: Convert GMU bindings to YAML dt-bindings: display: msm: Add required dma-range property arm64: dts: sdm845: Set the virtual address range for GMU allocations drm/msm/a6xx: Use the DMA API for GMU memory objects .../devicetree/bindings/display/msm/gmu.txt| 116 - .../devicetree/bindings/display/msm/gmu.yaml | 140 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 + drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 112 ++--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +- 5 files changed, 153 insertions(+), 222 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml -- 2.7.4 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 05/12] drm/msm/dpu: Stop copying around mode->private_flags
On Thu, Feb 20, 2020 at 05:33:09PM +0200, Ville Syrjälä wrote: > On Thu, Feb 20, 2020 at 11:24:20AM +, Emil Velikov wrote: > > On Wed, 19 Feb 2020 at 20:36, Ville Syrjala > > wrote: > > > > > > From: Ville Syrjälä > > > > > > The driver never sets mode->private_flags so copying > > > it back and forth is entirely pointless. Stop doing it. > > > > > > Also drop private_flags from the tracepoint. > > > > > > Cc: Rob Clark > > > Cc: Sean Paul > > > Cc: linux-arm-...@vger.kernel.org > > > Cc: freedreno@lists.freedesktop.org > > > Signed-off-by: Ville Syrjälä > > > > Perhaps the msm team has a WIP which makes use of it ? > > Maybe if it's one of them five year projects. But anyways, > with an atomic driver there are certainly better ways to > handle this. Yeah with atomic you have your display mode in drm_crtc_state, which you're subposed to subclass so that you can have terabytes of private state. At least in theory :-) ->private_flags was really only useful in pre-atomic drivers. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] drm/msm/a6xx: Fix CP_MEMPOOL state name
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
index 68cccfa2870a..bbbec8d26870 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
@@ -370,7 +370,7 @@ static const struct a6xx_indexed_registers {
};
static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
- "CP_MEMPOOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
+ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060,
};
--
2.24.1
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Re: [Freedreno] [PATCH 05/12] drm/msm/dpu: Stop copying around mode->private_flags
On Thu, Feb 20, 2020 at 11:24:20AM +, Emil Velikov wrote: > On Wed, 19 Feb 2020 at 20:36, Ville Syrjala > wrote: > > > > From: Ville Syrjälä > > > > The driver never sets mode->private_flags so copying > > it back and forth is entirely pointless. Stop doing it. > > > > Also drop private_flags from the tracepoint. > > > > Cc: Rob Clark > > Cc: Sean Paul > > Cc: linux-arm-...@vger.kernel.org > > Cc: freedreno@lists.freedesktop.org > > Signed-off-by: Ville Syrjälä > > Perhaps the msm team has a WIP which makes use of it ? Maybe if it's one of them five year projects. But anyways, with an atomic driver there are certainly better ways to handle this. -- Ville Syrjälä Intel ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 05/12] drm/msm/dpu: Stop copying around mode->private_flags
On Wed, 19 Feb 2020 at 20:36, Ville Syrjala wrote: > > From: Ville Syrjälä > > The driver never sets mode->private_flags so copying > it back and forth is entirely pointless. Stop doing it. > > Also drop private_flags from the tracepoint. > > Cc: Rob Clark > Cc: Sean Paul > Cc: linux-arm-...@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Signed-off-by: Ville Syrjälä Perhaps the msm team has a WIP which makes use of it ? Otherwise: Reviewed-by: Emil Velikov -Emil ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
On 2/11/2020 2:51 AM, Doug Anderson wrote: Hi, On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty wrote: This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty In v4 I added my tags [1]. Please keep them for future patches unless something major changes. AKA: Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file changed, 102 insertions(+) Just to summarize where we are: * As per my notes in v3 and v4 [1], this can't land until "mem_iface_clk" is in the bindings. Please post a patch for this and reply with a link here so others can follow the disucssion. I posted a patch for this @https://patchwork.freedesktop.org/patch/354130/ * This also can't land until the gpucc bindings change from Taniya recently [2] lands. ...so we're in limbo waiting for the bindings to be resolved, but otherwise this patch looks good. [1] https://lore.kernel.org/r/CAD=FV=ueq0moxudrszrcj8g6jb0elf1ttn+mn7t6d2tpcmu...@mail.gmail.com [2] https://lore.kernel.org/r/1581307266-26989-1-git-send-email-t...@codeaurora.org -Doug ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] Update arm,smmu.yaml bindings doc
Patch [1] adds a "mem_iface_clock" in the clocks list for smmu device. This patch updates the yaml doc file for smmu by adding the definition for this new clock. 1: https://patchwork.freedesktop.org/patch/352718/ Sharat Masetty (1): dt-bindings: arm-smmu: update clocks and bindings for sc7180 SoC Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) -- 1.9.1 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] dt-bindings: arm-smmu: update the list of clocks
This patch adds a clock definition needed for powering on the GPU TBUs and the GPU TCU. Signed-off-by: Sharat Masetty --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 6515dbe..235c0df 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -28,6 +28,7 @@ properties: - enum: - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 + - qcom,sc7180-smmu-v2 - qcom,sdm845-smmu-v2 - const: qcom,smmu-v2 @@ -116,6 +117,7 @@ properties: items: - const: bus - const: iface + - const: mem_iface_clk clocks: items: @@ -123,6 +125,7 @@ properties: smmu ptw - description: interface clock required to access smmu's registers through the TCU's programming interface. + - description: core clock required for the GPU SMMU TBUs and the GPU TCU power-domains: maxItems: 1 -- 1.9.1 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
