Re: [Freedreno] [PATCH] drm/msm/dpu: ensure device suspend happens during PM sleep
Hi, On Fri, May 15, 2020 at 9:37 AM Doug Anderson wrote: > > Hi, > > On Fri, May 15, 2020 at 5:06 AM wrote: > > > > On 2020-05-14 21:47, Doug Anderson wrote: > > > Hi, > > > > > > On Fri, May 1, 2020 at 6:31 AM Kalyan Thota > > > wrote: > > >> > > >> "The PM core always increments the runtime usage counter > > >> before calling the ->suspend() callback and decrements it > > >> after calling the ->resume() callback" > > >> > > >> DPU and DSI are managed as runtime devices. When > > >> suspend is triggered, PM core adds a refcount on all the > > >> devices and calls device suspend, since usage count is > > >> already incremented, runtime suspend was not getting called > > >> and it kept the clocks on which resulted in target not > > >> entering into XO shutdown. > > >> > > >> Add changes to force suspend on runtime devices during pm sleep. > > >> > > >> Changes in v1: > > >> - Remove unnecessary checks in the function > > >> _dpu_kms_disable_dpu (Rob Clark). > > >> > > >> Changes in v2: > > >> - Avoid using suspend_late to reset the usagecount > > >>as suspend_late might not be called during suspend > > >>call failures (Doug). > > >> > > >> Changes in v3: > > >> - Use force suspend instead of managing device usage_count > > >>via runtime put and get API's to trigger callbacks (Doug). > > >> > > >> Changes in v4: > > >> - Check the return values of pm_runtime_force_suspend and > > >>pm_runtime_force_resume API's and pass appropriately (Doug). > > >> > > >> Changes in v5: > > > > > > Can you please put the version number properly in your subject? It's > > > really hard to tell one version of your patch from another. > > > > > > > > >> - With v4 patch, test cycle has uncovered issues in device resume. > > >> > > >>On bubs: cmd tx failures were seen as SW is sending panel off > > >>commands when the dsi resources are turned off. > > >> > > >>Upon suspend, DRM driver will issue a NULL composition to the > > >>dpu, followed by turning off all the HW blocks. > > >> > > >>v5 changes will serialize the NULL commit and resource unwinding > > >>by handling them under PM prepare and PM complete phases there by > > >>ensuring that clks are on when panel off commands are being > > >>processed. > > > > > > I'm still most definitely not an expert in how all the DRM pieces all > > > hook up together, but the solution you have in this patch seems wrong > > > to me. As far as I can tell the "prepare" state isn't supposed to be > > > actually doing the suspend work and here that's exactly what you're > > > doing. I think you should find a different solution to ensure > > > ordering is correct. > > > > > > -Doug > > > > > > > Hi, > > Quite honestly I'm probably not the right person to be reviewing this > code. I mostly just noticed one of your early patches and it looked > strange to me. Hopefully someone with actual experience in how all > the DRM components work together can actually review and see if this > makes sense. Maybe Sean would know better? > > That being said, let me at least look at what you're saying... > > > > Prepare and Complete are callbacks defined as part of Sleep and Resume > > sequence > > > > Entering PM SUSPEND the phases are : prepare --> suspend --> > > suspend_late --> suspend_noirq. > > While leaving PM SUSPEND the phases are: resume_noirq --> resume_early > > --> resume --> complete. > > Sure, it's part of the sequence. It's also documented in pm.h as: > > * The principal role of this callback is to prevent new children of > * the device from being registered after it has returned (the driver's > * subsystem and generally the rest of the kernel is supposed to prevent > * new calls to the probe method from being made too once @prepare() has > * succeeded). > > It does not feel like that matches your usage of this call. > > > > The reason to push drm suspend handling to PM prepare phase is that > > parent here will trigger a modeset to turn off the timing and > > subsequently the panel. > > the child devices should not turn of their clocks before parent unwinds > > the composition. Hence they are serialized as per the sequence mentioned > > above. > > So the general model in Linux is that children suspend before their > parents, right? So you're saying that, in this case, the parent needs > to act on the child before the child suspends. Is that correct? > > Rather than hijacking the prepare/complete, I'd be at least slightly > inclined to move the other driver to turn off its clocks in > suspend_late and to turn them back on in resume_early? That seems to > be what was done in "analogix_dp-rockchip.c" to solve a similar > problem. > > > > A similar approach is taken by other driver that use drm framework. In > > this driver, the device registers for prepare and complete callbacks to > > handle drm_suspend and drm_resume. > > https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/exynos/exynos_drm_drv.c#L163 > >
Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth
On Wed, May 27, 2020 at 08:38:47AM -0700, Rob Clark wrote:
> On Wed, May 27, 2020 at 1:47 AM Sharat Masetty
> wrote:
> >
> > + more folks
> >
> > On 5/18/2020 9:55 PM, Rob Clark wrote:
> > > On Mon, May 18, 2020 at 7:23 AM Jordan Crouse
> > > wrote:
> > >> On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> > >>> This patches replaces the previously used static DDR vote and uses
> > >>> dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
> > >>> GPU frequency.
> > >>>
> > >>> Signed-off-by: Sharat Masetty
> > >>> ---
> > >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
> > >>> 1 file changed, 1 insertion(+), 5 deletions(-)
> > >>>
> > >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > >>> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > >>> index 2d8124b..79433d3 100644
> > >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > >>> @@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
> > >>> dev_pm_opp *opp)
> > >>>
> > >>>gmu->freq = gmu->gpu_freqs[perf_index];
> > >>>
> > >>> - /*
> > >>> - * Eventually we will want to scale the path vote with the
> > >>> frequency but
> > >>> - * for now leave it at max so that the performance is nominal.
> > >>> - */
> > >>> - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
> > >>> + dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
> > >>> }
> > >> This adds an implicit requirement that all targets need bandwidth
> > >> settings
> > >> defined in the OPP or they won't get a bus vote at all. I would prefer
> > >> that
> > >> there be an default escape valve but if not you'll need to add
> > >> bandwidth values for the sdm845 OPP that target doesn't regress.
> > >>
> > > it looks like we could maybe do something like:
> > >
> > >ret = dev_pm_opp_set_bw(...);
> > >if (ret) {
> > >dev_warn_once(dev, "no bandwidth settings");
> > >icc_set_bw(...);
> > >}
> > >
> > > ?
> > >
> > > BR,
> > > -R
> >
> > There is a bit of an issue here - Looks like its not possible to two icc
> > handles to the same path. Its causing double enumeration of the paths
> > in the icc core and messing up path votes. With [1] Since opp/core
> > already gets a handle to the icc path as part of table add, drm/msm
> > could do either
> >
> > a) Conditionally enumerate gpu->icc_path handle only when pm/opp core
> > has not got the icc path handle. I could use something like [2] to
> > determine if should initialize gpu->icc_path*
> >
> > b) Add peak-opp-configs in 845 dt and mandate all future versions to use
> > this bindings. With this, I can remove gpu->icc_path from msm/drm
> > completely and only rely on opp/core for bw voting.
>
> The main thing is that we want to make sure newer dtb always works on
> an older kernel without regression.. but, hmm.. I guess the
> interconnects/interconnects-names properties haven't landed yet in
> sdm845.dtsi? Maybe that lets us go with the simpler approach (b).
> Looks like we haven't wired up interconnect for 8916 or 8996 either,
> so probably we can just mandate this for all of them?
>
> If we have landed the interconnect dts hookup for gpu somewhere that
> I'm overlooking, I guess we would have to go with (a) and keep the
> existing interconnects/interconnects-names properties.
The main problem is that (on sdm845 at least) the path comes up with a very slow
default so even if we don't do scaling we had to set _something_. Perhaps if we
solved that problem somewhere else (inerconnect, rpmh?) then we wouldn't need to
worry about it in the leaf driver unless the full opp tables are described.
Jordan
> BR,
> -R
>
> > [1] - https://lore.kernel.org/patchwork/cover/1240687/
> >
> > [2] - https://patchwork.kernel.org/patch/11527573/
> >
> > Let me know your thoughts
> >
> > Sharat
> >
> > >
> > >> Jordan
> > >>
> > >>> unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
> > >>> --
> > >>> 2.7.4
> > >>>
> > >> --
> > >> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> > >> a Linux Foundation Collaborative Project
> > >> ___
> > >> Freedreno mailing list
> > >> Freedreno@lists.freedesktop.org
> > >> https://lists.freedesktop.org/mailman/listinfo/freedreno
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Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth
On 2020-05-27 23:01, Saravana Kannan wrote:
On Wed, May 27, 2020 at 8:38 AM Rob Clark wrote:
On Wed, May 27, 2020 at 1:47 AM Sharat Masetty
wrote:
>
> + more folks
>
> On 5/18/2020 9:55 PM, Rob Clark wrote:
> > On Mon, May 18, 2020 at 7:23 AM Jordan Crouse
wrote:
> >> On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> >>> This patches replaces the previously used static DDR vote and uses
> >>> dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
> >>> GPU frequency.
> >>>
> >>> Signed-off-by: Sharat Masetty
> >>> ---
> >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
> >>> 1 file changed, 1 insertion(+), 5 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >>> index 2d8124b..79433d3 100644
> >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >>> @@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
dev_pm_opp *opp)
> >>>
> >>>gmu->freq = gmu->gpu_freqs[perf_index];
> >>>
> >>> - /*
> >>> - * Eventually we will want to scale the path vote with the
frequency but
> >>> - * for now leave it at max so that the performance is nominal.
> >>> - */
> >>> - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
> >>> + dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
> >>> }
> >> This adds an implicit requirement that all targets need bandwidth settings
> >> defined in the OPP or they won't get a bus vote at all. I would prefer that
> >> there be an default escape valve but if not you'll need to add
> >> bandwidth values for the sdm845 OPP that target doesn't regress.
> >>
> > it looks like we could maybe do something like:
> >
> >ret = dev_pm_opp_set_bw(...);
> >if (ret) {
> >dev_warn_once(dev, "no bandwidth settings");
> >icc_set_bw(...);
> >}
> >
> > ?
> >
> > BR,
> > -R
>
> There is a bit of an issue here - Looks like its not possible to two icc
> handles to the same path. Its causing double enumeration of the paths
> in the icc core and messing up path votes. With [1] Since opp/core
> already gets a handle to the icc path as part of table add, drm/msm
> could do either
Are you sure this is the real issue? I'd be surprised if this is a
real limitation. And if it is, it either needs to be fixed in the ICC
framework or OPP shouldn't be getting path handles by default (and
not really, this is already handled well
in the icc framework. In this case
the max peak vote would be considered
among the two paths.
maybe let the driver set the handles before using OPP APIs to change
BW). I'd lean towards the former.
https://patchwork.kernel.org/patch/11573827/
Yes the core shouldn't get paths
by default unless the bw values
are specified in the opps.
> a) Conditionally enumerate gpu->icc_path handle only when pm/opp core
> has not got the icc path handle. I could use something like [2] to
> determine if should initialize gpu->icc_path*
This seems like a bandaid. Let's fix it correctly in ICC framework or
OPP framework.
> b) Add peak-opp-configs in 845 dt and mandate all future versions to use
I can't understand ^^ proposal as well.
We would ideally want to add scaling
support for SDM845 as well while we are
at it.
> this bindings. With this, I can remove gpu->icc_path from msm/drm
> completely and only rely on opp/core for bw voting.
I don't know what you mean by "peak-opp-configs" but I guess you are
referring to some kind of DT flag to say if you should vote for BW
directly or use the OPP framework? If so, I'm pretty sure that won't
fly. That's an OS implementation specific flag.
-Saravana
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Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth
On Wed, May 27, 2020 at 1:47 AM Sharat Masetty wrote:
>
> + more folks
>
> On 5/18/2020 9:55 PM, Rob Clark wrote:
> > On Mon, May 18, 2020 at 7:23 AM Jordan Crouse
> > wrote:
> >> On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> >>> This patches replaces the previously used static DDR vote and uses
> >>> dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
> >>> GPU frequency.
> >>>
> >>> Signed-off-by: Sharat Masetty
> >>> ---
> >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
> >>> 1 file changed, 1 insertion(+), 5 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >>> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >>> index 2d8124b..79433d3 100644
> >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >>> @@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
> >>> dev_pm_opp *opp)
> >>>
> >>>gmu->freq = gmu->gpu_freqs[perf_index];
> >>>
> >>> - /*
> >>> - * Eventually we will want to scale the path vote with the
> >>> frequency but
> >>> - * for now leave it at max so that the performance is nominal.
> >>> - */
> >>> - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
> >>> + dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
> >>> }
> >> This adds an implicit requirement that all targets need bandwidth settings
> >> defined in the OPP or they won't get a bus vote at all. I would prefer that
> >> there be an default escape valve but if not you'll need to add
> >> bandwidth values for the sdm845 OPP that target doesn't regress.
> >>
> > it looks like we could maybe do something like:
> >
> >ret = dev_pm_opp_set_bw(...);
> >if (ret) {
> >dev_warn_once(dev, "no bandwidth settings");
> >icc_set_bw(...);
> >}
> >
> > ?
> >
> > BR,
> > -R
>
> There is a bit of an issue here - Looks like its not possible to two icc
> handles to the same path. Its causing double enumeration of the paths
> in the icc core and messing up path votes. With [1] Since opp/core
> already gets a handle to the icc path as part of table add, drm/msm
> could do either
>
> a) Conditionally enumerate gpu->icc_path handle only when pm/opp core
> has not got the icc path handle. I could use something like [2] to
> determine if should initialize gpu->icc_path*
>
> b) Add peak-opp-configs in 845 dt and mandate all future versions to use
> this bindings. With this, I can remove gpu->icc_path from msm/drm
> completely and only rely on opp/core for bw voting.
The main thing is that we want to make sure newer dtb always works on
an older kernel without regression.. but, hmm.. I guess the
interconnects/interconnects-names properties haven't landed yet in
sdm845.dtsi? Maybe that lets us go with the simpler approach (b).
Looks like we haven't wired up interconnect for 8916 or 8996 either,
so probably we can just mandate this for all of them?
If we have landed the interconnect dts hookup for gpu somewhere that
I'm overlooking, I guess we would have to go with (a) and keep the
existing interconnects/interconnects-names properties.
BR,
-R
> [1] - https://lore.kernel.org/patchwork/cover/1240687/
>
> [2] - https://patchwork.kernel.org/patch/11527573/
>
> Let me know your thoughts
>
> Sharat
>
> >
> >> Jordan
> >>
> >>> unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
> >>> --
> >>> 2.7.4
> >>>
> >> --
> >> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> >> a Linux Foundation Collaborative Project
> >> ___
> >> Freedreno mailing list
> >> Freedreno@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/freedreno
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[Freedreno] [kbuild] Re: [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog
Hi Jonathan,
Thank you for the patch! Perhaps something to improve:
url:
https://github.com/0day-ci/linux/commits/Jonathan-Marek/Initial-SM8150-and-SM8250-DPU-bringup/20200526-112725
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
9cb1fd0efd195590b828b9b865421ad345a4a145
config: arm64-randconfig-s031-20200527 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-240-gf0fe1cd9-dirty
# save the attached .config to linux build tree
make W=1 C=1 ARCH=arm64 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot
sparse warnings: (new ones prefixed by >>)
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:98:26: sparse: sparse:
undefined identifier 'DPU_SSPP_SMART_DMA_V2_5'
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:96:10: sparse: sparse:
Initializer entry defined twice
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:104:10: sparse: also
>> defined here
#
https://github.com/0day-ci/linux/commit/6a90302321af832ea18679e1b29b0301caade709
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout 6a90302321af832ea18679e1b29b0301caade709
vim +104 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
7bdc0c4b812602f Kalyan Thota 2019-11-25 92
6a90302321af832 Jonathan Marek 2020-05-25 93 static const struct dpu_caps
sm8150_dpu_caps = {
6a90302321af832 Jonathan Marek 2020-05-25 94 .max_mixer_width =
DEFAULT_DPU_OUTPUT_LINE_WIDTH,
6a90302321af832 Jonathan Marek 2020-05-25 95 .max_mixer_blendstages
= 0xb,
6a90302321af832 Jonathan Marek 2020-05-25 96 .max_linewidth = 4096,
^^
6a90302321af832 Jonathan Marek 2020-05-25 97 .qseed_type =
DPU_SSPP_SCALER_QSEED3,
6a90302321af832 Jonathan Marek 2020-05-25 98 .smart_dma_rev =
DPU_SSPP_SMART_DMA_V2_5,
6a90302321af832 Jonathan Marek 2020-05-25 99 .ubwc_version =
DPU_HW_UBWC_VER_30,
6a90302321af832 Jonathan Marek 2020-05-25 100 .has_src_split = true,
6a90302321af832 Jonathan Marek 2020-05-25 101 .has_dim_layer = true,
6a90302321af832 Jonathan Marek 2020-05-25 102 .has_idle_pc = true,
6a90302321af832 Jonathan Marek 2020-05-25 103 .has_3d_merge = true,
6a90302321af832 Jonathan Marek 2020-05-25 @104 .max_linewidth = 4096,
^^
Delete duplicate code.
6a90302321af832 Jonathan Marek 2020-05-25 105 .pixel_ram_size =
DEFAULT_PIXEL_RAM_SIZE,
6a90302321af832 Jonathan Marek 2020-05-25 106 .max_hdeci_exp =
MAX_HORZ_DECIMATION,
6a90302321af832 Jonathan Marek 2020-05-25 107 .max_vdeci_exp =
MAX_VERT_DECIMATION,
6a90302321af832 Jonathan Marek 2020-05-25 108 };
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
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Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth
+ more folks
On 5/18/2020 9:55 PM, Rob Clark wrote:
On Mon, May 18, 2020 at 7:23 AM Jordan Crouse wrote:
On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
This patches replaces the previously used static DDR vote and uses
dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
GPU frequency.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 2d8124b..79433d3 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
dev_pm_opp *opp)
gmu->freq = gmu->gpu_freqs[perf_index];
- /*
- * Eventually we will want to scale the path vote with the frequency but
- * for now leave it at max so that the performance is nominal.
- */
- icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
+ dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
}
This adds an implicit requirement that all targets need bandwidth settings
defined in the OPP or they won't get a bus vote at all. I would prefer that
there be an default escape valve but if not you'll need to add
bandwidth values for the sdm845 OPP that target doesn't regress.
it looks like we could maybe do something like:
ret = dev_pm_opp_set_bw(...);
if (ret) {
dev_warn_once(dev, "no bandwidth settings");
icc_set_bw(...);
}
?
BR,
-R
There is a bit of an issue here - Looks like its not possible to two icc
handles to the same path. Its causing double enumeration of the paths
in the icc core and messing up path votes. With [1] Since opp/core
already gets a handle to the icc path as part of table add, drm/msm
could do either
a) Conditionally enumerate gpu->icc_path handle only when pm/opp core
has not got the icc path handle. I could use something like [2] to
determine if should initialize gpu->icc_path*
b) Add peak-opp-configs in 845 dt and mandate all future versions to use
this bindings. With this, I can remove gpu->icc_path from msm/drm
completely and only rely on opp/core for bw voting.
[1] - https://lore.kernel.org/patchwork/cover/1240687/
[2] - https://patchwork.kernel.org/patch/11527573/
Let me know your thoughts
Sharat
Jordan
unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
--
2.7.4
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