date:20210703

Re: [Freedreno] [RFC] Inline rotation support in dpu driver

2021-07-03 Thread Rob Clark

On Sat, Jul 3, 2021 at 4:32 AM Kalyan Thota  wrote:
>
> This change adds support for inline rotation in the dpu driver.
> When inline rotation is enabled the VIG pipes will directly fetch the image
> from memory in a rotated fashion
>
> Inline rotation has following restrictions
> 1) Supported only with compressed formats
> 2) max pre rotated height is 1088
> 3) restrictions with downscaling ratio
>
> Queries:
>
> 1) Since inline rotation works for fewer pixel formats with specific 
> modifier, how can we provide this information to the compositor so that
> chrome compositor can choose between overlaying or falling back to GPU. In 
> the patch it fails in the atomic check.
>
> 2) If a display composition fails in atomic check due to any of the 
> restrictions in overlays
> can chrome compositor switch it back to the GPU and re trigger the commit ?

The correct way to provide this information to userspace is for the
atomic test step to fail.  Admittedly the CrOS compositor makes some
invalid assumptions that if a given state was valid in the past, it
will be valid in the future.  But I don't see height/format/downscale
restrictions as a thing that would change from frame to frame.

BR,
-R

> posting it as RFC as validation is not complete, please share early comments 
> on this.
>
> Kalyan Thota (1):
>   drm/msm/disp/dpu1: add support for inline rotation in dpu driver
>
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 93 
> --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |  2 +
>  4 files changed, 128 insertions(+), 34 deletions(-)
>
> --
> 2.7.4
>
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[Freedreno] [RFC] Inline rotation support in dpu driver

2021-07-03 Thread Kalyan Thota

This change adds support for inline rotation in the dpu driver.
When inline rotation is enabled the VIG pipes will directly fetch the image
from memory in a rotated fashion

Inline rotation has following restrictions 
1) Supported only with compressed formats
2) max pre rotated height is 1088
3) restrictions with downscaling ratio

Queries: 

1) Since inline rotation works for fewer pixel formats with specific modifier, 
how can we provide this information to the compositor so that
chrome compositor can choose between overlaying or falling back to GPU. In the 
patch it fails in the atomic check.

2) If a display composition fails in atomic check due to any of the 
restrictions in overlays
can chrome compositor switch it back to the GPU and re trigger the commit ?

posting it as RFC as validation is not complete, please share early comments on 
this.

Kalyan Thota (1):
  drm/msm/disp/dpu1: add support for inline rotation in dpu driver

 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 93 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |  2 +
 4 files changed, 128 insertions(+), 34 deletions(-)

-- 
2.7.4

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[Freedreno] [RFC] drm/msm/disp/dpu1: add support for inline rotation in dpu driver

2021-07-03 Thread Kalyan Thota

Add inline rotation support in dpu driver. This change adds
rotation config for SC7280 target.

Change-Id: I15861dc03422274ffd823fc0fc2c1e47909bb22c
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 93 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |  2 +
 4 files changed, 128 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..45e4e56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -25,6 +25,9 @@
 #define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
 
+#define VIG_SC7280_MASK \
+   (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+
 #define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -102,6 +105,8 @@
 #define MAX_DOWNSCALE_RATIO4
 #define SSPP_UNITY_SCALE   1
 
+#define INLINE_ROTATOR_V2  2
+
 #define STRCAT(X, Y) (X Y)
 
 static const uint32_t plane_formats[] = {
@@ -177,6 +182,11 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_YVU420,
 };
 
+static const uint32_t rotation_formats[] = {
+   DRM_FORMAT_NV12,
+   /* TODO add formats after validation */
+};
+
 /*
  * DPU sub blocks config
  */
@@ -465,7 +475,16 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
 
 /* SSPP common configuration */
 
-#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
+static const struct dpu_rotation_cfg dpu_rot_cfg = {
+   .version = INLINE_ROTATOR_V2,
+   .rot_maxdwnscale_ratio_num = 1,
+   .rot_maxdwnscale_ratio_dem = 1,
+   .rot_maxheight = 1088,
+   .rot_num_formats = ARRAY_SIZE(rotation_formats),
+   .rot_format_list = rotation_formats,
+};
+
+#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
@@ -482,6 +501,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
+   .rotation_cfg = rot_cfg, \
}
 
 #define _DMA_SBLK(num, sdma_pri) \
@@ -498,13 +518,13 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
}
 
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
-   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3, 0);
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
-   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3, 0);
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
-   _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3, 0);
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
-   _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3, 0);
 
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
@@ -543,7 +563,10 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
 };
 
 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
-   _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
+   _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, 0);
+
+static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
+   _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, 
_rot_cfg);
 
 static const struct dpu_sspp_cfg sc7180_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
@@ -557,13 +580,13 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
 };
 
 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
-   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
+   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE, 
0);
 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
-   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
+   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE, 
0);
 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
-   _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
+   _VIG_SBLK("2", 7,

Re: [Freedreno] [RFC] Inline rotation support in dpu driver

[Freedreno] [RFC] Inline rotation support in dpu driver

[Freedreno] [RFC] drm/msm/disp/dpu1: add support for inline rotation in dpu driver

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