[Freedreno] [PATCH v4 1/7] drm/msm: Remove unnecessary pm_runtime_get/put
We already enable gpu power from msm_gpu_submit(), so avoid a duplicate pm_runtime_get/put from msm_job_run(). Signed-off-by: Akhil P Oommen --- (no changes since v1) drivers/gpu/drm/msm/msm_ringbuffer.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 56eecb4..cad4c35 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -29,8 +29,6 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) msm_gem_unlock(obj); } - pm_runtime_get_sync(>pdev->dev); - /* TODO move submit path over to using a per-ring lock.. */ mutex_lock(>lock); @@ -38,8 +36,6 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) mutex_unlock(>lock); - pm_runtime_put(>pdev->dev); - return dma_fence_get(submit->hw_fence); } -- 2.7.4
[Freedreno] [PATCH v4 4/7] drm/msm: Fix cx collapse issue during recovery
There are some hardware logic under CX domain. For a successful
recovery, we should ensure cx headswitch collapses to ensure all the
stale states are cleard out. This is especially true to for a6xx family
where we can GMU co-processor.
Currently, cx doesn't collapse due to a devlink between gpu and its
smmu. So the *struct gpu device* needs to be runtime suspended to ensure
that the iommu driver removes its vote on cx gdsc.
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Keep active_submit lock across the suspend & resume (Rob)
- Clear gpu->active_submits to silence a WARN() during runpm suspend (Rob)
Changes in v3:
- Simplied the pm refcount drop since we have just a single refcount now
for all active submits
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 32 +---
drivers/gpu/drm/msm/msm_gpu.c | 4 +---
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 42ed9a3..0c8f19e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1193,7 +1193,7 @@ static void a6xx_recover(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
- int i;
+ int i, active_submits;
adreno_dump_info(gpu);
@@ -1210,8 +1210,34 @@ static void a6xx_recover(struct msm_gpu *gpu)
*/
gmu_write(_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
- gpu->funcs->pm_suspend(gpu);
- gpu->funcs->pm_resume(gpu);
+ pm_runtime_dont_use_autosuspend(>pdev->dev);
+
+ /* active_submit won't change until we make a submission */
+ mutex_lock(>active_lock);
+ active_submits = gpu->active_submits;
+
+ /*
+* Temporarily clear active_submits count to silence a WARN() in the
+* runtime suspend cb
+*/
+ gpu->active_submits = 0;
+
+ /* Drop the rpm refcount from active submits */
+ if (active_submits)
+ pm_runtime_put(>pdev->dev);
+
+ /* And the final one from recover worker */
+ pm_runtime_put_sync(>pdev->dev);
+
+ pm_runtime_use_autosuspend(>pdev->dev);
+
+ if (active_submits)
+ pm_runtime_get(>pdev->dev);
+
+ pm_runtime_get_sync(>pdev->dev);
+
+ gpu->active_submits = active_submits;
+ mutex_unlock(>active_lock);
msm_gpu_hw_init(gpu);
}
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 1945efb..07e55a6 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -426,9 +426,7 @@ static void recover_worker(struct kthread_work *work)
/* retire completed submits, plus the one that hung: */
retire_submits(gpu);
- pm_runtime_get_sync(>pdev->dev);
gpu->funcs->recover(gpu);
- pm_runtime_put_sync(>pdev->dev);
/*
* Replay all remaining submits starting with highest priority
@@ -445,7 +443,7 @@ static void recover_worker(struct kthread_work *work)
}
}
- pm_runtime_put_sync(>pdev->dev);
+ pm_runtime_put(>pdev->dev);
mutex_unlock(>lock);
--
2.7.4
[Freedreno] [PATCH v4 3/7] drm/msm: Correct pm_runtime votes in recover worker
In the scenario where there is one a single submit which is hung, gpu is power collapsed when it is retired. Because of this, by the time we call reover(), gpu state would be already clear. Fix this by correctly managing the pm runtime votes. Signed-off-by: Akhil P Oommen --- (no changes since v1) drivers/gpu/drm/msm/msm_gpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index e1dd3cc..1945efb 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -398,7 +398,6 @@ static void recover_worker(struct kthread_work *work) /* Record the crash state */ pm_runtime_get_sync(>pdev->dev); msm_gpu_crashstate_capture(gpu, submit, comm, cmd); - pm_runtime_put_sync(>pdev->dev); kfree(cmd); kfree(comm); @@ -446,6 +445,8 @@ static void recover_worker(struct kthread_work *work) } } + pm_runtime_put_sync(>pdev->dev); + mutex_unlock(>lock); msm_gpu_retire(gpu); -- 2.7.4
[Freedreno] [PATCH v2 0/5] clk/qcom: Support gdsc collapse polling using 'reset' inteface
Some clients like adreno gpu driver would like to ensure that its gdsc is collapsed at hardware during a gpu reset sequence. This is because it has a votable gdsc which could be ON due to a vote from another subsystem like tz, hyp etc or due to an internal hardware signal. To allow this, gpucc driver can expose an interface to the client driver using reset framework. Using this the client driver can trigger a polling within the gdsc driver. This series is rebased on top of linus's master branch. Related discussion: https://patchwork.freedesktop.org/patch/493144/ Changes in v2: - Return error when a particular custom reset op is not implemented. (Dmitry) Akhil P Oommen (5): dt-bindings: clk: qcom: Support gpu cx gdsc reset clk: qcom: Allow custom reset ops clk: qcom: gdsc: Add a reset op to poll gdsc collapse clk: qcom: gpucc-sc7280: Add cx collapse reset support arm64: dts: qcom: sc7280: Add Reset support for gpu arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ drivers/clk/qcom/gdsc.c | 23 +++ drivers/clk/qcom/gdsc.h | 7 +++ drivers/clk/qcom/gpucc-sc7280.c | 10 ++ drivers/clk/qcom/reset.c | 27 +++ drivers/clk/qcom/reset.h | 8 include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 7 files changed, 77 insertions(+), 4 deletions(-) -- 2.7.4
[Freedreno] [PATCH v4 7/7] drm/msm/a6xx: Handle GMU prepare-slumber hfi failure
When prepare-slumber hfi fails, we should follow a6xx_gmu_force_off()
sequence.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index db05942..3d00ef9 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1082,7 +1082,11 @@ static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
a6xx_bus_clear_pending_transactions(adreno_gpu);
/* tell the GMU we want to slumber */
- a6xx_gmu_notify_slumber(gmu);
+ ret = a6xx_gmu_notify_slumber(gmu);
+ if (ret) {
+ a6xx_gmu_force_off(gmu);
+ return;
+ }
ret = gmu_poll_timeout(gmu,
REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
--
2.7.4
[Freedreno] [PATCH v4 0/7] Improve GPU Recovery
Recently, I debugged a few device crashes which occured during recovery after a hangcheck timeout. It looks like there are a few things we can do to improve our chance at a successful gpu recovery. First one is to ensure that CX GDSC collapses which clears the internal states in gpu's CX domain. First 5 patches tries to handle this. Rest of the patches are to ensure that few internal blocks like CP, GMU and GBIF are halted properly before proceeding for a snapshot followed by recovery. Also, handle 'prepare slumber' hfi failure correctly. These are A6x specific improvements. This series is rebased on top of v2 version of [1] which is based on linus's master branch. [1] https://patchwork.freedesktop.org/series/106860/ Changes in v4: - Keep active_submit lock across the suspend & resume (Rob) - Clear gpu->active_submits to silence a WARN() during runpm suspend (Rob) Changes in v3: - Use reset interface from gpucc driver to poll for cx gdsc collapse https://patchwork.freedesktop.org/series/106860/ - Use single pm refcount for all active submits Changes in v2: - Rebased on msm-next tip Akhil P Oommen (7): drm/msm: Remove unnecessary pm_runtime_get/put drm/msm: Take single rpm refcount on behalf of all submits drm/msm: Correct pm_runtime votes in recover worker drm/msm: Fix cx collapse issue during recovery drm/msm/a6xx: Ensure CX collapse during gpu recovery drm/msm/a6xx: Improve gpu recovery sequence drm/msm/a6xx: Handle GMU prepare-slumber hfi failure drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 ++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 83 ++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 -- drivers/gpu/drm/msm/msm_gpu.c | 21 ++--- drivers/gpu/drm/msm/msm_gpu.h | 4 ++ drivers/gpu/drm/msm/msm_ringbuffer.c | 4 -- 6 files changed, 114 insertions(+), 45 deletions(-) -- 2.7.4
[Freedreno] [PATCH v4 5/7] drm/msm/a6xx: Ensure CX collapse during gpu recovery
Because there could be transient votes from other drivers/tz/hyp which
may keep the cx gdsc enabled, we should poll until cx gdsc collapses.
We can use the reset framework to poll for cx gdsc collapse from gpucc
clk driver.
This feature requires support from the platform's gpucc driver.
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
(no changes since v3)
Changes in v3:
- Use reset interface from gpucc driver to poll for cx gdsc collapse
https://patchwork.freedesktop.org/series/106860/
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.h | 4
3 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 0c8f19e..0ec4fcd 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -10,6 +10,7 @@
#include
#include
+#include
#include
#define GPU_PAS_ID 13
@@ -1229,6 +1230,9 @@ static void a6xx_recover(struct msm_gpu *gpu)
/* And the final one from recover worker */
pm_runtime_put_sync(>pdev->dev);
+ /* Call into gpucc driver to poll for cx gdsc collapse */
+ reset_control_reset(gpu->cx_collapse);
+
pm_runtime_use_autosuspend(>pdev->dev);
if (active_submits)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 07e55a6..4a57627 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
/*
@@ -903,6 +904,9 @@ int msm_gpu_init(struct drm_device *drm, struct
platform_device *pdev,
if (IS_ERR(gpu->gpu_cx))
gpu->gpu_cx = NULL;
+ gpu->cx_collapse = devm_reset_control_get_optional(>dev,
+ "cx_collapse");
+
gpu->pdev = pdev;
platform_set_drvdata(pdev, >adreno_smmu);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 6def008..ab59fd2 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include "msm_drv.h"
#include "msm_fence.h"
@@ -268,6 +269,9 @@ struct msm_gpu {
bool hw_apriv;
struct thermal_cooling_device *cooling;
+
+ /* To poll for cx gdsc collapse during gpu recovery */
+ struct reset_control *cx_collapse;
};
static inline struct msm_gpu *dev_to_gpu(struct device *dev)
--
2.7.4
[Freedreno] [PATCH v2 4/5] clk: qcom: gpucc-sc7280: Add cx collapse reset support
Allow a consumer driver to poll for cx gdsc collapse through Reset
framework.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Minor update to use the updated custom reset ops implementation
drivers/clk/qcom/gpucc-sc7280.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
index 9a832f2..d4bc791 100644
--- a/drivers/clk/qcom/gpucc-sc7280.c
+++ b/drivers/clk/qcom/gpucc-sc7280.c
@@ -433,12 +433,22 @@ static const struct regmap_config
gpu_cc_sc7280_regmap_config = {
.fast_io = true,
};
+struct qcom_reset_ops cx_gdsc_reset = {
+ .reset = gdsc_wait_for_collapse,
+};
+
+static const struct qcom_reset_map gpucc_sc7280_resets[] = {
+ [GPU_CX_COLLAPSE] = { .ops = _gdsc_reset, .priv = _gdsc },
+};
+
static const struct qcom_cc_desc gpu_cc_sc7280_desc = {
.config = _cc_sc7280_regmap_config,
.clks = gpu_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks),
.gdscs = gpu_cc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
+ .resets = gpucc_sc7280_resets,
+ .num_resets = ARRAY_SIZE(gpucc_sc7280_resets),
};
static const struct of_device_id gpu_cc_sc7280_match_table[] = {
--
2.7.4
[Freedreno] [PATCH v2 5/5] arm64: dts: qcom: sc7280: Add Reset support for gpu
Add support for Reset using GPUCC driver for GPU. This helps to ensure
that GPU state is reset by making sure that CX head switch is collapsed.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67..f5257d6 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2243,6 +2243,9 @@
nvmem-cells = <_speed_bin>;
nvmem-cell-names = "speed_bin";
+ resets = < GPU_CX_COLLAPSE>;
+ reset-names = "cx_collapse";
+
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
--
2.7.4
[Freedreno] [PATCH v4 2/7] drm/msm: Take single rpm refcount on behalf of all submits
Instead of separate refcount for each submit, take single rpm refcount
on behalf of all the submits. This makes it easier to drop the rpm
refcount during recovery in an upcoming patch.
Signed-off-by: Akhil P Oommen
---
(no changes since v3)
Changes in v3:
- New patch
drivers/gpu/drm/msm/msm_gpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index c8cd9bf..e1dd3cc 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -663,11 +663,12 @@ static void retire_submit(struct msm_gpu *gpu, struct
msm_ringbuffer *ring,
mutex_lock(>active_lock);
gpu->active_submits--;
WARN_ON(gpu->active_submits < 0);
- if (!gpu->active_submits)
+ if (!gpu->active_submits) {
msm_devfreq_idle(gpu);
- mutex_unlock(>active_lock);
+ pm_runtime_put_autosuspend(>pdev->dev);
+ }
- pm_runtime_put_autosuspend(>pdev->dev);
+ mutex_unlock(>active_lock);
msm_gem_submit_put(submit);
}
@@ -756,14 +757,17 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
/* Update devfreq on transition from idle->active: */
mutex_lock(>active_lock);
- if (!gpu->active_submits)
+ if (!gpu->active_submits) {
+ pm_runtime_get(>pdev->dev);
msm_devfreq_active(gpu);
+ }
gpu->active_submits++;
mutex_unlock(>active_lock);
gpu->funcs->submit(gpu, submit);
gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
+ pm_runtime_put(>pdev->dev);
hangcheck_timer_reset(gpu);
}
--
2.7.4
[Freedreno] [PATCH v4 6/7] drm/msm/a6xx: Improve gpu recovery sequence
We can do a few more things to improve our chance at a successful gpu
recovery, especially during a hangcheck timeout:
1. Halt CP and GMU core
2. Do RBBM GBIF HALT sequence
3. Do a soft reset of GPU core
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 77 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7
3 files changed, 58 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index b03e2c4..beea4a7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -1413,6 +1413,10 @@ static inline uint32_t
REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00
#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x0011
+#define REG_A6XX_RBBM_GBIF_HALT
0x0016
+
+#define REG_A6XX_RBBM_GBIF_HALT_ACK0x0017
+
#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD0x001c
#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x0001
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 9f76f5b..db05942 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -869,9 +869,47 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
(val & 1), 100, 1000);
}
+#define GBIF_CLIENT_HALT_MASK BIT(0)
+#define GBIF_ARB_HALT_MASKBIT(1)
+
+static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
+{
+ struct msm_gpu *gpu = _gpu->base;
+
+ if (!a6xx_has_gbif(adreno_gpu)) {
+ gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
+ spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
+ 0xf) == 0xf);
+ gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
+
+ return;
+ }
+
+ /* Halt the gx side of GBIF */
+ gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
+ spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);
+
+ /* Halt new client requests on GBIF */
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
+ spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
+ (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
+
+ /* Halt all AXI requests on GBIF */
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
+ spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
+ (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
+
+ /* The GBIF halt needs to be explicitly cleared */
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
+}
+
/* Force the GMU off in case it isn't responsive */
static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
{
+ struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
+ struct adreno_gpu *adreno_gpu = _gpu->base;
+ struct msm_gpu *gpu = _gpu->base;
+
/* Flush all the queues */
a6xx_hfi_stop(gmu);
@@ -883,6 +921,15 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
/* Make sure there are no outstanding RPMh votes */
a6xx_gmu_rpmh_off(gmu);
+
+ /* Halt the gmu cm3 core */
+ gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
+
+ a6xx_bus_clear_pending_transactions(adreno_gpu);
+
+ /* Reset GPU core blocks */
+ gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
+ udelay(100);
}
static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu
*gmu)
@@ -1010,36 +1057,6 @@ bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
return true;
}
-#define GBIF_CLIENT_HALT_MASK BIT(0)
-#define GBIF_ARB_HALT_MASKBIT(1)
-
-static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
-{
- struct msm_gpu *gpu = _gpu->base;
-
- if (!a6xx_has_gbif(adreno_gpu)) {
- gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
- spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
- 0xf) == 0xf);
- gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
-
- return;
- }
-
- /* Halt new client requests on GBIF */
- gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
- spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
- (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
-
- /* Halt all AXI requests on GBIF */
- gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
- spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
- (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
-
- /* The GBIF halt needs to be explicitly cleared */
-
[Freedreno] [PATCH v2 3/5] clk: qcom: gdsc: Add a reset op to poll gdsc collapse
Add a reset op compatible function to poll for gdsc collapse.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Minor update to function prototype
drivers/clk/qcom/gdsc.c | 23 +++
drivers/clk/qcom/gdsc.h | 7 +++
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 44520ef..2d0f1d1 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -17,6 +17,7 @@
#include
#include
#include "gdsc.h"
+#include "reset.h"
#define PWR_ON_MASKBIT(31)
#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
@@ -116,7 +117,8 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
}
-static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
+static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status,
+ s64 timeout_us, unsigned int interval_ms)
{
ktime_t start;
@@ -124,7 +126,9 @@ static int gdsc_poll_status(struct gdsc *sc, enum
gdsc_status status)
do {
if (gdsc_check_status(sc, status))
return 0;
- } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
+ if (interval_ms)
+ msleep(interval_ms);
+ } while (ktime_us_delta(ktime_get(), start) < timeout_us);
if (gdsc_check_status(sc, status))
return 0;
@@ -172,7 +176,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum
gdsc_status status)
udelay(1);
}
- ret = gdsc_poll_status(sc, status);
+ ret = gdsc_poll_status(sc, status, TIMEOUT_US, 0);
WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
if (!ret && status == GDSC_OFF && sc->rsupply) {
@@ -343,7 +347,7 @@ static int _gdsc_disable(struct gdsc *sc)
*/
udelay(1);
- ret = gdsc_poll_status(sc, GDSC_ON);
+ ret = gdsc_poll_status(sc, GDSC_ON, TIMEOUT_US, 0);
if (ret)
return ret;
}
@@ -565,3 +569,14 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain
*domain)
return 0;
}
EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);
+
+int gdsc_wait_for_collapse(void *priv)
+{
+ struct gdsc *sc = priv;
+ int ret;
+
+ ret = gdsc_poll_status(sc, GDSC_OFF, 50, 5);
+ WARN(ret, "%s status stuck at 'on'", sc->pd.name);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(gdsc_wait_for_collapse);
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index ad313d7..d484bdb 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -12,6 +12,7 @@
struct regmap;
struct regulator;
struct reset_controller_dev;
+struct qcom_reset_map;
/**
* struct gdsc - Globally Distributed Switch Controller
@@ -79,6 +80,7 @@ int gdsc_register(struct gdsc_desc *desc, struct
reset_controller_dev *,
struct regmap *);
void gdsc_unregister(struct gdsc_desc *desc);
int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
+int gdsc_wait_for_collapse(void *priv);
#else
static inline int gdsc_register(struct gdsc_desc *desc,
struct reset_controller_dev *rcdev,
@@ -88,5 +90,10 @@ static inline int gdsc_register(struct gdsc_desc *desc,
}
static inline void gdsc_unregister(struct gdsc_desc *desc) {};
+
+static int gdsc_wait_for_collapse(void *priv)
+{
+ return -ENOSYS;
+}
#endif /* CONFIG_QCOM_GDSC */
#endif /* __QCOM_GDSC_H__ */
--
2.7.4
Re: [Freedreno] [RFC PATCH] drm/edid: Make 144 Hz not preferred on Sharp LQ140M1JW46
Hi, On Sun, Aug 14, 2022 at 11:46 PM Maxime Ripard wrote: > > On Fri, Jul 29, 2022 at 12:57:40PM -0700, Doug Anderson wrote: > > Hi, > > > > On Fri, Jul 29, 2022 at 9:41 AM Maxime Ripard wrote: > > > > > > On Fri, Jul 29, 2022 at 07:50:20AM -0700, Doug Anderson wrote: > > > > On Fri, Jul 29, 2022 at 12:51 AM Maxime Ripard > > > > wrote: > > > > > > > > > > On Thu, Jul 28, 2022 at 02:18:38PM -0700, Doug Anderson wrote: > > > > > > Hi, > > > > > > > > > > > > On Thu, Jul 28, 2022 at 10:34 AM Abhinav Kumar > > > > > > wrote: > > > > > > > > > > > > > > Hi Rob and Doug > > > > > > > > > > > > > > On 7/22/2022 10:36 AM, Rob Clark wrote: > > > > > > > > On Fri, Jul 22, 2022 at 9:48 AM Doug Anderson > > > > > > > > wrote: > > > > > > > >> > > > > > > > >> Hi, > > > > > > > >> > > > > > > > >> On Fri, Jul 22, 2022 at 9:37 AM Abhinav Kumar > > > > > > > >> wrote: > > > > > > > >>> > > > > > > > >>> + sankeerth > > > > > > > >>> > > > > > > > >>> Hi Doug > > > > > > > >>> > > > > > > > >>> On 7/21/2022 3:23 PM, Douglas Anderson wrote: > > > > > > > The Sharp LQ140M1JW46 panel is on the Qualcomm sc7280 CRD > > > > > > > reference > > > > > > > board. This panel supports 144 Hz and 60 Hz. In the EDID, > > > > > > > the 144 Hz > > > > > > > mode is listed first and thus is marked preferred. The EDID > > > > > > > decode I > > > > > > > ran says: > > > > > > > > > > > > > > First detailed timing includes the native pixel format > > > > > > > and preferred > > > > > > > refresh rate. > > > > > > > > > > > > > > ... > > > > > > > > > > > > > > Detailed Timing Descriptors: > > > > > > > DTD 1: 1920x1080 143.981 Hz 16:9 166.587 kHz > > > > > > > 346.500 MHz > > > > > > > Hfront 48 Hsync 32 Hback 80 Hpol N > > > > > > > Vfront3 Vsync 5 Vback 69 Vpol N > > > > > > > DTD 2: 1920x1080 59.990 Hz 16:969.409 kHz > > > > > > > 144.370 MHz > > > > > > > Hfront 48 Hsync 32 Hback 80 Hpol N > > > > > > > Vfront3 Vsync 5 Vback 69 Vpol N > > > > > > > > > > > > > > I'm proposing here that the above is actually a bug and that > > > > > > > the 60 Hz > > > > > > > mode really should be considered preferred by Linux. > > > > > > > > > > > > > > Its a bit tricky to say that this is a bug but I think we can > > > > > > > certainly > > > > > > > add here that for an internal display we would have ideally had > > > > > > > the > > > > > > > lower resolution first to indicate it as default. > > > > > > > > > > > > Yeah, it gets into the vagueness of the EDID spec in general. As far > > > > > > as I can find it's really up to the monitor to decide by what means > > > > > > it > > > > > > chooses the "preferred" refresh rate if the monitor can support > > > > > > many. > > > > > > Some displays may decide that the normal rate is "preferred" and > > > > > > some > > > > > > may decide that the high refresh rate is "preferred". Neither > > > > > > display > > > > > > is "wrong" per say, but it's nice to have some consistency here and > > > > > > to > > > > > > make it so that otherwise "dumb" userspace will get something > > > > > > reasonable by default. I'll change it to say: > > > > > > > > > > > > While the EDID spec appears to allow a display to use any criteria > > > > > > for > > > > > > picking which refresh mode is "preferred" or "optimal", that > > > > > > vagueness > > > > > > is a bit annoying. From Linux's point of view let's choose the 60 Hz > > > > > > one as the default. > > > > > > > > > > And if we start making that decision, it should be for all panels > > > > > with a > > > > > similar constraint, so most likely handled by the core, and the new > > > > > policy properly documented. > > > > > > > > > > Doing that just for a single panel is weird. > > > > > > > > Yeah, though having a "general policy" in the core can be problematic. > > > > > > > > In general I think panel EDIDs are only trustworthy as far as you can > > > > throw them. They are notorious for having wrong and incorrect > > > > information, which is why the EDID quirk list exists to begin with. > > > > Trying to change how we're going to interpret all EDIDs, even all > > > > EDIDs for eDP panels, seems like it will break someone somewhere. > > > > Maybe there are EDIDs out there that were only ever validated at the > > > > higher refresh rate and they don't work / flicker / cause digitizer > > > > noise at the lower refresh rate. Heck, we've seen eDP panel vendors > > > > that can't even get their checksum correct, so I'm not sure I want to > > > > make a global assertion that all panels validated their "secondary" > > > > display mode. > > > > > > > > In this particular case, we have validated that this particular Sharp > > > > panel works fine at the lower refresh
Re: [Freedreno] [PATCH] drm/msm/dsi: Set panel orientation when directly connected
Hi,
On Wed, Jul 20, 2022 at 3:42 PM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Jul 20, 2022 at 1:46 PM Rob Clark wrote:
> >
> > On Fri, Jul 8, 2022 at 8:25 AM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Wed, Jul 6, 2022 at 12:14 PM Stephen Boyd wrote:
> > > >
> > > > Set the panel orientation in drm when the panel is directly connected,
> > > > i.e. we're not using an external bridge. The external bridge case is
> > > > already handled by the panel bridge code, so we only update the path we
> > > > take when the panel is directly connected/internal. This silences a
> > > > warning splat coming from __drm_mode_object_add() on Wormdingler boards.
> > > >
> > > > Cc: Hsin-Yi Wang
> > > > Cc: Douglas Anderson
> > > > Signed-off-by: Stephen Boyd
> > > > ---
> > > >
> > > > This relies on commit 5e41b01a7808 ("drm/panel: Add an API to allow drm
> > > > to set orientation from panel") which is in drm-misc
> > > >
> > > > drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 ++
> > > > 1 file changed, 2 insertions(+)
> > >
> > > I don't personally have objections to this, but (to my understanding)
> > > "the future" is that everyone should use panel_bridge. If we made the
> > > move to panel_bridge today then we wouldn't need to do this. In
> > > general I think panel_bridge would end up letting us delete a bunch of
> > > code...
> > >
> > > See commit 4e5763f03e10 ("drm/bridge: ti-sn65dsi86: Wrap panel with
> > > panel-bridge") for when this was done by ti-sn65dsi86.
> > >
> > > Then again, I spent a small amount of time looking into this and it's
> > > definitely non-trivial. Still likely worthwhile, but not worth
> > > blocking a tiny fix like this. It also should be fairly obvious that
> > > we should delete this when we switch to panel_bridge.
> > >
> > > Thus:
> > >
> > > Reviewed-by: Douglas Anderson
> > >
> > > I'll assume that we'll just snooze this commit until drm-misc-next
> > > merges into a tree that msm-next is based on, which will probably be
> > > the next -rc1. If desired and Acked I could land this in
> > > drm-misc-next, but it's probably not worth it?
> >
> > if you want to land this patch via drm-misc, which might be the
> > easier/faster route, then:
> >
> > Acked-by: Rob Clark
>
> As per discussion on IRC, I'm not going to apply this to drm-misc-next.
>
> Given where we are in the cycle landing in drm-misc-next means it
> won't be in mainline for a couple versions and I suspect that'll cause
> merge conflicts with Dmitry's series [1]. ...and, of course, if
> Dmitry's series lands then we don't even need ${SUBJECT} patch...
>
> So I think the plan is:
>
> 1. Snooze waiting for the next -rc1 since
> drm_connector_set_orientation_from_panel() won't be in mainline until
> then.
>
> 2. If Dmitry's series looks like a long way off, we could land
> ${SUBJECT} patch in msm-next as a stopgap fix.
>
>
> [1]
> https://lore.kernel.org/r/20220711094320.368062-5-dmitry.barysh...@linaro.org/
Just checking up. What's the latest thinking here? Do we want to land
Stephen's change as a stopgap?
drm_connector_set_orientation_from_panel() is available in v6.0-rc1.
-Doug
Re: [Freedreno] [PATCH v2 4/7] regulator: core: Allow specifying an initial load w/ the bulk API
Hi, Douglas On Wed, 17 Aug 2022 at 22:26, Doug Anderson wrote: > > Hi, > > On Tue, Aug 16, 2022 at 5:58 AM Yongqin Liu wrote: > > > > HI, Douglas > > > > With this change, I get one kernel panic with my hikey960 > > android-mainline based Android build, > > if it's reverted, then the build could boot to the home screen successfully. > > From the log information I shared here, not sure if you have any idea > > what I could do to have the hikey960 > > build work with this change, > > > > The kernel panic is something like this, for details, please check the > > log here: http://ix.io/47Lq > > > > [ 10.738042][ T193] adv7511 1-0039: error : Failed > > to get supply 'v1p2' > > [ 10.748457][ T194] apexd: Found pre-installed APEX > > /system/apex/com.android.os.statsd.apex > > [ 10.752908][ T67] Unable to handle kernel read from unreadable > > memory at virtual address 004c > > [ 10.753116][T8] Unable to handle kernel read from unreadable > > memory at virtual address 0078 > > [ 10.753130][T8] Mem abort info: > > [ 10.753135][T8] ESR = 0x9605 > > [ 10.753142][T8] EC = 0x25: DABT (current EL), IL = 32 bits > > [ 10.753152][T8] SET = 0, FnV = 0 > > [ 10.753159][T8] EA = 0, S1PTW = 0 > > [ 10.753166][T8] FSC = 0x05: level 1 translation fault > > [ 10.753174][T8] Data abort info: > > [ 10.753179][T8] ISV = 0, ISS = 0x0005 > > [ 10.753184][T8] CM = 0, WnR = 0 > > [ 10.753192][T8] user pgtable: 4k pages, 39-bit VAs, > > pgdp=03098000 > > [ 10.753204][T8] [0078] pgd=, > > p4d=, pud= > > [ 10.753232][T8] Internal error: Oops: 9605 [#1] PREEMPT SMP > > [ 10.753245][T8] Modules linked in: adv7511(E+) tcpci_rt1711h(E) > > hci_uart(E) btqca(E) btbcm(E) cpufreq_dt(E) hi3660_i2s(E) > > hisi_hikey_usb(E) hi6421_pmic_core(E) syscon_reboot_mode(E) > > reboot_mode(E) hi3660_mailbox(E) dw_mmc_k3(E) hisi_thermal(E) > > dw_mmc_pltfm(E) dw_mmc(E) kirin_drm(E) snd_soc_simple_card(E) > > snd_soc_simple_card_utils(E) spi_pl022(E) kirin_dsi(E) > > phy_hi3660_usb3(E) i2c_designware_platform(E) drm_cma_helper(E) > > i2c_designware_core(E) mali_kbase(OE) k3dma(E) cma_heap(E) > > system_heap(E) > > [ 10.753436][T8] CPU: 2 PID: 8 Comm: kworker/u16:0 Tainted: G > >OE 5.19.0-mainline-03487-g86d047950300-dirty #1 > > [ 10.753454][T8] Hardware name: HiKey960 (DT) > > [ 10.753463][T8] Workqueue: events_unbound async_run_entry_fn > > [ 10.753497][T8] pstate: 6045 (nZCv daif +PAN -UAO -TCO -DIT > > -SSBS BTYPE=--) > > [ 10.753516][T8] pc : regulator_bulk_enable_async+0x3c/0x98 > > [ 10.753540][T8] lr : async_run_entry_fn+0x30/0xf8 > > [ 10.753559][T8] sp : ffc009ed3d20 > > [ 10.753567][T8] x29: ffc009ed3d40 x28: 0402 > > x27: ff801ad99828 > > [ 10.753592][T8] x26: ff803217b010 x25: 0002 > > x24: ff8003385da8 > > [ 10.753617][T8] x23: ff8003385da0 x22: ff801ad94805 > > x21: ff8003385da0 > > [ 10.753642][T8] x20: x19: ff8003143d20 > > x18: ffc008075028 > > [ 10.753667][T8] x17: 00040044 x16: 0001 > > x15: 0010 > > [ 10.753691][T8] x14: x13: 0f58 > > x12: 8235 > > [ 10.753715][T8] x11: 6acfbfa2f400 x10: 0016 x9 > > : 00ff > > [ 10.753740][T8] x8 : da9ecda1b63b0500 x7 : 8080 x6 > > : > > [ 10.753764][T8] x5 : 0001 x4 : 646e756f626e x3 > > : ff801ad99828 > > [ 10.753788][T8] x2 : ff8003385da8 x1 : ffc009ed3d20 x0 > > : ff8003143d20 > > [ 10.753812][T8] Call trace: > > [ 10.753818][T8] regulator_bulk_enable_async+0x3c/0x98 > > [ 10.753839][T8] async_run_entry_fn+0x30/0xf8 > > [ 10.753859][T8] process_one_work+0x1d0/0x404 > > [ 10.753879][T8] worker_thread+0x25c/0x43c > > [ 10.753897][T8] kthread+0xf0/0x2c0 > > [ 10.753912][T8] ret_from_fork+0x10/0x20 > > [ 10.753940][T8] Code: f81f83a8 f9400814 a900 f90003ff (f9403e95) > > [ 10.753950][T8] ---[ end trace ]--- > > [ 10.760621][ T194] apexd: Found pre-installed APEX > > /system/apex/com.android.permission.capex > > [ 10.767672][ T67] Mem abort info: > > [ 10.779658][ T194] apexd: Found pre-installed APEX > > /system/apex/com.android.art.capex > > [ 10.783690][ T67] ESR = 0x9605 > > [ 10.792424][ T194] apexd: Found pre-installed APEX > > /system/apex/com.android.scheduling.capex > > [ 10.794713][T8] Kernel panic - not syncing: Oops: Fatal exception > > [ 10.794723][T8] SMP: stopping secondary CPUs > > [ 10.798141][T8] Kernel Offset: 0x7 from 0xffc00800 > > [ 10.798150][
[Freedreno] [linux-next:master] BUILD SUCCESS WITH WARNING 95d10484d66e54d5c01e36389e9318221fb8f60b
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 95d10484d66e54d5c01e36389e9318221fb8f60b Add linux-next specific files for 20220817 Warning reports: https://lore.kernel.org/linux-doc/202208162058.7appivkl-...@intel.com https://lore.kernel.org/llvm/202207251313.gkhpeleq-...@intel.com Warning: (recently discovered and may have been fixed) Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/gpio/gpio-xilinx.txt drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1046:5: warning: no previous prototype for 'fill_dc_scaling_info' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1222:6: warning: no previous prototype for 'handle_cursor_update' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:152:6: warning: no previous prototype for 'modifier_has_dcc' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1576:5: warning: no previous prototype for 'amdgpu_dm_plane_init' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:157:10: warning: no previous prototype for 'modifier_gfx9_swizzle_mode' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:752:5: warning: no previous prototype for 'fill_plane_buffer_attributes' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:83:31: warning: no previous prototype for 'amd_get_format_info' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:88:6: warning: no previous prototype for 'fill_blending_from_plane_state' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:992:5: warning: no previous prototype for 'dm_plane_helper_check_state' [-Wmissing-prototypes] drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c:905:28: warning: variable 'top' set but not used [-Wunused-but-set-variable] drivers/iio/accel/bma400_core.c:1091 bma400_activity_event_en() error: uninitialized symbol 'field_value'. drivers/iio/cdc/ad7746.c:336:14: warning: use of uninitialized value '' [CWE-457] [-Wanalyzer-use-of-uninitialized-value] drivers/platform/mellanox/mlxreg-lc.c:866 mlxreg_lc_probe() warn: passing zero to 'PTR_ERR' mm/memory_hotplug.c:343 __add_pages() error: uninitialized symbol 'err'. Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-amd_get_format_info | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-amdgpu_dm_plane_init | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-dm_plane_helper_check_state | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-fill_blending_from_plane_state | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-fill_dc_scaling_info | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-fill_plane_buffer_attributes | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-handle_cursor_update | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-modifier_gfx9_swizzle_mode | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-modifier_has_dcc | `-- drivers-gpu-drm-msm-disp-dpu1-dpu_kms.c:warning:variable-top-set-but-not-used |-- alpha-randconfig-c023-20220815 | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-amd_get_format_info | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-amdgpu_dm_plane_init | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-dm_plane_helper_check_state | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-fill_blending_from_plane_state | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-fill_dc_scaling_info | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-fill_plane_buffer_attributes | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-handle_cursor_update | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_plane.c:warning:no-previous-prototype-for-modifier_gfx9_swizzle_mode | `-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm
Re: [Freedreno] [PATCH v2 4/7] regulator: core: Allow specifying an initial load w/ the bulk API
Hi,
On Tue, Aug 16, 2022 at 5:58 AM Yongqin Liu wrote:
>
> HI, Douglas
>
> With this change, I get one kernel panic with my hikey960
> android-mainline based Android build,
> if it's reverted, then the build could boot to the home screen successfully.
> From the log information I shared here, not sure if you have any idea
> what I could do to have the hikey960
> build work with this change,
>
> The kernel panic is something like this, for details, please check the
> log here: http://ix.io/47Lq
>
> [ 10.738042][ T193] adv7511 1-0039: error : Failed
> to get supply 'v1p2'
> [ 10.748457][ T194] apexd: Found pre-installed APEX
> /system/apex/com.android.os.statsd.apex
> [ 10.752908][ T67] Unable to handle kernel read from unreadable
> memory at virtual address 004c
> [ 10.753116][T8] Unable to handle kernel read from unreadable
> memory at virtual address 0078
> [ 10.753130][T8] Mem abort info:
> [ 10.753135][T8] ESR = 0x9605
> [ 10.753142][T8] EC = 0x25: DABT (current EL), IL = 32 bits
> [ 10.753152][T8] SET = 0, FnV = 0
> [ 10.753159][T8] EA = 0, S1PTW = 0
> [ 10.753166][T8] FSC = 0x05: level 1 translation fault
> [ 10.753174][T8] Data abort info:
> [ 10.753179][T8] ISV = 0, ISS = 0x0005
> [ 10.753184][T8] CM = 0, WnR = 0
> [ 10.753192][T8] user pgtable: 4k pages, 39-bit VAs,
> pgdp=03098000
> [ 10.753204][T8] [0078] pgd=,
> p4d=, pud=
> [ 10.753232][T8] Internal error: Oops: 9605 [#1] PREEMPT SMP
> [ 10.753245][T8] Modules linked in: adv7511(E+) tcpci_rt1711h(E)
> hci_uart(E) btqca(E) btbcm(E) cpufreq_dt(E) hi3660_i2s(E)
> hisi_hikey_usb(E) hi6421_pmic_core(E) syscon_reboot_mode(E)
> reboot_mode(E) hi3660_mailbox(E) dw_mmc_k3(E) hisi_thermal(E)
> dw_mmc_pltfm(E) dw_mmc(E) kirin_drm(E) snd_soc_simple_card(E)
> snd_soc_simple_card_utils(E) spi_pl022(E) kirin_dsi(E)
> phy_hi3660_usb3(E) i2c_designware_platform(E) drm_cma_helper(E)
> i2c_designware_core(E) mali_kbase(OE) k3dma(E) cma_heap(E)
> system_heap(E)
> [ 10.753436][T8] CPU: 2 PID: 8 Comm: kworker/u16:0 Tainted: G
>OE 5.19.0-mainline-03487-g86d047950300-dirty #1
> [ 10.753454][T8] Hardware name: HiKey960 (DT)
> [ 10.753463][T8] Workqueue: events_unbound async_run_entry_fn
> [ 10.753497][T8] pstate: 6045 (nZCv daif +PAN -UAO -TCO -DIT
> -SSBS BTYPE=--)
> [ 10.753516][T8] pc : regulator_bulk_enable_async+0x3c/0x98
> [ 10.753540][T8] lr : async_run_entry_fn+0x30/0xf8
> [ 10.753559][T8] sp : ffc009ed3d20
> [ 10.753567][T8] x29: ffc009ed3d40 x28: 0402
> x27: ff801ad99828
> [ 10.753592][T8] x26: ff803217b010 x25: 0002
> x24: ff8003385da8
> [ 10.753617][T8] x23: ff8003385da0 x22: ff801ad94805
> x21: ff8003385da0
> [ 10.753642][T8] x20: x19: ff8003143d20
> x18: ffc008075028
> [ 10.753667][T8] x17: 00040044 x16: 0001
> x15: 0010
> [ 10.753691][T8] x14: x13: 0f58
> x12: 8235
> [ 10.753715][T8] x11: 6acfbfa2f400 x10: 0016 x9
> : 00ff
> [ 10.753740][T8] x8 : da9ecda1b63b0500 x7 : 8080 x6
> :
> [ 10.753764][T8] x5 : 0001 x4 : 646e756f626e x3
> : ff801ad99828
> [ 10.753788][T8] x2 : ff8003385da8 x1 : ffc009ed3d20 x0
> : ff8003143d20
> [ 10.753812][T8] Call trace:
> [ 10.753818][T8] regulator_bulk_enable_async+0x3c/0x98
> [ 10.753839][T8] async_run_entry_fn+0x30/0xf8
> [ 10.753859][T8] process_one_work+0x1d0/0x404
> [ 10.753879][T8] worker_thread+0x25c/0x43c
> [ 10.753897][T8] kthread+0xf0/0x2c0
> [ 10.753912][T8] ret_from_fork+0x10/0x20
> [ 10.753940][T8] Code: f81f83a8 f9400814 a900 f90003ff (f9403e95)
> [ 10.753950][T8] ---[ end trace ]---
> [ 10.760621][ T194] apexd: Found pre-installed APEX
> /system/apex/com.android.permission.capex
> [ 10.767672][ T67] Mem abort info:
> [ 10.779658][ T194] apexd: Found pre-installed APEX
> /system/apex/com.android.art.capex
> [ 10.783690][ T67] ESR = 0x9605
> [ 10.792424][ T194] apexd: Found pre-installed APEX
> /system/apex/com.android.scheduling.capex
> [ 10.794713][T8] Kernel panic - not syncing: Oops: Fatal exception
> [ 10.794723][T8] SMP: stopping secondary CPUs
> [ 10.798141][T8] Kernel Offset: 0x7 from 0xffc00800
> [ 10.798150][T8] PHYS_OFFSET: 0x0
> [ 10.798156][T8] CPU features: 0x,00649020,1086
> [ 10.798167][T8] Memory Limit: none
Are you fixed by the patch ("regulator: core: Fix missing error return
from regulator_bulk_get()") [1]
[1]
[Freedreno] [PATCH v2 4/5] dt-bindings: display/msm: dpu-sc7280: add missing DPU opp-table
The 'display-controller' child (DPU) of Display SubSystem (MDSS) uses
opp-table, so reference it which allows restricting DPU schema to fixed
list of properties.
Fixes: 57fd4f34ddac ("dt-bindings: msm: add DT bindings for sc7280")
Signed-off-by: Krzysztof Kozlowski
---
Cc: Dmitry Baryshkov
Cc: Rob Clark
Cc: Sean Paul
Cc: Abhinav Kumar
---
Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
index f427eec3d3a4..584d646021d5 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
@@ -72,6 +72,7 @@ patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
+additionalProperties: false
properties:
compatible:
@@ -112,6 +113,8 @@ patternProperties:
maxItems: 1
operating-points-v2: true
+ opp-table:
+type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
--
2.34.1
[Freedreno] [PATCH v2 1/5] dt-bindings: display/msm: dpu-msm8998: add missing DPU opp-table
The 'display-controller' child (DPU) of Display SubSystem (MDSS) uses
opp-table, so reference it which allows restricting DPU schema to fixed
list of properties.
Fixes: 6e986a8f1cf1 ("dt-bindings: display: msm: Add binding for msm8998 dpu")
Signed-off-by: Krzysztof Kozlowski
---
Cc: Dmitry Baryshkov
Cc: Rob Clark
Cc: Sean Paul
Cc: Abhinav Kumar
---
.../devicetree/bindings/display/msm/dpu-msm8998.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
index 2df64afb76e6..253665c693e6 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
@@ -62,6 +62,7 @@ patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
+additionalProperties: false
properties:
compatible:
@@ -105,6 +106,9 @@ patternProperties:
maxItems: 1
operating-points-v2: true
+ opp-table:
+type: object
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
--
2.34.1
[Freedreno] [PATCH v2 3/5] dt-bindings: display/msm: dpu-sc7180: add missing DPU opp-table
The 'display-controller' child (DPU) of Display SubSystem (MDSS) uses
opp-table, so reference it which allows restricting DPU schema to fixed
list of properties.
Fixes: 3d7a0dd8f39b ("dt-bindings: msm: disp: add yaml schemas for DPU
bindings")
Signed-off-by: Krzysztof Kozlowski
---
Cc: Dmitry Baryshkov
Cc: Rob Clark
Cc: Sean Paul
Cc: Abhinav Kumar
---
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
index d3c3e4b07897..4890bc25f3fd 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
@@ -73,6 +73,7 @@ patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
+additionalProperties: false
properties:
compatible:
@@ -114,6 +115,8 @@ patternProperties:
maxItems: 1
operating-points-v2: true
+ opp-table:
+type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
--
2.34.1
[Freedreno] [PATCH v2 2/5] dt-bindings: display/msm: dpu-qcm2290: add missing DPU opp-table
The 'display-controller' child (DPU) of Display SubSystem (MDSS) uses
opp-table, so reference it which allows restricting DPU schema to fixed
list of properties.
Fixes: 164f69d9d45a ("dt-bindings: msm: disp: add yaml schemas for QCM2290 DPU
bindings")
Signed-off-by: Krzysztof Kozlowski
---
Cc: Dmitry Baryshkov
Cc: Rob Clark
Cc: Sean Paul
Cc: Abhinav Kumar
---
Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
index 734d14de966d..c5824e1d2382 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
@@ -74,6 +74,7 @@ patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
+additionalProperties: false
properties:
compatible:
@@ -113,6 +114,8 @@ patternProperties:
maxItems: 1
operating-points-v2: true
+ opp-table:
+type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
--
2.34.1
[Freedreno] [PATCH v2 0/5] dt-bindings: display/msm: dpu: opp-table fixes
Hi, Changes since v1 1. Use opp-table:object (Rob) Merging/other work == There is a conflicting series of https://lore.kernel.org/all/20220710090040.35193-1-dmitry.barysh...@linaro.org/ but I think this one here should go before to fix the issue before the refactoring. Best regards, Krzysztof Cc: Dmitry Baryshkov Cc: Rob Clark Cc: Sean Paul Cc: Abhinav Kumar Krzysztof Kozlowski (5): dt-bindings: display/msm: dpu-msm8998: add missing DPU opp-table dt-bindings: display/msm: dpu-qcm2290: add missing DPU opp-table dt-bindings: display/msm: dpu-sc7180: add missing DPU opp-table dt-bindings: display/msm: dpu-sc7280: add missing DPU opp-table dt-bindings: display/msm: dpu-sdm845: add missing DPU opp-table .../devicetree/bindings/display/msm/dpu-msm8998.yaml | 4 .../devicetree/bindings/display/msm/dpu-qcm2290.yaml | 3 +++ Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml | 3 +++ Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml | 3 +++ Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml | 4 5 files changed, 17 insertions(+) -- 2.34.1
Re: [Freedreno] [PATCH 1/5] dt-bindings: display/msm: dpu-msm8998: add missing DPU opp-table
On 15/08/2022 00:25, Rob Herring wrote: >> properties: >>compatible: >> @@ -105,6 +106,8 @@ patternProperties: >> maxItems: 1 >> >>operating-points-v2: true >> + opp-table: true > > type: object > > Otherwise, 'opp-table;' would be accepted. > Thanks, I'll fix it. Best regards, Krzysztof
