date:20221115

Re: [Freedreno] [PATCH v3 8/8] drm/msm: mdss: add support for SM8450

2022-11-15 Thread Abhinav Kumar





On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote:

Add support for the MDSS block on SM8450 platform.

Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Dmitry Baryshkov 

Reviewed-by: Abhinav Kumar 

---
  drivers/gpu/drm/msm/msm_mdss.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 6a4549ef34d4..5602fbaf6e0e 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
+   case DPU_HW_VER_810:
+   /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+   msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
+   break;
}
  
  	return ret;

@@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+   { .compatible = "qcom,sm8450-mdss" },
{}
  };
  MODULE_DEVICE_TABLE(of, mdss_dt_match);

Re: [Freedreno] [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole

2022-11-15 Thread Abhinav Kumar





On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote:

On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.

Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Dmitry Baryshkov 


I am confused with both the ordering and the split of this patch.

You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file in 
this patch but used it in the next.


But you also have code in this patch which relies on setting of this bit.

So if this patch is taken without the next, it will still crash.

Rather, you should combine the define part of this patch to the next 
patch in the series 
https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , 
then move that one in front of this patch.


So that its much more coherent that you defined DPU_MDP_PERIPH_0_REMOVED 
both in the catalog header and used it in the catalog.c file and the in 
the next change you used the caps to avoid touching that register.


Regarding the TOP hole itself, I need one day to investigate this. I am 
waiting for permissions to the documentation.


If i cannot get access by the time you have re-ordered this, I will ack 
this once the reorder is done within a day.



---
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  1 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 11 +--
  2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38ab1568..4730f8268f2a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -92,6 +92,7 @@ enum {
DPU_MDP_UBWC_1_0,
DPU_MDP_UBWC_1_5,
DPU_MDP_AUDIO_SELECT,
+   DPU_MDP_PERIPH_0_REMOVED,
DPU_MDP_MAX
  };
  
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

index f3660cd14f4f..95d8765c1c53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state 
*disp_state, struct msm_k
msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
  
-	msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,

-   dpu_kms->mmio + cat->mdp[0].base, "top");
+   if (dpu_kms->hw_mdp->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
+   msm_disp_snapshot_add_block(disp_state, 0x380,
+   dpu_kms->mmio + cat->mdp[0].base, "top");
+   msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8,
+   dpu_kms->mmio + cat->mdp[0].base + 0x3a8, 
"top_2");
+   } else {
+   msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
+   dpu_kms->mmio + cat->mdp[0].base, "top");
+   }
  
  	pm_runtime_put_sync(&dpu_kms->pdev->dev);

  }

Re: [Freedreno] [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0

2022-11-15 Thread Abhinav Kumar





On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote:

Add support for DSI 2.6.0 (block used on sm8450).

Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Dmitry Baryshkov 

Reviewed-by: Abhinav Kumar 

---
  drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
  drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
  2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 7e97c239ed48..59a4cc95a251 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] 
= {
&sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
&sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
+   &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
  };
  
  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 8f04e685a74e..95957fab499d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -25,6 +25,7 @@
  #define MSM_DSI_6G_VER_MINOR_V2_4_0   0x2004
  #define MSM_DSI_6G_VER_MINOR_V2_4_1   0x20040001
  #define MSM_DSI_6G_VER_MINOR_V2_5_0   0x2005
+#define MSM_DSI_6G_VER_MINOR_V2_6_00x2006
  
  #define MSM_DSI_V2_VER_MINOR_8064	0x0

Re: [Freedreno] [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450

2022-11-15 Thread Abhinav Kumar

On 11/7/2022 3:02 PM, Dmitry Baryshkov wrote:

On 07/11/2022 07:27, Abhinav Kumar wrote:

On 9/22/2022 4:30 AM, Dmitry Baryshkov wrote:

SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.

I do realize that there is common code across PHYs but i am concerned 
about this type of unification of phy drivers.

This more or less follows downstream, which has unifier v4.0 driver.

Ack, I just observed the same. Thanks for the pointer.
Its still prone to sequencing issues though. But for now, this is okay.

If we have features which are PHY sequence dependent such as ULPS, 
this will just complicate things for us.

During development we initially tried to create a separate 5nm driver. 
However this resulted in huuuge code duplication. This would be prone to 
significant amount of errors if we change one of the drivers at some 
point and not another one.

Also some PHY registers might get added some might get removed across 
chipsets as this is the most frequently changed component.

Yes, I completely agree here. However beforehand we have successfully 
managed to have per-generation drivers, handling minor differences with 
quirks.

I kind of agree with Konrad's earlier comment that "QUIRK" is really not 
the right naming for this. Its actually different phy sub-versions.

A cleanup is needed to change or move away from quirk terminology for this.

Even in this patch, I see this added to dsi_7nm_phy_disable()

 > +    /* Turn off REFGEN Vote */
 > +    dsi_phy_write(base + 
REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);

 > +    wmb();
 > +    /* Delay to ensure HW removes vote before PHY shut down */
 > +    udelay(2);
 > +

What would be the impact of writing this for the existing 7nm PHY?

Let's probably guard this with the v4.3 check.

hmmm, i see that in downstream also we are doing this for 7nm and 5nm 
PHYs. I am now wondering whether a write to 0 along with the 2 microsec 
delay was just missed out while writing the 7nm PHY. If so, can you move 
that to a separate patch instead of this one as a "fix". Adding it to 
this patch creates an impression that this is specific to the 5nm 
changes but seems like they arent.

I am having some access issues to check the software interface so 
wanted to check.

I don't remember having any issues on RB5, but I did not run any special 
checks.

When I meant access issues, I meant some permissions issue internally 
for accessing software register documentation not register access issues 
on the device :)

Co-developed-by: Robert Foss 
Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/msm/Kconfig   |   6 +-
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |   4 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |   2 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 --
  4 files changed, 131 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 4e0cbd682725..e6c5dfbad009 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
    Choose this option if DSI PHY on SDM845 is used on the platform.
  config DRM_MSM_DSI_7NM_PHY
-    bool "Enable DSI 7nm PHY driver in MSM DRM"
+    bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
  depends on DRM_MSM_DSI
  default y
  help
-  Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
-  the platform.
+  Choose this option if DSI PHY on 
SM8150/SM8250/SM8350/SM8450/SC7280

+  is used on the platform.
  config DRM_MSM_HDMI
  bool "Enable HDMI support in MSM DRM driver"
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

index 7fc0975cb869..97cf6b8b34cc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -567,6 +567,10 @@ static const struct of_device_id 
dsi_phy_dt_match[] = {

    .data = &dsi_phy_7nm_8150_cfgs },
  { .compatible = "qcom,sc7280-dsi-phy-7nm",
    .data = &dsi_phy_7nm_7280_cfgs },
+    { .compatible = "qcom,dsi-phy-5nm-8350",
+  .data = &dsi_phy_5nm_8350_cfgs },
+    { .compatible = "qcom,dsi-phy-5nm-8450",
+  .data = &dsi_phy_5nm_8450_cfgs },
  #endif
  {}
  };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

index 60a99c6525b2..654cbfa14d6e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -56,6 +56,8 @@ extern const struct msm_dsi_phy_cfg 
dsi_phy_10nm_8998_cfgs;

  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_845

Re: [Freedreno] [PATCH] drm/msm/dp: remove limitation of link rate at 5.4G to support HBR3

2022-11-15 Thread Kuogee Hsieh




On 11/9/2022 11:43 PM, Dmitry Baryshkov wrote:

On 10/11/2022 02:47, Kuogee Hsieh wrote:


On 11/2/2022 11:04 AM, Dmitry Baryshkov wrote:

On 02/11/2022 20:28, Doug Anderson wrote:

Hi,

On Wed, Nov 2, 2022 at 10:23 AM Dmitry Baryshkov
 wrote:



1. Someone figures out how to model this with the bridge chain and
then we only allow HBR3 if we detect we've got a TCPC that supports
it. This seems like the cleanest / best but feels like a long pole.
Not only have we been trying to get the TCPC-modeled-as-a-bridge 
stuff

landed for a long time but even when we do it we still don't have a
solution for how to communicate the number of lanes and other stuff
between the TCPC and the DP controller so we have to enrich the 
bridge

interface.


I think we'd need some OOB interface. For example for DSI 
interfaces we

have mipi_dsi_device struct to communicate such OOB data.

Also take a note regarding data-lanes from my previous email.


Right, we can somehow communicate the max link rate through the bridge
chain to the DP controller in an OOB manner that would work.


I'd note that our dp_panel has some notion of such OOB data. So do 
AUX drivers including the panel-edp. My suggestion would be to 
consider both of them while modelling the OOB data.






2. We add in a DT property to the display controller node that says
the max link rate for use on this board. This feels like a hack, but
maybe it's not too bad. Certainly it would be incredibly simple to
implement. Actually... ...one could argue that even if we later 
model
the TCPC as a bridge that this property would still be valid / 
useful!

You could certainly imagine that the SoC supports HBR3 and the TCPC
supports HBR3 but that the board routing between the SoC and the 
TCPC

is bad and only supports HBR2. In this case the only way out is
essentially a "board constraint" AKA a DT property in the DP
controller.


We have been discussing similar topics with Abhinav. Krzysztof 
suggested

using link-frequencies property to provide max and min values.


questions,

1)is Krzysztof suggested had been implemented?


I can not parse this question, please excuse me.

Yes, Krzysztof suggested this being implemented as a link property, 
see media/video-interfaces.txt.


Moreover your implementation goes against both the existing definition 
(array with the list of frequencies) and Krzysztof's suggested 
extension (min and max). Listing just a single frequency goes against 
both these suggestions. In case of DP we have a fixed set of 
frequencies. Thus I'd suggest listing all supported frequencies instead.


I think this proposal is kind of strange.

According to DP spec, if a link support 5,4G, then it must support 1.6, 
2.7 and 5.4.


If it support 8.1G, then it must support 1.6 , 2.7 and 5.4.

There is no link can only support 2.7 and 5.4G without supporting 1.6G.




2) where is link property i can add link-frequencies?


link node. Create outbound graph node, add link-frequencies there. 
Also as you are touching this part, please move the data-lanes 
property too.







This sounds good to me and seems worth doing even if we eventually 
do #1.


And the bonus point is that it can be done easily.

Re: [Freedreno] [PATCH] drm/msm: Enable clamp_to_idle for 7c3

2022-11-15 Thread Chia-I Wu

On Tue, Nov 15, 2022 at 8:01 AM Doug Anderson  wrote:
>
> Hi,
>
> On Tue, Nov 15, 2022 at 7:55 AM Rob Clark  wrote:
> >
> > From: Rob Clark 
> >
> > This was overlooked.
> >
> > Signed-off-by: Rob Clark 
> > ---
> >  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++---
> >  1 file changed, 7 insertions(+), 7 deletions(-)
>
> Reviewed-by: Douglas Anderson 
Reviewed-by: Chia-I Wu

Re: [Freedreno] [PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding

2022-11-15 Thread Rob Herring

On Tue, Nov 15, 2022 at 12:17:11PM +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for MDSS device
> tree bindings
> 
> Signed-off-by: Robert Foss 
> ---
>  .../display/msm/qcom,sm8350-mdss.yaml | 240 ++
>  1 file changed, 240 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> 
> diff --git 
> a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml 
> b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> new file mode 100644
> index ..9a0694853576
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> @@ -0,0 +1,240 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8350 Display MDSS
> +
> +maintainers:
> +  - Robert Foss 
> +
> +description:
> +  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that 
> encapsulates

Drop 'Device tree bindings for '. Describe what this h/w is.

> +  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device 
> tree
> +  bindings of MDSS are mentioned for SM8350 target.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> +  compatible:
> +items:
> +  - const: qcom,sm8350-mdss
> +
> +  clocks:
> +items:
> +  - description: Display AHB clock from gcc
> +  - description: Display hf axi clock
> +  - description: Display sf axi clock
> +  - description: Display core clock
> +
> +  clock-names:
> +items:
> +  - const: iface
> +  - const: bus
> +  - const: nrt_bus
> +  - const: core
> +
> +  iommus:
> +maxItems: 1
> +
> +  interconnects:
> +maxItems: 2
> +
> +  interconnect-names:
> +maxItems: 2

Need to define the names.

> +
> +patternProperties:
> +  "^display-controller@[0-9a-f]+$":
> +type: object
> +properties:
> +  compatible:
> +const: qcom,sm8350-dpu
> +
> +  "^dsi@[0-9a-f]+$":
> +type: object
> +properties:
> +  compatible:
> +const: qcom,mdss-dsi-ctrl
> +
> +  "^phy@[0-9a-f]+$":
> +type: object
> +properties:
> +  compatible:
> +const: qcom,dsi-phy-5nm-8350
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +display-subsystem@ae0 {
> +compatible = "qcom,sm8350-mdss";
> +reg = <0x0ae0 0x1000>;
> +reg-names = "mdss";
> +
> +interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> +<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> +interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> +power-domains = <&dispcc MDSS_GDSC>;
> +resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> +clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +clock-names = "iface", "bus", "nrt_bus", "core";
> +
> +iommus = <&apps_smmu 0x820 0x402>;
> +
> +interrupts = ;
> +interrupt-controller;
> +#interrupt-cells = <1>;
> +
> +#address-cells = <1>;
> +#size-cells = <1>;
> +ranges;
> +
> +display-controller@ae01000 {
> +compatible = "qcom,sm8350-dpu";
> +reg = <0x0ae01000 0x8f000>,
> +  <0x0aeb 0x2008>;
> +reg-names = "mdp", "vbif";
> +
> +clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +clock-names = "bus",
> +  "nrt_bus",
> +  "iface",
> +  "lut",
> +  "core",
> +  "vsync";
> +
> +assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +assigned-clock-rates = <1920>;
> +
> +operating-points-v2 = <&mdp_opp_table>;
> +power-domains = <&rpmhpd SM8350_MMCX>;
> +
> +interrupt-parent = <&mdss>;
> +interrupts = <0>;
> +
> +ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> +reg = <0>;
> +dpu_intf1_out: endpoint {
> +remote-endpoint = <&dsi0_in>;
> +};
> +};
> +

Re: [Freedreno] [PATCH v2 01/12] dt-bindings: display: msm: Add qcom, sm8350-dpu binding

2022-11-15 Thread Rob Herring

On Tue, Nov 15, 2022 at 12:17:10PM +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for DPU device
> tree bindings
> 
> Signed-off-by: Robert Foss 
> ---
>  .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
>  1 file changed, 120 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml

Reviewed-by: Rob Herring 

But since there is a dependency, no idea if this passes validation.

[Freedreno] [PATCH] drm/msm: Enable unpin/eviction by default

2022-11-15 Thread Rob Clark

From: Rob Clark 

We've had this enabled in the CrOS kernel for a while now without seeing
issues, so let's flip the switch upstream now.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/msm_gem_shrinker.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c 
b/drivers/gpu/drm/msm/msm_gem_shrinker.c
index 8f83454ceedf..f6de1bd9d2e1 100644
--- a/drivers/gpu/drm/msm/msm_gem_shrinker.c
+++ b/drivers/gpu/drm/msm/msm_gem_shrinker.c
@@ -16,7 +16,7 @@
 /* Default disabled for now until it has some more testing on the different
  * iommu combinations that can be paired with the driver:
  */
-static bool enable_eviction = false;
+static bool enable_eviction = true;
 MODULE_PARM_DESC(enable_eviction, "Enable swappable GEM buffers");
 module_param(enable_eviction, bool, 0600);
 
-- 
2.38.1

Re: [Freedreno] [PATCH] drm/msm: Enable clamp_to_idle for 7c3

2022-11-15 Thread Doug Anderson

Hi,

On Tue, Nov 15, 2022 at 7:55 AM Rob Clark  wrote:
>
> From: Rob Clark 
>
> This was overlooked.
>
> Signed-off-by: Rob Clark 
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Douglas Anderson

[Freedreno] [PATCH] drm/msm: Enable clamp_to_idle for 7c3

2022-11-15 Thread Rob Clark

From: Rob Clark 

This was overlooked.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ebe9599a8316..e495d8e192db 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2029,13 +2029,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
adreno_gpu->base.hw_apriv = true;
 
-   /*
-* For now only clamp to idle freq for devices where this is known not
-* to cause power supply issues:
-*/
-   if (info && (info->revn == 618))
-   gpu->clamp_to_idle = true;
-
a6xx_llc_slices_init(pdev, a6xx_gpu);
 
ret = a6xx_set_supported_hw(&pdev->dev, config->rev);
@@ -2050,6 +2043,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
return ERR_PTR(ret);
}
 
+   /*
+* For now only clamp to idle freq for devices where this is known not
+* to cause power supply issues:
+*/
+   if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu))
+   gpu->clamp_to_idle = true;
+
/* Check if there is a GMU phandle and set it up */
node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
 
-- 
2.38.1

[Freedreno] [PATCH v3] drm/msm/a6xx: Fix speed-bin detection vs probe-defer

2022-11-15 Thread Rob Clark

From: Rob Clark 

If we get an error (other than -ENOENT) we need to propagate that up the
stack.  Otherwise if the nvmem driver hasn't probed yet, we'll end up
end up claiming that we support all the OPPs which is not likely to be
true (and on some generations impossible to be true, ie. if there are
conflicting OPPs).

v2: Update commit msg, gc unused label, etc
v3: Add previously missing \n's

Fixed: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
Signed-off-by: Rob Clark 
Reviewed-by: Douglas Anderson 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7fe60c65a1eb..ebe9599a8316 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1931,7 +1931,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
adreno_rev rev, u32 fuse)
 
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
-   "missing support for speed-bin: %u. Some OPPs may not 
be supported by hardware",
+   "missing support for speed-bin: %u. Some OPPs may not 
be supported by hardware\n",
fuse);
return UINT_MAX;
}
@@ -1941,7 +1941,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
adreno_rev rev, u32 fuse)
 
 static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
 {
-   u32 supp_hw = UINT_MAX;
+   u32 supp_hw;
u32 speedbin;
int ret;
 
@@ -1953,15 +1953,13 @@ static int a6xx_set_supported_hw(struct device *dev, 
struct adreno_rev rev)
if (ret == -ENOENT) {
return 0;
} else if (ret) {
-   DRM_DEV_ERROR(dev,
- "failed to read speed-bin (%d). Some OPPs may not 
be supported by hardware",
- ret);
-   goto done;
+   dev_err_probe(dev, ret,
+ "failed to read speed-bin. Some OPPs may not be 
supported by hardware\n");
+   return ret;
}
 
supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
 
-done:
ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
if (ret)
return ret;
-- 
2.38.1

Re: [Freedreno] [PATCH v2 00/12] Enable Display for SM8350

2022-11-15 Thread Krzysztof Kozlowski

On 15/11/2022 14:30, Robert Foss wrote:
> Dependencies:
> https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/
> https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/
> https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/
> 
> Branch:
> https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2
> 
> This series implements display support for SM8350 and
> enables HDMI output for the SM8350-HDK platform.
> 

I received two of these patchsets... Which one is valid? Folks also
review in both...

Best regards,
Krzysztof

Re: [Freedreno] [PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding

2022-11-15 Thread Rob Herring



On Tue, 15 Nov 2022 12:17:11 +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for MDSS device
> tree bindings
> 
> Signed-off-by: Robert Foss 
> ---
>  .../display/msm/qcom,sm8350-mdss.yaml | 240 ++
>  1 file changed, 240 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml: Unable 
to find schema file matching $id: 
http://devicetree.org/schemas/display/msm/mdss-common.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.example.dtb:
 display-subsystem@ae0: False schema does not allow {'compatible': 
['qcom,sm8350-mdss'], 'reg': [[182452224, 4096]], 'reg-names': ['mdss'], 
'interconnects': [[4294967295, 7, 0, 4294967295, 1, 0], [4294967295, 8, 0, 
4294967295, 1, 0]], 'interconnect-names': ['mdp0-mem', 'mdp1-mem'], 
'power-domains': [[4294967295, 0]], 'resets': [[4294967295, 0]], 'clocks': 
[[4294967295, 0], [4294967295, 27], [4294967295, 28], [4294967295, 32]], 
'clock-names': ['iface', 'bus', 'nrt_bus', 'core'], 'iommus': [[4294967295, 
2080, 1026]], 'interrupts': [[0, 83, 4]], 'interrupt-controller': True, 
'#interrupt-cells': [[1]], '#address-cells': [[1]], '#size-cells': [[1]], 
'ranges': True, 'display-controller@ae01000': {'compatible': 
['qcom,sm8350-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 
'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 27], [4294967295, 28], 
[4294967295, 0], [42
 94967295, 34], [4294967295, 32], [4294967295, 44]], 'clock-names': ['bus', 
'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 
44]], 'assigned-clock-rates': [[1920]], 'operating-points-v2': [[1]], 
'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': 
{'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 
'endpoint': {'remote-endpoint': [[2]], 'phandle': [[4]]}}}, 'opp-table': 
{'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-2': 
{'opp-hz': [[0], [2]], 'required-opps': [[4294967295]]}, 
'opp-3': {'opp-hz': [[0], [3]], 'required-opps': 
[[4294967295]]}, 'opp-34500': {'opp-hz': [[0], [34500]], 
'required-opps': [[4294967295]]}, 'opp-46000': {'opp-hz': [[0], 
[46000]], 'required-opps': [[4294967295]]}}}, 'dsi@ae94000': {'compatible': 
['qcom,mdss-dsi-ctrl'], 'reg': [[183058432, 1024]], 'reg-names': ['dsi_ctrl'], 
'interrupts': [[4]], 'clocks': [[4294967295, 2], [4294967295,
  5], [4294967295, 36], [4294967295, 28], [4294967295, 0], [4294967295, 27]], 
'clock-names': ['byte', 'byte_intf', 'pixel', 'core', 'iface', 'bus'], 
'assigned-clocks': [[4294967295, 3], [4294967295, 37]], 
'assigned-clock-parents': [[3, 0], [3, 1]], 'operating-points-v2': 
[[4294967295]], 'power-domains': [[4294967295, 6]], 'phys': [[3]], 'phy-names': 
['dsi'], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': 
{'reg': [[0]], 'endpoint': {'remote-endpoint': [[4]], 'phandle': [[2]]}}, 
'port@1': {'reg': [[1]], 'endpoint': {, 'phy@ae94400': {'compatible': 
['qcom,dsi-phy-5nm-8350'], 'reg': [[183059456, 512], [183059968, 640], 
[183060736, 608]], 'reg-names': ['dsi_phy', 'dsi_phy_lane', 'dsi_pll'], 
'#clock-cells': [[1]], '#phy-cells': [[0]], 'clocks': [[4294967295, 0], 
[4294967295, 0]], 'clock-names': ['iface', 'ref'], 'vdds-supply': 
[[4294967295]], 'phandle': [[3]]}, '$nodename': ['display-subsystem@ae0']}
From schema: 
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.example.dtb:
 display-subsystem@ae0: Unevaluated properties are not allowed 
('#address-cells', '#interrupt-cells', '#size-cells', 'interrupt-controller', 
'interrupts', 'power-domains', 'ranges', 'reg', 'reg-names', 'resets' were 
unexpected)
From schema: 
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [Freedreno] [PATCH v2 01/12] dt-bindings: display: msm: Add qcom, sm8350-dpu binding

2022-11-15 Thread Rob Herring



On Tue, 15 Nov 2022 12:17:10 +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for DPU device
> tree bindings
> 
> Signed-off-by: Robert Foss 
> ---
>  .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
>  1 file changed, 120 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml: Unable to 
find schema file matching $id: 
http://devicetree.org/schemas/display/msm/dpu-common.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.example.dtb:
 display-controller@ae01000: False schema does not allow {'compatible': 
['qcom,sm8350-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 
'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 27], [4294967295, 28], 
[4294967295, 0], [4294967295, 34], [4294967295, 32], [4294967295, 44]], 
'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 
'assigned-clocks': [[4294967295, 44]], 'assigned-clock-rates': [[1920]], 
'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': 
[[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': 
{'reg': [[0]], 'endpoint': {'remote-endpoint': [[4294967295]]}}}, 'opp-table': 
{'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-2': 
{'opp-hz': [[0], [2]], 'required-opps': [[4294967295]]}, 
'opp-3': {'opp-hz': [[0], [3]], 'required-opps': [[4294967295
 ]]}, 'opp-34500': {'opp-hz': [[0], [34500]], 'required-opps': 
[[4294967295]]}, 'opp-46000': {'opp-hz': [[0], [46000]], 
'required-opps': [[4294967295]]}}, '$nodename': ['display-controller@ae01000']}
From schema: 
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.example.dtb:
 display-controller@ae01000: Unevaluated properties are not allowed 
('interrupts', 'operating-points-v2', 'opp-table', 'ports', 'power-domains' 
were unexpected)
From schema: 
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

[Freedreno] [PATCH] drm/msm/hdmi: remove unnecessary NULL check

2022-11-15 Thread Dan Carpenter

This code was refactored in commit 69a88d8633ec ("drm/msm/hdmi: move
resource allocation to probe function") and now the "hdmi" pointer can't
be NULL.  Checking causes a Smatch warning:

drivers/gpu/drm/msm/hdmi/hdmi.c:141 msm_hdmi_init()
warn: variable dereferenced before check 'hdmi' (see line 119)

Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 7001fabd0977..4d3fdc806bef 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -138,8 +138,7 @@ static int msm_hdmi_init(struct hdmi *hdmi)
return 0;
 
 fail:
-   if (hdmi)
-   msm_hdmi_destroy(hdmi);
+   msm_hdmi_destroy(hdmi);
 
return ret;
 }
-- 
2.35.1

Re: [Freedreno] [PATCH v2 10/12] arm64: dts: qcom: sm8350: Add display system nodes

2022-11-15 Thread Konrad Dybcio





On 15/11/2022 14:31, Robert Foss wrote:

Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.

Signed-off-by: Robert Foss 
---
  arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++-
  1 file changed, 193 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..5c98e5cf5ad0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
   * Copyright (c) 2020, Linaro Limited
   */
  
+#include 

  #include 
  #include 
  #include 
@@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a80 {
};
};
  
+		mdss: mdss@ae0 {

+   compatible = "qcom,sm8350-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt 
SLAVE_EBI1 0>,
+   <&mmss_noc MASTER_MDP1 0 &mc_virt 
SLAVE_EBI1 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   power-domains = <&dispcc MDSS_GDSC>;
+   resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+   clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface", "bus", "nrt_bus", "core";
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   iommus = <&apps_smmu 0x820 0x402>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss_mdp: display-controller@ae01000 {
+   compatible = "qcom,sm8350-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+   <&gcc GCC_DISP_SF_AXI_CLK>,
+   <&dispcc DISP_CC_MDSS_AHB_CLK>,
+   <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+   <&dispcc DISP_CC_MDSS_MDP_CLK>,
+   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+   assigned-clocks = <&dispcc 
DISP_CC_MDSS_VSYNC_CLK>;
+   assigned-clock-rates = <1920>;
+
+   operating-points-v2 = <&mdp_opp_table>;
+   power-domains = <&rpmhpd SM8350_MMCX>;
+
+   interrupt-parent = <&mdss>;
+   interrupts = <0>;
+
+   status = "disabled";
It doesn't make sense to disable mdp separately, as mdss is essentially 
useless without it.



+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dpu_intf1_out: endpoint {
+   remote-endpoint = 
<&dsi0_in>;
+   };
+   };
+   };
+
+   mdp_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+   opp-2 {
+   opp-hz = /bits/ 64 <2>;
+   required-opps = 
<&rpmhpd_opp_low_svs>;
+   };
+
+   opp-3 {
+   opp-hz = /bits/ 64 <3>;
+   required-opps = 
<&rpmhpd_opp_svs>;
+   };
+
+   opp-34500 {
+   opp-hz = /bit

Re: [Freedreno] [PATCH v2 09/12] arm64: dts: qcom: sm8350: Use 2 interconnect cells

2022-11-15 Thread Konrad Dybcio





On 15/11/2022 14:31, Robert Foss wrote:

Use two interconnect cells in order to optionally
support a path tag.

Signed-off-by: Robert Foss 
---

Reviewed-by: Konrad Dybcio 

Konrad

  arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
  1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 805d53d91952..434f8e8b12c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
  		mc_virt: interconnect@158 {

compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
  		system_noc: interconnect@168 {

compatible = "qcom,sm8350-system-noc";
reg = <0 0x0168 0 0x1c200>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
  		aggre1_noc: interconnect@16e {

compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e 0 0x1f180>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
  		aggre2_noc: interconnect@170 {

compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x0170 0 0x33000>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
  		mmss_noc: interconnect@174 {

compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x0174 0 0x1f080>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
  		lpass_ag_noc: interconnect@3c4 {

compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c4 0 0xf080>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
  		compute_noc: interconnect@a0c{

compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c 0 0xa180>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
  
@@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {

clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
  
-			interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,

-   <&gem_noc MASTER_APPSS_PROC &config_noc 
SLAVE_IPA_CFG>;
+   interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt 
SLAVE_EBI1 0>,
+   <&gem_noc MASTER_APPSS_PROC 0 &config_noc 
SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
 "config";
  
@@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {

<&rpmhpd SM8350_MSS>;
power-domain-names = "cx", "mss";
  
-			interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;

+   interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1 
0>;
  
  			memory-region = <&pil_modem_mem>;
  
@@ -2239,7 +2239,7 @@ cdsp: remoteproc@9890 {

<&rpmhpd SM8350_MXC>;
power-domain-names = "cx", "mxc";
  
-			interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;

+   interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt 
SLAVE_EBI1 0>;
  
  			memory-region = <&pil_cdsp_mem>;
  
@@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {

dc_noc: interconnect@90c {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c 0 0x4200>;
-   #interconnect-cells = <1>;
+

Re: [Freedreno] [PATCH v2 08/12] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name

2022-11-15 Thread Konrad Dybcio





On 15/11/2022 14:31, Robert Foss wrote:

The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).

Signed-off-by: Robert Foss 
---

Reviewed-by: Konrad Dybcio 

Konrad

  arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
  1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index cbd48f248df4..805d53d91952 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2558,7 +2558,6 @@ dispcc: clock-controller@af0 {
#power-domain-cells = <1>;
  
  			power-domains = <&rpmhpd SM8350_MMCX>;

-   power-domain-names = "mmcx";
};
  
  		adsp: remoteproc@1730 {

Re: [Freedreno] [PATCH v2 06/12] drm/msm: Add support for SM8350

2022-11-15 Thread Konrad Dybcio





On 15/11/2022 14:30, Robert Foss wrote:

Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.

Signed-off-by: Robert Foss 
---
  drivers/gpu/drm/msm/msm_mdss.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index a2264fb517a1..39746b972cdd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
+   case DPU_HW_VER_700:
+   msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
+   break;

Shouldn't the second-last argument be 2 or 3 depending on DDR type?

Konrad

case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+   { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
  };

Re: [Freedreno] [PATCH v2 04/12] drm/msm/dpu: Add SM8350 to hw catalog

2022-11-15 Thread Konrad Dybcio





On 15/11/2022 14:30, Robert Foss wrote:

Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.

Signed-off-by: Robert Foss 
---
  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   1 +
  2 files changed, 197 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8f2d634f7b6b..e21ef7d912a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
 BIT(MDP_INTF3_INTR) | \
 BIT(MDP_INTF4_INTR))
  
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \

+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
  #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
  BIT(MDP_SSPP_TOP0_INTR2) | \
  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  };
  
+static const struct dpu_caps sm8350_dpu_caps = {

+   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+   .max_mixer_blendstages = 0xb,
+   .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+   .ubwc_version = DPU_HW_UBWC_VER_40,
+   .has_src_split = true,
+   .has_dim_layer = true,
+   .has_idle_pc = true,
+   .has_3d_merge = true,
+   .max_linewidth = 4096,
+   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
  static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
  };
  
+static const struct dpu_mdp_cfg sm8350_mdp[] = {

+   {
+   .name = "top_0", .id = MDP_TOP,
+   .base = 0x0, .len = 0x494,
+   .features = 0,
+   .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+   .reg_off = 0x2AC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+   .reg_off = 0x2B4, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+   .reg_off = 0x2BC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+   .reg_off = 0x2C4, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+   .reg_off = 0x2AC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+   .reg_off = 0x2BC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+   .reg_off = 0x2C4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+   .reg_off = 0x2BC, .bit_off = 20},
+   },

Let's try not adding more uppercase hex.


+};
+
  static const struct dpu_mdp_cfg sm8450_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
  };
  
+static const struct dpu_ctl_cfg sm8350_ctl[] = {

+   {
+   .name = "ctl_0", .id = CTL_0,
+   .base = 0x15000, .len = 0x1e8,
+   .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+   },
+   {
+   .name = "ctl_1", .id = CTL_1,
+   .base = 0x16000, .len = 0x1e8,
+   .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+   },
+   {
+   .name = "ctl_2", .id = CTL_2,
+   .base = 0x17000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+   },
+   {
+   .name = "ctl_3", .id = CTL_3,
+   .base = 0x18000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+   },
+   {
+   .name = "ctl_4", .id = CTL_4,
+   .base = 0x19000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+   },
+   {
+   .name = "ctl_5", .id = CTL_5,
+   .base = 0x1a000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+   },
+};
+
  static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1301,6 +1390,27 @@ static const struct dpu_pingpong_cfg sc7280_pp[]

Re: [Freedreno] [PATCH v2 03/12] drm/msm/dpu: Refactor sc7280_pp location

2022-11-15 Thread Konrad Dybcio





On 15/11/2022 14:30, Robert Foss wrote:

The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.

Signed-off-by: Robert Foss 
Reviewed-by: Dmitry Baryshkov 
---

This is already merged.

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=1a5b5372e3b0a4cc65a0cbb724b1b0859f4ac63c

Konrad

  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..8f2d634f7b6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1294,6 +1294,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
  };
  
+static const struct dpu_pingpong_cfg sc7280_pp[] = {

+   PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
  static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1352,13 +1359,6 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = 
{
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
  };
  
-static const struct dpu_pingpong_cfg sc7280_pp[] = {

-   PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
  /*
   * DSC sub blocks config
   */

[Freedreno] [PATCH v2 07/12] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names

2022-11-15 Thread Robert Foss

Add GPIO line names as described by the sm8350-hdk schematic.

Signed-off-by: Robert Foss 
---
 arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205 
 1 file changed, 205 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts 
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ &slpi {
 
 &tlmm {
gpio-reserved-ranges = <52 8>;
+
+   gpio-line-names =
+   "APPS_I2C_SDA", /* GPIO_0 */
+   "APPS_I2C_SCL",
+   "FSA_INT_N",
+   "USER_LED3_EN",
+   "SMBUS_SDA_1P8",
+   "SMBUS_SCL_1P8",
+   "2M2_3P3_EN",
+   "ALERT_DUAL_M2_N",
+   "EXP_UART_CTS",
+   "EXP_UART_RFR",
+   "EXP_UART_TX", /* GPIO_10 */
+   "EXP_UART_RX",
+   "NC",
+   "NC",
+   "RCM_MARKER1",
+   "WSA0_EN",
+   "CAM1_RESET_N",
+   "CAM0_RESET_N",
+   "DEBUG_UART_TX",
+   "DEBUG_UART_RX",
+   "TS_I2C_SDA", /* GPIO_20 */
+   "TS_I2C_SCL",
+   "TS_RESET_N",
+   "TS_INT_N",
+   "DISP0_RESET_N",
+   "DISP1_RESET_N",
+   "ETH_RESET",
+   "RCM_MARKER2",
+   "CAM_DC_MIPI_MUX_EN",
+   "CAM_DC_MIPI_MUX_SEL",
+   "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+   "AFC_PHY_TA_D_MINUS",
+   "PM8008_1_IRQ",
+   "PM8008_1_RESET_N",
+   "PM8008_2_IRQ",
+   "PM8008_2_RESET_N",
+   "CAM_DC_I3C_SDA",
+   "CAM_DC_I3C_SCL",
+   "FP_INT_N",
+   "FP_WUHB_INT_N",
+   "SMB_SPMI_DATA", /* GPIO_40 */
+   "SMB_SPMI_CLK",
+   "USB_HUB_RESET",
+   "FORCE_USB_BOOT",
+   "LRF_IRQ",
+   "NC",
+   "IMU2_INT",
+   "HDMI_3P3_EN",
+   "HDMI_RSTN",
+   "HDMI_1P2_EN",
+   "HDMI_INT", /* GPIO_50 */
+   "USB1_ID",
+   "FP_SPI_MISO",
+   "FP_SPI_MOSI",
+   "FP_SPI_CLK",
+   "FP_SPI_CS_N",
+   "NFC_ESE_SPI_MISO",
+   "NFC_ESE_SPI_MOSI",
+   "NFC_ESE_SPI_CLK",
+   "NFC_ESE_SPI_CS",
+   "NFC_I2C_SDA", /* GPIO_60 */
+   "NFC_I2C_SCLC",
+   "NFC_EN",
+   "NFC_CLK_REQ",
+   "HST_WLAN_EN",
+   "HST_BT_EN",
+   "HST_SW_CTRL",
+   "NC",
+   "HST_BT_UART_CTS",
+   "HST_BT_UART_RFR",
+   "HST_BT_UART_TX", /* GPIO_70 */
+   "HST_BT_UART_RX",
+   "CAM_DC_SPI0_MISO",
+   "CAM_DC_SPI0_MOSI",
+   "CAM_DC_SPI0_CLK",
+   "CAM_DC_SPI0_CS_N",
+   "CAM_DC_SPI1_MISO",
+   "CAM_DC_SPI1_MOSI",
+   "CAM_DC_SPI1_CLK",
+   "CAM_DC_SPI1_CS_N",
+   "HALL_INT_N", /* GPIO_80 */
+   "USB_PHY_PS",
+   "MDP_VSYNC_P",
+   "MDP_VSYNC_S",
+   "ETH_3P3_EN",
+   "RADAR_INT",
+   "NFC_DWL_REQ",
+   "SM_GPIO_87",
+   "WCD_RESET_N",
+   "ALSP_INT_N",
+   "PRESS_INT", /* GPIO_90 */
+   "SAR_INT_N",
+   "SD_CARD_DET_N",
+   "NC",
+   "PCIE0_RESET_N",
+   "PCIE0_CLK_REQ_N",
+   "PCIE0_WAKE_N",
+   "PCIE1_RESET_N",
+   "PCIE1_CLK_REQ_N",
+   "PCIE1_WAKE_N",
+   "CAM_MCLK0", /* GPIO_100 */
+   "CAM_MCLK1",
+   "CAM_MCLK2",
+   "CAM_MCLK3",
+   "CAM_MCLK4",
+   "CAM_MCLK5",
+   "CAM2_RESET_N",
+   "CCI_I2C0_SDA",
+   "CCI_I2C0_SCL",
+   "CCI_I2C1_SDA",
+   "CCI_I2C1_SCL", /* GPIO_110 */
+   "CCI_I2C2_SDA",
+   "CCI_I2C2_SCL",
+   "CCI_I2C3_SDA",
+   "CCI_I2C3_SCL",
+   "CAM5_RESET_N",
+   "CAM4_RESET_N",
+   "CAM3_RESET_N",
+   "IMU1_INT",
+   "MAG_INT_N",
+   "MI2S2_I2S_SCK", /* GPIO_120 */
+   "MI2S2_I2S_DAT0",
+   "MI2S2_I2S_WS",
+   "HIFI_DAC_I2S_MCLK",
+   "MI2S2_I2S_DAT1",
+   "HIFI_DAC_I2S_SCK",
+   "HIFI_DAC_I2S_DAT0",
+   "NC",
+   "HIFI_DAC_I2S_WS",
+   "HST_BT_WLAN_SLIMBUS_CLK",
+   "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */
+   "BT_LED_EN",
+   "WLAN_LED_EN",
+   "NC",
+

[Freedreno] [PATCH v2 10/12] arm64: dts: qcom: sm8350: Add display system nodes

2022-11-15 Thread Robert Foss

Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.

Signed-off-by: Robert Foss 
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++-
 1 file changed, 193 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..5c98e5cf5ad0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2020, Linaro Limited
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a80 {
};
};
 
+   mdss: mdss@ae0 {
+   compatible = "qcom,sm8350-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt 
SLAVE_EBI1 0>,
+   <&mmss_noc MASTER_MDP1 0 &mc_virt 
SLAVE_EBI1 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   power-domains = <&dispcc MDSS_GDSC>;
+   resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+   clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface", "bus", "nrt_bus", "core";
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   iommus = <&apps_smmu 0x820 0x402>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss_mdp: display-controller@ae01000 {
+   compatible = "qcom,sm8350-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+   <&gcc GCC_DISP_SF_AXI_CLK>,
+   <&dispcc DISP_CC_MDSS_AHB_CLK>,
+   <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+   <&dispcc DISP_CC_MDSS_MDP_CLK>,
+   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+   assigned-clocks = <&dispcc 
DISP_CC_MDSS_VSYNC_CLK>;
+   assigned-clock-rates = <1920>;
+
+   operating-points-v2 = <&mdp_opp_table>;
+   power-domains = <&rpmhpd SM8350_MMCX>;
+
+   interrupt-parent = <&mdss>;
+   interrupts = <0>;
+
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dpu_intf1_out: endpoint {
+   remote-endpoint = 
<&dsi0_in>;
+   };
+   };
+   };
+
+   mdp_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+   opp-2 {
+   opp-hz = /bits/ 64 <2>;
+   required-opps = 
<&rpmhpd_opp_low_svs>;
+   };
+
+   opp-3 {
+   opp-hz = /bits/ 64 <3>;
+   required-opps = 
<&rpmhpd_opp_svs>;
+   };
+
+   opp-34500 {
+   opp-hz = /bits/ 64 <34500>;
+   required-opps = 
<&rpmhpd_opp_svs_l1>;
+

[Freedreno] [PATCH v2 09/12] arm64: dts: qcom: sm8350: Use 2 interconnect cells

2022-11-15 Thread Robert Foss

Use two interconnect cells in order to optionally
support a path tag.

Signed-off-by: Robert Foss 
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 805d53d91952..434f8e8b12c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
mc_virt: interconnect@158 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
system_noc: interconnect@168 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x0168 0 0x1c200>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
aggre1_noc: interconnect@16e {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e 0 0x1f180>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
aggre2_noc: interconnect@170 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x0170 0 0x33000>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
mmss_noc: interconnect@174 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x0174 0 0x1f080>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
lpass_ag_noc: interconnect@3c4 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c4 0 0xf080>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
compute_noc: interconnect@a0c{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c 0 0xa180>;
-   #interconnect-cells = <1>;
+   #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
 
@@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
 
-   interconnects = <&aggre2_noc MASTER_IPA &mc_virt 
SLAVE_EBI1>,
-   <&gem_noc MASTER_APPSS_PROC &config_noc 
SLAVE_IPA_CFG>;
+   interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt 
SLAVE_EBI1 0>,
+   <&gem_noc MASTER_APPSS_PROC 0 
&config_noc SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
 "config";
 
@@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {
<&rpmhpd SM8350_MSS>;
power-domain-names = "cx", "mss";
 
-   interconnects = <&mc_virt MASTER_LLCC &mc_virt 
SLAVE_EBI1>;
+   interconnects = <&mc_virt MASTER_LLCC &mc_virt 
SLAVE_EBI1 0>;
 
memory-region = <&pil_modem_mem>;
 
@@ -2239,7 +2239,7 @@ cdsp: remoteproc@9890 {
<&rpmhpd SM8350_MXC>;
power-domain-names = "cx", "mxc";
 
-   interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt 
SLAVE_EBI1>;
+   interconnects = <&compute_noc MASTER_CDSP_PROC 0 
&mc_virt SLAVE_EBI1 0>;
 
memory-region = <&pil_cdsp_mem>;
 
@@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {
dc_noc: interconnect@90c {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c 0 0x4200>;
-

[Freedreno] [PATCH v2 12/12] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge

2022-11-15 Thread Robert Foss

The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.

In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.

Signed-off-by: Robert Foss 
---
 arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105 
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts 
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 39462c659c58..3aa4ca8271e5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
 
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con: endpoint {
+   remote-endpoint = <<9611_out>;
+   };
+   };
+   };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+   lt9611_1v2: lt9611-1v2-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "LT9611_1V2";
+
+   vin-supply = <&vph_pwr>;
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-boot-on;
+   };
+
+   lt9611_3v3: lt9611-3v3-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "LT9611_3V3";
+
+   vin-supply = <&vreg_bob>;
+   gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   enable-active-high;
+   regulator-boot-on;
+   regulator-always-on;
+   };
 };
 
 &adsp {
@@ -220,6 +256,15 @@ &dispcc {
 &dsi0 {
vdda-supply = <&vreg_l6b_1p2>;
status = "okay";
+
+   ports {
+   port@1 {
+   endpoint {
+   remote-endpoint = <<9611_a>;
+   data-lanes = <0 1 2 3>;
+   };
+   };
+   };
 };
 
 &dsi0_phy  {
@@ -231,6 +276,46 @@ &gpi_dma1 {
status = "okay";
 };
 
+&i2c15 {
+   clock-frequency = <40>;
+   status = "okay";
+
+   lt9611_codec: hdmi-bridge@2b {
+   compatible = "lontium,lt9611uxc";
+   reg = <0x2b>;
+
+   interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+   vdd-supply = <<9611_1v2>;
+   vcc-supply = <<9611_3v3>;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <<9611_state>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+
+   lt9611_a: endpoint {
+   remote-endpoint = <&dsi0_out>;
+   };
+   };
+
+   port@2 {
+   reg = <2>;
+
+   lt9611_out: endpoint {
+   remote-endpoint = <&hdmi_con>;
+   };
+   };
+   };
+   };
+};
+
 &mdss {
status = "okay";
 };
@@ -248,6 +333,10 @@ &qupv3_id_0 {
status = "okay";
 };
 
+&qupv3_id_2 {
+   status = "okay";
+};
+
 &slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+   lt9611_state: lt9611-state {
+   lt9611_rst_pin {
+   pins = "gpio48";
+   function = "normal";
+
+   output-high;
+   input-disable;
+   };
+
+   lt9611_irq_pin {
+   pins = "gpio50";
+   function = "gpio";
+   bias-disable;
+   };
+   };
 };
-- 
2.34.1

[Freedreno] [PATCH v2 08/12] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name

2022-11-15 Thread Robert Foss

The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).

Signed-off-by: Robert Foss 
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index cbd48f248df4..805d53d91952 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2558,7 +2558,6 @@ dispcc: clock-controller@af0 {
#power-domain-cells = <1>;
 
power-domains = <&rpmhpd SM8350_MMCX>;
-   power-domain-names = "mmcx";
};
 
adsp: remoteproc@1730 {
-- 
2.34.1

[Freedreno] [PATCH v2 11/12] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes

2022-11-15 Thread Robert Foss

Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.

Signed-off-by: Robert Foss 
---
 arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts 
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..39462c659c58 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
 };
 
+&dispcc {
+   status = "okay";
+};
+
+&dsi0 {
+   vdda-supply = <&vreg_l6b_1p2>;
+   status = "okay";
+};
+
+&dsi0_phy  {
+   vdds-supply = <&vreg_l5b_0p88>;
+   status = "okay";
+};
+
 &gpi_dma1 {
status = "okay";
 };
 
+&mdss {
+   status = "okay";
+};
+
+&mdss_mdp {
+   status = "okay";
+};
+
 &mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
-- 
2.34.1

[Freedreno] [PATCH v2 06/12] drm/msm: Add support for SM8350

2022-11-15 Thread Robert Foss

Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.

Signed-off-by: Robert Foss 
---
 drivers/gpu/drm/msm/msm_mdss.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index a2264fb517a1..39746b972cdd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
+   case DPU_HW_VER_700:
+   msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
+   break;
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+   { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
 };
-- 
2.34.1

[Freedreno] [PATCH v2 04/12] drm/msm/dpu: Add SM8350 to hw catalog

2022-11-15 Thread Robert Foss

Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.

Signed-off-by: Robert Foss 
---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   1 +
 2 files changed, 197 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8f2d634f7b6b..e21ef7d912a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
 BIT(MDP_INTF3_INTR) | \
 BIT(MDP_INTF4_INTR))
 
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
 #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
  BIT(MDP_SSPP_TOP0_INTR2) | \
  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };
 
+static const struct dpu_caps sm8350_dpu_caps = {
+   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+   .max_mixer_blendstages = 0xb,
+   .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+   .ubwc_version = DPU_HW_UBWC_VER_40,
+   .has_src_split = true,
+   .has_dim_layer = true,
+   .has_idle_pc = true,
+   .has_3d_merge = true,
+   .max_linewidth = 4096,
+   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
 static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
 };
 
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+   {
+   .name = "top_0", .id = MDP_TOP,
+   .base = 0x0, .len = 0x494,
+   .features = 0,
+   .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+   .reg_off = 0x2AC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+   .reg_off = 0x2B4, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+   .reg_off = 0x2BC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+   .reg_off = 0x2C4, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+   .reg_off = 0x2AC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+   .reg_off = 0x2BC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+   .reg_off = 0x2C4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+   .reg_off = 0x2BC, .bit_off = 20},
+   },
+};
+
 static const struct dpu_mdp_cfg sm8450_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
 };
 
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+   {
+   .name = "ctl_0", .id = CTL_0,
+   .base = 0x15000, .len = 0x1e8,
+   .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+   },
+   {
+   .name = "ctl_1", .id = CTL_1,
+   .base = 0x16000, .len = 0x1e8,
+   .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+   },
+   {
+   .name = "ctl_2", .id = CTL_2,
+   .base = 0x17000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+   },
+   {
+   .name = "ctl_3", .id = CTL_3,
+   .base = 0x18000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+   },
+   {
+   .name = "ctl_4", .id = CTL_4,
+   .base = 0x19000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+   },
+   {
+   .name = "ctl_5", .id = CTL_5,
+   .base = 0x1a000, .len = 0x1e8,
+   .features = CTL_SC7280_MASK,
+   .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+   },
+};
+
 static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1301,6 +1390,27 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
 };
 
+static const stru

[Freedreno] [PATCH v2 05/12] drm/msm/dpu: Add support for SM8350

2022-11-15 Thread Robert Foss

Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.

Signed-off-by: Robert Foss 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9827914dc096..6048bfae0824 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+   { .compatible = "qcom,sm8350-dpu", },
{ .compatible = "qcom,sm8450-dpu", },
{}
 };
-- 
2.34.1

[Freedreno] [PATCH v2 03/12] drm/msm/dpu: Refactor sc7280_pp location

2022-11-15 Thread Robert Foss

The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.

Signed-off-by: Robert Foss 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..8f2d634f7b6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1294,6 +1294,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
 };
 
+static const struct dpu_pingpong_cfg sc7280_pp[] = {
+   PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
 static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1352,13 +1359,6 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = 
{
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
 };
 
-static const struct dpu_pingpong_cfg sc7280_pp[] = {
-   PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
 /*
  * DSC sub blocks config
  */
-- 
2.34.1

[Freedreno] [PATCH v2 00/12] Enable Display for SM8350

2022-11-15 Thread Robert Foss

Dependencies:
https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/
https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/
https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/

Branch:
https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2

This series implements display support for SM8350 and
enables HDMI output for the SM8350-HDK platform.


Changes from v1:
 - Added R-b tags from v1
 - Added qcom,sm8350-dpu binding patch
 - Added qcom,sm8350-mdss binding patch
 - Corrected sm8350.dtsi according to new dpu/mdss bindings
 - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator
 - Bjorn: Moved lt9611 pinctl pins into a common node
 - Bjorn/Krzysztof: Moved status property to last in node
 - Krzysztof: Changed hdmi-out to hdmi-connector
 - Krzysztof: Fixed regulator node name
 - Krzysztof: Changed &mdss to status=disabled as default
 - Krzysztof: Changed &mdss_mdp node name to display-controller
 - Krzysztof: Fixed opp-table node name
 - Krzysztof: Fixed phy node name
 - Dmitry: Split commit containing dpu & mdss compatibles string
 - Dmitry: Added msm_mdss_enable case
 - Dmitry: Fixed dpu ctl features
 


Robert Foss (12):
  dt-bindings: display: msm: Add qcom,sm8350-dpu binding
  dt-bindings: display: msm: Add qcom,sm8350-mdss binding
  drm/msm/dpu: Refactor sc7280_pp location
  drm/msm/dpu: Add SM8350 to hw catalog
  drm/msm/dpu: Add support for SM8350
  drm/msm: Add support for SM8350
  arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
  arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
  arm64: dts: qcom: sm8350: Use 2 interconnect cells
  arm64: dts: qcom: sm8350: Add display system nodes
  arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
  arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge

 .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++
 .../display/msm/qcom,sm8350-mdss.yaml | 240 +
 arch/arm64/boot/dts/qcom/sm8350-hdk.dts   | 332 ++
 arch/arm64/boot/dts/qcom/sm8350.dtsi  | 226 +++-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 210 ++-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   1 +
 drivers/gpu/drm/msm/msm_mdss.c|   4 +
 8 files changed, 1108 insertions(+), 26 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

-- 
2.34.1

[Freedreno] [PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding

2022-11-15 Thread Robert Foss

Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings

Signed-off-by: Robert Foss 
---
 .../display/msm/qcom,sm8350-mdss.yaml | 240 ++
 1 file changed, 240 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

diff --git 
a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml 
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index ..9a0694853576
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+  - Robert Foss 
+
+description:
+  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device 
tree
+  bindings of MDSS are mentioned for SM8350 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+items:
+  - const: qcom,sm8350-mdss
+
+  clocks:
+items:
+  - description: Display AHB clock from gcc
+  - description: Display hf axi clock
+  - description: Display sf axi clock
+  - description: Display core clock
+
+  clock-names:
+items:
+  - const: iface
+  - const: bus
+  - const: nrt_bus
+  - const: core
+
+  iommus:
+maxItems: 1
+
+  interconnects:
+maxItems: 2
+
+  interconnect-names:
+maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,sm8350-dpu
+
+  "^dsi@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+display-subsystem@ae0 {
+compatible = "qcom,sm8350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem";
+
+power-domains = <&dispcc MDSS_GDSC>;
+resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "nrt_bus", "core";
+
+iommus = <&apps_smmu 0x820 0x402>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+  <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+  "nrt_bus",
+  "iface",
+  "lut",
+  "core",
+  "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+

[Freedreno] [PATCH v2 01/12] dt-bindings: display: msm: Add qcom, sm8350-dpu binding

2022-11-15 Thread Robert Foss

Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings

Signed-off-by: Robert Foss 
---
 .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
 1 file changed, 120 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml 
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index ..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+  - Robert Foss 
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+  compatible:
+const: qcom,sm8350-dpu
+
+  reg:
+items:
+  - description: Address offset and size for mdp register set
+  - description: Address offset and size for vbif register set
+
+  reg-names:
+items:
+  - const: mdp
+  - const: vbif
+
+  clocks:
+items:
+  - description: Display hf axi clock
+  - description: Display sf axi clock
+  - description: Display ahb clock
+  - description: Display lut clock
+  - description: Display core clock
+  - description: Display vsync clock
+
+  clock-names:
+items:
+  - const: bus
+  - const: nrt_bus
+  - const: iface
+  - const: lut
+  - const: core
+  - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+#include 
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+  <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+  "nrt_bus",
+  "iface",
+  "lut",
+  "core",
+  "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz = /bits/ 64 <46000>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+};
+};
+...
-- 
2.34.1

Re: [Freedreno] [PATCH v2 00/12] Enable Display for SM8350

2022-11-15 Thread Konrad Dybcio





On 15/11/2022 12:17, Robert Foss wrote:

Dependencies:
https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/
https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/
https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/


Looks like only patches 0-3 reached linux-arm-msm and freedreno lists?

Konrad

Branch:
https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2

This series implements display support for SM8350 and
enables HDMI output for the SM8350-HDK platform.

Changes from v1:
  - Added R-b tags from v1
  - Added qcom,sm8350-dpu binding patch
  - Added qcom,sm8350-mdss binding patch
  - Corrected sm8350.dtsi according to new dpu/mdss bindings
  - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator
  - Bjorn: Moved lt9611 pinctl pins into a common node
  - Bjorn/Krzysztof: Moved status property to last in node
  - Krzysztof: Changed hdmi-out to hdmi-connector
  - Krzysztof: Fixed regulator node name
  - Krzysztof: Changed &mdss to status=disabled as default
  - Krzysztof: Changed &mdss_mdp node name to display-controller
  - Krzysztof: Fixed opp-table node name
  - Krzysztof: Fixed phy node name
  - Dmitry: Split commit containing dpu & mdss compatibles string
  - Dmitry: Added msm_mdss_enable case
  - Dmitry: Fixed dpu ctl features
  


Robert Foss (12):
   dt-bindings: display: msm: Add qcom,sm8350-dpu binding
   dt-bindings: display: msm: Add qcom,sm8350-mdss binding
   drm/msm/dpu: Refactor sc7280_pp location
   drm/msm/dpu: Add SM8350 to hw catalog
   drm/msm/dpu: Add support for SM8350
   drm/msm: Add support for SM8350
   arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
   arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
   arm64: dts: qcom: sm8350: Use 2 interconnect cells
   arm64: dts: qcom: sm8350: Add display system nodes
   arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
   arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge

  .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++
  .../display/msm/qcom,sm8350-mdss.yaml | 240 +
  arch/arm64/boot/dts/qcom/sm8350-hdk.dts   | 332 ++
  arch/arm64/boot/dts/qcom/sm8350.dtsi  | 226 +++-
  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 210 ++-
  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   1 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   1 +
  drivers/gpu/drm/msm/msm_mdss.c|   4 +
  8 files changed, 1108 insertions(+), 26 deletions(-)
  create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
  create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

[Freedreno] [PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding

2022-11-15 Thread Robert Foss

Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings

Signed-off-by: Robert Foss 
---
 .../display/msm/qcom,sm8350-mdss.yaml | 240 ++
 1 file changed, 240 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

diff --git 
a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml 
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index ..9a0694853576
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+  - Robert Foss 
+
+description:
+  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device 
tree
+  bindings of MDSS are mentioned for SM8350 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+items:
+  - const: qcom,sm8350-mdss
+
+  clocks:
+items:
+  - description: Display AHB clock from gcc
+  - description: Display hf axi clock
+  - description: Display sf axi clock
+  - description: Display core clock
+
+  clock-names:
+items:
+  - const: iface
+  - const: bus
+  - const: nrt_bus
+  - const: core
+
+  iommus:
+maxItems: 1
+
+  interconnects:
+maxItems: 2
+
+  interconnect-names:
+maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,sm8350-dpu
+
+  "^dsi@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+display-subsystem@ae0 {
+compatible = "qcom,sm8350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem";
+
+power-domains = <&dispcc MDSS_GDSC>;
+resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "nrt_bus", "core";
+
+iommus = <&apps_smmu 0x820 0x402>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+  <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+  "nrt_bus",
+  "iface",
+  "lut",
+  "core",
+  "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+

[Freedreno] [PATCH v2 03/12] drm/msm/dpu: Refactor sc7280_pp location

2022-11-15 Thread Robert Foss

The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.

Signed-off-by: Robert Foss 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..8f2d634f7b6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1294,6 +1294,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
 };
 
+static const struct dpu_pingpong_cfg sc7280_pp[] = {
+   PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+   PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
 static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1352,13 +1359,6 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = 
{
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
 };
 
-static const struct dpu_pingpong_cfg sc7280_pp[] = {
-   PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
-   PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
 /*
  * DSC sub blocks config
  */
-- 
2.34.1

[Freedreno] [PATCH v2 01/12] dt-bindings: display: msm: Add qcom, sm8350-dpu binding

2022-11-15 Thread Robert Foss

Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings

Signed-off-by: Robert Foss 
---
 .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
 1 file changed, 120 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml 
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index ..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+  - Robert Foss 
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+  compatible:
+const: qcom,sm8350-dpu
+
+  reg:
+items:
+  - description: Address offset and size for mdp register set
+  - description: Address offset and size for vbif register set
+
+  reg-names:
+items:
+  - const: mdp
+  - const: vbif
+
+  clocks:
+items:
+  - description: Display hf axi clock
+  - description: Display sf axi clock
+  - description: Display ahb clock
+  - description: Display lut clock
+  - description: Display core clock
+  - description: Display vsync clock
+
+  clock-names:
+items:
+  - const: bus
+  - const: nrt_bus
+  - const: iface
+  - const: lut
+  - const: core
+  - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+#include 
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+  <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+  "nrt_bus",
+  "iface",
+  "lut",
+  "core",
+  "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz = /bits/ 64 <46000>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+};
+};
+...
-- 
2.34.1

[Freedreno] [PATCH v2 00/12] Enable Display for SM8350

2022-11-15 Thread Robert Foss

Dependencies:
https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/
https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/
https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/

Branch:
https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2

This series implements display support for SM8350 and
enables HDMI output for the SM8350-HDK platform.

Changes from v1:
 - Added R-b tags from v1
 - Added qcom,sm8350-dpu binding patch
 - Added qcom,sm8350-mdss binding patch
 - Corrected sm8350.dtsi according to new dpu/mdss bindings
 - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator
 - Bjorn: Moved lt9611 pinctl pins into a common node
 - Bjorn/Krzysztof: Moved status property to last in node
 - Krzysztof: Changed hdmi-out to hdmi-connector
 - Krzysztof: Fixed regulator node name
 - Krzysztof: Changed &mdss to status=disabled as default
 - Krzysztof: Changed &mdss_mdp node name to display-controller
 - Krzysztof: Fixed opp-table node name
 - Krzysztof: Fixed phy node name
 - Dmitry: Split commit containing dpu & mdss compatibles string
 - Dmitry: Added msm_mdss_enable case
 - Dmitry: Fixed dpu ctl features
 

Robert Foss (12):
  dt-bindings: display: msm: Add qcom,sm8350-dpu binding
  dt-bindings: display: msm: Add qcom,sm8350-mdss binding
  drm/msm/dpu: Refactor sc7280_pp location
  drm/msm/dpu: Add SM8350 to hw catalog
  drm/msm/dpu: Add support for SM8350
  drm/msm: Add support for SM8350
  arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
  arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
  arm64: dts: qcom: sm8350: Use 2 interconnect cells
  arm64: dts: qcom: sm8350: Add display system nodes
  arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
  arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge

 .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++
 .../display/msm/qcom,sm8350-mdss.yaml | 240 +
 arch/arm64/boot/dts/qcom/sm8350-hdk.dts   | 332 ++
 arch/arm64/boot/dts/qcom/sm8350.dtsi  | 226 +++-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 210 ++-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   1 +
 drivers/gpu/drm/msm/msm_mdss.c|   4 +
 8 files changed, 1108 insertions(+), 26 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

-- 
2.34.1

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