[Freedreno] [PATCH v7 10/11] arm64: dts: qcom: rename mdp nodes to display-controller
Follow the schema change and rename mdp nodes to generic name
'display-controller'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index b688df272207..027eb99340e2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -988,7 +988,7 @@ mdss: display-subsystem@1a0 {
#size-cells = <1>;
ranges;
- mdp: mdp@1a01000 {
+ mdp: display-controller@1a01000 {
compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi
b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 9d4b785409b1..4e17bc9f8167 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -699,7 +699,7 @@ mdss: display-subsystem@1a0 {
status = "disabled";
- mdp: mdp@1a01000 {
+ mdp: display-controller@1a01000 {
compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
reg = <0x1a01000 0x89000>;
reg-names = "mdp_phys";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 97979f7a8050..5321b217c1de 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -934,7 +934,7 @@ mdss: display-subsystem@90 {
status = "disabled";
- mdp: mdp@901000 {
+ mdp: display-controller@901000 {
compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
reg = <0x00901000 0x9>;
reg-names = "mdp_phys";
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi
b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 2ca2f75f2aa7..5827cda270a0 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1497,7 +1497,7 @@ mdss: display-subsystem@c90 {
ranges;
status = "disabled";
- mdp: mdp@c901000 {
+ mdp: display-controller@c901000 {
compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
reg = <0x0c901000 0x89000>;
reg-names = "mdp_phys";
--
2.39.0
[Freedreno] [PATCH v7 11/11] ARM: dts: qcom: rename mdp nodes to display-controller
Follow the schema change and rename mdp nodes to generic name
'display-controller'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +-
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index e045edeb5736..95705703fe8f 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1493,7 +1493,7 @@ hdmi_phy: phy@4a00400 {
status = "disabled";
};
- mdp: mdp@510 {
+ mdp: display-controller@510 {
compatible = "qcom,mdp4";
reg = <0x0510 0xf>;
interrupts = ;
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index ec0c526d0483..2879b29a109c 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1579,7 +1579,7 @@ mdss: display-subsystem@fd90 {
#size-cells = <1>;
ranges;
- mdp: mdp@fd90 {
+ mdp: display-controller@fd90 {
compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
reg = <0xfd900100 0x22000>;
reg-names = "mdp_phys";
--
2.39.0
[Freedreno] [PATCH v7 08/11] arm64: dts: qcom: rename mdss nodes to display-subsystem
Follow the schema change and rename mdss nodes to generic name
'display-subsystem'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 68cdf255c474..b688df272207 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -963,7 +963,7 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x3>;
};
- mdss: mdss@1a0 {
+ mdss: display-subsystem@1a0 {
status = "disabled";
compatible = "qcom,mdss";
reg = <0x01a0 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi
b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 068eac8dc97f..9d4b785409b1 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -670,7 +670,7 @@ tcsr_phy_clk_scheme_sel: syscon@193f044 {
reg = <0x193f044 0x4>;
};
- mdss: mdss@1a0 {
+ mdss: display-subsystem@1a0 {
compatible = "qcom,mdss";
reg = <0x1a0 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c05d2a85247e..97979f7a8050 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -908,7 +908,7 @@ mmcc: clock-controller@8c {
<82500>;
};
- mdss: mdss@90 {
+ mdss: display-subsystem@90 {
compatible = "qcom,mdss";
reg = <0x0090 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 3a0bd0fb56b4..b2ea615e7df1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2922,7 +2922,7 @@ camcc: clock-controller@ad0 {
#power-domain-cells = <1>;
};
- mdss: mdss@ae0 {
+ mdss: display-subsystem@ae0 {
compatible = "qcom,sc7180-mdss";
reg = <0 0x0ae0 0 0x1000>;
reg-names = "mdss";
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi
b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index d1542335be74..2ca2f75f2aa7 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1470,7 +1470,7 @@ opp-26250 {
};
};
- mdss: mdss@c90 {
+ mdss: display-subsystem@c90 {
compatible = "qcom,mdss";
reg = <0x0c90 0x1000>,
<0x0c9b 0x1040>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0f1cb2c8addd..72c5ec84d3ef 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4414,7 +4414,7 @@ clock_camcc: clock-controller@ad0 {
clock-names = "bi_tcxo";
};
- mdss: mdss@ae0 {
+ mdss: display-subsystem@ae0 {
compatible = "qcom,sdm845-mdss";
reg = <0 0x0ae0 0 0x1000>;
reg-names = "mdss";
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a4ce9cf14d9c..dabed46f04a7 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3970,7 +3970,7 @@ camcc: clock-controller@ad0 {
#power-domain-cells = <1>;
};
- mdss: mdss@ae0 {
+ mdss: display-subsystem@ae0 {
compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae0 0 0x1000>;
reg-names = "mdss";
--
2.39.0
[Freedreno] [PATCH v7 09/11] ARM: dts: qcom-msm8974: rename mdss node to display-subsystem
Follow the schema change and rename mdss node to generic name
'display-subsystem'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index ced62937165a..ec0c526d0483 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1556,7 +1556,7 @@ mmcc: clock-controller@fd8c {
"edp_vco_div";
};
- mdss: mdss@fd90 {
+ mdss: display-subsystem@fd90 {
compatible = "qcom,mdss";
reg = <0xfd90 0x100>, <0xfd924000 0x1000>;
reg-names = "mdss_phys", "vbif_phys";
--
2.39.0
[Freedreno] [PATCH v7 07/11] arm64: dts: qcom: add SoC specific compat strings to mdp5 nodes
Add SoC-specific compat string to the MDP5 device nodes to ease
distinguishing between various platforms.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 ++
4 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index cf248e10660b..68cdf255c474 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -989,7 +989,7 @@ mdss: mdss@1a0 {
ranges;
mdp: mdp@1a01000 {
- compatible = "qcom,mdp5";
+ compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index b8cf5c461d98..c05d2a85247e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -935,7 +935,7 @@ mdss: mdss@90 {
status = "disabled";
mdp: mdp@901000 {
- compatible = "qcom,mdp5";
+ compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
reg = <0x00901000 0x9>;
reg-names = "mdp_phys";
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi
b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index e08ead06d4d3..d1542335be74 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1498,7 +1498,7 @@ mdss: mdss@c90 {
status = "disabled";
mdp: mdp@c901000 {
- compatible = "qcom,mdp5";
+ compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
reg = <0x0c901000 0x89000>;
reg-names = "mdp_phys";
diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi
b/arch/arm64/boot/dts/qcom/sdm660.dtsi
index d6908aa4c6e1..f0f27fc12c18 100644
--- a/arch/arm64/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -142,6 +142,8 @@ {
};
{
+ compatible = "qcom,sdm660-mdp5", "qcom,mdp5";
+
ports {
port@1 {
reg = <1>;
--
2.39.0
[Freedreno] [PATCH v7 05/11] dt-bindings: display/msm: rename mdp nodes to display-controller
Follow the 'generic names' rule and rename mdp nodes to
display-controller.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dpu-common.yaml | 8
.../devicetree/bindings/display/msm/qcom,mdp5.yaml| 3 +++
.../devicetree/bindings/display/msm/qcom,mdss.yaml| 6 +++---
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml
index 870158bb2aa0..3f953aa5e694 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml
@@ -13,7 +13,15 @@ maintainers:
description: |
Common properties for QCom DPU display controller.
+# Do not select this by default, otherwise it is also selected for all
+# display-controller@ nodes
+select:
+ false
+
properties:
+ $nodename:
+pattern: '^display-controller@[0-9a-f]+$'
+
interrupts:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
index cb7bf48c3a58..ef461ad6ce4a 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
@@ -33,6 +33,9 @@ properties:
- qcom,sdm660-mdp5
- const: qcom,mdp5
+ $nodename:
+pattern: '^display-controller@[0-9a-f]+$'
+
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
index 7dceb2c54edd..ef89ffe9b578 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
@@ -99,7 +99,7 @@ required:
- ranges
patternProperties:
- "^mdp@[1-9a-f][0-9a-f]*$":
+ "^display-controller@[1-9a-f][0-9a-f]*$":
type: object
properties:
compatible:
@@ -171,8 +171,8 @@ examples:
#size-cells = <1>;
ranges;
-mdp@1a01000 {
-compatible = "qcom,mdp5";
+display-controller@1a01000 {
+compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
--
2.39.0
[Freedreno] [PATCH v7 04/11] dt-bindings: display/msm: rename mdss nodes to display-subsystem
Follow the 'generic names' rule and rename mdss nodes to
display-subsystem.
Signed-off-by: Dmitry Baryshkov
---
Note, this patch might generate warnings in qcom,sm6115-mdss and
qcom,qcm2290-mdss examples, but they have been fixed by the commit
e5266ca38294 ("dt-bindings: display: msm: Rename mdss node name in
example")
See https://gitlab.freedesktop.org/drm/msm/-/commit/e5266ca38294
---
.../devicetree/bindings/display/msm/mdss-common.yaml | 8
.../devicetree/bindings/display/msm/qcom,mdss.yaml| 5 -
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
index 59f17ac898aa..ccd7d6417523 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
@@ -15,7 +15,15 @@ description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc.
+# Do not select this by default, otherwise it is also selected for qcom,mdss
+# devices.
+select:
+ false
+
properties:
+ $nodename:
+pattern: "^display-subsystem@[0-9a-f]+$"
+
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
index 461cb13c7092..7dceb2c54edd 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
@@ -15,6 +15,9 @@ description:
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
properties:
+ $nodename:
+pattern: "^display-subsystem@[0-9a-f]+$"
+
compatible:
enum:
- qcom,mdss
@@ -144,7 +147,7 @@ examples:
- |
#include
#include
-mdss@1a0 {
+display-subsystem@1a0 {
compatible = "qcom,mdss";
reg = <0x1a0 0x1000>,
<0x1ac8000 0x3000>;
--
2.39.0
[Freedreno] [PATCH v7 06/11] ARM: dts: qcom-msm8974: add SoC specific compat string to mdp5 node
Add SoC-specific compat string to the MDP5 device node to ease
distinguishing between various platforms.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 44c4d8d8f51f..ced62937165a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1580,7 +1580,7 @@ mdss: mdss@fd90 {
ranges;
mdp: mdp@fd90 {
- compatible = "qcom,mdp5";
+ compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
reg = <0xfd900100 0x22000>;
reg-names = "mdp_phys";
--
2.39.0
[Freedreno] [PATCH v7 03/11] dt-bindings: display/msm: add core clock to the mdss bindings
Add (optional) core clock to the mdss bindings to let the MDSS driver access hardware registers before MDP driver probes. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/qcom,mdss.yaml | 32 +-- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index d09842db3825..461cb13c7092 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -44,18 +44,30 @@ properties: The MDSS power domain provided by GCC clocks: -minItems: 1 -items: - - description: Display abh clock - - description: Display axi clock - - description: Display vsync clock +oneOf: + - minItems: 3 +items: + - description: Display abh clock + - description: Display axi clock + - description: Display vsync clock + - description: Display core clock + - minItems: 1 +items: + - description: Display abh clock + - description: Display core clock clock-names: -minItems: 1 -items: - - const: iface - - const: bus - - const: vsync +oneOf: + - minItems: 3 +items: + - const: iface + - const: bus + - const: vsync + - const: core + - minItems: 1 +items: + - const: iface + - const: core "#address-cells": const: 1 -- 2.39.0
[Freedreno] [PATCH v7 02/11] dt-bindings: display/msm: add SoC-specific compats to qcom, mdp5.yaml
Add platform-specific compatible entries to the qcom,mdp5.yaml to allow distinguishing between various platforms. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/qcom,mdp5.yaml | 17 - .../bindings/display/msm/qcom,mdss.yaml | 3 ++- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index 5e3cd7abf046..cb7bf48c3a58 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -16,7 +16,22 @@ maintainers: properties: compatible: -const: qcom,mdp5 +oneOf: + - const: qcom,mdp5 +deprecated: true + - items: + - enum: + - qcom,apq8084-mdp5 + - qcom,msm8916-mdp5 + - qcom,msm8917-mdp5 + - qcom,msm8953-mdp5 + - qcom,msm8974-mdp5 + - qcom,msm8976-mdp5 + - qcom,msm8994-mdp5 + - qcom,msm8996-mdp5 + - qcom,sdm630-mdp5 + - qcom,sdm660-mdp5 + - const: qcom,mdp5 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index 7479cd96fdec..d09842db3825 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -88,7 +88,8 @@ patternProperties: type: object properties: compatible: -const: qcom,mdp5 +contains: + const: qcom,mdp5 "^dsi@[1-9a-f][0-9a-f]*$": type: object -- 2.39.0
[Freedreno] [PATCH v7 01/11] dt-bindings: display/msm: convert MDP5 schema to YAML format
Convert the mdp5.txt into the yaml format. Changes to the existing (txt) schema:
- MSM8996 has additional "iommu" clock, define it separately
- Add new properties used on some of platforms:
- interconnects, interconnect-names
- iommus
- power-domains
- operating-points-v2, opp-table
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/mdp5.txt | 132 -
.../bindings/display/msm/qcom,mdp5.yaml | 138 ++
2 files changed, 138 insertions(+), 132 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/mdp5.txt
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt
b/Documentation/devicetree/bindings/display/msm/mdp5.txt
deleted file mode 100644
index 65d03c58dee6..
--- a/Documentation/devicetree/bindings/display/msm/mdp5.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-Qualcomm adreno/snapdragon MDP5 display controller
-
-Description:
-
-This is the bindings documentation for the MDP5 display
-controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
-
-MDP5:
-Required properties:
-- compatible:
- * "qcom,mdp5" - MDP5
-- reg: Physical base address and length of the controller's registers.
-- reg-names: The names of register regions. The following regions are required:
- * "mdp_phys"
-- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
-- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required.
-- * "bus"
-- * "iface"
-- * "core"
-- * "vsync"
-- ports: contains the list of output ports from MDP. These connect to
interfaces
- that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
- special case since it is a part of the MDP block itself).
-
- Each output port contains an endpoint that describes how it is connected to
an
- external interface. These are described by the standard properties documented
- here:
- Documentation/devicetree/bindings/graph.txt
- Documentation/devicetree/bindings/media/video-interfaces.txt
-
- The availability of output ports can vary across SoC revisions:
-
- For MSM8974 and APQ8084:
-Port 0 -> MDP_INTF0 (eDP)
-Port 1 -> MDP_INTF1 (DSI1)
-Port 2 -> MDP_INTF2 (DSI2)
-Port 3 -> MDP_INTF3 (HDMI)
-
- For MSM8916:
-Port 0 -> MDP_INTF1 (DSI1)
-
- For MSM8994 and MSM8996:
-Port 0 -> MDP_INTF1 (DSI1)
-Port 1 -> MDP_INTF2 (DSI2)
-Port 2 -> MDP_INTF3 (HDMI)
-
-Optional properties:
-- clock-names: the following clocks are optional:
- * "lut"
- * "tbu"
- * "tbu_rt"
-
-Example:
-
-/ {
- ...
-
- mdss: mdss@1a0 {
- compatible = "qcom,mdss";
- reg = <0x1a0 0x1000>,
- <0x1ac8000 0x3000>;
- reg-names = "mdss_phys", "vbif_phys";
-
- power-domains = < MDSS_GDSC>;
-
- clocks = < GCC_MDSS_AHB_CLK>,
-< GCC_MDSS_AXI_CLK>,
-< GCC_MDSS_VSYNC_CLK>;
- clock-names = "iface",
- "bus",
- "vsync"
-
- interrupts = <0 72 0>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mdp: mdp@1a01000 {
- compatible = "qcom,mdp5";
- reg = <0x1a01000 0x9>;
- reg-names = "mdp_phys";
-
- interrupt-parent = <>;
- interrupts = <0 0>;
-
- clocks = < GCC_MDSS_AHB_CLK>,
-< GCC_MDSS_AXI_CLK>,
-< GCC_MDSS_MDP_CLK>,
-< GCC_MDSS_VSYNC_CLK>;
- clock-names = "iface",
- "bus",
- "core",
- "vsync";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- mdp5_intf1_out: endpoint {
- remote-endpoint = <_in>;
- };
- };
- };
- };
-
- dsi0: dsi@1a98000 {
- ...
- ports {
- ...
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
-
[Freedreno] [PATCH v7 00/11] dt-bindings: display/msm: rework MDP5 and MDSS schema
Krzysztof asked me to merge all pending MDSS/MDP5/DPU patches to a
single series to ease review and to let one to see the whole picture.
This combines three series: MDP5 schema conversion, mdss/mdp renaming
and addition of the "core" clock to the MDSS device node.
Patch 4 might generate warnings in qcom,sm6115-mdss and
qcom,qcm2290-mdss examples, but they have been fixed by the commit
e5266ca38294 ("dt-bindings: display: msm: Rename mdss node name in
example"). See https://gitlab.freedesktop.org/drm/msm/-/commit/e5266ca38294
Changes since v6:
- Switched qcom,mdss.yaml to use contains rather than oneOf (Rob
Herring)
- Fixed typo in patch 3 commit message (Rob Herring)
- Reworked clocks/clock-names to have oneOf under the properties
themselves, rather than having a toplevel switch (Rob Herring)
Changes since v5:
- Merged in the mdss/mdp node renaming and core clock series
- Fixed the formatting of descriptions in qcom,mdp5 schema.
Changes since v4:
- Adjust qcom,mdss.yaml to follow the addition of per-SoC compatibles
Changes since v3:
- Drop MSM8998 completely, it conflicts with qcom,msm8998-dpu.yaml
Changes since v2:
- Fix MSM8998 compatible list: "qcom,msm8998-dpu", "msm,mdp5" to allow
handling this device by either of the drivers.
Dmitry Baryshkov (11):
dt-bindings: display/msm: convert MDP5 schema to YAML format
dt-bindings: display/msm: add SoC-specific compats to qcom,mdp5.yaml
dt-bindings: display/msm: add core clock to the mdss bindings
dt-bindings: display/msm: rename mdss nodes to display-subsystem
dt-bindings: display/msm: rename mdp nodes to display-controller
ARM: dts: qcom-msm8974: add SoC specific compat string to mdp5 node
arm64: dts: qcom: add SoC specific compat strings to mdp5 nodes
arm64: dts: qcom: rename mdss nodes to display-subsystem
ARM: dts: qcom-msm8974: rename mdss node to display-subsystem
arm64: dts: qcom: rename mdp nodes to display-controller
ARM: dts: qcom: rename mdp nodes to display-controller
.../bindings/display/msm/dpu-common.yaml | 8 +
.../devicetree/bindings/display/msm/mdp5.txt | 132 ---
.../bindings/display/msm/mdss-common.yaml | 8 +
.../bindings/display/msm/qcom,mdp5.yaml | 156 ++
.../bindings/display/msm/qcom,mdss.yaml | 46 --
arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +-
arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 +-
arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
15 files changed, 223 insertions(+), 165 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/mdp5.txt
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
--
2.39.0
Re: [Freedreno] [PATCH 2/3] drm/msm/disp/dpu1: allow dspp selection for all the interfaces
On 18/01/2023 05:30, Kalyan Thota wrote:
-Original Message-
From: Dmitry Baryshkov
Sent: Tuesday, January 17, 2023 10:26 PM
To: Kalyan Thota (QUIC) ; dri-
de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
; Abhinav Kumar (QUIC)
Subject: Re: [PATCH 2/3] drm/msm/disp/dpu1: allow dspp selection for all the
interfaces
WARNING: This email originated from outside of Qualcomm. Please be wary of
any links or attachments, and do not enable macros.
On 17/01/2023 18:21, Kalyan Thota wrote:
Allow dspps to be populated as a requirement for all the encoder types
it need not be just DSI. If for any encoder the dspp allocation
doesn't go through then there can be an option to fallback for color
features.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..e39b345 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
*drm_enc)
static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
- struct drm_display_mode *mode)
+ struct drm_display_mode *mode,
+ struct drm_crtc_state *crtc_state)
Is this new argument used at all?
{
struct msm_display_topology topology = {0};
int i, intf_count = 0;
@@ -563,8 +564,9 @@ static struct msm_display_topology
dpu_encoder_get_topology(
* 1 LM, 1 INTF
* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
*
- * Adding color blocks only to primary interface if available in
- * sufficient number
+ * dspp blocks are made optional. If RM manager cannot allocate
+ * dspp blocks, then reservations will still go through with non dspp LM's
+ * so as to allow color management support via composer
+ fallbacks
*/
No, this is not the way to go.
First, RM should prefer non-DSPP-enabled LMs if DSPP blocks are not required.
Right now your patch makes it possible to allocate LMs, that have DSPP attached,
for non-CTM-enabled encoder and later fail allocation of DSPP for the CRTC
which has CTM blob attached.
Second, the decision on using DSPPs should come from dpu_crtc_atomic_check().
Pass 'bool need_dspp' to this function from dpu_atomic_check(). Fail if the
need_dspp constraint can't be fulfilled.
We may not get color_mgmt_changed property set during modeset commit, where as
our resource allocation happens during modeset.
So, you have to fix the conditions to perform LM reallocation if CTM
usage has changed (note, color_mgmt_changed is not a correct one here).
With this approach, dspps will get allocated on first come first serve basis
I don't think that this is what we have agreed upon.
@Rob, is it possible to send color management property during modeset, in that
case, we can use it for dspp allocation to the datapath. The current approach
doesn't assume it.
On chrome compositor, I see that color property was being set in the subsequent
commits but not in modeset.
if (intf_count == 2)
topology.num_lm = 2;
@@ -573,11 +575,9 @@ static struct msm_display_topology
dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT)
? 2 : 1;
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
- if (dpu_kms->catalog->dspp &&
- (dpu_kms->catalog->dspp_count >= topology.num_lm))
- topology.num_dspp = topology.num_lm;
- }
+ if (dpu_kms->catalog->dspp &&
+ (dpu_kms->catalog->dspp_count >= topology.num_lm))
+ topology.num_dspp = topology.num_lm;
topology.num_enc = 0;
topology.num_intf = intf_count;
@@ -643,7 +643,7 @@ static int dpu_encoder_virt_atomic_check(
}
}
- topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
+ topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
+ crtc_state);
/* Reserve dynamic resources now. */
if (!ret) {
--
With best wishes
Dmitry
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 2/3] drm/msm/disp/dpu1: allow dspp selection for all the interfaces
>-Original Message-
>From: Dmitry Baryshkov
>Sent: Tuesday, January 17, 2023 10:26 PM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [PATCH 2/3] drm/msm/disp/dpu1: allow dspp selection for all the
>interfaces
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 17/01/2023 18:21, Kalyan Thota wrote:
>> Allow dspps to be populated as a requirement for all the encoder types
>> it need not be just DSI. If for any encoder the dspp allocation
>> doesn't go through then there can be an option to fallback for color
>> features.
>>
>> Signed-off-by: Kalyan Thota
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +-
>> 1 file changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 9c6817b..e39b345 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
>*drm_enc)
>> static struct msm_display_topology dpu_encoder_get_topology(
>> struct dpu_encoder_virt *dpu_enc,
>> struct dpu_kms *dpu_kms,
>> - struct drm_display_mode *mode)
>> + struct drm_display_mode *mode,
>> + struct drm_crtc_state *crtc_state)
>
>Is this new argument used at all?
>
>> {
>> struct msm_display_topology topology = {0};
>> int i, intf_count = 0;
>> @@ -563,8 +564,9 @@ static struct msm_display_topology
>dpu_encoder_get_topology(
>>* 1 LM, 1 INTF
>>* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
>>*
>> - * Adding color blocks only to primary interface if available in
>> - * sufficient number
>> + * dspp blocks are made optional. If RM manager cannot allocate
>> + * dspp blocks, then reservations will still go through with non dspp
>> LM's
>> + * so as to allow color management support via composer
>> + fallbacks
>>*/
>
>No, this is not the way to go.
>
>First, RM should prefer non-DSPP-enabled LMs if DSPP blocks are not required.
>Right now your patch makes it possible to allocate LMs, that have DSPP
>attached,
>for non-CTM-enabled encoder and later fail allocation of DSPP for the CRTC
>which has CTM blob attached.
>
>Second, the decision on using DSPPs should come from dpu_crtc_atomic_check().
>Pass 'bool need_dspp' to this function from dpu_atomic_check(). Fail if the
>need_dspp constraint can't be fulfilled.
>
We may not get color_mgmt_changed property set during modeset commit, where as
our resource allocation happens during modeset.
With this approach, dspps will get allocated on first come first serve basis
@Rob, is it possible to send color management property during modeset, in that
case, we can use it for dspp allocation to the datapath. The current approach
doesn't assume it.
On chrome compositor, I see that color property was being set in the subsequent
commits but not in modeset.
>
>> if (intf_count == 2)
>> topology.num_lm = 2;
>> @@ -573,11 +575,9 @@ static struct msm_display_topology
>dpu_encoder_get_topology(
>> else
>> topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT)
>> ? 2 : 1;
>>
>> - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
>> - if (dpu_kms->catalog->dspp &&
>> - (dpu_kms->catalog->dspp_count >= topology.num_lm))
>> - topology.num_dspp = topology.num_lm;
>> - }
>> + if (dpu_kms->catalog->dspp &&
>> + (dpu_kms->catalog->dspp_count >= topology.num_lm))
>> + topology.num_dspp = topology.num_lm;
>>
>> topology.num_enc = 0;
>> topology.num_intf = intf_count;
>> @@ -643,7 +643,7 @@ static int dpu_encoder_virt_atomic_check(
>> }
>> }
>>
>> - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
>> + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
>> + crtc_state);
>>
>> /* Reserve dynamic resources now. */
>> if (!ret) {
>
>--
>With best wishes
>Dmitry
Re: [Freedreno] [PATCH v8 1/3] dt-bindings: msm: dsi-controller-main: Add compatible strings for every current SoC
On 17/01/2023 00:52, Bryan O'Donoghue wrote: Currently we do not differentiate between the various users of the qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one compatible string but, the hardware does have some significant differences in the number of clocks. To facilitate documenting the clocks add the following compatible strings - qcom,apq8064-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,qcm2290-dsi-ctrl Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of the desired format while we do so. Several MDSS yaml files exist which document the dsi sub-node. For each existing SoC MDSS yaml, provide the right dsi compat string. Signed-off-by: Bryan O'Donoghue --- .../display/msm/dsi-controller-main.yaml | 30 --- .../bindings/display/msm/qcom,mdss.yaml | 3 +- .../display/msm/qcom,msm8998-mdss.yaml| 8 +++-- .../display/msm/qcom,sc7180-mdss.yaml | 6 ++-- .../display/msm/qcom,sc7280-mdss.yaml | 6 ++-- .../display/msm/qcom,sdm845-mdss.yaml | 8 +++-- .../display/msm/qcom,sm8150-mdss.yaml | 8 +++-- .../display/msm/qcom,sm8250-mdss.yaml | 8 +++-- .../display/msm/qcom,sm8350-mdss.yaml | 6 ++-- .../display/msm/qcom,sm8450-mdss.yaml | 4 ++- 10 files changed, 63 insertions(+), 24 deletions(-) [skipped] diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml index c268e0b662cf9..599a6bad80f43 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -46,7 +46,9 @@ patternProperties: type: object properties: compatible: -const: qcom,mdss-dsi-ctrl +items: + - const: qcom,sm8450-dsi-ctrl + - const: qcom,mdss-dsi-ctrl "^phy@[0-9a-f]+$": type: object The example also should be updated in this file to include qcom,sm8450-dsi-ctrl for DSI nodes -- With best wishes Dmitry
Re: [Freedreno] [PATCH 1/3] drm/msm/disp/dpu1: allow reservation even if dspps are not available.
On 18/01/2023 05:24, Kalyan Thota wrote:
-Original Message-
From: Dmitry Baryshkov
Sent: Tuesday, January 17, 2023 10:10 PM
To: Kalyan Thota (QUIC) ; dri-
de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
; Abhinav Kumar (QUIC)
Subject: Re: [PATCH 1/3] drm/msm/disp/dpu1: allow reservation even if dspps are
not available.
WARNING: This email originated from outside of Qualcomm. Please be wary of
any links or attachments, and do not enable macros.
On 17/01/2023 18:35, Dmitry Baryshkov wrote:
On 17/01/2023 18:21, Kalyan Thota wrote:
if any topology requests for dspps and catalogue doesn't have the
allocation, avoid failing the reservation.
This can pave way to build logic allowing composer fallbacks for all
the color features that are handled in dspp.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 73b3442..c8899ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -343,7 +343,13 @@ static bool
_dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm,
return true;
idx = lm_cfg->dspp - DSPP_0;
-if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
+
+if (idx < 0) {
The change doesn't correspond to commit message.
+DPU_DEBUG("lm doesn't have dspp, ignoring the request %d\n",
lm_cfg->dspp);
+return true;
+}
+
+if (idx >= ARRAY_SIZE(rm->dspp_blks)) {
DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp);
return false;
}
If you'd like to remove duplicate for the (idx >= ARRAY_SIZE) check,
I'd suggest dropping the second one
I've misread the patch. However I don't see, why would one request DSPP_NONE
while specifying topology->num_dspp. I think that you are trying to put
additional
logic into a function that should just check for the available resources.
The link is specified in the catalogue.
For example:
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
_lm_sblk, PINGPONG_0, 0, DSPP_0), --> This LM has
DSPP attached
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
_lm_sblk, PINGPONG_2, LM_3, 0), --> no DSPP
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
_lm_sblk, PINGPONG_3, LM_2, 0), --> no DSPP
For the above example, num_dspps will be 1 which is nonzero. But if a request
comes on second interface and if there are no dspps then we are not failing the
reservation of data path as color features can be offloaded to GPU.
Idx for LM_2 and LM_3 will be -1 for above case hence the check not to fail
reservation.
topology->num_dspp previously was filled based on encoder type, since we want
to move away from encoder checks, we are now passing it same as LM number. If
there are dspps available we will allocate,
in case of non-availability then we are not failing the datapath reservation so
that composer fallbacks can be implemented.
As I wrote, num_dspps should be filled correctly (by the
dpu_get_topology) to request DSPP for CTM-enabled CRTCs and to set the
field to 0 if CRTC doesn't have CTM enabled.
Then RM code should adhere to the num_dspps passed. It must return an
error if it can not fulfil the requirements. Also if no DSPPs are
requested, RM should prefer non-DSPP-enabled LMs.
--
With best wishes
Dmitry
[Freedreno] [PATCH 3/4] dt-bindings: display/msm: dsi-controller-main: allow using fewer lanes
Some platforms might use less than full 4 lanes DSI interface. Allow using any amount of lanes starting from 1 up to 4. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 357036470b1f..dc318762ef7a 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -123,7 +123,7 @@ properties: properties: data-lanes: maxItems: 4 -minItems: 4 +minItems: 1 items: enum: [ 0, 1, 2, 3 ] @@ -139,7 +139,7 @@ properties: properties: data-lanes: maxItems: 4 -minItems: 4 +minItems: 1 items: enum: [ 0, 1, 2, 3 ] -- 2.39.0
[Freedreno] [PATCH 1/4] dt-bindings: display/msm: dsi-controller-main: remove #address/#size-cells
Stop mentioning #address-cells/#size-cells which are defined in display/dsi-controller.yaml. Use unevaluatedProperties instead of additionalProperties to allow skipping properties defined in other schema files. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dsi-controller-main.yaml | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 7c326f8927fc..b07bdddc1570 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -72,10 +72,6 @@ properties: deprecated: true const: dsi - "#address-cells": true - - "#size-cells": true - syscon-sfpb: description: A phandle to mmss_sfpb syscon node (only for DSIv2). $ref: "/schemas/types.yaml#/definitions/phandle" @@ -357,7 +353,7 @@ allOf: - const: iface - const: bus -additionalProperties: false +unevaluatedProperties: false examples: - | -- 2.39.0
[Freedreno] [PATCH 2/4] dt-bindings: display/msm: dsi-controller-main: account for apq8064
APQ8064 requires listing four clocks in the assigned-clocks / assigned-clock-parents properties. Account for that. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dsi-controller-main.yaml | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index b07bdddc1570..357036470b1f 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -83,12 +83,16 @@ properties: 2 DSI links. assigned-clocks: -maxItems: 2 +minItems: 2 +maxItems: 4 description: | Parents of "byte" and "pixel" for the given platform. + For DSIv2 platforms this should contain "byte", "esc", "src" and + "pixel_src" clocks. assigned-clock-parents: -maxItems: 2 +minItems: 2 +maxItems: 4 description: | The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. -- 2.39.0
[Freedreno] [PATCH 4/4] dt-binbings: display/msm: dsi-controller-main: add missing supplies
Describe DSI supplies used on apq8064 (vdda-supply) and msm8994/96 (vcca-supply). Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dsi-controller-main.yaml | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index dc318762ef7a..31d389249c1d 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -147,6 +147,14 @@ properties: - port@0 - port@1 + avdd-supply: +description: + Phandle to vdd regulator device node + + vcca-supply: +description: + Phandle to vdd regulator device node + vdd-supply: description: VDD regulator -- 2.39.0
Re: [Freedreno] [PATCH 1/3] drm/msm/disp/dpu1: allow reservation even if dspps are not available.
>-Original Message-
>From: Dmitry Baryshkov
>Sent: Tuesday, January 17, 2023 10:10 PM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [PATCH 1/3] drm/msm/disp/dpu1: allow reservation even if dspps are
>not available.
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 17/01/2023 18:35, Dmitry Baryshkov wrote:
>> On 17/01/2023 18:21, Kalyan Thota wrote:
>>> if any topology requests for dspps and catalogue doesn't have the
>>> allocation, avoid failing the reservation.
>>>
>>> This can pave way to build logic allowing composer fallbacks for all
>>> the color features that are handled in dspp.
>>>
>>> Signed-off-by: Kalyan Thota
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +++-
>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> index 73b3442..c8899ae 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> @@ -343,7 +343,13 @@ static bool
>>> _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm,
>>> return true;
>>> idx = lm_cfg->dspp - DSPP_0;
>>> -if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
>>> +
>>> +if (idx < 0) {
>>
>> The change doesn't correspond to commit message.
>>
>>> +DPU_DEBUG("lm doesn't have dspp, ignoring the request %d\n",
>>> lm_cfg->dspp);
>>> +return true;
>>> +}
>>> +
>>> +if (idx >= ARRAY_SIZE(rm->dspp_blks)) {
>>> DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp);
>>> return false;
>>> }
>>
>> If you'd like to remove duplicate for the (idx >= ARRAY_SIZE) check,
>> I'd suggest dropping the second one
>>
>
>I've misread the patch. However I don't see, why would one request DSPP_NONE
>while specifying topology->num_dspp. I think that you are trying to put
>additional
>logic into a function that should just check for the available resources.
>
The link is specified in the catalogue.
For example:
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
_lm_sblk, PINGPONG_0, 0, DSPP_0), --> This LM has
DSPP attached
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
_lm_sblk, PINGPONG_2, LM_3, 0), --> no DSPP
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
_lm_sblk, PINGPONG_3, LM_2, 0), --> no DSPP
For the above example, num_dspps will be 1 which is nonzero. But if a request
comes on second interface and if there are no dspps then we are not failing the
reservation of data path as color features can be offloaded to GPU.
Idx for LM_2 and LM_3 will be -1 for above case hence the check not to fail
reservation.
topology->num_dspp previously was filled based on encoder type, since we want
to move away from encoder checks, we are now passing it same as LM number. If
there are dspps available we will allocate,
in case of non-availability then we are not failing the datapath reservation so
that composer fallbacks can be implemented.
>--
>With best wishes
>Dmitry
[Freedreno] [PATCH 0/4] dt-bindings: display/msm: more dsi-controller fixes
A small set of patches to go on top of Bryan's changes to fix a small number of remaining issues. Dependencies: [1] [1] https://lore.kernel.org/linux-arm-msm/20230116225217.1056258-1-bryan.odonog...@linaro.org/ Dmitry Baryshkov (4): dt-bindings: display/msm: dsi-controller-main: remove #address/#size-cells dt-bindings: display/msm: dsi-controller-main: account for apq8064 dt-bindings: display/msm: dsi-controller-main: allow using fewer lanes dt-binbings: display/msm: dsi-controller-main: add missing supplies .../display/msm/dsi-controller-main.yaml | 26 --- 1 file changed, 17 insertions(+), 9 deletions(-) -- 2.39.0
[Freedreno] [PATCH] arm64: dts: qcom: sm8350: use qcom, sm8350-dsi-ctrl compatibles
Add the per-SoC (qcom,sm8350-dsi-ctrl) compatible strings to DSI nodes
to follow the pending DSI bindings changes.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 703ba3d81e82..a066566b6ea9 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2883,7 +2883,7 @@ dpu_intf1_out: endpoint {
};
mdss_dsi0: dsi@ae94000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ compatible = "qcom,sm8350-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
@@ -2978,7 +2978,7 @@ mdss_dsi0_phy: phy@ae94400 {
};
mdss_dsi1: dsi@ae96000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ compatible = "qcom,sm8350-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae96000 0 0x400>;
reg-names = "dsi_ctrl";
--
2.39.0
[Freedreno] [PATCH 3/4] arm64: dts: qcom: sc8280xp-crd: drop #sound-dai-cells from eDP node
The eDP device doesn't provide sound DAI. Drop corresponding property
from the eDP node.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 4e92dc28e2ce..a3b9c9d0a94d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -253,6 +253,7 @@ {
_dp3 {
compatible = "qcom,sc8280xp-edp";
+ /delete-property/ #sound-dai-cells;
data-lanes = <0 1 2 3>;
--
2.39.0
[Freedreno] [PATCH 4/4] arm64: dts: qcom: sc8280xp: add p1 register blocks to DP nodes
Per DT bindings add p1 register blocks to all DP controllers on SC8280XP
platform.
Fixes: 6f299ae7f96d ("arm64: dts: qcom: sc8280xp: add p1 register blocks to DP
nodes")
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index ea2c8ad37ccb..ed11fb89cdc7 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2448,7 +2448,8 @@ mdss0_dp2: displayport-controller@ae9a000 {
reg = <0 0xae9a000 0 0x200>,
<0 0xae9a200 0 0x200>,
<0 0xae9a400 0 0x600>,
- <0 0xae9b000 0 0x400>;
+ <0 0xae9b000 0 0x400>,
+ <0 0xae9b400 0 0x400>;
clocks = < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_DPTX2_AUX_CLK>,
@@ -2519,7 +2520,8 @@ mdss0_dp3: displayport-controller@aea {
reg = <0 0xaea 0 0x200>,
<0 0xaea0200 0 0x200>,
<0 0xaea0400 0 0x600>,
- <0 0xaea1000 0 0x400>;
+ <0 0xaea1000 0 0x400>,
+ <0 0xaea1400 0 0x400>;
clocks = < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_DPTX3_AUX_CLK>,
@@ -3394,7 +3396,8 @@ mdss1_dp0: displayport-controller@2209 {
reg = <0 0x2209 0 0x200>,
<0 0x22090200 0 0x200>,
<0 0x22090400 0 0x600>,
- <0 0x22091000 0 0x400>;
+ <0 0x22091000 0 0x400>,
+ <0 0x22091400 0 0x400>;
clocks = < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_DPTX0_AUX_CLK>,
@@ -3466,7 +3469,8 @@ mdss1_dp1: displayport-controller@22098000 {
reg = <0 0x22098000 0 0x200>,
<0 0x22098200 0 0x200>,
<0 0x22098400 0 0x600>,
- <0 0x22099000 0 0x400>;
+ <0 0x22099000 0 0x400>,
+ <0 0x22099400 0 0x400>;
clocks = < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_DPTX1_AUX_CLK>,
@@ -3537,7 +3541,8 @@ mdss1_dp2: displayport-controller@2209a000 {
reg = <0 0x2209a000 0 0x200>,
<0 0x2209a200 0 0x200>,
<0 0x2209a400 0 0x600>,
- <0 0x2209b000 0 0x400>;
+ <0 0x2209b000 0 0x400>,
+ <0 0x2209b400 0 0x400>;
clocks = < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_DPTX2_AUX_CLK>,
@@ -3608,7 +3613,8 @@ mdss1_dp3: displayport-controller@220a {
reg = <0 0x220a 0 0x200>,
<0 0x220a0200 0 0x200>,
<0 0x220a0400 0 0x600>,
- <0 0x220a1000 0 0x400>;
+ <0 0x220a1000 0 0x400>,
+ <0 0x220a1400 0 0x400>;
clocks = < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_DPTX3_AUX_CLK>,
--
2.39.0
[Freedreno] [PATCH 2/4] dt-bindings: display/msm: qcom, sc8280xp-mdss: add DP / eDP child nodes
Describe DP and eDP devices as subdevices to the MDSS on SC8280XP
platform.
Fixes: 45af56bf2d74 ("dt-bindings: display/msm: Add binding for SC8280XP MDSS")
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/qcom,sc8280xp-mdss.yaml | 8
1 file changed, 8 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
index b67e7874ed56..c239544bc37f 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
@@ -38,6 +38,14 @@ patternProperties:
compatible:
const: qcom,sc8280xp-dpu
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+enum:
+ - qcom,sc8280xp-dp
+ - qcom,sc8280xp-edp
+
unevaluatedProperties: false
examples:
--
2.39.0
[Freedreno] [PATCH 1/4] dt-bindings: display/msm: add qcom, sc8280xp-edp to list of eDP devices
Add qcom,sc8280xp-edp to the list of eDP devices, unblocking `aux-bus'
property and fobidding `#sound-dai-cells' property. Also since
sc8280xp-edp, overriding sc8280xp-dp, will contain 5 reg resources, drop
the reg contraint (as it will become equivalent to the top-level one,
requiring min 4 and max 5 reg entries).
Fixes: b6f8c4debc00 ("dt-bindings: msm/dp: Add SDM845 and SC8280XP compatibles")
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dp-controller.yaml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 3e54956e57db..efe4257c031f 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -151,11 +151,10 @@ allOf:
enum:
- qcom,sc7280-edp
- qcom,sc8180x-edp
+ - qcom,sc8280xp-edp
then:
properties:
"#sound-dai-cells": false
-reg:
- maxItems: 4
else:
properties:
aux-bus: false
--
2.39.0
Re: [Freedreno] [PATCH v5 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks
On 08/12/2022 00:00, Bjorn Andersson wrote:
From: Bjorn Andersson
Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v4:
- None
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
1 file changed, 838 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 9f3132ac2857..c2f186495506 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4,6 +4,7 @@
* Copyright (c) 2022, Linaro Limited
*/
+#include
#include
#include
#include
@@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 {
status = "disabled";
};
+ mdss1_dp0_phy: phy@8909a00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x08909a00 0 0x19c>,
+ <0 0x08909200 0 0xec>,
+ <0 0x08909600 0 0xec>,
+ <0 0x08909000 0 0x1c8>;
+
+ clocks = < DISP_CC_MDSS_DPTX0_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ power-domains = < SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp1_phy: phy@890ca00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x0890ca00 0 0x19c>,
+ <0 0x0890c200 0 0xec>,
+ <0 0x0890c600 0 0xec>,
+ <0 0x0890c000 0 0x1c8>;
+
+ clocks = < DISP_CC_MDSS_DPTX1_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ power-domains = < SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
system-cache-controller@920 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x0920 0 0x58000>, <0 0x0960 0
0x58000>;
@@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a80 {
};
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sc8280xp-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = < MDSS_GDSC>;
+
+ clocks = < GCC_DISP_AHB_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+
+ resets = < DISP_CC_MDSS_CORE_BCR>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <_noc MASTER_MDP0 0 _virt
SLAVE_EBI1 0>,
+ <_noc MASTER_MDP1 0 _virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ iommus = <_smmu 0x1000 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sc8280xp-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_LUT_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_MDP_CLK>,
+ <
DISP_CC_MDSS_VSYNC_CLK>;
+
Re: [Freedreno] [PATCH v8 2/3] dt-bindings: msm: dsi-controller-main: Document clocks on a per compatible basis
On 17/01/2023 00:52, Bryan O'Donoghue wrote: Each compatible has a different set of clocks which are associated with it. Add in the list of clocks for each compatible. Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue --- .../display/msm/dsi-controller-main.yaml | 219 -- 1 file changed, 202 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 35668caa190c4..47faf08a37443 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml [skipped] + + - if: + properties: +compatible: + contains: +enum: + - qcom,msm8974-dsi-ctrl +then: + properties: +clocks: + maxItems: 7 +clock-names: + items: +- const: mdp_core +- const: iface +- const: bus +- const: vsync vsync clock is not used on msm8974 platform, it causes DT verification errors. +- const: byte +- const: pixel +- const: core +- const: core_mmss +-- With best wishes Dmitry
Re: [Freedreno] [PATCH v8 2/3] dt-bindings: msm: dsi-controller-main: Document clocks on a per compatible basis
On 17/01/2023 00:52, Bryan O'Donoghue wrote: Each compatible has a different set of clocks which are associated with it. Add in the list of clocks for each compatible. Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue --- .../display/msm/dsi-controller-main.yaml | 219 -- 1 file changed, 202 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 35668caa190c4..47faf08a37443 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -9,9 +9,6 @@ title: Qualcomm Display DSI controller maintainers: - Krishna Manikandan -allOf: - - $ref: "../dsi-controller.yaml#" - properties: compatible: oneOf: @@ -50,22 +47,23 @@ properties: maxItems: 1 clocks: -items: - - description: Display byte clock - - description: Display byte interface clock - - description: Display pixel clock - - description: Display core clock - - description: Display AHB clock - - description: Display AXI clock +description: | + Several clocks are used, depending on the variant. Typical ones are:: + - bus:: Display AHB clock. + - byte:: Display byte clock. + - byte_intf:: Display byte interface clock. + - core:: Display core clock. + - core_mss:: Core MultiMedia SubSystem clock. + - iface:: Display AXI clock. + - mdp_core:: MDP Core clock. + - mnoc:: MNOC clock + - pixel:: Display pixel clock. +minItems: 3 +maxItems: 9 clock-names: -items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus +minItems: 3 +maxItems: 9 phys: maxItems: 1 @@ -161,6 +159,193 @@ required: - assigned-clock-parents - ports +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +enum: + - qcom,apq8064-dsi-ctrl +then: + properties: +clocks: + maxItems: 7 +clock-names: + items: +- const: iface +- const: bus +- const: core_mmss +- const: src +- const: byte +- const: pixel +- const: core + + - if: + properties: +compatible: + contains: +enum: + - qcom,msm8916-dsi-ctrl +then: + properties: +clocks: + maxItems: 6 +clock-names: + items: +- const: mdp_core +- const: iface +- const: bus +- const: byte +- const: pixel +- const: core + + - if: + properties: +compatible: + contains: +enum: + - qcom,msm8953-dsi-ctrl +then: + properties: +clocks: + maxItems: 6 +clock-names: + items: +- const: mdp_core +- const: iface +- const: bus +- const: byte +- const: pixel +- const: core + + - if: + properties: +compatible: + contains: +enum: + - qcom,msm8974-dsi-ctrl +then: + properties: +clocks: + maxItems: 7 +clock-names: + items: +- const: mdp_core +- const: iface +- const: bus +- const: vsync +- const: byte +- const: pixel +- const: core +- const: core_mmss + + - if: + properties: +compatible: + contains: +enum: + - qcom,msm8996-dsi-ctrl +then: + properties: +clocks: + maxItems: 7 +clock-names: + items: +- const: mdp_core +- const: byte +- const: iface +- const: bus +- const: core_mmss +- const: pixel +- const: core + + - if: + properties: +compatible: + contains: +enum: + - qcom,msm8998-dsi-ctrl +then: + properties: +clocks: + maxItems: 6 +clock-names: + items: +- const: byte +- const: byte_intf +- const: pixel +- const: core +- const: iface +- const: bus + + - if: + properties: +compatible: + contains: +enum: + - qcom,sc7180-dsi-ctrl + - qcom,sc7280-dsi-ctrl + - qcom,sm8250-dsi-ctrl + - qcom,sm8150-dsi-ctrl + - qcom,sm8250-dsi-ctrl Fails with:
Re: [Freedreno] [PATCH v6 04/11] dt-bindings: display/msm: rename mdss nodes to display-subsystem
On 13/01/2023 17:26, Rob Herring wrote:
On Fri, 13 Jan 2023 10:37:13 +0200, Dmitry Baryshkov wrote:
Follow the 'generic names' rule and rename mdss nodes to
display-subsystem.
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/mdss-common.yaml | 8
.../devicetree/bindings/display/msm/qcom,mdss.yaml| 5 -
2 files changed, 12 insertions(+), 1 deletion(-)
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.example.dtb:
mdss@5e0: $nodename:0: 'mdss@5e0' does not match
'^display-subsystem@[0-9a-f]+$'
From schema:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.example.dtb:
mdss@5e0: $nodename:0: 'mdss@5e0' does not match
'^display-subsystem@[0-9a-f]+$'
From schema:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
This should be fixed already by the commit e5266ca38294 ("dt-bindings:
display: msm: Rename mdss node name in example")
See https://gitlab.freedesktop.org/drm/msm/-/commit/e5266ca38294
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH] drm/msm/dpu: Reapply CTM if modeset is needed
On Wed, 18 Jan 2023 at 04:14, Jessica Zhang wrote:
>
> Add a !drm_atomic_crtc_needs_modeset() check to
> _dpu_crtc_setup_cp_blocks() so that CTM is reapplied after a
> suspend/resume.
.. or if the LM/DSPP blocks were reallocated by resource allocation
during the modeset.
>
> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/23
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 13ce321283ff..aa120a230222 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -748,7 +748,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc
> *crtc)
> int i;
>
>
> - if (!state->color_mgmt_changed)
> + if (!state->color_mgmt_changed &&
> !drm_atomic_crtc_needs_modeset(state))
> return;
>
> for (i = 0; i < cstate->num_mixers; i++) {
> --
> 2.39.0
>
--
With best wishes
Dmitry
[Freedreno] [PATCH] drm/msm/dpu: Reapply CTM if modeset is needed
Add a !drm_atomic_crtc_needs_modeset() check to
_dpu_crtc_setup_cp_blocks() so that CTM is reapplied after a
suspend/resume.
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/23
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..aa120a230222 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -748,7 +748,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
int i;
- if (!state->color_mgmt_changed)
+ if (!state->color_mgmt_changed && !drm_atomic_crtc_needs_modeset(state))
return;
for (i = 0; i < cstate->num_mixers; i++) {
--
2.39.0
Re: [Freedreno] [PATCH 2/2] drm/msm/dpu: use sm8350_regdma on SM8350 platform
On 1/17/2023 6:09 PM, Abhinav Kumar wrote:
On 1/17/2023 6:04 PM, Dmitry Baryshkov wrote:
Correct sm8350_dpu_cfg.dma_cfg to point to sm8350_regdma rather than
sm8250_regdma.
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 3d0fbc1746e2..e6618e678384 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2737,7 +2737,7 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.reg_dma_count = 1,
Since you are adding the .dma_cfg, lets stick to the convention of the
rest of the entries and use ARRAY_SIZE.
Since reg_dma is not an array yet,
Reviewed-by: Abhinav Kumar
- .dma_cfg = _regdma,
+ .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = IRQ_SM8350_MASK,
};
Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: point sc8280xp_dpu_cfg to sc8280xp_regdma
On 1/17/2023 6:09 PM, Dmitry Baryshkov wrote:
On 18/01/2023 04:08, Abhinav Kumar wrote:
On 1/17/2023 6:04 PM, Dmitry Baryshkov wrote:
SC8280XP configuration missed the reg_dma configuration. We do not use
regdma for now, but let's put the correct pointer anyway.
Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4375e72a9aab..3d0fbc1746e2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2680,6 +2680,8 @@ static const struct dpu_mdss_cfg
sc8280xp_dpu_cfg = {
.intf = sc8280xp_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
+ .reg_dma_count = 1,
Lets stick to the convention of the rest of the entries and use
ARRAY_SIZE.
regdma is not an array, so all platforms use 1 here. We should probably
change this, as some of newer platforms seem to have two regdma blocks,
but I haven't taken a look into that.
Ah ack, then this is fine. We should probably change that though,
Reviewed-by: Abhinav Kumar
+ .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = IRQ_SC8280XP_MASK,
};
Re: [Freedreno] [PATCH] drm/msm/dpu: add missing dpu_encoder kerneldoc
On 1/17/2023 6:05 PM, Dmitry Baryshkov wrote:
Describe missing dpu_encoder_phys_wb_is_master() argument and struct
dpu_encoder_virt.wide_bus_en field.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d1a528ff0f28..758261e8ac73 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -162,6 +162,7 @@ enum dpu_enc_rc_states {
* @vsync_event_work: worker to handle vsync event for autorefresh
* @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
+ * @wide_bus_en: wide bus is enabled on this interface
* @dsc: drm_dsc_config pointer, for DSC-enabled encoders
*/
struct dpu_encoder_virt {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 95921efd8139..bac4aa807b4b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -26,6 +26,7 @@
/**
* dpu_encoder_phys_wb_is_master - report wb always as master encoder
+ * @phys_enc: Pointer to physical encoder
*/
static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
{
Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: point sc8280xp_dpu_cfg to sc8280xp_regdma
On 18/01/2023 04:08, Abhinav Kumar wrote:
On 1/17/2023 6:04 PM, Dmitry Baryshkov wrote:
SC8280XP configuration missed the reg_dma configuration. We do not use
regdma for now, but let's put the correct pointer anyway.
Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4375e72a9aab..3d0fbc1746e2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2680,6 +2680,8 @@ static const struct dpu_mdss_cfg
sc8280xp_dpu_cfg = {
.intf = sc8280xp_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
+ .reg_dma_count = 1,
Lets stick to the convention of the rest of the entries and use ARRAY_SIZE.
regdma is not an array, so all platforms use 1 here. We should probably
change this, as some of newer platforms seem to have two regdma blocks,
but I haven't taken a look into that.
+ .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = IRQ_SC8280XP_MASK,
};
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 2/2] drm/msm/dpu: use sm8350_regdma on SM8350 platform
On 1/17/2023 6:04 PM, Dmitry Baryshkov wrote:
Correct sm8350_dpu_cfg.dma_cfg to point to sm8350_regdma rather than
sm8250_regdma.
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 3d0fbc1746e2..e6618e678384 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2737,7 +2737,7 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.reg_dma_count = 1,
Since you are adding the .dma_cfg, lets stick to the convention of the
rest of the entries and use ARRAY_SIZE.
- .dma_cfg = _regdma,
+ .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = IRQ_SM8350_MASK,
};
Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: point sc8280xp_dpu_cfg to sc8280xp_regdma
On 1/17/2023 6:04 PM, Dmitry Baryshkov wrote:
SC8280XP configuration missed the reg_dma configuration. We do not use
regdma for now, but let's put the correct pointer anyway.
Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4375e72a9aab..3d0fbc1746e2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2680,6 +2680,8 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
.intf = sc8280xp_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
+ .reg_dma_count = 1,
Lets stick to the convention of the rest of the entries and use ARRAY_SIZE.
+ .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = IRQ_SC8280XP_MASK,
};
Re: [Freedreno] [PATCH v3 1/2] drm/msm/dsi: add a helper method to compute the dsi byte clk
On Wed, 11 Jan 2023 16:15:59 -0800, Abhinav Kumar wrote: > Re-arrange the dsi_calc_pclk method to two helpers, one to > compute the DSI byte clk and the other to compute the pclk. > > This makes the separation of the two clean and also allows > clients to compute and use the dsi byte clk separately. > > changes in v2: > - move the assignments to definition lines > > [...] Applied, thanks! [1/2] drm/msm/dsi: add a helper method to compute the dsi byte clk https://gitlab.freedesktop.org/lumag/msm/-/commit/8b054353375c [2/2] drm/msm/dsi: implement opp table based check for dsi_mgr_bridge_mode_valid() https://gitlab.freedesktop.org/lumag/msm/-/commit/adc5d0f5af8d Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH] dt-bindings: display/msm: qcom, mdss: fix HDMI PHY node names
On Mon, 09 Jan 2023 06:54:53 +0200, Dmitry Baryshkov wrote: > On Qualcomm devices HDMI PHY node names were changed from hdmi-phy to > phy. Follow this change. > > Applied, thanks! [1/1] dt-bindings: display/msm: qcom,mdss: fix HDMI PHY node names https://gitlab.freedesktop.org/lumag/msm/-/commit/759cc4914fb0 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH] drm/msm/gem: Add check for kmalloc
On Mon, 12 Dec 2022 17:11:17 +0800, Jiasheng Jiang wrote: > Add the check for the return value of kmalloc in order to avoid > NULL pointer dereference in copy_from_user. > > Applied, thanks! [1/1] drm/msm/gem: Add check for kmalloc https://gitlab.freedesktop.org/lumag/msm/-/commit/d839f0811a31 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH] drm/msm/dp: Remove INIT_SETUP delay
On Tue, 17 Jan 2023 09:29:51 -0800, Bjorn Andersson wrote: > During initalization of the DisplayPort controller an EV_HPD_INIT_SETUP > event is generated, but with a delay of 100 units. This delay existed to > circumvent bug in the QMP combo PHY driver, where if the DP part was > powered up before USB, the common properties would not be properly > initialized - and USB wouldn't work. > > This issue was resolved in the recent refactoring of the QMP driver, > so it's now possible to remove this delay. > > [...] Applied, thanks! [1/1] drm/msm/dp: Remove INIT_SETUP delay https://gitlab.freedesktop.org/lumag/msm/-/commit/e17af1c9d861 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH v3] drm/msm/dpu: Disallow unallocated resources to be returned
On Tue, 10 Jan 2023 00:15:55 +0100, Marijn Suijten wrote: > In the event that the topology requests resources that have not been > created by the system (because they are typically not represented in > dpu_mdss_cfg ^1), the resource(s) in global_state (in this case DSC > blocks, until their allocation/assignment is being sanity-checked in > "drm/msm/dpu: Reject topologies for which no DSC blocks are available") > remain NULL but will still be returned out of > dpu_rm_get_assigned_resources, where the caller expects to get an array > containing num_blks valid pointers (but instead gets these NULLs). > > [...] Applied, thanks! [1/1] drm/msm/dpu: Disallow unallocated resources to be returned https://gitlab.freedesktop.org/lumag/msm/-/commit/abc40122d9a6 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH 1/2] dt-bindings: display/msm: Add SM6375 DSI PHY
On Mon, 16 Jan 2023 12:40:58 +0100, Konrad Dybcio wrote: > SM6375 has a single 7nm DSI PHY. Document it. > > Applied, thanks! [1/2] dt-bindings: display/msm: Add SM6375 DSI PHY https://gitlab.freedesktop.org/lumag/msm/-/commit/f8e6d45c8152 [2/2] drm/msm/dsi: Add phy configuration for SM6375 https://gitlab.freedesktop.org/lumag/msm/-/commit/88f46d2ccdf0 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH v2] drm/msm/dsi: Drop the redundant fail label
On Wed, 11 Jan 2023 09:10:06 +0800, Jiasheng Jiang wrote: > Drop the redundant fail label and change the "goto fail" into "return ret" > since they are the same. > > Applied, thanks! [1/1] drm/msm/dsi: Drop the redundant fail label https://gitlab.freedesktop.org/lumag/msm/-/commit/dc57f09acc34 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH v3] drm/msm/dsi: Add missing check for alloc_ordered_workqueue
On Tue, 10 Jan 2023 10:16:51 +0800, Jiasheng Jiang wrote: > Add check for the return value of alloc_ordered_workqueue as it may return > NULL pointer and cause NULL pointer dereference. > > Applied, thanks! [1/1] drm/msm/dsi: Add missing check for alloc_ordered_workqueue https://gitlab.freedesktop.org/lumag/msm/-/commit/e5237cd6ad68 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH v2] drm/msm: Add missing check and destroy for alloc_ordered_workqueue
On Mon, 09 Jan 2023 10:20:38 +0800, Jiasheng Jiang wrote: > Add check for the return value of alloc_ordered_workqueue as it may return > NULL pointer. > Moreover, use the destroy_workqueue in the later fails in order to avoid > memory leak. > > Applied, thanks! [1/1] drm/msm: Add missing check and destroy for alloc_ordered_workqueue https://gitlab.freedesktop.org/lumag/msm/-/commit/643b7d0869cc Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH 1/3] dt-bindings: display/msm: Add SM8150 MDSS & DPU
On Mon, 12 Dec 2022 10:33:12 +0100, Konrad Dybcio wrote: > Add bindings for the display hardware on SM8150. > > Applied, thanks! [1/3] dt-bindings: display/msm: Add SM8150 MDSS & DPU https://gitlab.freedesktop.org/lumag/msm/-/commit/9ffbefc1553c Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH] dt-bindings: msm/dsi: Don't require vdds-supply on 7nm PHY
On Mon, 16 Jan 2023 12:51:32 +0100, Konrad Dybcio wrote: > On some SoCs (hello SM6375) vdds-supply is not wired to any smd-rpm > or rpmh regulator, but instead powered by the VDD_MX/mx.lvl line, > which is voted for in the DSI ctrl node. > > Applied, thanks! [1/1] dt-bindings: msm/dsi: Don't require vdds-supply on 7nm PHY https://gitlab.freedesktop.org/lumag/msm/-/commit/4ff00ebb193a Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH] drm/msm/dpu: merge two CRTC debugfs dirs
On Thu, 12 Jan 2023 07:36:59 +0200, Dmitry Baryshkov wrote: > For each CRTC we are creating two different debugfs directories one > using crtc index (created automatically for the CRC files) and another > one using CRTC name/object ID (for state and status files). > > This can be confusing, so move our custom files to crtc->debugfs_entry, > effetively merging two debugfs dirs. > > [...] Applied, thanks! [1/1] drm/msm/dpu: merge two CRTC debugfs dirs https://gitlab.freedesktop.org/lumag/msm/-/commit/f377ea2c3c3a Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH] drm/msm/dpu: enable sourcesplit for sc7180/sc7280
On Mon, 16 Jan 2023 05:44:35 +0200, Dmitry Baryshkov wrote: > According to the vendor dts files, both sc7180 and sc7280 support the > source split mode (using two LMs for a single output). Change these two > platforms to use MIXER_SDM845_MASK, which includes > DPU_MIXER_SOURCESPLIT. Rename MIXER_SC7180_MASK to MIXER_QCM2290_MASK, > since this platform doesn't seem to support source split mode. > > > [...] Applied, thanks! [1/1] drm/msm/dpu: enable sourcesplit for sc7180/sc7280 https://gitlab.freedesktop.org/lumag/msm/-/commit/00feff8f1274 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH v8 0/3] mdss-dsi-ctrl binding and dts fixes
On Mon, 16 Jan 2023 22:52:14 +, Bryan O'Donoghue wrote: > V8: > - Squash first and last patch to fix bisectability > > link: > https://lore.kernel.org/linux-arm-msm/167388664232.594279.4607492026981202284.r...@kernel.org/T/#u > > V7: > - The bulk of the patches for this series have been merged. > There are still four patches to be pushed/updated. > - Adds clocks for msm8974 - Dmitry > - Adds compat strings for sm8150, sm8350, sm8450, sm8550 - Dmitry > - Changes last patch in series to state - Rob > compatible: > contains: > const: qcom,mdss-dsi-ctrl > > [...] Applied, thanks! [3/3] dt-bindings: msm: dsi-controller-main: Add vdd* descriptions back in https://gitlab.freedesktop.org/lumag/msm/-/commit/e0c2a96cc939 Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: remove dpu_encoder_virt_ops
On Mon, 02 Jan 2023 17:47:47 +0200, Dmitry Baryshkov wrote: > Struct dpu_encoder_virt_ops is used to provide several callbacks to the > phys_enc backends. However these ops are static and are not supposed to > change in the foreseeble future. Drop the indirection and call > corresponding functions directly. > > Applied, thanks! [1/2] drm/msm/dpu: remove dpu_encoder_virt_ops https://gitlab.freedesktop.org/lumag/msm/-/commit/59f0182a291c Best regards, -- Dmitry Baryshkov
Re: [Freedreno] [PATCH 1/3] drm/msm/dpu: fix blend setup for DMA4 and DMA5 layers
On Mon, 16 Jan 2023 08:33:14 +0200, Dmitry Baryshkov wrote: > SM8550 uses new register to map SSPP_DMA4 and SSPP_DMA5 units to blend > stages. Add proper support for this register to allow using these two > planes for image processing. > > Applied, thanks! [1/3] drm/msm/dpu: fix blend setup for DMA4 and DMA5 layers https://gitlab.freedesktop.org/lumag/msm/-/commit/80ca10dc64ff [2/3] drm/msm/dpu: simplify ctl_setup_blendstage calculation https://gitlab.freedesktop.org/lumag/msm/-/commit/644eddf9f166 [3/3] drm/msm/dpu: simplify blend configuration https://gitlab.freedesktop.org/lumag/msm/-/commit/63e3386b86d7 Best regards, -- Dmitry Baryshkov
[Freedreno] [PATCH] drm/msm/dpu: add missing dpu_encoder kerneldoc
Describe missing dpu_encoder_phys_wb_is_master() argument and struct
dpu_encoder_virt.wide_bus_en field.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d1a528ff0f28..758261e8ac73 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -162,6 +162,7 @@ enum dpu_enc_rc_states {
* @vsync_event_work: worker to handle vsync event for autorefresh
* @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
+ * @wide_bus_en: wide bus is enabled on this interface
* @dsc: drm_dsc_config pointer, for DSC-enabled encoders
*/
struct dpu_encoder_virt {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 95921efd8139..bac4aa807b4b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -26,6 +26,7 @@
/**
* dpu_encoder_phys_wb_is_master - report wb always as master encoder
+ * @phys_enc: Pointer to physical encoder
*/
static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
{
--
2.39.0
[Freedreno] [PATCH 2/2] drm/msm/dpu: use sm8350_regdma on SM8350 platform
Correct sm8350_dpu_cfg.dma_cfg to point to sm8350_regdma rather than
sm8250_regdma.
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 3d0fbc1746e2..e6618e678384 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2737,7 +2737,7 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.reg_dma_count = 1,
- .dma_cfg = _regdma,
+ .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = IRQ_SM8350_MASK,
};
--
2.39.0
[Freedreno] [PATCH 1/2] drm/msm/dpu: point sc8280xp_dpu_cfg to sc8280xp_regdma
SC8280XP configuration missed the reg_dma configuration. We do not use
regdma for now, but let's put the correct pointer anyway.
Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4375e72a9aab..3d0fbc1746e2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2680,6 +2680,8 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
.intf = sc8280xp_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = IRQ_SC8280XP_MASK,
};
--
2.39.0
[Freedreno] [PATCH] drm/msm: use strscpy instead of strncpy
Using strncpy can result in non-NULL-terminated destination string. Use
strscpy instead. This fixes following warning:
drivers/gpu/drm/msm/msm_fence.c: In function ‘msm_fence_context_alloc’:
drivers/gpu/drm/msm/msm_fence.c:25:9: warning: ‘strncpy’ specified bound 32
equals destination size [-Wstringop-truncation]
25 | strncpy(fctx->name, name, sizeof(fctx->name));
| ^
Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c
index a47e5837c528..56641408ea74 100644
--- a/drivers/gpu/drm/msm/msm_fence.c
+++ b/drivers/gpu/drm/msm/msm_fence.c
@@ -22,7 +22,7 @@ msm_fence_context_alloc(struct drm_device *dev, volatile
uint32_t *fenceptr,
return ERR_PTR(-ENOMEM);
fctx->dev = dev;
- strncpy(fctx->name, name, sizeof(fctx->name));
+ strscpy(fctx->name, name, sizeof(fctx->name));
fctx->context = dma_fence_context_alloc(1);
fctx->index = index++;
fctx->fenceptr = fenceptr;
--
2.39.0
Re: [Freedreno] [PATCH v2] drm/msm/dsi: Drop the redundant fail label
On 11/01/2023 03:10, Jiasheng Jiang wrote: Drop the redundant fail label and change the "goto fail" into "return ret" since they are the same. Reviewed-by: Doug Anderson Signed-off-by: Jiasheng Jiang --- Changelog: v1 -> v2: 1. No change of the error handling of the irq_of_parse_and_map. --- drivers/gpu/drm/msm/dsi/dsi_host.c | 24 1 file changed, 8 insertions(+), 16 deletions(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [Freedreno] [PATCH v3] drm/msm/dpu: Disallow unallocated resources to be returned
On 10/01/2023 01:15, Marijn Suijten wrote:
In the event that the topology requests resources that have not been
created by the system (because they are typically not represented in
dpu_mdss_cfg ^1), the resource(s) in global_state (in this case DSC
blocks, until their allocation/assignment is being sanity-checked in
"drm/msm/dpu: Reject topologies for which no DSC blocks are available")
remain NULL but will still be returned out of
dpu_rm_get_assigned_resources, where the caller expects to get an array
containing num_blks valid pointers (but instead gets these NULLs).
To prevent this from happening, where null-pointer dereferences
typically result in a hard-to-debug platform lockup, num_blks shouldn't
increase past NULL blocks and will print an error and break instead.
After all, max_blks represents the static size of the maximum number of
blocks whereas the actual amount varies per platform.
^1: which can happen after a git rebase ended up moving additions to
_dpu_cfg to a different struct which has the same patch context.
Fixes: bb00a452d6f7 ("drm/msm/dpu: Refactor resource manager")
Signed-off-by: Marijn Suijten
---
Changes since v2:
- Dropped all 7 other patches that were queued for -next;
- Reworded error message to clarify that the requested resource should
have already been allocated, rather than sounding like
dpu_rm_get_assigned_resources is (re)allocating/(re)assigning
resources here;
- This patch is now (implicitly!) based after "drm/msm/dpu: Reject
topologies for which no DSC blocks are available", which should make
it impossible to reach this condition, making it more of a safeguard
in case of future code changes and/or hidden issues: and is more
clearly conveyed in the patch message as well.
v2:
https://lore.kernel.org/linux-arm-msm/20221221231943.1961117-5-marijn.suij...@somainline.org/
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 5 +
1 file changed, 5 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v6 2/2] drm/msm/dp: enhance dp controller isr
On 28/12/2022 04:16, Kuogee Hsieh wrote: dp_display_irq_handler() is the main isr handler with the helps of two sub isr, dp_aux_isr and dp_ctrl_isr, to service all DP interrupts on every irq triggered. Current all three isr does not return IRQ_HANDLED if there are any interrupts it had serviced. This patch fix this ambiguity by having all isr return IRQ_HANDLED if there are interrupts had been serviced or IRQ_NONE otherwise. Changes in v5: -- move complete into dp_aux_native_handler() -- move complete into dp_aux_i2c_handler() -- restore null ctrl check at isr -- return IRQ_NODE directly Signed-off-by: Kuogee Hsieh Suggested-by: Stephen Boyd --- drivers/gpu/drm/msm/dp/dp_aux.c | 95 ++--- drivers/gpu/drm/msm/dp/dp_aux.h | 2 +- drivers/gpu/drm/msm/dp/dp_ctrl.c| 12 - drivers/gpu/drm/msm/dp/dp_ctrl.h| 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 16 +-- 5 files changed, 89 insertions(+), 38 deletions(-) Stephen, Dough, do we still want this patch in? -- With best wishes Dmitry
Re: [Freedreno] [PATCH v2] drm/msm: Add missing check and destroy for alloc_ordered_workqueue
On 09/01/2023 04:20, Jiasheng Jiang wrote: Add check for the return value of alloc_ordered_workqueue as it may return NULL pointer. Moreover, use the destroy_workqueue in the later fails in order to avoid memory leak. Signed-off-by: Jiasheng Jiang --- Changelog: v1 -> v2: 1. Convert "goto err_destroy_workqueue" into "goto err_msm_unit" and remove "err_destroy_workqueue" label. --- drivers/gpu/drm/msm/msm_drv.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [Freedreno] [PATCH] drm/msm/gem: Add check for kmalloc
On 12/12/2022 11:11, Jiasheng Jiang wrote:
Add the check for the return value of kmalloc in order to avoid
NULL pointer dereference in copy_from_user.
Fixes: 20224d715a88 ("drm/msm/submit: Move copy_from_user ahead of locking bos")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/msm_gem_submit.c | 4
1 file changed, 4 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
[Freedreno] [PATCH v2 2/3] drm/msm/mdss: add data for sc8180xp
Add platform data for sc8180xp based on sdmshrike-sde.dtsi.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 799672b88716..158d7850c4ba 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -516,6 +516,13 @@ static const struct msm_mdss_data sc7280_data = {
.macrotile_mode = 1,
};
+static const struct msm_mdss_data sc8180x_data = {
+ .ubwc_version = UBWC_3_0,
+ .ubwc_dec_version = UBWC_3_0,
+ .highest_bank_bit = 3,
+ .macrotile_mode = 1,
+};
+
static const struct msm_mdss_data sc8280xp_data = {
.ubwc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
@@ -555,7 +562,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sc7180-mdss", .data = _data },
{ .compatible = "qcom,sc7280-mdss", .data = _data },
- { .compatible = "qcom,sc8180x-mdss" },
+ { .compatible = "qcom,sc8180x-mdss", .data = _data },
{ .compatible = "qcom,sc8280xp-mdss", .data = _data },
{ .compatible = "qcom,sm6115-mdss", .data = _data },
{ .compatible = "qcom,sm8150-mdss", .data = _data },
--
2.39.0
[Freedreno] [PATCH v2 3/3] drm/msm/mdss: add the sdm845 data for completeness
Add the platform data for sdm845 platform.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 158d7850c4ba..c15d1e2dc718 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -532,6 +532,12 @@ static const struct msm_mdss_data sc8280xp_data = {
.macrotile_mode = 1,
};
+static const struct msm_mdss_data sdm845_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .highest_bank_bit = 2,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -559,7 +565,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss" },
{ .compatible = "qcom,qcm2290-mdss" },
- { .compatible = "qcom,sdm845-mdss" },
+ { .compatible = "qcom,sdm845-mdss", .data = _data },
{ .compatible = "qcom,sc7180-mdss", .data = _data },
{ .compatible = "qcom,sc7280-mdss", .data = _data },
{ .compatible = "qcom,sc8180x-mdss", .data = _data },
--
2.39.0
[Freedreno] [PATCH v2 1/3] drm/msm/mdss: convert UBWC setup to use match data
To simplify adding new platforms and to make settings more obvious,
rewrite the UBWC setup to use the data structure to pass platform config
rather than just calling the functions direcly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 181 +++--
1 file changed, 105 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 02646e4bb4cd..799672b88716 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -16,9 +16,6 @@
#include "msm_drv.h"
#include "msm_kms.h"
-/* for DPU_HW_* defines */
-#include "disp/dpu1/dpu_hw_catalog.h"
-
#define HW_REV 0x0
#define HW_INTR_STATUS 0x0010
@@ -29,6 +26,16 @@
#define MIN_IB_BW 4UL /* Min ib vote 400MB */
+struct msm_mdss_data {
+ u32 ubwc_version;
+ /* can be read from register 0x58 */
+ u32 ubwc_dec_version;
+ u32 ubwc_swizzle;
+ u32 ubwc_static;
+ u32 highest_bank_bit;
+ u32 macrotile_mode;
+};
+
struct msm_mdss {
struct device *dev;
@@ -40,6 +47,7 @@ struct msm_mdss {
unsigned long enabled_mask;
struct irq_domain *domain;
} irq_controller;
+ const struct msm_mdss_data *mdss_data;
struct icc_path *path[2];
u32 num_paths;
};
@@ -182,46 +190,40 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss
*msm_mdss)
#define UBWC_3_0 0x3000
#define UBWC_4_0 0x4000
-static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss,
- u32 ubwc_static)
+static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
{
- writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC);
+ const struct msm_mdss_data *data = msm_mdss->mdss_data;
+
+ writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC);
}
-static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss,
- unsigned int ubwc_version,
- u32 ubwc_swizzle,
- u32 highest_bank_bit,
- u32 macrotile_mode)
+static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
{
- u32 value = (ubwc_swizzle & 0x1) |
- (highest_bank_bit & 0x3) << 4 |
- (macrotile_mode & 0x1) << 12;
+ const struct msm_mdss_data *data = msm_mdss->mdss_data;
+ u32 value = (data->ubwc_swizzle & 0x1) |
+ (data->highest_bank_bit & 0x3) << 4 |
+ (data->macrotile_mode & 0x1) << 12;
- if (ubwc_version == UBWC_3_0)
+ if (data->ubwc_version == UBWC_3_0)
value |= BIT(10);
- if (ubwc_version == UBWC_1_0)
+ if (data->ubwc_version == UBWC_1_0)
value |= BIT(8);
writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
}
-static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss,
- unsigned int ubwc_version,
- u32 ubwc_swizzle,
- u32 ubwc_static,
- u32 highest_bank_bit,
- u32 macrotile_mode)
+static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
{
- u32 value = (ubwc_swizzle & 0x7) |
- (ubwc_static & 0x1) << 3 |
- (highest_bank_bit & 0x7) << 4 |
- (macrotile_mode & 0x1) << 12;
+ const struct msm_mdss_data *data = msm_mdss->mdss_data;
+ u32 value = (data->ubwc_swizzle & 0x7) |
+ (data->ubwc_static & 0x1) << 3 |
+ (data->highest_bank_bit & 0x7) << 4 |
+ (data->macrotile_mode & 0x1) << 12;
writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
- if (ubwc_version == UBWC_3_0) {
+ if (data->ubwc_version == UBWC_3_0) {
writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
} else {
@@ -233,7 +235,6 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss
*msm_mdss,
static int msm_mdss_enable(struct msm_mdss *msm_mdss)
{
int ret;
- u32 hw_rev;
/*
* Several components have AXI clocks that can only be turned on if
@@ -249,57 +250,36 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
}
/*
-* HW_REV requires MDSS_MDP_CLK, which is not enabled by the mdss on
-* mdp5 hardware. Skip reading it for now.
+* Register access requires MDSS_MDP_CLK, which is not enabled by the
+* mdss on mdp5 hardware. Skip it for now.
*/
- if (msm_mdss->is_mdp5)
+ if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)
return 0;
- hw_rev =
[Freedreno] [PATCH v2 0/3] drm/msm/mdss: rework UBWC setup
The commit 92bab9142456 ("drm/msm: less magic numbers in
msm_mdss_enable") reworked the static UBWC setup to replace magic
numbers with calulating written values from the SoC/device parameters.
This simplified adding new platforms.
However I did not estimate that the values would still be cryptic and
would be C instead of being determined from the vendor DT. Some
of the platform (sc8180x) completely missed this setup step.
This series attempts to rework the static UBWC setup to be both
manageable and hopefully easier to write.
Changes since RFC:
- Merged sm6115 fixup patch into the main patch, since only the comment
was incorrect
- Moved reading HW revision and UBWC decoder version to the error case
only
Dmitry Baryshkov (3):
drm/msm/mdss: convert UBWC setup to use match data
drm/msm/mdss: add data for sc8180xp
drm/msm/mdss: add the sdm845 data for completeness
drivers/gpu/drm/msm/msm_mdss.c | 198 -
1 file changed, 120 insertions(+), 78 deletions(-)
--
2.39.0
Re: [Freedreno] [PATCH] drm/msm/dpu: merge two CRTC debugfs dirs
On 1/11/2023 9:36 PM, Dmitry Baryshkov wrote:
For each CRTC we are creating two different debugfs directories one
using crtc index (created automatically for the CRC files) and another
one using CRTC name/object ID (for state and status files).
This can be confusing, so move our custom files to crtc->debugfs_entry,
effetively merging two debugfs dirs.
Signed-off-by: Dmitry Baryshkov
Makes sense to me and also verified it on my chromebook.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 7f0f467dbabd..659fdfec5346 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1380,16 +1380,12 @@ DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state);
static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
{
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
- struct dentry *debugfs_root;
-
- debugfs_root = debugfs_create_dir(dpu_crtc->name,
- crtc->dev->primary->debugfs_root);
debugfs_create_file("status", 0400,
- debugfs_root,
+ crtc->debugfs_entry,
dpu_crtc, &_dpu_debugfs_status_fops);
debugfs_create_file("state", 0600,
- debugfs_root,
+ crtc->debugfs_entry,
_crtc->base,
_crtc_debugfs_state_fops);
Re: [Freedreno] [PATCH 2/5] drm/msm: Fix IS_ERR() vs NULL check in a5xx_submit_in_rb()
On 10/11/2022 11:44, Gaosheng Cui wrote:
The msm_gem_get_vaddr() returns an ERR_PTR() on failure, we should
use IS_ERR() to check the return value.
Fixes: 6a8bd08d0465 ("drm/msm: add sudo flag to submit ioctl")
Signed-off-by: Gaosheng Cui
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 3c537c0016fa..0abc802e8d5f 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -89,7 +89,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct
msm_gem_submit *submit
* since we've already mapped it once in
* submit_reloc()
*/
- if (WARN_ON(!ptr))
+ if (WARN_ON(IS_ERR(ptr)))
return;
for (i = 0; i < dwords; i++) {
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
[Freedreno] [PATCH v2] drm/probe_helper: sort out poll_running vs poll_enabled
There are two flags attemting to guard connector polling:
poll_enabled and poll_running. While poll_enabled semantics is clearly
defined and fully adhered (mark that drm_kms_helper_poll_init() was
called and not finalized by the _fini() call), the poll_running flag
doesn't have such clearliness.
This flag is used only in drm_helper_probe_single_connector_modes() to
guard calling of drm_kms_helper_poll_enable, it doesn't guard the
drm_kms_helper_poll_fini(), etc. Change it to only be set if the polling
is actually running. Tie HPD enablement to this flag.
This fixes the following warning reported after merging the HPD series:
Hot plug detection already enabled
WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_bridge.c:1257
drm_bridge_hpd_enable+0x94/0x9c [drm]
Modules linked in: videobuf2_memops snd_soc_simple_card
snd_soc_simple_card_utils fsl_imx8_ddr_perf videobuf2_common snd_soc_imx_spdif
adv7511 etnaviv imx8m_ddrc imx_dcss mc cec nwl_dsi gov
CPU: 2 PID: 9 Comm: kworker/u8:0 Not tainted 6.2.0-rc2-15208-g25b283acd578 #6
Hardware name: NXP i.MX8MQ EVK (DT)
Workqueue: events_unbound deferred_probe_work_func
pstate: 6005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : drm_bridge_hpd_enable+0x94/0x9c [drm]
lr : drm_bridge_hpd_enable+0x94/0x9c [drm]
sp : 89ef3740
x29: 89ef3740 x28: 09331f00 x27: 1000
x26: 0020 x25: 81148ed8 x24: 0a8fe000
x23: fffd x22: 05086348 x21: 81133ee0
x20: 0550d800 x19: 05086288 x18: 0006
x17: x16: 896ef008 x15: 972891004260
x14: 2a1403e19400 x13: 972891004260 x12: 2a1403e19400
x11: 7100385f29400801 x10: 0aa0 x9 : 88112744
x8 : 00250b00 x7 : 0003 x6 : 0011
x5 : x4 : bd986a48 x3 : 0001
x2 : x1 : x0 : 0025
Call trace:
drm_bridge_hpd_enable+0x94/0x9c [drm]
drm_bridge_connector_enable_hpd+0x2c/0x3c [drm_kms_helper]
drm_kms_helper_poll_enable+0x94/0x10c [drm_kms_helper]
drm_helper_probe_single_connector_modes+0x1a8/0x510 [drm_kms_helper]
drm_client_modeset_probe+0x204/0x1190 [drm]
__drm_fb_helper_initial_config_and_unlock+0x5c/0x4a4 [drm_kms_helper]
drm_fb_helper_initial_config+0x54/0x6c [drm_kms_helper]
drm_fbdev_client_hotplug+0xd0/0x140 [drm_kms_helper]
drm_fbdev_generic_setup+0x90/0x154 [drm_kms_helper]
dcss_kms_attach+0x1c8/0x254 [imx_dcss]
dcss_drv_platform_probe+0x90/0xfc [imx_dcss]
platform_probe+0x70/0xcc
really_probe+0xc4/0x2e0
__driver_probe_device+0x80/0xf0
driver_probe_device+0xe0/0x164
__device_attach_driver+0xc0/0x13c
bus_for_each_drv+0x84/0xe0
__device_attach+0xa4/0x1a0
device_initial_probe+0x1c/0x30
bus_probe_device+0xa4/0xb0
deferred_probe_work_func+0x90/0xd0
process_one_work+0x200/0x474
worker_thread+0x74/0x43c
kthread+0xfc/0x110
ret_from_fork+0x10/0x20
---[ end trace ]---
Reported-by: Laurentiu Palcu
Fixes: c8268795c9a9 ("drm/probe-helper: enable and disable HPD on connectors")
Tested-by: Marek Szyprowski
Tested-by: Chen-Yu Tsai
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Fixed drm_kms_helper_enable_hpd() to call enable_hpd() instead of
disable_hpd().
---
drivers/gpu/drm/drm_probe_helper.c | 110 +
1 file changed, 63 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/drm_probe_helper.c
b/drivers/gpu/drm/drm_probe_helper.c
index 7973f2589ced..04754bb7b131 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -222,6 +222,45 @@ drm_connector_mode_valid(struct drm_connector *connector,
return ret;
}
+static void drm_kms_helper_disable_hpd(struct drm_device *dev)
+{
+ struct drm_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+
+ drm_connector_list_iter_begin(dev, _iter);
+ drm_for_each_connector_iter(connector, _iter) {
+ const struct drm_connector_helper_funcs *funcs =
+ connector->helper_private;
+
+ if (funcs && funcs->disable_hpd)
+ funcs->disable_hpd(connector);
+ }
+ drm_connector_list_iter_end(_iter);
+}
+
+static bool drm_kms_helper_enable_hpd(struct drm_device *dev)
+{
+ bool poll = false;
+ struct drm_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+
+ drm_connector_list_iter_begin(dev, _iter);
+ drm_for_each_connector_iter(connector, _iter) {
+ const struct drm_connector_helper_funcs *funcs =
+ connector->helper_private;
+
+ if (funcs && funcs->enable_hpd)
+ funcs->enable_hpd(connector);
+
+ if (connector->polled & (DRM_CONNECTOR_POLL_CONNECT |
+DRM_CONNECTOR_POLL_DISCONNECT))
+ poll = true;
+
Re: [Freedreno] [PATCH] drm/msm/dpu: Remove some unused variables
On 1/11/2023 7:38 PM, Jiapeng Chong wrote:
Variables 'sc8280xp_regdma' and 'sm8350_regdma' are defined in the
dpu_hw_catalog.c file, but not used elsewhere, so remove these unused
variables.
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:2029:37: warning: unused
variable 'sc8280xp_regdma'.
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:2053:37: warning: unused
variable 'sm8350_regdma'.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3722
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
We should be adding the regdma entries to .dma_cfg of these chipsets.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0f3da480b066..79bbef93948f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2026,14 +2026,6 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
},
};
-static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
- .base = 0x0,
- .version = 0x0002,
- .trigger_sel_off = 0x119c,
- .xin_id = 7,
- .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
static const struct dpu_reg_dma_cfg sdm845_regdma = {
.base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
};
@@ -2050,14 +2042,6 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
};
-static const struct dpu_reg_dma_cfg sm8350_regdma = {
- .base = 0x400,
- .version = 0x0002,
- .trigger_sel_off = 0x119c,
- .xin_id = 7,
- .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
static const struct dpu_reg_dma_cfg sm8450_regdma = {
.base = 0x0,
.version = 0x0002,
Re: [Freedreno] [PATCH] drm/msm/dpu: enable sourcesplit for sc7180/sc7280
On 1/15/2023 7:44 PM, Dmitry Baryshkov wrote:
According to the vendor dts files, both sc7180 and sc7280 support the
source split mode (using two LMs for a single output). Change these two
platforms to use MIXER_SDM845_MASK, which includes
DPU_MIXER_SOURCESPLIT. Rename MIXER_SC7180_MASK to MIXER_QCM2290_MASK,
since this platform doesn't seem to support source split mode.
Signed-off-by: Dmitry Baryshkov
Names are getting confusing with mask name re-uses, till the hw catalog
split have to live with it I guess.
I need to double-check about QCM 2290, but since this change is keeping
current masks for it and just renaming,
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 22ad996e9014..835d6d2c4115 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -56,7 +56,7 @@
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) |
BIT(DPU_MIXER_COMBINED_ALPHA))
-#define MIXER_SC7180_MASK \
+#define MIXER_QCM2290_MASK \
(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
#define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
@@ -1464,9 +1464,9 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
};
static const struct dpu_lm_cfg sc7180_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_1, LM_0, 0),
};
@@ -1499,11 +1499,11 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
};
static const struct dpu_lm_cfg sc7280_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_0, 0, DSPP_0),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_3, LM_2, 0),
};
@@ -1518,7 +1518,7 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
};
static const struct dpu_lm_cfg qcm2290_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
_lm_sblk, PINGPONG_0, 0, DSPP_0),
};
Re: [Freedreno] [PATCH v8 1/3] dt-bindings: msm: dsi-controller-main: Add compatible strings for every current SoC
On Mon, 16 Jan 2023 22:52:15 +, Bryan O'Donoghue wrote: > Currently we do not differentiate between the various users of the > qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one > compatible string but, the hardware does have some significant differences > in the number of clocks. > > To facilitate documenting the clocks add the following compatible strings > > - qcom,apq8064-dsi-ctrl > - qcom,msm8916-dsi-ctrl > - qcom,msm8953-dsi-ctrl > - qcom,msm8974-dsi-ctrl > - qcom,msm8996-dsi-ctrl > - qcom,msm8998-dsi-ctrl > - qcom,sc7180-dsi-ctrl > - qcom,sc7280-dsi-ctrl > - qcom,sdm660-dsi-ctrl > - qcom,sdm845-dsi-ctrl > - qcom,sm8150-dsi-ctrl > - qcom,sm8250-dsi-ctrl > - qcom,sm8350-dsi-ctrl > - qcom,sm8450-dsi-ctrl > - qcom,sm8550-dsi-ctrl > - qcom,qcm2290-dsi-ctrl > > Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of the desired format while we > do so. > > Several MDSS yaml files exist which document the dsi sub-node. > For each existing SoC MDSS yaml, provide the right dsi compat string. > > Signed-off-by: Bryan O'Donoghue > --- > .../display/msm/dsi-controller-main.yaml | 30 --- > .../bindings/display/msm/qcom,mdss.yaml | 3 +- > .../display/msm/qcom,msm8998-mdss.yaml| 8 +++-- > .../display/msm/qcom,sc7180-mdss.yaml | 6 ++-- > .../display/msm/qcom,sc7280-mdss.yaml | 6 ++-- > .../display/msm/qcom,sdm845-mdss.yaml | 8 +++-- > .../display/msm/qcom,sm8150-mdss.yaml | 8 +++-- > .../display/msm/qcom,sm8250-mdss.yaml | 8 +++-- > .../display/msm/qcom,sm8350-mdss.yaml | 6 ++-- > .../display/msm/qcom,sm8450-mdss.yaml | 4 ++- > 10 files changed, 63 insertions(+), 24 deletions(-) > Acked-by: Rob Herring
Re: [Freedreno] [PATCH v7 4/4] dt-bindings: display/msm: Add list of mdss-dsi-ctrl compats
On Mon, 16 Jan 2023 15:21:28 +, Bryan O'Donoghue wrote: > Add the list of current compats absent the deprecated qcm2290 to the list > of dsi compats listed here. > > Several MDSS yaml files exist which document the dsi sub-node. > For each existing SoC MDSS yaml, provide the right dsi compat string. > > Signed-off-by: Bryan O'Donoghue > --- > .../devicetree/bindings/display/msm/qcom,mdss.yaml| 3 ++- > .../bindings/display/msm/qcom,msm8998-mdss.yaml | 8 +--- > .../devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml | 6 -- > .../devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml | 6 -- > .../devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml | 8 +--- > .../devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml | 8 +--- > .../devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml | 8 +--- > .../devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6 -- > .../devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml | 4 +++- > 9 files changed, 37 insertions(+), 20 deletions(-) > Acked-by: Rob Herring
Re: [Freedreno] [PATCH v8 0/3] mdss-dsi-ctrl binding and dts fixes
For the series: Acked-by: David Heidelberg
Re: [Freedreno] (subset) [PATCH v16 0/5] Add data-lanes and link-frequencies to dp_out endpoint
On Tue, 27 Dec 2022 09:44:58 -0800, Kuogee Hsieh wrote: > Add DP both data-lanes and link-frequencies property to dp_out endpoint and > support > functions to DP driver. > > Kuogee Hsieh (5): > arm64: dts: qcom: add data-lanes and link-freuencies into dp_out > endpoint > dt-bindings: msm/dp: add data-lanes and link-frequencies property > drm/msm/dp: parse data-lanes as property of dp_out endpoint > Add capability to parser and retrieve max DP link supported rate from >link-frequencies property of dp_out endpoint. > drm/msm/dp: add support of max dp link rate > > [...] Applied, thanks! [1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint commit: 26c5aa54f5973a3b1181939811f231faa638332a Best regards, -- Bjorn Andersson
Re: [Freedreno] [PATCH] drm/msm/dp: Remove INIT_SETUP delay
On 1/17/2023 9:29 AM, Bjorn Andersson wrote: During initalization of the DisplayPort controller an EV_HPD_INIT_SETUP event is generated, but with a delay of 100 units. This delay existed to circumvent bug in the QMP combo PHY driver, where if the DP part was powered up before USB, the common properties would not be properly initialized - and USB wouldn't work. This issue was resolved in the recent refactoring of the QMP driver, so it's now possible to remove this delay. While there is still a timing dependency in the current implementation, test indicates that it's now possible to boot with an external display on USB Type-C and have the display power up, without disconnecting and reconnecting the cable. Signed-off-by: Bjorn Andersson Reviewed-by: Kuogee Hsieh --- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index db9783ffd5cf..bde1a7ce442f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1506,7 +1506,7 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display) dp = container_of(dp_display, struct dp_display_private, dp_display); if (!dp_display->is_edp) - dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100); + dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 0); } bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
Re: [Freedreno] [PATCH v6 05/11] dt-bindings: display/msm: rename mdp nodes to display-controller
On Fri, 13 Jan 2023 10:37:14 +0200, Dmitry Baryshkov wrote: > Follow the 'generic names' rule and rename mdp nodes to > display-controller. > > Signed-off-by: Dmitry Baryshkov > --- > .../devicetree/bindings/display/msm/dpu-common.yaml | 8 > .../devicetree/bindings/display/msm/qcom,mdp5.yaml| 3 +++ > .../devicetree/bindings/display/msm/qcom,mdss.yaml| 6 +++--- > 3 files changed, 14 insertions(+), 3 deletions(-) > Reviewed-by: Rob Herring
Re: [Freedreno] [PATCH v6 03/11] dt-bindings: display/msm: add core clock to the mdss bindings
On Fri, Jan 13, 2023 at 10:37:12AM +0200, Dmitry Baryshkov wrote: > Add (optional) core clock to the mdss bindings to let the MDSS driver > access harware registers before MDP driver probes. typo > > Signed-off-by: Dmitry Baryshkov > --- > .../bindings/display/msm/qcom,mdss.yaml | 34 ++- > 1 file changed, 26 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml > b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml > index dcde34ffc8d0..6948ae3ac7bc 100644 > --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml > +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml > @@ -45,17 +45,11 @@ properties: > >clocks: > minItems: 1 > -items: > - - description: Display abh clock > - - description: Display axi clock > - - description: Display vsync clock > +maxItems: 4 > >clock-names: > minItems: 1 > -items: > - - const: iface > - - const: bus > - - const: vsync > +maxItems: 4 > >"#address-cells": > const: 1 > @@ -69,6 +63,30 @@ properties: > items: >- description: MDSS_CORE reset > > +oneOf: This is not based on compatible? If not rather than at the top level, you can do 'oneOf' under 'clocks' and 'clock-names'. > + - properties: > + clocks: > +minItems: 3 > +maxItems: 4 > + > + clock-names: > +minItems: 3 > +items: > + - const: iface > + - const: bus > + - const: vsync > + - const: core > + - properties: > + clocks: > +minItems: 1 > +maxItems: 2 > + > + clock-names: > +minItems: 1 > +items: > + - const: iface > + - const: core > + > required: >- compatible >- reg > -- > 2.39.0 >
Re: [Freedreno] [PATCH v6 02/11] dt-bindings: display/msm: add SoC-specific compats to qcom, mdp5.yaml
On Fri, Jan 13, 2023 at 10:37:11AM +0200, Dmitry Baryshkov wrote:
> Add platform-specific compatible entries to the qcom,mdp5.yaml to allow
> distinguishing between various platforms.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../bindings/display/msm/qcom,mdp5.yaml | 17 -
> .../bindings/display/msm/qcom,mdss.yaml | 6 +-
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
> b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
> index 5e3cd7abf046..cb7bf48c3a58 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
> @@ -16,7 +16,22 @@ maintainers:
>
> properties:
>compatible:
> -const: qcom,mdp5
> +oneOf:
> + - const: qcom,mdp5
> +deprecated: true
> + - items:
> + - enum:
> + - qcom,apq8084-mdp5
> + - qcom,msm8916-mdp5
> + - qcom,msm8917-mdp5
> + - qcom,msm8953-mdp5
> + - qcom,msm8974-mdp5
> + - qcom,msm8976-mdp5
> + - qcom,msm8994-mdp5
> + - qcom,msm8996-mdp5
> + - qcom,sdm630-mdp5
> + - qcom,sdm660-mdp5
> + - const: qcom,mdp5
>
>reg:
> maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
> b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
> index ba0460268731..dcde34ffc8d0 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
> @@ -88,7 +88,11 @@ patternProperties:
> type: object
> properties:
>compatible:
> -const: qcom,mdp5
> +oneOf:
> + - const: qcom,mdp5
> + - items:
> + - {}
> + - const: qcom,mdp5
Just 'contains' is sufficient for all this. The exact length and order
will be checked by qcom,mdp5.yaml. With that,
Reviewed-by: Rob Herring
Rob
Re: [Freedreno] [PATCH v6 01/11] dt-bindings: display/msm: convert MDP5 schema to YAML format
On Fri, 13 Jan 2023 10:37:10 +0200, Dmitry Baryshkov wrote: > Convert the mdp5.txt into the yaml format. Changes to the existing (txt) > schema: > - MSM8996 has additional "iommu" clock, define it separately > - Add new properties used on some of platforms: >- interconnects, interconnect-names >- iommus >- power-domains >- operating-points-v2, opp-table > > Signed-off-by: Dmitry Baryshkov > --- > .../devicetree/bindings/display/msm/mdp5.txt | 132 - > .../bindings/display/msm/qcom,mdp5.yaml | 138 ++ > 2 files changed, 138 insertions(+), 132 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/display/msm/mdp5.txt > create mode 100644 > Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml > Reviewed-by: Rob Herring
[Freedreno] [PATCH] drm/msm/dp: Remove INIT_SETUP delay
During initalization of the DisplayPort controller an EV_HPD_INIT_SETUP event is generated, but with a delay of 100 units. This delay existed to circumvent bug in the QMP combo PHY driver, where if the DP part was powered up before USB, the common properties would not be properly initialized - and USB wouldn't work. This issue was resolved in the recent refactoring of the QMP driver, so it's now possible to remove this delay. While there is still a timing dependency in the current implementation, test indicates that it's now possible to boot with an external display on USB Type-C and have the display power up, without disconnecting and reconnecting the cable. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index db9783ffd5cf..bde1a7ce442f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1506,7 +1506,7 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display) dp = container_of(dp_display, struct dp_display_private, dp_display); if (!dp_display->is_edp) - dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100); + dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 0); } bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) -- 2.37.3
Re: [Freedreno] [PATCH 2/3] drm/msm/disp/dpu1: allow dspp selection for all the interfaces
On 17/01/2023 18:21, Kalyan Thota wrote:
Allow dspps to be populated as a requirement for all the encoder
types it need not be just DSI. If for any encoder the dspp
allocation doesn't go through then there can be an option to
fallback for color features.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..e39b345 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
- struct drm_display_mode *mode)
+ struct drm_display_mode *mode,
+ struct drm_crtc_state *crtc_state)
Is this new argument used at all?
{
struct msm_display_topology topology = {0};
int i, intf_count = 0;
@@ -563,8 +564,9 @@ static struct msm_display_topology dpu_encoder_get_topology(
* 1 LM, 1 INTF
* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
*
-* Adding color blocks only to primary interface if available in
-* sufficient number
+* dspp blocks are made optional. If RM manager cannot allocate
+* dspp blocks, then reservations will still go through with non dspp
LM's
+* so as to allow color management support via composer fallbacks
*/
No, this is not the way to go.
First, RM should prefer non-DSPP-enabled LMs if DSPP blocks are not
required. Right now your patch makes it possible to allocate LMs, that
have DSPP attached, for non-CTM-enabled encoder and later fail
allocation of DSPP for the CRTC which has CTM blob attached.
Second, the decision on using DSPPs should come from
dpu_crtc_atomic_check(). Pass 'bool need_dspp' to this function from
dpu_atomic_check(). Fail if the need_dspp constraint can't be fulfilled.
if (intf_count == 2)
topology.num_lm = 2;
@@ -573,11 +575,9 @@ static struct msm_display_topology
dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
- if (dpu_kms->catalog->dspp &&
- (dpu_kms->catalog->dspp_count >= topology.num_lm))
- topology.num_dspp = topology.num_lm;
- }
+ if (dpu_kms->catalog->dspp &&
+ (dpu_kms->catalog->dspp_count >= topology.num_lm))
+ topology.num_dspp = topology.num_lm;
topology.num_enc = 0;
topology.num_intf = intf_count;
@@ -643,7 +643,7 @@ static int dpu_encoder_virt_atomic_check(
}
}
- topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
+ topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
crtc_state);
/* Reserve dynamic resources now. */
if (!ret) {
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 1/3] drm/msm/disp/dpu1: allow reservation even if dspps are not available.
On 17/01/2023 18:35, Dmitry Baryshkov wrote:
On 17/01/2023 18:21, Kalyan Thota wrote:
if any topology requests for dspps and catalogue doesn't have the
allocation, avoid failing the reservation.
This can pave way to build logic allowing composer fallbacks
for all the color features that are handled in dspp.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 73b3442..c8899ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -343,7 +343,13 @@ static bool
_dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm,
return true;
idx = lm_cfg->dspp - DSPP_0;
- if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
+
+ if (idx < 0) {
The change doesn't correspond to commit message.
+ DPU_DEBUG("lm doesn't have dspp, ignoring the request %d\n",
lm_cfg->dspp);
+ return true;
+ }
+
+ if (idx >= ARRAY_SIZE(rm->dspp_blks)) {
DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp);
return false;
}
If you'd like to remove duplicate for the (idx >= ARRAY_SIZE) check, I'd
suggest dropping the second one
I've misread the patch. However I don't see, why would one request
DSPP_NONE while specifying topology->num_dspp. I think that you are
trying to put additional logic into a function that should just check
for the available resources.
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 1/3] drm/msm/disp/dpu1: allow reservation even if dspps are not available.
On 17/01/2023 18:21, Kalyan Thota wrote:
if any topology requests for dspps and catalogue doesn't have the
allocation, avoid failing the reservation.
This can pave way to build logic allowing composer fallbacks
for all the color features that are handled in dspp.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 73b3442..c8899ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -343,7 +343,13 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct
dpu_rm *rm,
return true;
idx = lm_cfg->dspp - DSPP_0;
- if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
+
+ if (idx < 0) {
The change doesn't correspond to commit message.
+ DPU_DEBUG("lm doesn't have dspp, ignoring the request %d\n",
lm_cfg->dspp);
+ return true;
+ }
+
+ if (idx >= ARRAY_SIZE(rm->dspp_blks)) {
DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp);
return false;
}
If you'd like to remove duplicate for the (idx >= ARRAY_SIZE) check, I'd
suggest dropping the second one
--
With best wishes
Dmitry
[Freedreno] [PATCH 3/3] drm/msm/disp/dpu1: fail atomic check if color feature is requested with no dspp
Fail atomic check if any color feature is requested with no
dspps allocated in the datapath so that composer can offload those
features.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4170fbe..de8d799 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1147,6 +1147,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
int left_zpos_cnt = 0, right_zpos_cnt = 0;
struct drm_rect crtc_rect = { 0 };
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
+ struct dpu_crtc_mixer *mixer = cstate->mixers;
pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
@@ -1173,6 +1174,16 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
_dpu_crtc_setup_lm_bounds(crtc, crtc_state);
}
+ if (crtc_state->color_mgmt_changed) {
+ for (i = 0; i < cstate->num_mixers; i++) {
+ if (!mixer[i].hw_dspp) {
+ DPU_DEBUG("%s: failed to get dspp for crtc%d
state\n",
+ dpu_crtc->name, crtc->base.id);
+ return -EINVAL;
+ }
+ }
+ }
+
crtc_rect.x2 = mode->hdisplay;
crtc_rect.y2 = mode->vdisplay;
--
2.7.4
[Freedreno] [PATCH 2/3] drm/msm/disp/dpu1: allow dspp selection for all the interfaces
Allow dspps to be populated as a requirement for all the encoder
types it need not be just DSI. If for any encoder the dspp
allocation doesn't go through then there can be an option to
fallback for color features.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..e39b345 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
- struct drm_display_mode *mode)
+ struct drm_display_mode *mode,
+ struct drm_crtc_state *crtc_state)
{
struct msm_display_topology topology = {0};
int i, intf_count = 0;
@@ -563,8 +564,9 @@ static struct msm_display_topology dpu_encoder_get_topology(
* 1 LM, 1 INTF
* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
*
-* Adding color blocks only to primary interface if available in
-* sufficient number
+* dspp blocks are made optional. If RM manager cannot allocate
+* dspp blocks, then reservations will still go through with non dspp
LM's
+* so as to allow color management support via composer fallbacks
*/
if (intf_count == 2)
topology.num_lm = 2;
@@ -573,11 +575,9 @@ static struct msm_display_topology
dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
- if (dpu_kms->catalog->dspp &&
- (dpu_kms->catalog->dspp_count >= topology.num_lm))
- topology.num_dspp = topology.num_lm;
- }
+ if (dpu_kms->catalog->dspp &&
+ (dpu_kms->catalog->dspp_count >= topology.num_lm))
+ topology.num_dspp = topology.num_lm;
topology.num_enc = 0;
topology.num_intf = intf_count;
@@ -643,7 +643,7 @@ static int dpu_encoder_virt_atomic_check(
}
}
- topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
+ topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
crtc_state);
/* Reserve dynamic resources now. */
if (!ret) {
--
2.7.4
[Freedreno] [PATCH 0/3] Allow composer fallbacks for color features
This series will enable color features on sc7280 target which has primary panel as eDP The series removes dspp allocation based on encoder type and allows the datapath reservation even if dspps are not available. The series also adds a check to fail the composition during atomic check , if color management is requested and no dspps are allocated in the datapath. This can allow composer fallbacks for color features if no relevant HW blocks are available. Kalyan Thota (3): drm/msm/disp/dpu1: allow reservation even if dspps are not available. drm/msm/disp/dpu1: allow dspp selection for all the interfaces drm/msm/disp/dpu1: fail atomic check if color feature is requested with no dspp drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 11 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +++- 3 files changed, 27 insertions(+), 10 deletions(-) -- 2.7.4
[Freedreno] [PATCH 1/3] drm/msm/disp/dpu1: allow reservation even if dspps are not available.
if any topology requests for dspps and catalogue doesn't have the
allocation, avoid failing the reservation.
This can pave way to build logic allowing composer fallbacks
for all the color features that are handled in dspp.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 73b3442..c8899ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -343,7 +343,13 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct
dpu_rm *rm,
return true;
idx = lm_cfg->dspp - DSPP_0;
- if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
+
+ if (idx < 0) {
+ DPU_DEBUG("lm doesn't have dspp, ignoring the request %d\n",
lm_cfg->dspp);
+ return true;
+ }
+
+ if (idx >= ARRAY_SIZE(rm->dspp_blks)) {
DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp);
return false;
}
--
2.7.4
Re: [Freedreno] [PATCH] drm/msm: Initialize mode_config earlier
On Mon, Jan 16, 2023 at 08:51:22PM -0600, Bjorn Andersson wrote: > On Fri, Jan 13, 2023 at 10:57:18AM +0200, Dmitry Baryshkov wrote: > > On 13/01/2023 06:23, Dmitry Baryshkov wrote: > > > On 13/01/2023 06:10, Bjorn Andersson wrote: > > > > Invoking drm_bridge_hpd_notify() on a drm_bridge with a HPD-enabled > > > > bridge_connector ends up in drm_bridge_connector_hpd_cb() calling > > > > drm_kms_helper_hotplug_event(), which assumes that the associated > > > > drm_device's mode_config.funcs is a valid pointer. > > > > > > > > But in the MSM DisplayPort driver the HPD enablement happens at bind > > > > time and mode_config.funcs is initialized late in msm_drm_init(). This > > > > means that there's a window for hot plug events to dereference a NULL > > > > mode_config.funcs. > > > > > > > > Move the assignment of mode_config.funcs before the bind, to avoid this > > > > scenario. > > > > > > Cam we make DP driver not to report HPD events until the enable_hpd() > > > was called? I think this is what was fixed by your internal_hpd > > > patchset. > > > > Or to express this in another words: I thought that internal_hpd already > > deferred enabling hpd event reporting till the time when we need it, didn't > > it? > > > > I added a WARN_ON(1) in drm_bridge_hpd_enable() to get a sense of when > this window of "opportunity" opens up, and here's the callstack: > > [ cut here ] > WARNING: CPU: 6 PID: 99 at drivers/gpu/drm/drm_bridge.c:1260 > drm_bridge_hpd_enable+0x48/0x94 [drm] > ... > Call trace: > drm_bridge_hpd_enable+0x48/0x94 [drm] > drm_bridge_connector_enable_hpd+0x30/0x3c [drm_kms_helper] > drm_kms_helper_poll_enable+0xa4/0x114 [drm_kms_helper] > drm_kms_helper_poll_init+0x6c/0x7c [drm_kms_helper] > msm_drm_bind+0x370/0x628 [msm] > try_to_bring_up_aggregate_device+0x170/0x1bc > __component_add+0xb0/0x168 > component_add+0x20/0x2c > dp_display_probe+0x40c/0x468 [msm] > platform_probe+0xb4/0xdc > really_probe+0x13c/0x300 > __driver_probe_device+0xc0/0xec > driver_probe_device+0x48/0x204 > __device_attach_driver+0x124/0x14c > bus_for_each_drv+0x90/0xdc > __device_attach+0xdc/0x1a8 > device_initial_probe+0x20/0x2c > bus_probe_device+0x40/0xa4 > deferred_probe_work_func+0x94/0xd0 > process_one_work+0x1a8/0x3c0 > worker_thread+0x254/0x47c > kthread+0xf8/0x1b8 > ret_from_fork+0x10/0x20 > ---[ end trace ]--- > > As drm_kms_helper_poll_init() is the last thing being called in > msm_drm_init() shifting around the mode_config.func assignment would not > have any impact. > > Perhaps we have shuffled other things around to avoid this bug? Either > way, let's this on hold until further proof that it's still > reproducible. As I've mentioned off list, I haven't hit the apparent race I reported here: https://lore.kernel.org/all/y1efjh11b5uqz...@hovoldconsulting.com/ since moving to 6.2. I did hit it with both 6.0 and 6.1-rc2, but it could very well be that something has changes that fixes (or hides) the issue since. Johan
