Re: [Freedreno] db820c: Input signal Out of range

[Archit Taneja]

On Monday 13 August 2018 06:11 PM, Ricardo Ribalda Delgado wrote:

Hello again


On Mon, Aug 13, 2018 at 2:16 PM Archit Taneja  wrote:




Are you seeing issues only for this mode in particular(1680x1050)? I'm
wondering if the issue is specific to a frequency range.



I have only tried with the native resolution of the panel, which on
both screens in 1680x1050


Result of the tests

Screen 1 (Lenovo)

FAILS: xrandr --output HDMI-1 --mode 1600x1000 --rate 60.01
OK: xrandr --output HDMI-1 --mode 1280x1024 --rate 75.02
FAILS: xrandr --output HDMI-1 --mode 1280x1024 --rate 72.05
FAILS: xrandr --output HDMI-1 --mode 1280x1024 --rate 60.02
OK: xrandr --output HDMI-1 --mode 1440x900  --rate 74.98
OK: xrandr --output HDMI-1 --mode 1440x900  --rate 59.90
FAILS: xrandr --output HDMI-1 --mode 1152x864  --rate 75.00
OK: xrandr --output HDMI-1 --mode 1024x768 --rate 75.03
OK: xrandr --output HDMI-1 --mode 1024x768 --rate 70.07
FAILS: xrandr --output HDMI-1 --mode 1024x768 --rate 60.00
FAILS: xrandr --output HDMI-1 --mode 800x600 --rate 72.19
FAILS: xrandr --output HDMI-1 --mode 800x600 --rate 75.00
OK: xrandr --output HDMI-1 --mode 800x600 --rate 60.32
OK: xrandr --output HDMI-1 --mode 640x480 --rate 75.00
OK: xrandr --output HDMI-1 --mode 640x480 --rate 72.81
FAILS: xrandr --output HDMI-1 --mode 640x480 --rate 66.67
FAILS: xrandr --output HDMI-1 --mode 640x480 --rate 59.94
FAILS:xrandr --output HDMI-1 --mode 720x400 --rate 70.08




Thanks for the info. The number of failed modes is quite bad,
and across a wide range of modes.

Another query: Does the mode fail to set every time you set it?
i.e, if we call the following successively, do we get the
"out of range" issue every time?

xrandr --output HDMI-1 --mode 1600x1000 --rate 60.01

I'd looped in some friends who can help verify if the
driver is configuring the regs correctly.

Thanks,
Archit



[16.216] (II) modeset(0): EDID (in hex):
[16.216] (II) modeset(0): 000030ae0c0a01010101
[16.216] (II) modeset(0): 1e140103802f1e78eedc55a359489e24
[16.216] (II) modeset(0): 115054bdcf00714f8180818c9500950f
[16.216] (II) modeset(0): a900b300010126399030621a274068b0
[16.216] (II) modeset(0): 3600da28111a00fd00324b1e
[16.216] (II) modeset(0): 5311000a20202020202000fc004c
[16.216] (II) modeset(0): 32323530702057696465202000ff
[16.217] (II) modeset(0): 003656365637350a2020202000a8
[16.217] (II) modeset(0): Printing probed modes for output HDMI-1
[16.217] (II) modeset(0): Modeline "1680x1050"x60.0  146.30  1680
1784 1960 2240  1050 1053 1059 1089 +hsync -vsync (65.3 kHz eP)
[16.217] (II) modeset(0): Modeline "1600x1000"x60.0  133.16  1600
1704 1872 2144  1000 1001 1004 1035 -hsync +vsync (62.1 kHz)
[16.217] (II) modeset(0): Modeline "1280x1024"x75.0  135.00  1280
1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
[16.217] (II) modeset(0): Modeline "1280x1024"x72.0  132.84  1280
1368 1504 1728  1024 1025 1028 1067 -hsync +vsync (76.9 kHz)
[16.217] (II) modeset(0): Modeline "1280x1024"x60.0  108.00  1280
1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
[16.217] (II) modeset(0): Modeline "1440x900"x75.0  136.75  1440
1536 1688 1936  900 903 909 942 -hsync +vsync (70.6 kHz e)
[16.217] (II) modeset(0): Modeline "1440x900"x59.9   88.75  1440
1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
[16.217] (II) modeset(0): Modeline "1152x864"x75.0  108.00  1152
1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
[16.217] (II) modeset(0): Modeline "1024x768"x75.0   78.75  1024
1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
[16.217] (II) modeset(0): Modeline "1024x768"x70.1   75.00  1024
1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
[16.217] (II) modeset(0): Modeline "1024x768"x60.0   65.00  1024
1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
[16.217] (II) modeset(0): Modeline "800x600"x72.2   50.00  800 856
976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
[16.217] (II) modeset(0): Modeline "800x600"x75.0   49.50  800 816
896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
[16.217] (II) modeset(0): Modeline "800x600"x60.3   40.00  800 840
968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
[16.217] (II) modeset(0): Modeline "640x480"x75.0   31.50  640 656
720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
[16.217] (II) modeset(0): Modeline "640x480"x72.8   31.50  640 664
704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
[16.217] (II) modeset(0): Modeline "640x480"x66.7   30.24  640 704
768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
[16.217] (II) modeset(0): Modeline "640x480"x59.9   25.18  640 656
752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
[16.217] (II) modese

Re: [Freedreno] db820c: Input signal Out of range

[Archit Taneja]

Hi,



On Monday 13 August 2018 02:24 PM, Ricardo Ribalda Delgado wrote:

Hi Archit
On Sun, Aug 12, 2018 at 9:47 AM Archit Taneja  wrote:


Hi,

On Friday 10 August 2018 12:08 PM, Ricardo Ribalda Delgado wrote:

Hello

I have a screen that via edid expects the following modeline by
default via detailed mode:

Modeline "1680x1050"x60.0  146.30  1680 1784 1960 2240  1050 1053 1059
1089 +hsync -vsync

When the card is configured to that modeline the screen cannot output
the image and shows the following error message: Input signal out of
range.

I have tried with a different card and that exact modeline:

xrandr --newmode fast 146.30  1680 1784 1960 2240  1050 1053 1059 1089
+hsync -vsync
xrandr --addmode HDMI-1 slow
xrandr --output HDMI-1 --mode fast

and the screen works just fine.


If I just tweak down a bit the clock:
xrandr --newmode slow 146.25  1680 1784 1960 2240  1050 1053 1059 1089
+hsync -vsync
the screen shows an image as expected.

I believe that there might be a misscalculation on the pll code. And I
am printing the debug info from:
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

The configuration that fails shows:

[  138.553168] VCO freq: 877800
[  138.553172] fdata: 146300
[  138.553187] pix_clk: 14630
[  138.555447] tmds clk: 14630
[  138.558336] HSCLK_SEL: 1
[  138.561277] DEC_START: 114
[  138.564316] DIV_FRAC_START: 311296
[  138.567080] PLL_CPCTRL: 11
[  138.569614] PLL_RCTRL: 22
[  138.572996] PLL_CCTRL: 40
[  138.575698] INTEGLOOP_GAIN: 256
[  138.578366] TX_BAND: 0
[  138.580986] PLL_CMP: 7802
[  138.583936] com_svs_mode_clk_sel = 0x2
[  138.586351] com_hsclk_sel = 0x21
[  138.589067] com_lock_cmp_en = 0x0
[  138.592704] com_pll_cctrl_mode0 = 0x28
[  138.596089] com_pll_rctrl_mode0 = 0x16
[  138.599286] com_cp_ctrl_mode0 = 0xb
[  138.602955] com_dec_start_mode0 = 0x72
[  138.606678] com_div_frac_start1_mode0 = 0x0
[  138.610064] com_div_frac_start2_mode0 = 0xc0
[  138.613894] com_div_frac_start3_mode0 = 0x4
[  138.617964] com_integloop_gain0_mode0 = 0x0
[  138.622478] com_integloop_gain1_mode0 = 0x1
[  138.626393] com_lock_cmp1_mode0 = 0x7a
[  138.630550] com_lock_cmp2_mode0 = 0x1e
[  138.634719] com_lock_cmp3_mode0 = 0x0
[  138.638545] com_core_clk_en = 0x2c
[  138.642271] com_coreclk_div = 0x5
[  138.646001] phy_mode = 0x0
[  138.649308] tx_l0_lane_mode = 0x43
[  138.652684] tx_l2_lane_mode = 0x43
[  138.655275] tx_l0_tx_band = 0x4
[  138.658679] tx_l0_tx_drv_lvl = 0x25
[  138.662070] tx_l0_tx_emp_post1_lvl = 0x23
[  138.665101] tx_l0_vmode_ctrl1 = 0x0
[  138.668571] tx_l0_vmode_ctrl2 = 0xd
[  138.672747] tx_l1_tx_band = 0x4
[  138.676037] tx_l1_tx_drv_lvl = 0x25
[  138.679493] tx_l1_tx_emp_post1_lvl = 0x23
[  138.682633] tx_l1_vmode_ctrl1 = 0x0
[  138.686117] tx_l1_vmode_ctrl2 = 0xd
[  138.690272] tx_l2_tx_band = 0x4
[  138.693571] tx_l2_tx_drv_lvl = 0x25
[  138.697050] tx_l2_tx_emp_post1_lvl = 0x23
[  138.700168] tx_l2_vmode_ctrl1 = 0x0
[  138.703641] tx_l2_vmode_ctrl2 = 0xd
[  138.707816] tx_l3_tx_band = 0x4
[  138.711092] tx_l3_tx_drv_lvl = 0x25
[  138.714577] tx_l3_tx_emp_post1_lvl = 0x23
[  138.717705] tx_l3_vmode_ctrl1 = 0x0
[  138.721182] tx_l3_vmode_ctrl2 = 0x0

and the configuration that works:

[   62.936970] VCO freq: 877500
[   62.936976] fdata: 146250
[   62.936990] pix_clk: 14625
[   62.939250] tmds clk: 14625
[   62.942175] HSCLK_SEL: 1
[   62.945095] DEC_START: 114
[   62.948117] DIV_FRAC_START: 270336
[   62.950881] PLL_CPCTRL: 11
[   62.953421] PLL_RCTRL: 22
[   62.956798] PLL_CCTRL: 40
[   62.959475] INTEGLOOP_GAIN: 256
[   62.962179] TX_BAND: 0
[   62.964785] PLL_CMP: 7799
[   62.967738] com_svs_mode_clk_sel = 0x2
[   62.970153] com_hsclk_sel = 0x21
[   62.972862] com_lock_cmp_en = 0x0
[   62.976506] com_pll_cctrl_mode0 = 0x28
[   62.979893] com_pll_rctrl_mode0 = 0x16
[   62.983088] com_cp_ctrl_mode0 = 0xb
[   62.986749] com_dec_start_mode0 = 0x72
[   62.990480] com_div_frac_start1_mode0 = 0x0
[   62.993868] com_div_frac_start2_mode0 = 0x20
[   62.997688] com_div_frac_start3_mode0 = 0x4
[   63.001769] com_integloop_gain0_mode0 = 0x0
[   63.006281] com_integloop_gain1_mode0 = 0x1
[   63.010189] com_lock_cmp1_mode0 = 0x77
[   63.014354] com_lock_cmp2_mode0 = 0x1e
[   63.018521] com_lock_cmp3_mode0 = 0x0
[   63.022338] com_core_clk_en = 0x2c
[   63.026072] com_coreclk_div = 0x5
[   63.029804] phy_mode = 0x0
[   63.033103] tx_l0_lane_mode = 0x43
[   63.036488] tx_l2_lane_mode = 0x43
[   63.039078] tx_l0_tx_band = 0x4
[   63.042479] tx_l0_tx_drv_lvl = 0x25
[   63.045864] tx_l0_tx_emp_post1_lvl = 0x23
[   63.048901] tx_l0_vmode_ctrl1 = 0x0
[   63.052375] tx_l0_vmode_ctrl2 = 0xd
[   63.056541] tx_l1_tx_band = 0x4
[   63.059840] tx_l1_tx_drv_lvl = 0x25
[   63.063295] tx_l1_tx_emp_post1_lvl = 0x23
[   63.066437] tx_l1_vmode_ctrl1 = 0x0
[   63.069908] tx_l1_vmode_ctrl2 = 0xd
[   63.074075] tx_l2_tx_band = 0x4
[   63.077373] tx_l2_tx_drv_lvl = 0x25
[   63.080844] tx_l2_tx_emp_post1_lvl = 0x23
[   63.083971] tx_l2_vmode_ctrl1 = 0x0
[  

Re: [Freedreno] db820c: Input signal Out of range

[Archit Taneja]

Hi,

On Friday 10 August 2018 12:08 PM, Ricardo Ribalda Delgado wrote:

Hello

I have a screen that via edid expects the following modeline by
default via detailed mode:

Modeline "1680x1050"x60.0  146.30  1680 1784 1960 2240  1050 1053 1059
1089 +hsync -vsync

When the card is configured to that modeline the screen cannot output
the image and shows the following error message: Input signal out of
range.

I have tried with a different card and that exact modeline:

xrandr --newmode fast 146.30  1680 1784 1960 2240  1050 1053 1059 1089
+hsync -vsync
xrandr --addmode HDMI-1 slow
xrandr --output HDMI-1 --mode fast

and the screen works just fine.


If I just tweak down a bit the clock:
xrandr --newmode slow 146.25  1680 1784 1960 2240  1050 1053 1059 1089
+hsync -vsync
the screen shows an image as expected.

I believe that there might be a misscalculation on the pll code. And I
am printing the debug info from:
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

The configuration that fails shows:

[  138.553168] VCO freq: 877800
[  138.553172] fdata: 146300
[  138.553187] pix_clk: 14630
[  138.555447] tmds clk: 14630
[  138.558336] HSCLK_SEL: 1
[  138.561277] DEC_START: 114
[  138.564316] DIV_FRAC_START: 311296
[  138.567080] PLL_CPCTRL: 11
[  138.569614] PLL_RCTRL: 22
[  138.572996] PLL_CCTRL: 40
[  138.575698] INTEGLOOP_GAIN: 256
[  138.578366] TX_BAND: 0
[  138.580986] PLL_CMP: 7802
[  138.583936] com_svs_mode_clk_sel = 0x2
[  138.586351] com_hsclk_sel = 0x21
[  138.589067] com_lock_cmp_en = 0x0
[  138.592704] com_pll_cctrl_mode0 = 0x28
[  138.596089] com_pll_rctrl_mode0 = 0x16
[  138.599286] com_cp_ctrl_mode0 = 0xb
[  138.602955] com_dec_start_mode0 = 0x72
[  138.606678] com_div_frac_start1_mode0 = 0x0
[  138.610064] com_div_frac_start2_mode0 = 0xc0
[  138.613894] com_div_frac_start3_mode0 = 0x4
[  138.617964] com_integloop_gain0_mode0 = 0x0
[  138.622478] com_integloop_gain1_mode0 = 0x1
[  138.626393] com_lock_cmp1_mode0 = 0x7a
[  138.630550] com_lock_cmp2_mode0 = 0x1e
[  138.634719] com_lock_cmp3_mode0 = 0x0
[  138.638545] com_core_clk_en = 0x2c
[  138.642271] com_coreclk_div = 0x5
[  138.646001] phy_mode = 0x0
[  138.649308] tx_l0_lane_mode = 0x43
[  138.652684] tx_l2_lane_mode = 0x43
[  138.655275] tx_l0_tx_band = 0x4
[  138.658679] tx_l0_tx_drv_lvl = 0x25
[  138.662070] tx_l0_tx_emp_post1_lvl = 0x23
[  138.665101] tx_l0_vmode_ctrl1 = 0x0
[  138.668571] tx_l0_vmode_ctrl2 = 0xd
[  138.672747] tx_l1_tx_band = 0x4
[  138.676037] tx_l1_tx_drv_lvl = 0x25
[  138.679493] tx_l1_tx_emp_post1_lvl = 0x23
[  138.682633] tx_l1_vmode_ctrl1 = 0x0
[  138.686117] tx_l1_vmode_ctrl2 = 0xd
[  138.690272] tx_l2_tx_band = 0x4
[  138.693571] tx_l2_tx_drv_lvl = 0x25
[  138.697050] tx_l2_tx_emp_post1_lvl = 0x23
[  138.700168] tx_l2_vmode_ctrl1 = 0x0
[  138.703641] tx_l2_vmode_ctrl2 = 0xd
[  138.707816] tx_l3_tx_band = 0x4
[  138.711092] tx_l3_tx_drv_lvl = 0x25
[  138.714577] tx_l3_tx_emp_post1_lvl = 0x23
[  138.717705] tx_l3_vmode_ctrl1 = 0x0
[  138.721182] tx_l3_vmode_ctrl2 = 0x0

and the configuration that works:

[   62.936970] VCO freq: 877500
[   62.936976] fdata: 146250
[   62.936990] pix_clk: 14625
[   62.939250] tmds clk: 14625
[   62.942175] HSCLK_SEL: 1
[   62.945095] DEC_START: 114
[   62.948117] DIV_FRAC_START: 270336
[   62.950881] PLL_CPCTRL: 11
[   62.953421] PLL_RCTRL: 22
[   62.956798] PLL_CCTRL: 40
[   62.959475] INTEGLOOP_GAIN: 256
[   62.962179] TX_BAND: 0
[   62.964785] PLL_CMP: 7799
[   62.967738] com_svs_mode_clk_sel = 0x2
[   62.970153] com_hsclk_sel = 0x21
[   62.972862] com_lock_cmp_en = 0x0
[   62.976506] com_pll_cctrl_mode0 = 0x28
[   62.979893] com_pll_rctrl_mode0 = 0x16
[   62.983088] com_cp_ctrl_mode0 = 0xb
[   62.986749] com_dec_start_mode0 = 0x72
[   62.990480] com_div_frac_start1_mode0 = 0x0
[   62.993868] com_div_frac_start2_mode0 = 0x20
[   62.997688] com_div_frac_start3_mode0 = 0x4
[   63.001769] com_integloop_gain0_mode0 = 0x0
[   63.006281] com_integloop_gain1_mode0 = 0x1
[   63.010189] com_lock_cmp1_mode0 = 0x77
[   63.014354] com_lock_cmp2_mode0 = 0x1e
[   63.018521] com_lock_cmp3_mode0 = 0x0
[   63.022338] com_core_clk_en = 0x2c
[   63.026072] com_coreclk_div = 0x5
[   63.029804] phy_mode = 0x0
[   63.033103] tx_l0_lane_mode = 0x43
[   63.036488] tx_l2_lane_mode = 0x43
[   63.039078] tx_l0_tx_band = 0x4
[   63.042479] tx_l0_tx_drv_lvl = 0x25
[   63.045864] tx_l0_tx_emp_post1_lvl = 0x23
[   63.048901] tx_l0_vmode_ctrl1 = 0x0
[   63.052375] tx_l0_vmode_ctrl2 = 0xd
[   63.056541] tx_l1_tx_band = 0x4
[   63.059840] tx_l1_tx_drv_lvl = 0x25
[   63.063295] tx_l1_tx_emp_post1_lvl = 0x23
[   63.066437] tx_l1_vmode_ctrl1 = 0x0
[   63.069908] tx_l1_vmode_ctrl2 = 0xd
[   63.074075] tx_l2_tx_band = 0x4
[   63.077373] tx_l2_tx_drv_lvl = 0x25
[   63.080844] tx_l2_tx_emp_post1_lvl = 0x23
[   63.083971] tx_l2_vmode_ctrl1 = 0x0
[   63.087428] tx_l2_vmode_ctrl2 = 0xd
[   63.091609] tx_l3_tx_band = 0x4
[   63.094906] tx_l3_tx_drv_lvl = 0x25
[   63.098379] tx_l3_tx_emp_post1_lvl = 

Re: [Freedreno] [PATCH v2] drm/msm/display: negative x/y in cursor move

[Archit Taneja]

On Wednesday 25 July 2018 08:40 PM, Carsten Behling wrote:

Hi,


Thanks for the patch. Could you tell how to reproduce this issue
on a db410c?

 >

I was playing with xrandr's --rotate and --reflect options to get
a rotated output, but wasn't able to generate negative x/y
co-ordinates. I'm using linaro's debian userspace, running lxqt.


I used Yocto Rocko from 96Boards

https://github.com/96boards/oe-rpb-manifest/tree/rocko

MACHINE=dragonboard-410c
DISTRO=rpb

rpb-desktop-image

Connect HDMI monitor and USB mouse, then

1.) Just boot. Wait for X-Server up.
2.) From my serial console:
      DISPLAY=:0.0 xrandr -o 2
3.) Try to move the mouse to the upper (the rotated lower) border.

Interesting to know that your debian user space is ok. The yocto X11 
configuration is very basic.

There may be a X11 configuration or extension that does the trick on Debian.


Thanks, I'll give this a try.

The patch looks good, anyway. Rob's queued it for msm-next.

Archit



Therefore, I asked the X11 people where to fix:

https://www.spinics.net/lists/xorg/msg58969.html

Best regards
-Carsten


2018-07-24 19:33 GMT+02:00 Archit Taneja <mailto:arch...@codeaurora.org>>:


Hi,

On Tuesday 17 July 2018 04:33 AM, Carsten Behling wrote:

modesetting X11 driver may provide negative x/y cordinates in
mdp5_crtc_cursor_move call when rotation is enabled.

Cursor buffer can overlap down to its negative width/height.

ROI has to be recalculated for negative x/y indicating using the
lower/right corner of the cursor buffer and hotspot must be set
in MDP5_LM_CURSOR_XY_SRC_Y MDP5_LM_CURSOR_XY_SRC_X.


Thanks for the patch. Could you tell how to reproduce this issue
on a db410c?

I was playing with xrandr's --rotate and --reflect options to get
a rotated output, but wasn't able to generate negative x/y
co-ordinates. I'm using linaro's debian userspace, running lxqt.

Thanks,
Archit



Signed-off-by: Carsten Behling mailto:carsten.behl...@gmail.com>>
---
Changes in v2:
- fixed format specifier in debug message

   drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 51
++-
   1 file changed, 43 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 10271359789e..a7f4a6688fec 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -65,7 +65,7 @@ struct mdp5_crtc {
                 struct drm_gem_object *scanout_bo;
                 uint64_t iova;
                 uint32_t width, height;
-               uint32_t x, y;
+               int x, y;
         } cursor;
   };
   #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
@@ -760,20 +760,31 @@ static void get_roi(struct drm_crtc *crtc,
uint32_t *roi_w, uint32_t *roi_h)
          * Cursor Region Of Interest (ROI) is a plane read from
cursor
          * buffer to render. The ROI region is determined by
the visibility of
          * the cursor point. In the default Cursor image the
cursor point will
-        * be at the top left of the cursor image, unless it is
specified
-        * otherwise using hotspot feature.
+        * be at the top left of the cursor image.
          *
+        * Without rotation:
          * If the cursor point reaches the right (xres - x <
cursor.width) or
          * bottom (yres - y < cursor.height) boundary of the
screen, then ROI
          * width and ROI height need to be evaluated to crop
the cursor image
          * accordingly.
          * (xres-x) will be new cursor width when x > (xres -
cursor.width)
          * (yres-y) will be new cursor height when y > (yres -
cursor.height)
+        *
+        * With rotation:
+        * We get negative x and/or y coordinates.
+        * (cursor.width - abs(x)) will be new cursor width when
x < 0
+        * (cursor.height - abs(y)) will be new cursor width
when y < 0
          */
-       *roi_w = min(mdp5_crtc->cursor.width, xres -
+       if (mdp5_crtc->cursor.x >= 0)
+               *roi_w = min(mdp5_crtc->cursor.width, xres -
                         mdp5_crtc->cursor.x);
-       *roi_h = min(mdp5_crtc->cursor.height, yres -
+       else
+               *roi_w = mdp5_crtc->cursor.width -
abs(mdp5_crtc->cursor.x);
+       if (mdp5_crtc->cursor.y >= 0)
+               *roi_h = min(mdp5_crtc->curso

Re: [Freedreno] [PATCH v2] drm/msm/display: negative x/y in cursor move

[Archit Taneja]

Hi,

On Tuesday 17 July 2018 04:33 AM, Carsten Behling wrote:

modesetting X11 driver may provide negative x/y cordinates in
mdp5_crtc_cursor_move call when rotation is enabled.

Cursor buffer can overlap down to its negative width/height.

ROI has to be recalculated for negative x/y indicating using the
lower/right corner of the cursor buffer and hotspot must be set
in MDP5_LM_CURSOR_XY_SRC_Y MDP5_LM_CURSOR_XY_SRC_X.


Thanks for the patch. Could you tell how to reproduce this issue
on a db410c?

I was playing with xrandr's --rotate and --reflect options to get
a rotated output, but wasn't able to generate negative x/y
co-ordinates. I'm using linaro's debian userspace, running lxqt.

Thanks,
Archit



Signed-off-by: Carsten Behling 
---
Changes in v2:
- fixed format specifier in debug message

  drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 51 ++-
  1 file changed, 43 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 10271359789e..a7f4a6688fec 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -65,7 +65,7 @@ struct mdp5_crtc {
struct drm_gem_object *scanout_bo;
uint64_t iova;
uint32_t width, height;
-   uint32_t x, y;
+   int x, y;
} cursor;
  };
  #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
@@ -760,20 +760,31 @@ static void get_roi(struct drm_crtc *crtc, uint32_t 
*roi_w, uint32_t *roi_h)
 * Cursor Region Of Interest (ROI) is a plane read from cursor
 * buffer to render. The ROI region is determined by the visibility of
 * the cursor point. In the default Cursor image the cursor point will
-* be at the top left of the cursor image, unless it is specified
-* otherwise using hotspot feature.
+* be at the top left of the cursor image.
 *
+* Without rotation:
 * If the cursor point reaches the right (xres - x < cursor.width) or
 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 * width and ROI height need to be evaluated to crop the cursor image
 * accordingly.
 * (xres-x) will be new cursor width when x > (xres - cursor.width)
 * (yres-y) will be new cursor height when y > (yres - cursor.height)
+*
+* With rotation:
+* We get negative x and/or y coordinates.
+* (cursor.width - abs(x)) will be new cursor width when x < 0
+* (cursor.height - abs(y)) will be new cursor width when y < 0
 */
-   *roi_w = min(mdp5_crtc->cursor.width, xres -
+   if (mdp5_crtc->cursor.x >= 0)
+   *roi_w = min(mdp5_crtc->cursor.width, xres -
mdp5_crtc->cursor.x);
-   *roi_h = min(mdp5_crtc->cursor.height, yres -
+   else
+   *roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x);
+   if (mdp5_crtc->cursor.y >= 0)
+   *roi_h = min(mdp5_crtc->cursor.height, yres -
mdp5_crtc->cursor.y);
+   else
+   *roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y);
  }
  
  static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)

@@ -783,7 +794,7 @@ static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
struct mdp5_kms *mdp5_kms = get_kms(crtc);
const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
uint32_t blendcfg, stride;
-   uint32_t x, y, width, height;
+   uint32_t x, y, src_x, src_y, width, height;
uint32_t roi_w, roi_h;
int lm;
  
@@ -800,6 +811,26 @@ static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
  
  	get_roi(crtc, _w, _h);
  
+	/* If cusror buffer overlaps due to rotation on the

+* upper or left screen border the pixel offset inside
+* the cursor buffer of the ROI is the positive overlap
+* distance.
+*/
+   if (mdp5_crtc->cursor.x < 0) {
+   src_x = abs(mdp5_crtc->cursor.x);
+   x = 0;
+   } else {
+   src_x = 0;
+   }
+   if (mdp5_crtc->cursor.y < 0) {
+   src_y = abs(mdp5_crtc->cursor.y);
+   y = 0;
+   } else {
+   src_y = 0;
+   }
+   DBG("%s: x=%u, y=%u roi_w=%u roi_h=%u src_x=%u src_y=%u",
+   crtc->name, x, y, roi_w, roi_h, src_x, src_y);
+
mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB));
@@ -812,6 +843,9 @@ static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
MDP5_LM_CURSOR_START_XY_Y_START(y) |
MDP5_LM_CURSOR_START_XY_X_START(x));
+   mdp5_write(mdp5_kms, 

Re: [Freedreno] [PATCH 11/21] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor

[Archit Taneja]

On Monday 09 July 2018 11:01 PM, Sean Paul wrote:

From: Abhinav Kumar 

Make the pclk_rate u64 to accommodate higher pixel clock
rates.

Changes in v4:
  - fixed commit message

Signed-off-by: Abhinav Kumar 
Signed-off-by: Sean Paul 
---
  drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++---
  1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 671039b7b75b..73587e731a23 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, 
bool is_dual_dsi)
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
-   u32 pclk_rate;
+   u64 pclk_rate;
+   u64 pclk_bpp;
  


Minor nit, I don't think we need to change pclk_rate to u64. A u32 can
hold up to a 2.14 Ghz pixel clock, which we're still quite far away
from in real life. u64 for pclk_bpp is right, though.

Thanks,
Archit


if (!mode) {
pr_err("%s: mode not set\n", __func__);
@@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host 
*msm_host, bool is_dual_dsi)
if (is_dual_dsi)
pclk_rate /= 2;
  
+	pclk_bpp = pclk_rate * bpp;

if (lanes > 0) {
-   msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+   do_div(pclk_bpp, (8 * lanes));
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
-   msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+   do_div(pclk_bpp, 8);
}
msm_host->pixel_clk_rate = pclk_rate;
+   msm_host->byte_clk_rate = pclk_bpp;
  
  	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,

msm_host->byte_clk_rate);


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Re: [Freedreno] [PATCH 09/21] drm/msm/mdp5: subclass msm_mdss for mdp5

[Archit Taneja]

On Monday 09 July 2018 11:01 PM, Sean Paul wrote:

From: Rajesh Yadav 

SoCs having mdp5 or dpu have identical tree like
device hierarchy where MDSS top level wrapper manages
common power resources for all child devices.

Subclass msm_mdss so that msm_mdss includes common defines
and mdp5/dpu mdss derivations to include any extensions.

Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.

This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.


Reviewed-by: Archit Taneja 



Changes in v3:
- none

Changes in v2:
- fixed indentation for irq_domain_add_linear call (Sean Paul)

Signed-off-by: Rajesh Yadav 
Reviewed-by: Sean Paul 
[seanpaul rebased on msm-next and resolved conflicts]
Signed-off-by: Sean Paul 
---
  drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 --
  drivers/gpu/drm/msm/msm_drv.c |  22 +++-
  drivers/gpu/drm/msm/msm_kms.h |  17 ++-
  3 files changed, 109 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
index f2a0db7a8a03..1cc4e57f0226 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
@@ -20,12 +20,10 @@
  #include "msm_drv.h"
  #include "mdp5_kms.h"
  
-/*

- * If needed, this can become more specific: something like struct mdp5_mdss,
- * which contains a 'struct msm_mdss base' member.
- */
-struct msm_mdss {
-   struct drm_device *dev;
+#define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
+
+struct mdp5_mdss {
+   struct msm_mdss base;
  
  	void __iomem *mmio, *vbif;
  
@@ -41,22 +39,22 @@ struct msm_mdss {

} irqcontroller;
  };
  
-static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)

+static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
  {
-   msm_writel(data, mdss->mmio + reg);
+   msm_writel(data, mdp5_mdss->mmio + reg);
  }
  
-static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)

+static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
  {
-   return msm_readl(mdss->mmio + reg);
+   return msm_readl(mdp5_mdss->mmio + reg);
  }
  
  static irqreturn_t mdss_irq(int irq, void *arg)

  {
-   struct msm_mdss *mdss = arg;
+   struct mdp5_mdss *mdp5_mdss = arg;
u32 intr;
  
-	intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);

+   intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
  
  	VERB("intr=%08x", intr);
  
@@ -64,7 +62,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)

irq_hw_number_t hwirq = fls(intr) - 1;
  
  		generic_handle_irq(irq_find_mapping(

-   mdss->irqcontroller.domain, hwirq));
+   mdp5_mdss->irqcontroller.domain, hwirq));
intr &= ~(1 << hwirq);
}
  
@@ -84,19 +82,19 @@ static irqreturn_t mdss_irq(int irq, void *arg)
  
  static void mdss_hw_mask_irq(struct irq_data *irqd)

  {
-   struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+   struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
  
  	smp_mb__before_atomic();

-   clear_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+   clear_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
  }
  
  static void mdss_hw_unmask_irq(struct irq_data *irqd)

  {
-   struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+   struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
  
  	smp_mb__before_atomic();

-   set_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+   set_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
  }
  
@@ -109,13 +107,13 @@ static struct irq_chip mdss_hw_irq_chip = {

  static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
 irq_hw_number_t hwirq)
  {
-   struct msm_mdss *mdss = d->host_data;
+   struct mdp5_mdss *mdp5_mdss = d->host_data;
  
  	if (!(VALID_IRQS & (1 << hwirq)))

return -EPERM;
  
  	irq_set_chip_and_handler(irq, _hw_irq_chip, handle_level_irq);

-   irq_set_chip_data(irq, mdss);
+   irq_set_chip_data(irq, mdp5_mdss);
  
  	return 0;

  }
@@ -126,90 +124,99 @@ static const struct irq_domain_ops mdss_hw_irqdomain_ops 
= {
  };
  
  
-static int mdss_irq_domain_init(struct msm_mdss *mdss)

+static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
  {
-   struct device *dev = mdss->dev->dev;
+   struct device *dev = mdp5_mdss->base.dev->dev;
struct irq_domain *d;
  
  	d = irq_domain_add_linear(dev->of_node, 32, _hw_irqdomain_ops,

- mdss);
+ mdp5_mdss);
if (!d) {

Re: [Freedreno] [PATCH 07/21] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll

[Archit Taneja]

On Monday 09 July 2018 11:01 PM, Sean Paul wrote:

From: Rajesh Yadav 

postdiv_lock spinlock was used before initialization
for 10nm pll. It causes following spin_bug:
"BUG: spinlock bad magic on CPU#0".
Initialize spinlock before its usage.


Reviewed-by: Archit Taneja 



Signed-off-by: Rajesh Yadav 
Signed-off-by: Sean Paul 
---
  drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index c4c37a7df637..4c03f0b7343e 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -798,6 +798,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct 
platform_device *pdev, int id)
return ERR_PTR(-ENOMEM);
}
  
+	spin_lock_init(_10nm->postdiv_lock);

+
pll = _10nm->base;
pll->min_rate = 10UL;
pll->max_rate = 35UL;


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Re: [Freedreno] [PATCH 05/21] drm/msm/dsi: adjust dsi timing for dual dsi mode

[Archit Taneja]

On Monday 09 July 2018 11:01 PM, Sean Paul wrote:

From: Chandan Uddaraju 

For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.


Reviewed-by: Archit Taneja 



Changes in V2:
--Removed Change-Id from the commit text tags.

Changes in V3:
--Instead of adjusting the DRM mode structure, divide
   the clocks and horizontal timings in DSI host just
   before configuring the values.

Signed-off-by: Chandan Uddaraju 
Signed-off-by: Sean Paul 
---
  drivers/gpu/drm/msm/dsi/dsi.h |  6 ++-
  drivers/gpu/drm/msm/dsi/dsi_host.c| 55 +--
  drivers/gpu/drm/msm/dsi/dsi_manager.c |  7 ++--
  3 files changed, 52 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 70d9a9a47acd..01c38f67d699 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -162,7 +162,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host 
*host,
  int msm_dsi_host_enable(struct mipi_dsi_host *host);
  int msm_dsi_host_disable(struct mipi_dsi_host *host);
  int msm_dsi_host_power_on(struct mipi_dsi_host *host,
-   struct msm_dsi_phy_shared_timings *phy_shared_timings);
+   struct msm_dsi_phy_shared_timings *phy_shared_timings,
+   bool is_dual_dsi);
  int msm_dsi_host_power_off(struct mipi_dsi_host *host);
  int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
struct drm_display_mode *mode);
@@ -175,7 +176,8 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll);
  void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
  void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
-   struct msm_dsi_phy_clk_request *clk_req);
+   struct msm_dsi_phy_clk_request *clk_req,
+   bool is_dual_dsi);
  void msm_dsi_host_destroy(struct mipi_dsi_host *host);
  int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 2f1a2780658a..671039b7b75b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -118,6 +118,7 @@ struct msm_dsi_host {
struct clk *byte_intf_clk;
  
  	u32 byte_clk_rate;

+   u32 pixel_clk_rate;
u32 esc_clk_rate;
  
  	/* DSI v2 specific clocks */

@@ -511,7 +512,7 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host 
*msm_host)
goto error;
}
  
-	ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);

+   ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -592,7 +593,7 @@ static int dsi_link_clk_enable_v2(struct msm_dsi_host 
*msm_host)
goto error;
}
  
-	ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);

+   ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -662,7 +663,7 @@ static void dsi_link_clk_disable(struct msm_dsi_host 
*msm_host)
}
  }
  
-static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)

+static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
  {
struct drm_display_mode *mode = msm_host->mode;
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
@@ -676,14 +677,28 @@ static int dsi_calc_clk_rate(struct msm_dsi_host 
*msm_host)
}
  
  	pclk_rate = mode->clock * 1000;

+
+   /*
+* For dual DSI mode, the current DRM mode has
+* the complete width of the panel. Since, the complete
+* panel is driven by two DSI controllers, the
+* the clock rates have to be split between
+* the two dsi controllers. Adjust the byte and
+* pixel clock rates for each dsi host accordingly.
+*/
+   if (is_dual_dsi)
+   pclk_rate /= 2;
+
if (lanes > 0) {
msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
}
+   msm_host->pixel_clk_rate = pclk_rate;
  
-	DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);

+   DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
+   msm_host->byte_clk_rate);
  
  	msm_host->esc_clk_rate = clk_get_rate(

Re: [Freedreno] [DPU PATCH] drm/msm/dsi: add only dsi nodes with a valid device to list

[Archit Taneja]

On Saturday 16 June 2018 11:35 AM, Abhinav Kumar wrote:

Before adding a DSI node to the private list check if the
node has a valid device connected to it through an endpoint.

This is required in cases where the chipset supports multiple
DSI hosts but only one of them is being used.

In the current implementation even inactive nodes get added
resulting in creation of redundant connectors.


Reviewed-by: Archit Taneja 



Signed-off-by: Abhinav Kumar 
---
  drivers/gpu/drm/msm/dsi/dsi.c  |  6 +-
  drivers/gpu/drm/msm/dsi/dsi.h  |  1 +
  drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++
  3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index b744bcc..46a4906 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -120,7 +120,11 @@ static int dsi_bind(struct device *dev, struct device 
*master, void *data)
if (IS_ERR(msm_dsi))
return PTR_ERR(msm_dsi);
  
-	priv->dsi[msm_dsi->id] = msm_dsi;

+   /* Add only the host which has a device attached to it */
+   if (msm_dsi_has_valid_device(msm_dsi->host)) {
+   pr_info("id = %d has valid device\n", msm_dsi->id);
+   priv->dsi[msm_dsi->id] = msm_dsi;
+   }
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 70d9a9a..aa198ef 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -180,6 +180,7 @@ void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host 
*host,
  int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
  int msm_dsi_host_init(struct msm_dsi *msm_dsi);
+bool msm_dsi_has_valid_device(struct mipi_dsi_host *host);
  int msm_dsi_runtime_suspend(struct device *dev);
  int msm_dsi_runtime_resume(struct device *dev);
  
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c

index 2f1a278..25d65e5 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -470,6 +470,16 @@ static void dsi_bus_clk_disable(struct msm_dsi_host 
*msm_host)
clk_disable_unprepare(msm_host->bus_clks[i]);
  }
  
+bool msm_dsi_has_valid_device(struct mipi_dsi_host *host)

+{
+   struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+
+   if (msm_host->device_node)
+   return true;
+
+   return false;
+}
+
  int msm_dsi_runtime_suspend(struct device *dev)
  {
struct platform_device *pdev = to_platform_device(dev);


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Re: [Freedreno] [DPU PATCH] drm/msm/dsi: set encoder mode for DRM bridge explicitly

[Archit Taneja]

On Saturday 16 June 2018 11:26 AM, Abhinav Kumar wrote:

Currently, DRM bridge for DPU relies on the default video
mode setting to set the encoder mode.

Add an explicit call to set the encoder mode for bridges.


Reviewed-by: Archit Taneja 



Signed-off-by: Abhinav Kumar 
---
  drivers/gpu/drm/msm/dsi/dsi_manager.c | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 4cb1cb6..0607ad0 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -836,6 +836,7 @@ void msm_dsi_manager_attach_dsi_device(int id, u32 
device_flags)
struct msm_drm_private *priv;
struct msm_kms *kms;
struct drm_encoder *encoder;
+   bool cmd_mode;
  
  	/*

 * drm_device pointer is assigned to msm_dsi only in the modeset_init
@@ -850,10 +851,11 @@ void msm_dsi_manager_attach_dsi_device(int id, u32 
device_flags)
priv = dev->dev_private;
kms = priv->kms;
encoder = msm_dsi_get_encoder(msm_dsi);
+   cmd_mode = !(device_flags &
+MIPI_DSI_MODE_VIDEO);
  
  	if (encoder && kms->funcs->set_encoder_mode)

-   if (!(device_flags & MIPI_DSI_MODE_VIDEO))
-   kms->funcs->set_encoder_mode(kms, encoder, true);
+   kms->funcs->set_encoder_mode(kms, encoder, cmd_mode);
  }
  
  int msm_dsi_manager_register(struct msm_dsi *msm_dsi)



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Re: [Freedreno] [DPU PATCH v2 1/2] drm/panel: Add Truly NT35597 panel

[Archit Taneja]

Hi,

On Saturday 14 April 2018 12:55 PM, Abhinav Kumar wrote:

From: Archit Taneja <arch...@codeaurora.org>


You can drop DPU from the subject. Also, you'd need to add
Theirry Reading for panel related patches, and Rob Herring
for an Ack on the DT bindings.

I think you can change the author to yourself. You've had to
make plenty of changes to get this in upstream state. You
can keep my Signed-off-by, though.



Add support for Truly NT35597 panel used
in MSM reference platforms.


You can mention here that the panel supports both single
and dual DSI modes, and that we support only dual-DSI
mode for now.



Changes in v2:
- Renamed panel to truly,nt35597
- Added SPDX license
- Used endpoints instead of custom node
- Renamed and cleaned up power supplies

Signed-off-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
---
  .../devicetree/bindings/display/truly,nt35597.txt  |  47 ++
  drivers/gpu/drm/panel/Kconfig  |   7 +
  drivers/gpu/drm/panel/Makefile |   1 +
  drivers/gpu/drm/panel/panel-truly-nt35597.c| 597 +
  4 files changed, 652 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/display/truly,nt35597.txt
  create mode 100644 drivers/gpu/drm/panel/panel-truly-nt35597.c

diff --git a/Documentation/devicetree/bindings/display/truly,nt35597.txt 
b/Documentation/devicetree/bindings/display/truly,nt35597.txt
new file mode 100644
index 000..22b6f19
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/truly,nt35597.txt
@@ -0,0 +1,47 @@
+Truly model NT35597 1440x2560 DSI Panel
+
+Required properties:
+- compatible: should be "truly,nt35597"
+- vdda-supply: phandle of the regulator that provides the supply voltage
+  Power IC supply
+- vdispp-supply: phandle of the regulator that provides the supply voltage
+  for positive LCD bias
+- vdispn-supply: phandle of the regulator that provides the supply voltage
+  for negative LCD bias
+- reset-gpios: phandle of gpio for reset line
+  This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
+- mode-gpios: phandle of the gpio for choosing the mode of the display
+  for single DSI or Dual DSI
+  This should be low for dual DSI and high for single DSI mode
+- display-timings: Node for the Panel timings
+


You need to specify the of-graph bindings here. Especially, what port #
corresponds to master DSI, and what # for slave DSI.


+Example:
+
+   dsi@ae94000 {
+   panel@0 {
+   compatible = "truly,nt35597";
+   reg = <0>;
+   vdda-supply = <_l14>;
+   vdispp-supply = <_regulator>;
+   vdispn-supply = <_regulator>;
+   pinctrl-names = "default", "suspend";
+   pinctrl-0 = <_dsi_active>;
+   pinctrl-1 = <_dsi_suspend>;
+
+   reset-gpios = < 6 0>;
+   mode-gpios = < 52 0>;
+   display-timings {
+   timing0: timing-0 {
+   clock-frequency = <268316138>;
+   hactive = <1440>;
+   vactie = <2560>;
+   hfront-porch = <200>;
+   hback-porch = <64>;
+   hsync-len = <32>;
+   vfront-porch = <8>;
+   vback-porch = <7>;
+   vsync-len = <1>;
+   };
+   };
+   };


The example should specify the port too.


+   };
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 988048e..9f0c490 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -168,4 +168,11 @@ config DRM_PANEL_SITRONIX_ST7789V
  Say Y here if you want to enable support for the Sitronix
  ST7789V controller for 240x320 LCD panels
  
+config DRM_PANEL_TRULY_NT35597_WQXGA

+   tristate "Truly WQXGA"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   help
+ Say Y here if you want to enable support for Truly NT35597 WQXGA Dual 
DSI
+ Video Mode panel
  endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 3d2a88d..b5b4b60 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
  obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
  obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043

Re: [Freedreno] [DPU PATCH v3 2/2] drm/msm/dsi: Use one connector for dual DSI mode

[Archit Taneja]

On Thursday 19 April 2018 01:15 AM, Chandan Uddaraju wrote:

Current DSI driver uses two connectors for dual DSI case even
though we only have one panel. Fix this by implementing one
connector/bridge for dual DSI use case. Use master DSI
controllers to register one connector/bridge.

Changes in V2:
 -Removed Change-Id from the commit text tags.
 -Remove extra parentheses

Changes in V3:
 -None


Reviewed-by: Archit Taneja <arch...@codeaurora.org>



Signed-off-by: Chandan Uddaraju <chand...@codeaurora.org>
---
  drivers/gpu/drm/msm/dsi/dsi.c |   3 +
  drivers/gpu/drm/msm/dsi/dsi.h |   1 +
  drivers/gpu/drm/msm/dsi/dsi_manager.c | 110 --
  3 files changed, 29 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index b744bcc..ff8164c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -208,6 +208,9 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct 
drm_device *dev,
goto fail;
}
  
+	if (!msm_dsi_manager_validate_current_config(msm_dsi->id))

+   goto fail;
+
msm_dsi->encoder = encoder;
  
  	msm_dsi->bridge = msm_dsi_manager_bridge_init(msm_dsi->id);

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 01c38f6..c858e8e 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -100,6 +100,7 @@ struct msm_dsi {
  void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
  int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
  void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
+bool msm_dsi_manager_validate_current_config(u8 id);
  
  /* msm dsi */

  static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 3bb506b..2a11f82 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -306,67 +306,6 @@ static void dsi_mgr_connector_destroy(struct drm_connector 
*connector)
kfree(dsi_connector);
  }
  
-static void dsi_dual_connector_fix_modes(struct drm_connector *connector)

-{
-   struct drm_display_mode *mode, *m;
-
-   /* Only support left-right mode */
-   list_for_each_entry_safe(mode, m, >probed_modes, head) {
-   mode->clock >>= 1;
-   mode->hdisplay >>= 1;
-   mode->hsync_start >>= 1;
-   mode->hsync_end >>= 1;
-   mode->htotal >>= 1;
-   drm_mode_set_name(mode);
-   }
-}
-
-static int dsi_dual_connector_tile_init(
-   struct drm_connector *connector, int id)
-{
-   struct drm_display_mode *mode;
-   /* Fake topology id */
-   char topo_id[8] = {'M', 'S', 'M', 'D', 'U', 'D', 'S', 'I'};
-
-   if (connector->tile_group) {
-   DBG("Tile property has been initialized");
-   return 0;
-   }
-
-   /* Use the first mode only for now */
-   mode = list_first_entry(>probed_modes,
-   struct drm_display_mode,
-   head);
-   if (!mode)
-   return -EINVAL;
-
-   connector->tile_group = drm_mode_get_tile_group(
-   connector->dev, topo_id);
-   if (!connector->tile_group)
-   connector->tile_group = drm_mode_create_tile_group(
-   connector->dev, topo_id);
-   if (!connector->tile_group) {
-   pr_err("%s: failed to create tile group\n", __func__);
-   return -ENOMEM;
-   }
-
-   connector->has_tile = true;
-   connector->tile_is_single_monitor = true;
-
-   /* mode has been fixed */
-   connector->tile_h_size = mode->hdisplay;
-   connector->tile_v_size = mode->vdisplay;
-
-   /* Only support left-right mode */
-   connector->num_h_tile = 2;
-   connector->num_v_tile = 1;
-
-   connector->tile_v_loc = 0;
-   connector->tile_h_loc = (id == DSI_RIGHT) ? 1 : 0;
-
-   return 0;
-}
-
  static int dsi_mgr_connector_get_modes(struct drm_connector *connector)
  {
int id = dsi_mgr_connector_get_id(connector);
@@ -377,31 +316,15 @@ static int dsi_mgr_connector_get_modes(struct 
drm_connector *connector)
if (!panel)
return 0;
  
-	/* Since we have 2 connectors, but only 1 drm_panel in dual DSI mode,

-* panel should not attach to any connector.
-* Only temporarily attach panel to the current connector here,
-* to let panel set mode to this connector.
+   /*
+* In dual DSI mode, we have one connector that can be
+* attached to the drm_panel.
 */
drm_panel_attach(panel, conne

Re: [Freedreno] [DPU PATCH 1/2] drm/panel: Add Truly Dual DSI video mode panel

[Archit Taneja]

Hi Abhinav,

Thanks for posting this driver. Some comments below.

On Saturday 07 April 2018 12:36 PM, Abhinav Kumar wrote:

From: Archit Taneja <arch...@codeaurora.org>

Add support for truly dual DSI video mode panel
panel used in MSM reference platforms >
Signed-off-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
---
  .../bindings/display/truly,dual_wqxga.txt  |  47 ++
  drivers/gpu/drm/panel/Kconfig  |   7 +
  drivers/gpu/drm/panel/Makefile |   1 +
  drivers/gpu/drm/panel/panel-truly-dual-dsi.c   | 530 +
  4 files changed, 585 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/display/truly,dual_wqxga.txt
  create mode 100644 drivers/gpu/drm/panel/panel-truly-dual-dsi.c

diff --git a/Documentation/devicetree/bindings/display/truly,dual_wqxga.txt 
b/Documentation/devicetree/bindings/display/truly,dual_wqxga.txt
new file mode 100644
index 000..a1b24c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/truly,dual_wqxga.txt
@@ -0,0 +1,47 @@
+Truly model NT35597 1440x2560 DSI Panel
+
+Required properties:
+- compatible: should be "truly,dual_wqxga"


The compatible string, kernel config and the driver file should be based
on the panel model no. There can be many truly based panels that
support wqxga. Something like "truly,nt35597" would be better.


+- vdda-supply: phandle of the regulator that provides the supply voltage
+  Power IC supply
+- lab-supply: phandle of the regulator that provides the supply voltage
+  for LCD bias
+- ibb-supply: phandle of the regulator that provides the supply voltage
+  for LCD bias


Both seem to have the same description. Aren't lab and ibb qualcomm
specific terms? Could we use the pin names specified in the panel's
data sheet?


+- reset-gpios: phandle of gpio for reset line
+  This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
+- mode-gpios: phandle of the gpio for choosing the mode of the display
+  for single DSI or Dual DSI


Could we describe here how to use this gpio? I.e, whether we need to set
it to low for dual DSI, etc?


+- display-timings: Node for the Panel timings
+- link2: phandle to the secondary node of the panel


The link2 binding was a temporary hack we used. We should use the
of-graph bindings to represent the two DSI input ports of the panel.


+
+Example:
+
+   dsi@ae94000 {
+   panel@0 {
+   compatible = "truly,dual_wqxga";
+   reg = <0>;
+   link2 = <>;
+   vdda-supply = <_l14>;
+
+   pinctrl-names = "default", "suspend";
+   pinctrl-0 = <_dsi_active>;
+   pinctrl-1 = <_dsi_suspend>;
+
+   reset-gpios = < 6 0>;
+   mode-gpios = < 52 0>;
+   display-timings {
+   timing0: timing-0 {
+   clock-frequency = <268316138>;
+   hactive = <1440>;
+   vactive = <2560>;
+   hfront-porch = <200>;
+   hback-porch = <64>;
+   hsync-len = <32>;
+   vfront-porch = <8>;
+   vback-porch = <7>;
+   vsync-len = <1>;
+   };
+   };
+   };
+   };
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 988048e..a63c3f7 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -168,4 +168,11 @@ config DRM_PANEL_SITRONIX_ST7789V
  Say Y here if you want to enable support for the Sitronix
  ST7789V controller for 240x320 LCD panels
  
+config DRM_PANEL_TRULY_WQXGA

+   tristate "Truly WQXGA"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   help
+ Say Y here if you want to enable support for Truly WQXGA Dual DSI
+ Video Mode panel
  endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 3d2a88d..64891f6 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
  obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
  obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
  obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
+obj-$(CONFIG_DRM_PANEL_TRULY_WQXGA) += panel-truly-dual-dsi.o
diff --git a/drivers/gpu/drm/pa

Re: [Freedreno] [DPU PATCH 2/2] drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY

[Archit Taneja]

On Saturday 07 April 2018 01:20 PM, Abhinav Kumar wrote:

Currently the DSI PHY timings are hard-coded for a specific panel
for the 10nm PHY.

Replace this with the auto PHY timing calculator which can calculate
the PHY timings for any panel.


Reviewed-by: Archit Taneja <arch...@codeaurora.org>



Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
---
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c  | 111 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h  |   2 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c |  28 
  3 files changed, 113 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 8e9d5c2..5b42885 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -265,6 +265,117 @@ int msm_dsi_dphy_timing_calc_v2(struct 
msm_dsi_dphy_timing *timing,
return 0;
  }
  
+int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,

+  struct msm_dsi_phy_clk_request *clk_req)
+{
+   const unsigned long bit_rate = clk_req->bitclk_rate;
+   const unsigned long esc_rate = clk_req->escclk_rate;
+   s32 ui, ui_x8, lpx;
+   s32 tmax, tmin;
+   s32 pcnt0 = 50;
+   s32 pcnt1 = 50;
+   s32 pcnt2 = 10;
+   s32 pcnt3 = 30;
+   s32 pcnt4 = 10;
+   s32 pcnt5 = 2;
+   s32 coeff = 1000; /* Precision, should avoid overflow */
+   s32 hb_en, hb_en_ckln;
+   s32 temp;
+
+   if (!bit_rate || !esc_rate)
+   return -EINVAL;
+
+   timing->hs_halfbyte_en = 0;
+   hb_en = 0;
+   timing->hs_halfbyte_en_ckln = 0;
+   hb_en_ckln = 0;
+
+   ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
+   ui_x8 = ui << 3;
+   lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
+
+   temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
+   tmin = max_t(s32, temp, 0);
+   temp = (95 * coeff) / ui_x8;
+   tmax = max_t(s32, temp, 0);
+   timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
+
+
+   temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
+   tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
+   tmax = (tmin > 255) ? 511 : 255;
+   timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
+
+   tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
+   temp = 105 * coeff + 12 * ui - 20 * coeff;
+   tmax = (temp + 3 * ui) / ui_x8;
+   timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
+
+   temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
+   tmin = max_t(s32, temp, 0);
+   temp = (85 * coeff + 6 * ui) / ui_x8;
+   tmax = max_t(s32, temp, 0);
+   timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
+
+   temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
+   tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
+   tmax = 255;
+   timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
+
+   tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
+   temp = 105 * coeff + 12 * ui - 20 * coeff;
+   tmax = (temp / ui_x8) - 1;
+   timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
+
+   temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
+   timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
+
+   tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
+   tmax = 255;
+   timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
+
+   temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
+   timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
+
+   temp = 60 * coeff + 52 * ui - 43 * ui;
+   tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
+   tmax = 63;
+   timing->shared_timings.clk_post =
+   linear_inter(tmax, tmin, pcnt2, 0, false);
+
+   temp = 8 * ui + (timing->clk_prepare << 3) * ui;
+   temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
+   temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
+   (((timing->hs_rqst_ckln << 3) + 8) * ui);
+   tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
+   tmax = 63;
+   if (tmin > tmax) {
+   temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
+   timing->shared_timings.clk_pre = temp >> 1;
+   timing->shared_timings.clk_pre_inc_by_2 = 1;
+   } else {
+   timing->shared_timings.clk_pre =
+   linear_inter(tmax, tmin, pcnt2, 0, false);
+   timing->shared_timings.clk_pre_inc_by_2 = 0;
+   }
+
+   timing->ta_go = 3;
+   timing->ta_sure = 0;
+   timing->ta_get = 4;
+
+   DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
+   timing->shared_timings.clk_pre, timing->sh

Re: [Freedreno] [PATCH v2 4/6] drm/msm: Issue queued events when disabling crtc

[Archit Taneja]

On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:

Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).


Reviewed-by: Archit Taneja <arch...@codeaurora.org>



Changes in v2:
- None

Signed-off-by: Sean Paul <seanp...@chromium.org>
---
  drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 +
  1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 76b96081916f..10271359789e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -430,6 +430,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct device *dev = _kms->pdev->dev;
+   unsigned long flags;
  
  	DBG("%s", crtc->name);
  
@@ -445,6 +446,14 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,

mdp_irq_unregister(_kms->base, _crtc->err);
pm_runtime_put_sync(dev);
  
+	if (crtc->state->event && !crtc->state->active) {

+   WARN_ON(mdp5_crtc->event);
+   spin_lock_irqsave(_kms->dev->event_lock, flags);
+   drm_crtc_send_vblank_event(crtc, crtc->state->event);
+   crtc->state->event = NULL;
+   spin_unlock_irqrestore(_kms->dev->event_lock, flags);
+   }
+
mdp5_crtc->enabled = false;
  }
  


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Re: [Freedreno] [PATCH v2 3/6] drm/msm: Mark the crtc->state->event consumed

[Archit Taneja]

On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:

Don't leave the event != NULL once it's consumed, this is used a signal

s/used a/used as a ?

to the atomic helpers that the event will be handled by the driver.



Reviewed-by: Archit Taneja <arch...@codeaurora.org>


Changes in v2:
- None

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
  drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 1 +
  drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 1 +
  2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 6e5e1aa54ce1..b001699297c4 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -351,6 +351,7 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
  
  	spin_lock_irqsave(>event_lock, flags);

mdp4_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
  
  	blend_setup(crtc);

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 9893e43ba6c5..76b96081916f 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -708,6 +708,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
  
  	spin_lock_irqsave(>event_lock, flags);

mdp5_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
  
  	/*



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Re: [Freedreno] [PATCH] drm/msm/dsi: use correct enum in dsi_get_cmd_fmt

[Archit Taneja]

On Tuesday 20 March 2018 02:56 AM, Stefan Agner wrote:

The function dsi_get_cmd_fmt returns enum dsi_cmd_dst_format,
use the correct enum value also for MIPI_DSI_FMT_RGB666/_PACKED.

This has been discovered using clang:
   drivers/gpu/drm/msm/dsi/dsi_host.c:743:35: warning: implicit conversion
 from enumeration type 'enum dsi_vid_dst_format' to different
 enumeration type 'enum dsi_cmd_dst_format' [-Wenum-conversion]
   case MIPI_DSI_FMT_RGB666:   return VID_DST_FORMAT_RGB666;
   ~~ ^

Signed-off-by: Stefan Agner <ste...@agner.ch>


Reviewed-by: Archit Taneja <arch...@codeaurora.org>

Archit


---
  drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0f7324a686ca..d729b2b4b66d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -740,7 +740,7 @@ static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
switch (mipi_fmt) {
case MIPI_DSI_FMT_RGB888:   return CMD_DST_FORMAT_RGB888;
case MIPI_DSI_FMT_RGB666_PACKED:
-   case MIPI_DSI_FMT_RGB666:   return VID_DST_FORMAT_RGB666;
+   case MIPI_DSI_FMT_RGB666:   return CMD_DST_FORMAT_RGB666;
case MIPI_DSI_FMT_RGB565:   return CMD_DST_FORMAT_RGB565;
default:return CMD_DST_FORMAT_RGB888;
}


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Re: [Freedreno] [PATCH 4/5] drm/msm/dsi: implement 6G v2.0+ DSI command broadcast

[Archit Taneja]

On Monday 12 March 2018 06:53 PM, Sibi S wrote:

From: Archit Taneja <arch...@codeaurora.org>



I'm a bit uncertain about using this patch in its current state.
Some reasons below.


Add command broadcast support for DSI 6G v2.0+ controller
on SDM845

Signed-off-by: Sibi S <si...@codeaurora.org>
---
  drivers/gpu/drm/msm/dsi/dsi.h |  5 +++
  drivers/gpu/drm/msm/dsi/dsi_cfg.c | 14 +++-
  drivers/gpu/drm/msm/dsi/dsi_host.c| 62 ++--
  drivers/gpu/drm/msm/dsi/dsi_manager.c | 66 +++
  4 files changed, 143 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index dfa049d..22342c30 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -96,7 +96,9 @@ struct msm_dsi {
  struct drm_connector *msm_dsi_manager_connector_init(u8 id);
  struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id);
  int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
+int msm_dsi_manager_cmd_xfer_6g_v2(int id, const struct mipi_dsi_msg *msg);
  bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
+bool msm_dsi_manager_cmd_xfer_trigger_6g_v2(int id, u32 dma_base, u32 len);
  void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
  int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
  void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
@@ -152,6 +154,9 @@ static inline int msm_dsi_pll_set_usecase(struct 
msm_dsi_pll *pll,
  struct msm_dsi_host;
  int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg);
+int msm_dsi_host_xfer_prepare_6g_v2(struct mipi_dsi_host *host,
+   const struct mipi_dsi_msg *msg,
+   bool broadcast, bool master);
  void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg);
  int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index dc51aaa..dcdfb1b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -157,6 +157,18 @@
.dma_base_get = dsi_dma_base_get_6g,
.calc_clk_rate = dsi_calc_clk_rate_6g,
  };
+
+const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
+   .link_clk_enable = dsi_link_clk_enable_6g,
+   .link_clk_disable = dsi_link_clk_disable_6g,
+   .clk_init_ver = dsi_clk_init_6g_v2,
+   .tx_buf_alloc = dsi_tx_buf_alloc_6g,
+   .tx_buf_get = dsi_tx_buf_get_6g,
+   .tx_buf_put = dsi_tx_buf_put_6g,
+   .dma_base_get = dsi_dma_base_get_6g,
+   .calc_clk_rate = dsi_calc_clk_rate_6g,
+};
+
  static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
_dsi_cfg, _dsi_v2_host_ops},
@@ -175,7 +187,7 @@
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
_dsi_cfg, _dsi_6g_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
-   _dsi_cfg, _dsi_6g_host_ops},
+   _dsi_cfg, _dsi_6g_v2_host_ops},
  };
  
  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b755b69..bd61cad 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1251,9 +1251,14 @@ static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, 
int len)
reinit_completion(_host->dma_comp);
  
  	dsi_wait4video_eng_busy(msm_host);

+   if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
+   (cfg_hnd->minor < MSM_DSI_6G_VER_MINOR_V2_2_1))
+   triggered = msm_dsi_manager_cmd_xfer_trigger(msm_host->id,
+   dma_base, len);
+   else
+   triggered = msm_dsi_manager_cmd_xfer_trigger_6g_v2(
+ msm_host->id, dma_base, len);
  
-	triggered = msm_dsi_manager_cmd_xfer_trigger(

-   msm_host->id, dma_base, len);
if (triggered) {
ret = wait_for_completion_timeout(_host->dma_comp,
msecs_to_jiffies(200));
@@ -1602,13 +1607,21 @@ static ssize_t dsi_host_transfer(struct mipi_dsi_host 
*host,
const struct mipi_dsi_msg *msg)
  {
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+   const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
int ret;
  
  	if (!msg || !msm_host->power_on)

return -EINVAL;
  
  	mutex_lock(_host->cmd_mutex);

-   ret = msm_dsi_manager_cmd_xf

Re: [Freedreno] [PATCH 3/5] drm/msm/dsi: replace version checks with helper functions

[Archit Taneja]

On Monday 12 March 2018 06:53 PM, Sibi S wrote:

Replace version checks with the helper functions bound to
cfg_handler for DSI v2 and DSI 6G 1.x controllers



With the ops set up for DSI6G 2.x too:

Reviewed-by: Archit Taneja <arch...@codeaurora.org>

Thanks,
Archit


Signed-off-by: Sibi S <si...@codeaurora.org>
---
  drivers/gpu/drm/msm/dsi/dsi_host.c | 242 +
  1 file changed, 29 insertions(+), 213 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index f7a066d..b755b69 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -426,19 +426,6 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host)
goto exit;
}
  
-	if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&

-   cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_2_1) {
-   msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
-   if (IS_ERR(msm_host->byte_intf_clk)) {
-   ret = PTR_ERR(msm_host->byte_intf_clk);
-   pr_err("%s: can't find byte_intf clock. ret=%d\n",
-   __func__, ret);
-   goto exit;
-   }
-   } else {
-   msm_host->byte_intf_clk = NULL;
-   }
-
msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
if (!msm_host->byte_clk_src) {
ret = -ENODEV;
@@ -453,31 +440,8 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host)
goto exit;
}
  
-	if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {

-   msm_host->src_clk = msm_clk_get(pdev, "src");
-   if (IS_ERR(msm_host->src_clk)) {
-   ret = PTR_ERR(msm_host->src_clk);
-   pr_err("%s: can't find src clock. ret=%d\n",
-   __func__, ret);
-   msm_host->src_clk = NULL;
-   goto exit;
-   }
-
-   msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
-   if (!msm_host->esc_clk_src) {
-   ret = -ENODEV;
-   pr_err("%s: can't get esc clock parent. ret=%d\n",
-   __func__, ret);
-   goto exit;
-   }
-
-   msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
-   if (!msm_host->dsi_clk_src) {
-   ret = -ENODEV;
-   pr_err("%s: can't get src clock parent. ret=%d\n",
-   __func__, ret);
-   }
-   }
+   if (cfg_hnd->ops->clk_init_ver)
+   ret = cfg_hnd->ops->clk_init_ver(msm_host);
  exit:
return ret;
  }
@@ -681,16 +645,6 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
return ret;
  }
  
-static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)

-{
-   const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-
-   if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
-   return dsi_link_clk_enable_6g(msm_host);
-   else
-   return dsi_link_clk_enable_v2(msm_host);
-}
-
  void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
  {
clk_disable_unprepare(msm_host->esc_clk);
@@ -708,24 +662,6 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
clk_disable_unprepare(msm_host->byte_clk);
  }
  
-static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)

-{
-   const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-
-   if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
-   clk_disable_unprepare(msm_host->esc_clk);
-   clk_disable_unprepare(msm_host->pixel_clk);
-   if (msm_host->byte_intf_clk)
-   clk_disable_unprepare(msm_host->byte_intf_clk);
-   clk_disable_unprepare(msm_host->byte_clk);
-   } else {
-   clk_disable_unprepare(msm_host->pixel_clk);
-   clk_disable_unprepare(msm_host->src_clk);
-   clk_disable_unprepare(msm_host->esc_clk);
-   clk_disable_unprepare(msm_host->byte_clk);
-   }
-}
-
  int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
  {
struct drm_display_mode *mode = msm_host->mode;
@@ -814,73 +750,6 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
return 0;
  }
  
-static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)

-{
-   struct drm_display_mode *mode = msm_host->mode;
-   const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-   u8 lanes = msm_host->lanes;
-   u32 bpp = dsi_get_bpp(msm_host->format);
-   u32 pclk_rate;
-
-   if

Re: [Freedreno] [PATCH 2/5] drm/msm/dsi: add implementation for helper functions

[Archit Taneja]

On Monday 12 March 2018 06:53 PM, Sibi S wrote:

Add dsi host helper function implementation for DSI v2
and DSI 6G 1.x controllers

Signed-off-by: Sibi S 
---
  drivers/gpu/drm/msm/dsi/dsi.h  |  15 +++
  drivers/gpu/drm/msm/dsi/dsi_cfg.c  |  44 +--
  drivers/gpu/drm/msm/dsi/dsi_host.c | 250 -
  3 files changed, 298 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 80be83e..dfa049d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -183,6 +183,21 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
  int msm_dsi_host_init(struct msm_dsi *msm_dsi);
  int msm_dsi_runtime_suspend(struct device *dev);
  int msm_dsi_runtime_resume(struct device *dev);
+int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
+int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
+void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host);
+void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host);
+int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size);
+int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size);
+void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host);
+void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host);
+void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host);
+int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova);
+int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova);
+int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
+int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
  
  /* dsi phy */

  struct msm_dsi_phy;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 0327bb5..dc51aaa 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -136,20 +136,46 @@
.num_dsi = 2,
  };
  
+const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {

+   .link_clk_enable = dsi_link_clk_enable_v2,
+   .link_clk_disable = dsi_link_clk_disable_v2,
+   .clk_init_ver = dsi_clk_init_v2,
+   .tx_buf_alloc = dsi_tx_buf_alloc_v2,
+   .tx_buf_get = dsi_tx_buf_get_v2,
+   .tx_buf_put = NULL,
+   .dma_base_get = dsi_dma_base_get_v2,
+   .calc_clk_rate = dsi_calc_clk_rate_v2,
+};
+
+const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
+   .link_clk_enable = dsi_link_clk_enable_6g,
+   .link_clk_disable = dsi_link_clk_disable_6g,
+   .clk_init_ver = NULL,
+   .tx_buf_alloc = dsi_tx_buf_alloc_6g,
+   .tx_buf_get = dsi_tx_buf_get_6g,
+   .tx_buf_put = dsi_tx_buf_put_6g,
+   .dma_base_get = dsi_dma_base_get_6g,
+   .calc_clk_rate = dsi_calc_clk_rate_6g,
+};


Could you introduce the host ops for SDM845 (i.e,
msm_dsi_6g_v2_host_ops) in this patch itself? It would be nice to
keep the DSI command broadcast code as a separate patch since it
probably needs to go through more iterations.

The ops approach looks good otherwise.

Thanks,
Archit


  static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
-   {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, _dsi_cfg},
+   {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
+   _dsi_cfg, _dsi_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
-   _apq8084_dsi_cfg},
+   _apq8084_dsi_cfg, _dsi_6g_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
-   _apq8084_dsi_cfg},
+   _apq8084_dsi_cfg, _dsi_6g_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
-   _apq8084_dsi_cfg},
+   _apq8084_dsi_cfg, _dsi_6g_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
-   _apq8084_dsi_cfg},
-   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, _dsi_cfg},
-   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, _dsi_cfg},
-   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, _dsi_cfg},
-   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, _dsi_cfg},
+   _apq8084_dsi_cfg, _dsi_6g_host_ops},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
+   _dsi_cfg, _dsi_6g_host_ops},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
+   _dsi_cfg, _dsi_6g_host_ops},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
+   _dsi_cfg, _dsi_6g_host_ops},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
+   _dsi_cfg, _dsi_6g_host_ops},
  };
  
  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 

Re: [Freedreno] [PATCH] mdp5: Return error values from mdp5_cfg_init

[Archit Taneja]

On 12/01/2017 02:34 AM, Will Newton wrote:

The return value of this function is a pointer checked with
IS_ERR, so we should be returning an error pointer rather than
NULL when the init fails.


Reviewed-by: Archit Taneja <arch...@codeaurora.org>



Signed-off-by: Will Newton <will.new...@gmail.com>
---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 824067d2d427..42f0ecb0cf35 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -635,7 +635,7 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms 
*mdp5_kms,
if (cfg_handler)
mdp5_cfg_destroy(cfg_handler);
  
-	return NULL;

+   return ERR_PTR(ret);
  }
  
  static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)




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Re: [Freedreno] [PATCH 09/15] drm/msm/mdp5: Use drm_mode_get_hv_timing() to populate plane clip rectangle

[Archit Taneja]

On 11/24/2017 12:34 AM, Ville Syrjala wrote:

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

Use drm_mode_get_hv_timing() to fill out the plane clip rectangle.

Note that this replaces crtc_state->adjusted_mode usage with
crtc_state->mode. The latter is the correct choice since that's the
mode the user provided and it matches the plane crtc coordinates
the user also provided.

Once everyone agrees on this we can move the clip handling into
drm_atomic_helper_check_plane_state().


For this and the msm change in patch # 15/15:

Reviewed-by: Archit Taneja <arch...@codeaurora.org>

Thanks,
Archit



Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Cc: Rob Clark <robdcl...@gmail.com>
Cc: Archit Taneja <arch...@codeaurora.org>
Cc: linux-arm-...@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 20 ++--
  1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index ee41423baeb7..09f758e7bb1b 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -286,7 +286,7 @@ static int mdp5_plane_atomic_check_with_state(struct 
drm_crtc_state *crtc_state,
uint32_t max_width, max_height;
bool out_of_bounds = false;
uint32_t caps = 0;
-   struct drm_rect clip;
+   struct drm_rect clip = {};
int min_scale, max_scale;
int ret;
  
@@ -320,13 +320,13 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,

return -ERANGE;
}
  
-	clip.x1 = 0;

-   clip.y1 = 0;
-   clip.x2 = crtc_state->adjusted_mode.hdisplay;
-   clip.y2 = crtc_state->adjusted_mode.vdisplay;
min_scale = FRAC_16_16(1, 8);
max_scale = FRAC_16_16(8, 1);
  
+	if (crtc_state->enable)

+   drm_mode_get_hv_timing(_state->mode,
+  , );
+
ret = drm_atomic_helper_check_plane_state(state, crtc_state, ,
  min_scale, max_scale,
  true, true);
@@ -471,7 +471,7 @@ static int mdp5_plane_atomic_async_check(struct drm_plane 
*plane,
  {
struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
struct drm_crtc_state *crtc_state;
-   struct drm_rect clip;
+   struct drm_rect clip = {};
int min_scale, max_scale;
int ret;
  
@@ -499,13 +499,13 @@ static int mdp5_plane_atomic_async_check(struct drm_plane *plane,

plane->state->fb != state->fb)
return -EINVAL;
  
-	clip.x1 = 0;

-   clip.y1 = 0;
-   clip.x2 = crtc_state->adjusted_mode.hdisplay;
-   clip.y2 = crtc_state->adjusted_mode.vdisplay;
min_scale = FRAC_16_16(1, 8);
max_scale = FRAC_16_16(8, 1);
  
+	if (crtc_state->enable)

+   drm_mode_get_hv_timing(_state->mode,
+  , );
+
ret = drm_atomic_helper_check_plane_state(state, crtc_state, ,
  min_scale, max_scale,
  true, true);



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Re: [Freedreno] [PATCH] drm/msm/mdp5: restore cursor state when enabling crtc

[Archit Taneja]

sh_mask = mdp_ctl_flush_mask_cursor(0);
-   uint32_t roi_w, roi_h;
bool cursor_enable = true;
unsigned long flags;
  
@@ -767,6 +825,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,

if (!handle) {
DBG("Cursor off");
cursor_enable = false;
+   mdp5_crtc->cursor.iova = 0;
pm_runtime_get_sync(>dev);
goto set_cursor;
}
@@ -775,13 +834,11 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
if (!cursor_bo)
return -ENOENT;
  
-	ret = msm_gem_get_iova(cursor_bo, kms->aspace, _addr);

+   ret = msm_gem_get_iova(cursor_bo, kms->aspace,
+   _crtc->cursor.iova);
if (ret)
return -EINVAL;
  
-	lm = mdp5_cstate->pipeline.mixer->lm;

-   stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB, 0);
-
pm_runtime_get_sync(>dev);
  
  	spin_lock_irqsave(_crtc->cursor.lock, flags);

@@ -791,22 +848,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
mdp5_crtc->cursor.width = width;
mdp5_crtc->cursor.height = height;
  
-	get_roi(crtc, _w, _h);

-
-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
-   MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB));
-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
-   MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
-   MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
-   MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
-   MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
-
-   blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
-   blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
+   mdp5_crtc_restore_cursor(crtc);
  
  	spin_unlock_irqrestore(_crtc->cursor.lock, flags);
  
@@ -835,7 +877,6 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)

struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
-   uint32_t lm = mdp5_cstate->pipeline.mixer->lm;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w;
uint32_t roi_h;


I guess we could get rid of roi_w, roi_h and the call to get_roi() in this fucn 
too?

Otherwise:
Reviewed-by: Archit Taneja <arch...@codeaurora.org>


@@ -857,12 +898,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, 
int x, int y)
pm_runtime_get_sync(_kms->pdev->dev);
  
  	spin_lock_irqsave(_crtc->cursor.lock, flags);

-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
-   MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
-   MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
-   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
-   MDP5_LM_CURSOR_START_XY_Y_START(y) |
-   MDP5_LM_CURSOR_START_XY_X_START(x));
+   mdp5_crtc_restore_cursor(crtc);
spin_unlock_irqrestore(_crtc->cursor.lock, flags);
  
  	crtc_flush(crtc, flush_mask);




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Re: [Freedreno] [PATCH] drm/msm/mdp5: don't use autosuspend

[Archit Taneja]

On 10/20/2017 05:47 PM, Rob Clark wrote:

It's only likely to paper over bugs.  Unlike the gpu, where we want to
keep things alive a bit longer in expectation of the next frame's
submit, when the display is shut down we can power off immediately.


Acked-by: Archit Taneja <arch...@codeaurora.org>



Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c |  2 +-
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  6 +++---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  2 +-
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 10 +-
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  6 +++---
  5 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
index 60790df91bfa..1abc7f5c345c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
@@ -224,7 +224,7 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder 
*encoder,
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
   MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 0b6ace26d622..6aa3a688d9a4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -429,7 +429,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
mdp_irq_unregister(_kms->base, _crtc->pp_done);
  
  	mdp_irq_unregister(_kms->base, _crtc->err);

-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	mdp5_crtc->enabled = false;

  }
@@ -821,7 +821,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
crtc_flush(crtc, flush_mask);
  
  end:

-   pm_runtime_put_autosuspend(>dev);
+   pm_runtime_put_sync(>dev);
if (old_bo) {
drm_flip_work_queue(_crtc->unref_cursor_work, old_bo);
/* enable vblank to complete cursor work: */
@@ -867,7 +867,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int 
x, int y)
  
  	crtc_flush(crtc, flush_mask);
  
-	pm_runtime_put_autosuspend(_kms->pdev->dev);

+   pm_runtime_put_sync(_kms->pdev->dev);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
index 5b851380d3f2..36ad3cbe5f79 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -384,7 +384,7 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder 
*encoder,
  
  	mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
  
-	pm_runtime_put_autosuspend(dev);

+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index bb5deb00c899..280e368bc9bb 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -54,7 +54,7 @@ void mdp5_irq_preinstall(struct msm_kms *kms)
pm_runtime_get_sync(dev);
mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0x);
mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  }
  
  int mdp5_irq_postinstall(struct msm_kms *kms)

@@ -72,7 +72,7 @@ int mdp5_irq_postinstall(struct msm_kms *kms)
  
  	pm_runtime_get_sync(dev);

mdp_irq_register(mdp_kms, error_handler);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
@@ -84,7 +84,7 @@ void mdp5_irq_uninstall(struct msm_kms *kms)
  
  	pm_runtime_get_sync(dev);

mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  }
  
  irqreturn_t mdp5_irq(struct msm_kms *kms)

@@ -119,7 +119,7 @@ int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc 
*crtc)
pm_runtime_get_sync(dev);
mdp_update_vblank_mask(to_mdp_kms(kms),
mdp5_crtc_vblank(crtc), true);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  
  	return 0;

  }
@@ -132,5 +132,5 @@ void mdp5_disable_vblank(struct msm_kms *kms, struct 
drm_crtc *crtc)
pm_runtime_get_sync(dev);
mdp_update_vblank_mask(to_mdp_kms(kms),
mdp5_crtc_vblank(crtc), false);
-   pm_runtime_put_autosuspend(dev);
+   pm_runtime_put_sync(dev);
  }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index c664eb1d47dc..ca8f20206b6c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -125,7 +125,7 @

Re: [Freedreno] [PATCH 2/3] drm/msm/mdp5: mark runtime_pm functions as __maybe_unused

[Archit Taneja]

On 08/03/2017 05:20 PM, Arnd Bergmann wrote:

When CONFIG_PM is disabled, we get harmless warnings about unused
functions:

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1025:12: error: 'mdp5_runtime_resume' 
defined but not used [-Werror=unused-function]
  static int mdp5_runtime_resume(struct device *dev)
 ^~~
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1015:12: error: 'mdp5_runtime_suspend' 
defined but not used [-Werror=unused-function]
  static int mdp5_runtime_suspend(struct device *dev)
 ^~~~

This marks both functions as __maybe_unused so the compiler
can drop them silently.


Thanks for the fix. Since the commit is still in Rob's -next branch,
I'll post a new version which fixes this.

Archit



Fixes: d68fe15b1878 ("drm/msm/mdp5: Use runtime PM get/put API instead of toggling 
clocks")
Signed-off-by: Arnd Bergmann 
---
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 9f9d95f7c80f..f7c0698fec40 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -1012,7 +1012,7 @@ static int mdp5_dev_remove(struct platform_device *pdev)
return 0;
  }
  
-static int mdp5_runtime_suspend(struct device *dev)

+static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
  {
struct platform_device *pdev = to_platform_device(dev);
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
@@ -1022,7 +1022,7 @@ static int mdp5_runtime_suspend(struct device *dev)
return mdp5_disable(mdp5_kms);
  }
  
-static int mdp5_runtime_resume(struct device *dev)

+static __maybe_unused int mdp5_runtime_resume(struct device *dev)
  {
struct platform_device *pdev = to_platform_device(dev);
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);



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Re: [Freedreno] [PATCH 14/16] drm/msm: Convert to use new iterator macros, v2.

[Archit Taneja]

On 07/12/2017 04:15 PM, Maarten Lankhorst wrote:

Op 12-07-17 om 11:48 schreef Daniel Vetter:

On Wed, Jul 12, 2017 at 10:13:42AM +0200, Maarten Lankhorst wrote:

for_each_obj_in_state is about to be removed, so convert
to the new iterator macros.

Just like in omap, use crtc_state->active instead of
crtc_state->enable when waiting for completion.


Tested-by: Archit Taneja <arch...@codeaurora.org>



Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Rob Clark <robdcl...@gmail.com>
Cc: Archit Taneja <arch...@codeaurora.org>
Cc: Vincent Abriou <vincent.abr...@st.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Russell King <rmk+ker...@armlinux.org.uk>
Cc: Rob Herring <r...@kernel.org>
Cc: Markus Elfring <elfr...@users.sourceforge.net>
Cc: Sushmita Susheelendra <ssush...@codeaurora.org>
Cc: linux-arm-...@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
---
  drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c |  4 ++--
  drivers/gpu/drm/msm/msm_atomic.c| 16 
  2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
index bcd1f5cac72c..f7f087419ed8 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
@@ -114,7 +114,7 @@ static void mdp4_prepare_commit(struct msm_kms *kms, struct 
drm_atomic_state *st
mdp4_enable(mdp4_kms);
  
  	/* see 119ecb7fd */

-   for_each_crtc_in_state(state, crtc, crtc_state, i)
+   for_each_new_crtc_in_state(state, crtc, crtc_state, i)
drm_crtc_vblank_get(crtc);
  }
  
@@ -126,7 +126,7 @@ static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s

struct drm_crtc_state *crtc_state;
  
  	/* see 119ecb7fd */

-   for_each_crtc_in_state(state, crtc, crtc_state, i)
+   for_each_new_crtc_in_state(state, crtc, crtc_state, i)
drm_crtc_vblank_put(crtc);
  
  	mdp4_disable(mdp4_kms);

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 9633a68b14d7..9d3cc1f5e31a 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -84,13 +84,13 @@ static void msm_atomic_wait_for_commit_done(struct 
drm_device *dev,
struct drm_atomic_state *old_state)
  {
struct drm_crtc *crtc;
-   struct drm_crtc_state *crtc_state;
+   struct drm_crtc_state *new_crtc_state;
struct msm_drm_private *priv = old_state->dev->dev_private;
struct msm_kms *kms = priv->kms;
int i;
  
-	for_each_crtc_in_state(old_state, crtc, crtc_state, i) {

-   if (!crtc->state->enable)
+   for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
+   if (!new_crtc_state->active)
continue;
  
  		kms->funcs->wait_for_crtc_commit_done(kms, crtc);

@@ -195,7 +195,7 @@ int msm_atomic_commit(struct drm_device *dev,
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane *plane;
-   struct drm_plane_state *plane_state;
+   struct drm_plane_state *old_plane_state, *new_plane_state;
int i, ret;
  
  	ret = drm_atomic_helper_prepare_planes(dev, state);

@@ -211,15 +211,15 @@ int msm_atomic_commit(struct drm_device *dev,
/*
 * Figure out what crtcs we have:
 */
-   for_each_crtc_in_state(state, crtc, crtc_state, i)
+   for_each_new_crtc_in_state(state, crtc, crtc_state, i)
c->crtc_mask |= drm_crtc_mask(crtc);
  
  	/*

 * Figure out what fence to wait for:
 */
-   for_each_plane_in_state(state, plane, plane_state, i) {
-   if ((plane->state->fb != plane_state->fb) && plane_state->fb) {
-   struct drm_gem_object *obj = 
msm_framebuffer_bo(plane_state->fb, 0);
+   for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
new_plane_state, i) {
+   if ((new_plane_state->fb != old_plane_state->fb) && 
new_plane_state->fb) {
+   struct drm_gem_object *obj = 
msm_framebuffer_bo(new_plane_state->fb, 0);
struct msm_gem_object *msm_obj = to_msm_bo(obj);
struct dma_fence *fence = 
reservation_object_get_excl_rcu(msm_obj->resv);

Pretty sure this fails to compile, you've forgotten to do one more
s/plane_state/new_plane_state/.

With that fixed:

Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch>


--->8---
for_each_obj_in_state is about to be removed, so convert
to the new iterator macros.

Just like in omap, use crtc_state->active instead of
crtc_state->enable when waiting for completion.

Changes since v1:
- Fix compilation.

Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>

Re: [Freedreno] [PATCH 05/11] drm/msm: get an iova from the address space instead of an id

[Archit Taneja]

On 02/06/2017 11:09 PM, Jordan Crouse wrote:

In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.

This forces a few changes in the gem object however: instead
of using a simple index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c |   8 +-
 drivers/gpu/drm/msm/adreno/a5xx_power.c   |   5 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   |   6 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c|  15 +++-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c  |   8 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  18 ++---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |   3 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c |  13 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c  |   5 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  11 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |   4 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  13 ++--
 drivers/gpu/drm/msm/msm_drv.c |  14 
 drivers/gpu/drm/msm/msm_drv.h |  25 +++---
 drivers/gpu/drm/msm/msm_fb.c  |  15 ++--
 drivers/gpu/drm/msm/msm_fbdev.c   |  10 ++-
 drivers/gpu/drm/msm/msm_gem.c | 124 +-
 drivers/gpu/drm/msm/msm_gem.h |   4 +-
 drivers/gpu/drm/msm/msm_gem_submit.c  |   4 +-
 drivers/gpu/drm/msm/msm_gpu.c |   8 +-
 drivers/gpu/drm/msm/msm_gpu.h |   1 -
 drivers/gpu/drm/msm/msm_kms.h |   3 +
 22 files changed, 184 insertions(+), 133 deletions(-)






diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index e8f41eb..0b5b839 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
@@ -20,6 +20,7 @@
 #include "drm_crtc.h"
 #include "drm_fb_helper.h"
 #include "msm_gem.h"
+#include "msm_kms.h"

 extern int msm_gem_mmap_obj(struct drm_gem_object *obj,
struct vm_area_struct *vma);
@@ -78,6 +79,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
 {
struct msm_fbdev *fbdev = to_msm_fbdev(helper);
struct drm_device *dev = helper->dev;
+   struct msm_drm_private *priv = dev->dev_private;
struct drm_framebuffer *fb = NULL;
struct fb_info *fbi = NULL;
struct drm_mode_fb_cmd2 mode_cmd = {0};
@@ -129,7 +131,13 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
 * in panic (ie. lock-safe, etc) we could avoid pinning the
 * buffer now:
 */
-   ret = msm_gem_get_iova_locked(fbdev->bo, 0, );
+
+   if (!priv->kms) {
+   ret = -ENODEV;
+   goto fail_unlock;
+   }


This check isn't needed. As of now, we don't create a fbdev device if we don't
have kms initialized.

Otherwise,

Reviewed-by: Archit Taneja <arch...@codeaurora.org>

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Re: [Freedreno] [PATCH 1/5] drm/msm/mdp5: introduce mdp5_hw_pipe

[Archit Taneja]

On 11/7/2016 8:18 PM, Rob Clark wrote:

On Mon, Nov 7, 2016 at 5:38 AM, Archit Taneja <arch...@codeaurora.org> wrote:



On 11/05/2016 09:55 PM, Rob Clark wrote:


Split out the hardware pipe specifics from mdp5_plane.  To start, the hw
pipes are statically assigned to planes, but next step is to assign the
hw pipes during plane->atomic_check() based on requested caps (scaling,
YUV, etc).  And then hw pipe re-assignment if required if required SMP
blocks changes.

Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
 drivers/gpu/drm/msm/Makefile  |   1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   | 126
+++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |   7 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c  |  43 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h  |  39 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  66 +++-
 6 files changed, 197 insertions(+), 85 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index fb5be3e..90f66c4 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -37,6 +37,7 @@ msm-y := \
mdp/mdp5/mdp5_irq.o \
mdp/mdp5/mdp5_mdss.o \
mdp/mdp5/mdp5_kms.o \
+   mdp/mdp5/mdp5_pipe.o \
mdp/mdp5/mdp5_plane.o \
mdp/mdp5/mdp5_smp.o \
msm_atomic.o \
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index f1288c7..d3d45ed 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -119,6 +119,10 @@ static void mdp5_kms_destroy(struct msm_kms *kms)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
struct msm_gem_address_space *aspace = mdp5_kms->aspace;
+   int i;
+
+   for (i = 0; i < mdp5_kms->num_hwpipes; i++)
+   mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);

if (aspace) {
aspace->mmu->funcs->detach(aspace->mmu,
@@ -323,15 +327,6 @@ static int modeset_init_intf(struct mdp5_kms
*mdp5_kms, int intf_num)

 static int modeset_init(struct mdp5_kms *mdp5_kms)
 {
-   static const enum mdp5_pipe rgb_planes[] = {
-   SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
-   };
-   static const enum mdp5_pipe vig_planes[] = {
-   SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
-   };
-   static const enum mdp5_pipe dma_planes[] = {
-   SSPP_DMA0, SSPP_DMA1,
-   };
struct drm_device *dev = mdp5_kms->dev;
struct msm_drm_private *priv = dev->dev_private;
const struct mdp5_cfg_hw *hw_cfg;
@@ -339,58 +334,34 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)

hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

-   /* construct CRTCs and their private planes: */
-   for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
+   /* Construct planes equaling the number of hw pipes, and CRTCs
+* for the N layer-mixers (LM).  The first N planes become primary
+* planes for the CRTCs, with the remainder as overlay planes:
+*/



Jfyi, we might need to change this a bit in the future. It'll be better to
get the max number of displays connected on our platform via parsing DT,
etc, and calculate CRTCs based on that, and not number of layermixers. Maybe
add a couple for writeback too. This way, we get the right number of
CRTCs, and we don't rely on #LMs, since we can have 2 per crtc
in the future.


I *guess* when we get to that stage, we'll dynamically assign LM's
too, in a similar way as hwpipe.  And I suppose we could also put a
cap on # of crtc's based on # of encoders?


Yeah. Currently, we end up creating 2 encoders for each DSI instance,
i.e, 1 for command mode, and another for video mode. Only one can be
used at a time. If we adjust for that, then I guess # of crtcs should
equal to # of encoders.

Archit



BR,
-R


Reviewed-by: Archit Taneja <arch...@codeaurora.org>

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Re: [Freedreno] [PATCH 1/5] drm/msm/mdp5: introduce mdp5_hw_pipe

[Archit Taneja]

On 11/05/2016 09:55 PM, Rob Clark wrote:

Split out the hardware pipe specifics from mdp5_plane.  To start, the hw
pipes are statically assigned to planes, but next step is to assign the
hw pipes during plane->atomic_check() based on requested caps (scaling,
YUV, etc).  And then hw pipe re-assignment if required if required SMP
blocks changes.

Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
 drivers/gpu/drm/msm/Makefile  |   1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   | 126 +++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |   7 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c  |  43 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h  |  39 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  66 +++-
 6 files changed, 197 insertions(+), 85 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index fb5be3e..90f66c4 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -37,6 +37,7 @@ msm-y := \
mdp/mdp5/mdp5_irq.o \
mdp/mdp5/mdp5_mdss.o \
mdp/mdp5/mdp5_kms.o \
+   mdp/mdp5/mdp5_pipe.o \
mdp/mdp5/mdp5_plane.o \
mdp/mdp5/mdp5_smp.o \
msm_atomic.o \
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index f1288c7..d3d45ed 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -119,6 +119,10 @@ static void mdp5_kms_destroy(struct msm_kms *kms)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
struct msm_gem_address_space *aspace = mdp5_kms->aspace;
+   int i;
+
+   for (i = 0; i < mdp5_kms->num_hwpipes; i++)
+   mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);

if (aspace) {
aspace->mmu->funcs->detach(aspace->mmu,
@@ -323,15 +327,6 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 
int intf_num)

 static int modeset_init(struct mdp5_kms *mdp5_kms)
 {
-   static const enum mdp5_pipe rgb_planes[] = {
-   SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
-   };
-   static const enum mdp5_pipe vig_planes[] = {
-   SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
-   };
-   static const enum mdp5_pipe dma_planes[] = {
-   SSPP_DMA0, SSPP_DMA1,
-   };
struct drm_device *dev = mdp5_kms->dev;
struct msm_drm_private *priv = dev->dev_private;
const struct mdp5_cfg_hw *hw_cfg;
@@ -339,58 +334,34 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)

hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

-   /* construct CRTCs and their private planes: */
-   for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
+   /* Construct planes equaling the number of hw pipes, and CRTCs
+* for the N layer-mixers (LM).  The first N planes become primary
+* planes for the CRTCs, with the remainder as overlay planes:
+*/


Jfyi, we might need to change this a bit in the future. It'll be better to
get the max number of displays connected on our platform via parsing DT,
etc, and calculate CRTCs based on that, and not number of layermixers. Maybe
add a couple for writeback too. This way, we get the right number of
CRTCs, and we don't rely on #LMs, since we can have 2 per crtc
in the future.

Reviewed-by: Archit Taneja <arch...@codeaurora.org>

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Re: [Freedreno] [PATCH 3/5] drm/msm/mdp5: add skeletal mdp5_state

[Archit Taneja]

On 11/05/2016 09:55 PM, Rob Clark wrote:

Add basic state duplication/apply mechanism.  Following commits will
move actual global hw state into this.

The state_lock allows multiple concurrent updates to proceed as long as
they don't both try to alter global state.  The ww_mutex mechanism will
trigger backoff in case of deadlock between multiple threads trying to
update state.

Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 43 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 22 +
 2 files changed, 65 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index d3d45ed..ca6dfeb 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -72,6 +72,39 @@ static int mdp5_hw_init(struct msm_kms *kms)
return 0;
 }

+struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s)
+{
+   struct msm_drm_private *priv = s->dev->dev_private;
+   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
+   struct msm_kms_state *state = to_kms_state(s);
+   struct mdp5_state *new_state;
+   int ret;
+
+   if (state->state)
+   return state->state;
+
+   ret = drm_modeset_lock(_kms->state_lock, s->acquire_ctx);
+   if (ret)
+   return ERR_PTR(ret);
+
+   new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
+   if (!new_state)
+   return ERR_PTR(-ENOMEM);
+
+   /* Copy state: */
+   /* TODO */
+
+   state->state = new_state;
+
+   return new_state;
+}
+
+static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state 
*state)
+{
+   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+   swap(to_kms_state(state)->state, mdp5_kms->state);
+}
+
 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state 
*state)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
@@ -140,6 +173,7 @@ static const struct mdp_kms_funcs kms_funcs = {
.irq = mdp5_irq,
.enable_vblank   = mdp5_enable_vblank,
.disable_vblank  = mdp5_disable_vblank,
+   .swap_state  = mdp5_swap_state,
.prepare_commit  = mdp5_prepare_commit,
.complete_commit = mdp5_complete_commit,
.wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done,
@@ -645,6 +679,8 @@ static void mdp5_destroy(struct platform_device *pdev)

if (mdp5_kms->rpm_enabled)
pm_runtime_disable(>dev);
+
+   kfree(mdp5_kms->state);
 }

 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
@@ -729,6 +765,13 @@ static int mdp5_init(struct platform_device *pdev, struct 
drm_device *dev)
mdp5_kms->dev = dev;
mdp5_kms->pdev = pdev;

+   drm_modeset_lock_init(_kms->state_lock);
+   mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
+   if (!mdp5_kms->state) {
+   ret = -ENOMEM;
+   goto fail;
+   }
+


This would probably be better in mdp5_kms_init() since it's intializing kms 
stuff, and
not hw resources. Otherwise:

Reviewed-by: Archit Taneja <arch...@codeaurora.org>



mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
if (IS_ERR(mdp5_kms->mmio)) {
ret = PTR_ERR(mdp5_kms->mmio);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index 88120c5..52914ec 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -27,6 +27,8 @@
 #include "mdp5_pipe.h"
 #include "mdp5_smp.h"

+struct mdp5_state;
+
 struct mdp5_kms {
struct mdp_kms base;

@@ -40,6 +42,11 @@ struct mdp5_kms {
struct mdp5_cfg_handler *cfg;
uint32_t caps;  /* MDP capabilities (MDP_CAP_XXX bits) */

+   /**
+* Global atomic state.  Do not access directly, use mdp5_get_state()
+*/
+   struct mdp5_state *state;
+   struct drm_modeset_lock state_lock;

/* mapper-id used to request GEM buffer mapped for scanout: */
int id;
@@ -69,6 +76,21 @@ struct mdp5_kms {
 };
 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)

+/* Global atomic state for tracking resources that are shared across
+ * multiple kms objects (planes/crtcs/etc).
+ *
+ * For atomic updates which require modifying global state,
+ */
+struct mdp5_state {
+   uint32_t dummy;
+};
+
+struct mdp5_state *__must_check
+mdp5_get_state(struct drm_atomic_state *s);
+
+/* Atomic plane state.  Subclasses the base drm_plane_state in order to
+ * track assigned hwpipe and hw specific state.
+ */
 struct mdp5_plane_state {
struct drm_plane_state

Re: [Freedreno] [PATCH] drm/msm/mdp5: handle non-fullscreen base plane case

[Archit Taneja]

On 10/13/2016 10:18 PM, Rob Clark wrote:

If the bottom-most layer is not fullscreen, we need to use the BASE
mixer stage for solid fill (ie. MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT).  The
blend_setup() code pretty much handled this already, we just had to
figure this out in _atomic_check() and assign the stages appropriately.

Signed-off-by: Rob Clark 
---
TODO mdp4 might need similar treatment?

 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 44 
 1 file changed, 27 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index fa2be7c..e42f62d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -223,11 +223,6 @@ static void blend_setup(struct drm_crtc *crtc)
plane_cnt++;
}

-   /*
-   * If there is no base layer, enable border color.
-   * Although it's not possbile in current blend logic,
-   * put it here as a reminder.
-   */
if (!pstates[STAGE_BASE] && plane_cnt) {
ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
DBG("Border Color is enabled");
@@ -365,6 +360,15 @@ static int pstate_cmp(const void *a, const void *b)
return pa->state->zpos - pb->state->zpos;
 }

+/* is there a helper for this? */
+static bool is_fullscreen(struct drm_crtc_state *cstate,
+   struct drm_plane_state *pstate)
+{
+   return (pstate->crtc_x == 0) && (pstate->crtc_y == 0) &&
+   (pstate->crtc_w == cstate->mode.hdisplay) &&
+   (pstate->crtc_h == cstate->mode.vdisplay);
+}
+
 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -375,21 +379,11 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
struct plane_state pstates[STAGE_MAX + 1];
const struct mdp5_cfg_hw *hw_cfg;
const struct drm_plane_state *pstate;
-   int cnt = 0, i;
+   int cnt = 0, base = 0, i;

DBG("%s: check", mdp5_crtc->name);

-   /* verify that there are not too many planes attached to crtc
-* and that we don't have conflicting mixer stages:
-*/
-   hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
-   if (cnt >= (hw_cfg->lm.nb_stages)) {
-   dev_err(dev->dev, "too many planes!\n");
-   return -EINVAL;
-   }
-
-
pstates[cnt].plane = plane;
pstates[cnt].state = to_mdp5_plane_state(pstate);

@@ -399,8 +393,24 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
/* assign a stage based on sorted zpos property */
sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);

+   /* if the bottom-most layer is not fullscreen, we need to use
+* it for solid-color:
+*/
+   if (!is_fullscreen(state, [0].state->base))
+   base++;
+


I get a crash here when fbcon is enabled and there are no connectors
connected. We're trying to refer pstates[0] when there is no plane
connected to the crtc. I guess we could bail out much earlier if cnt
is 0.

Archit


+   /* verify that there are not too many planes attached to crtc
+* and that we don't have conflicting mixer stages:
+*/
+   hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
+
+   if ((cnt + base) >= hw_cfg->lm.nb_stages) {
+   dev_err(dev->dev, "too many planes!\n");
+   return -EINVAL;
+   }
+
for (i = 0; i < cnt; i++) {
-   pstates[i].state->stage = STAGE_BASE + i;
+   pstates[i].state->stage = STAGE_BASE + i + base;
DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
pipe2name(mdp5_plane_pipe(pstates[i].plane)),
pstates[i].state->stage);



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Re: [Freedreno] [PATCH] drm/msm/mdp5: handle non-fullscreen base plane case

[Archit Taneja]

On 10/13/2016 10:18 PM, Rob Clark wrote:

If the bottom-most layer is not fullscreen, we need to use the BASE
mixer stage for solid fill (ie. MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT).  The
blend_setup() code pretty much handled this already, we just had to
figure this out in _atomic_check() and assign the stages appropriately.


The patch looks good. I couldn't test the problematic scenario since I
don't have an easy way to reproduce it, but it doesn't break regular
usage (where base layer is full screen).

Reviewed-by: Archit Taneja <arch...@codeaurora.org>



Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
TODO mdp4 might need similar treatment?

 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 44 
 1 file changed, 27 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index fa2be7c..e42f62d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -223,11 +223,6 @@ static void blend_setup(struct drm_crtc *crtc)
plane_cnt++;
}

-   /*
-   * If there is no base layer, enable border color.
-   * Although it's not possbile in current blend logic,
-   * put it here as a reminder.
-   */
if (!pstates[STAGE_BASE] && plane_cnt) {
ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
DBG("Border Color is enabled");
@@ -365,6 +360,15 @@ static int pstate_cmp(const void *a, const void *b)
return pa->state->zpos - pb->state->zpos;
 }

+/* is there a helper for this? */
+static bool is_fullscreen(struct drm_crtc_state *cstate,
+   struct drm_plane_state *pstate)
+{
+   return (pstate->crtc_x == 0) && (pstate->crtc_y == 0) &&
+   (pstate->crtc_w == cstate->mode.hdisplay) &&
+   (pstate->crtc_h == cstate->mode.vdisplay);
+}
+
 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -375,21 +379,11 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
struct plane_state pstates[STAGE_MAX + 1];
const struct mdp5_cfg_hw *hw_cfg;
const struct drm_plane_state *pstate;
-   int cnt = 0, i;
+   int cnt = 0, base = 0, i;

DBG("%s: check", mdp5_crtc->name);

-   /* verify that there are not too many planes attached to crtc
-* and that we don't have conflicting mixer stages:
-*/
-   hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
-   if (cnt >= (hw_cfg->lm.nb_stages)) {
-   dev_err(dev->dev, "too many planes!\n");
-   return -EINVAL;
-   }
-
-
pstates[cnt].plane = plane;
pstates[cnt].state = to_mdp5_plane_state(pstate);

@@ -399,8 +393,24 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
/* assign a stage based on sorted zpos property */
sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);

+   /* if the bottom-most layer is not fullscreen, we need to use
+* it for solid-color:
+*/
+   if (!is_fullscreen(state, [0].state->base))
+   base++;
+
+   /* verify that there are not too many planes attached to crtc
+* and that we don't have conflicting mixer stages:
+*/
+   hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
+
+   if ((cnt + base) >= hw_cfg->lm.nb_stages) {
+   dev_err(dev->dev, "too many planes!\n");
+   return -EINVAL;
+   }
+
for (i = 0; i < cnt; i++) {
-   pstates[i].state->stage = STAGE_BASE + i;
+   pstates[i].state->stage = STAGE_BASE + i + base;
DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
pipe2name(mdp5_plane_pipe(pstates[i].plane)),
pstates[i].state->stage);



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Re: [Freedreno] [PATCH] drm: msm: mdp4: mark symbols static where possible

[Archit Taneja]

On 09/07/2016 04:28 PM, Baoyou Xie wrote:

We get 2 warnings when building kernel with W=1:
drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c:96:23: warning: no previous 
prototype for 'get_connector' [-Wmissing-prototypes]
drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c:84:5: warning: no previous prototype 
for 'mdp4_plane_set_property' [-Wmissing-prototypes]

In fact, these functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.


Reviewed-by: Archit Taneja <arch...@codeaurora.org>



Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
  drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c | 2 +-
  drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c| 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c
index bc3d8e7..a06b064 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c
@@ -93,7 +93,7 @@ static const struct drm_encoder_funcs mdp4_lcdc_encoder_funcs 
= {
  };

  /* this should probably be a helper: */
-struct drm_connector *get_connector(struct drm_encoder *encoder)
+static struct drm_connector *get_connector(struct drm_encoder *encoder)
  {
struct drm_device *dev = encoder->dev;
struct drm_connector *connector;
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
index 9f96dfe..c5adef0 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
@@ -81,7 +81,7 @@ static void mdp4_plane_install_properties(struct drm_plane 
*plane,
// XXX
  }

-int mdp4_plane_set_property(struct drm_plane *plane,
+static int mdp4_plane_set_property(struct drm_plane *plane,
struct drm_property *property, uint64_t val)
  {
// XXX



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Re: [Freedreno] [PATCH 6/7] drm/msm: Remove redundant calls to drm_connector_register_all()

[Archit Taneja]

On 06/17/2016 01:55 PM, Chris Wilson wrote:

Up to now, the recommendation was for drivers to call drm_dev_register()
followed by drm_connector_register_all(). Now that
drm_connector_register() is safe against multiple invocations, we can
move drm_connector_register_all() to drm_dev_register() and not suffer
from any backwards compatibility issues with drivers not following the
more rigorous init ordering.



Tested-by: Archit Taneja <arch...@codeaurora.org>


Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
Cc: Rob Clark <robdcl...@gmail.com>
Cc: David Airlie <airl...@linux.ie>
Cc: dri-de...@lists.freedesktop.org
Cc: linux-arm-...@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
---
  drivers/gpu/drm/msm/msm_drv.c | 8 
  1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 9c654092ef78..568fcc328f27 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -197,8 +197,6 @@ static int msm_drm_uninit(struct device *dev)

drm_kms_helper_poll_fini(ddev);

-   drm_connector_unregister_all(ddev);
-
drm_dev_unregister(ddev);

  #ifdef CONFIG_DRM_FBDEV_EMULATION
@@ -431,12 +429,6 @@ static int msm_drm_init(struct device *dev, struct 
drm_driver *drv)
if (ret)
goto fail;

-   ret = drm_connector_register_all(ddev);
-   if (ret) {
-   dev_err(dev, "failed to register connectors\n");
-   goto fail;
-   }
-
drm_mode_config_reset(ddev);

  #ifdef CONFIG_DRM_FBDEV_EMULATION



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