Re: [PATCH] drm/msm/dpu: drop duplicate drm formats from wb2_formats arrays
On Fri, May 24, 2024 at 11:19:41AM -0700, Abhinav Kumar wrote:
>
>
> On 5/24/2024 8:01 AM, Junhao Xie wrote:
> > There are duplicate items in wb2_formats_rgb and wb2_formats_rgb_yuv,
> > which cause weston assertions failed.
> >
> > weston: libweston/drm-formats.c:131: weston_drm_format_array_add_format:
> > Assertion `!weston_drm_format_array_find_format(formats, format)' failed.
> >
> > Signed-off-by: Junhao Xie
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 --
> > 1 file changed, 6 deletions(-)
> >
>
> I think we need two fixes tag here, one for the RGB array and the other one
> for the RGB+YUV array.
>
> Fixes: 8c16b988ba2d ("drm/msm/dpu: introduce separate wb2_format arrays for
> rgb and yuv")
>
> Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU
> catalog")
>
> Reviewed-by: Abhinav Kumar
>
> (pls ignore the line breaks in the fixes line, I will fix it while applying)
With the Fixes tags in place:
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH v2] Revert "drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set"
On Fri, May 24, 2024 at 12:58:53PM -0700, Abhinav Kumar wrote:
>
>
> On 5/22/2024 3:24 AM, Dmitry Baryshkov wrote:
> > In the DPU driver blank IRQ handling is called from a vblank worker and
> > can happen outside of the irq_enable / irq_disable pair. Using the
> > worker makes that completely asynchronous with the rest of the code.
> > Revert commit d13f638c9b88 ("drm/msm/dpu: drop
> > dpu_encoder_phys_ops.atomic_mode_set") to fix vblank IRQ assignment for
> > CMD DSI panels.
> >
> > Call trace:
> > dpu_encoder_phys_cmd_control_vblank_irq+0x218/0x294
> >dpu_encoder_toggle_vblank_for_crtc+0x160/0x194
> >dpu_crtc_vblank+0xbc/0x228
> >dpu_kms_enable_vblank+0x18/0x24
> >vblank_ctrl_worker+0x34/0x6c
> >process_one_work+0x218/0x620
> >worker_thread+0x1ac/0x37c
> >kthread+0x114/0x118
> >ret_from_fork+0x10/0x20
> >
>
> Thanks for the stack.
>
> Agreed that vblank can be controlled asynchronously through the worker.
>
> And I am guessing that the worker thread ran and printed this error message
> because phys_enc->irq[INTR_IDX_VSYNC] was not valid as modeset had not
> happened by then?
modeset happened, but the vblanks can be enabled and disabled
afterwards.
>
> 272 end:
> 273 if (ret) {
> 274 DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n",
> 275 DRMID(phys_enc->parent),
> 276 phys_enc->hw_pp->idx - PINGPONG_0, ret,
> 277 enable ? "true" : "false", refcount);
> 278 }
>
> But how come this did not happen even with this revert.
>
> IOW, I am still missing how moving the irq assignment back to modeset from
> enable is fixing this?
It removes clearing of the IRQ fields in the irq_disable path, which
removes a requirement that vblank IRQ manipulations are called only
within the irq_enable/irq_disable brackets. I didn't have time to debug
this further on, so I think it's better to revert it now and return to
this cleanup later.
>
> > Fixes: d13f638c9b88 ("drm/msm/dpu: drop
> > dpu_encoder_phys_ops.atomic_mode_set")
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > Changes in v2:
> > - Expanded commit message to describe the reason for revert and added a
> >call trace (Abhinav)
> > - Link to v1:
> > https://lore.kernel.org/r/20240514-dpu-revert-ams-v1-1-b13623d6c...@linaro.org
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 2 ++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5
> > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 32
> > --
> > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 +++--
> > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 11 +++-
> > 5 files changed, 46 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 119f3ea50a7c..a7d8ecf3f5be 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -1200,6 +1200,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct
> > drm_encoder *drm_enc,
> > phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
> > phys->cached_mode = crtc_state->adjusted_mode;
> > + if (phys->ops.atomic_mode_set)
> > + phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
> > }
> > }
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > index 002e89cc1705..30470cd15a48 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > @@ -69,6 +69,8 @@ struct dpu_encoder_phys;
> >* @is_master:Whether this phys_enc is the current
> > master
> >*encoder. Can be switched at enable
> > time. Based
> >*on split_role and current mode
> > (CMD/VID).
> > + * @atomic_mode_set: DRM Call. Set a DRM mode.
> > + * This likely caches the mode, for use at enable.
> >* @enable: DRM Call. Enable a DRM mode.
> >* @disable: DRM Call. Disable mode.
> >* @control_vblank_irqRegister/Deregister for VBLANK IRQ
> > @@ -93,6 +95,9 @@ struct dpu_encoder_phys;
> > struct dpu_encoder
Re: [PATCH v4 1/5] drm/msm/dpu: fix video mode DSC for DSI
On Fri, May 24, 2024 at 09:18:21PM +0800, Jun Nie wrote:
> From: Jonathan Marek
>
> Add necessary DPU timing and control changes for DSC to work with DSI
> video mode.
>
> Signed-off-by: Jonathan Marek
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4
> 4 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 119f3ea50a7c..48cef6e79c70 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
> *drm_enc)
> return (num_dsc > 0) && (num_dsc > intf_count);
> }
>
> -static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
> *drm_enc)
> +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
> *drm_enc)
> {
> struct msm_drm_private *priv = drm_enc->dev->dev_private;
> struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index 002e89cc1705..2167c46c1a45 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode
> dpu_encoder_helper_get_3d_blend_mode(
> */
> unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
>
> +/**
> + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
> + * This helper function is used by physical encoder to get DSC config
> + * used for this encoder.
> + * @drm_enc: Pointer to encoder structure
> + */
> +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
> *drm_enc);
> +
> /**
> * dpu_encoder_get_drm_fmt - return DRM fourcc format
> * @phys_enc: Pointer to physical encoder structure
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ef69c2f408c3..7047b607ca91 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -115,6 +115,19 @@ static void drm_mode_to_intf_timing_params(
> timing->h_front_porch = timing->h_front_porch >> 1;
> timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
> }
> +
> + /*
> + * for DSI, if compression is enabled, then divide the horizonal active
> + * timing parameters by compression ratio. bits of 3 components(R/G/B)
> + * is compressed into bits of 1 pixel.
> + */
> + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
> + struct drm_dsc_config *dsc =
> +dpu_encoder_get_dsc_config(phys_enc->parent);
> + timing->width = timing->width * (dsc->bits_per_pixel >> 4) /
Here you are truncating fractional part of BPP. Please use
drm_dsc_get_bpp_int(), at least it will warn if there is a fractional
part. Or, even better, add a helper to calculate width * bpp / 64 / (bpc
* 3) and use it here and in dsi_adjust_pclk_for_compression()
> + (dsc->bits_per_component * 3);
> + timing->xres = timing->width;
> + }
> }
>
> static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params
> *timing)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 225c1c7768ff..2cf1f8c116b5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -168,6 +168,10 @@ static void dpu_hw_intf_setup_timing_engine(struct
> dpu_hw_intf *intf,
>
> data_width = p->width;
>
> + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
> + if (p->compression_en && !dp_intf)
> + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
> +
Separate commit, please
> hsync_data_start_x = hsync_start_x;
> hsync_data_end_x = hsync_start_x + data_width - 1;
>
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
Re: [PATCH 1/7] dt-bindings: display/msm/dsi: allow specifying TE source
On Thu, 23 May 2024 at 02:57, Abhinav Kumar wrote:
>
>
>
> On 5/22/2024 1:05 PM, Dmitry Baryshkov wrote:
> > On Wed, 22 May 2024 at 21:38, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
> >>> Command mode panels provide TE signal back to the DSI host to signal
> >>> that the frame display has completed and update of the image will not
> >>> cause tearing. Usually it is connected to the first GPIO with the
> >>> mdp_vsync function, which is the default. In such case the property can
> >>> be skipped.
> >>>
> >>
> >> This is a good addition overall. Some comments below.
> >>
> >>> Signed-off-by: Dmitry Baryshkov
> >>> ---
> >>>.../bindings/display/msm/dsi-controller-main.yaml| 16
> >>>
> >>>1 file changed, 16 insertions(+)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> index 1fa28e976559..c1771c69b247 100644
> >>> ---
> >>> a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> +++
> >>> b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> @@ -162,6 +162,21 @@ properties:
> >>>items:
> >>> enum: [ 0, 1, 2, 3 ]
> >>>
> >>> + qcom,te-source:
> >>> +$ref: /schemas/types.yaml#/definitions/string
> >>> +description:
> >>> + Specifies the source of vsync signal from the panel
> >>> used for
> >>> + tearing elimination. The default is mdp_gpio0.
> >>
> >> panel --> command mode panel?
> >>
> >>> +enum:
> >>> + - mdp_gpio0
> >>> + - mdp_gpio1
> >>> + - mdp_gpio2
> >>
> >> are gpio0, gpio1 and gpio2 referring to the vsync_p, vsync_s and vsync_e
> >> sources?
> >
> > No idea, unfortunately. They are gpioN or just mdp_vsync all over the
> > place. For the reference, in case of the SDM845 and Pixel3 the signal
> > is routed through SoC GPIO12.
> >
>
> GPIO12 on sdm845 is mdp_vsync_e.
>
> Thats why I think its better we use mdp_vsync_p/s/e instead of mdp_gpio0/1/2
Sure. This matches pins description. Are you fine with changing
defines in DPU driver to VSYNC_P / _S / _E too ?
>
> >> In that case wouldnt it be better to name it like that?
> >>
> >>> + - timer0
> >>> + - timer1
> >>> + - timer2
> >>> + - timer3
> >>> + - timer4
> >>> +
> >>
> >> These are indicating watchdog timer sources right?
> >
> > Yes.
> >
> >>
> >>>required:
> >>> - port@0
> >>> - port@1
> >>> @@ -452,6 +467,7 @@ examples:
> >>> dsi0_out: endpoint {
> >>> remote-endpoint = <_in>;
> >>> data-lanes = <0 1 2 3>;
> >>> + qcom,te-source = "mdp_gpio2";
> >>
> >> I have a basic doubt on this. Should te-source should be in the input
> >> port or the output one for the controller? Because TE is an input to the
> >> DSI. And if the source is watchdog timer then it aligns even more as a
> >> property of the input endpoint.
> >
> > I don't really want to split this. Both data-lanes and te-source are
> > properties of the link between the DSI and panel. You can not really
> > say which side has which property.
> >
>
> TE is an input to the DSI from the panel. Between input and output port,
> I think it belongs more to the input port.
Technically we don't have in/out ports. There are two ports which
define a link between two instances. For example, if the panel
supports getting information through DCS commands, then "panel input"
also becomes "panel output".
>
> I didnt follow why this is a link property. Sorry , I didnt follow the
> split part.
There is a link between the DSI host and the panel. I don't want to
end up in a situation when the properties of the link are split
between two different nodes.
>
> If we are unsure about input vs output port, do you think its better we
> make it a property of the main dsi node instead?
No, it's not a property of the DSI node at all. If the vendor rewires
the panel GPIOs or (just for example regulators), it has nothing to do
with the DSI host.
--
With best wishes
Dmitry
Re: [PATCH 1/7] dt-bindings: display/msm/dsi: allow specifying TE source
On Wed, 22 May 2024 at 21:38, Abhinav Kumar wrote:
>
>
>
> On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
> > Command mode panels provide TE signal back to the DSI host to signal
> > that the frame display has completed and update of the image will not
> > cause tearing. Usually it is connected to the first GPIO with the
> > mdp_vsync function, which is the default. In such case the property can
> > be skipped.
> >
>
> This is a good addition overall. Some comments below.
>
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > .../bindings/display/msm/dsi-controller-main.yaml| 16
> >
> > 1 file changed, 16 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> > b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> > index 1fa28e976559..c1771c69b247 100644
> > --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> > +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> > @@ -162,6 +162,21 @@ properties:
> > items:
> > enum: [ 0, 1, 2, 3 ]
> >
> > + qcom,te-source:
> > +$ref: /schemas/types.yaml#/definitions/string
> > +description:
> > + Specifies the source of vsync signal from the panel used
> > for
> > + tearing elimination. The default is mdp_gpio0.
>
> panel --> command mode panel?
>
> > +enum:
> > + - mdp_gpio0
> > + - mdp_gpio1
> > + - mdp_gpio2
>
> are gpio0, gpio1 and gpio2 referring to the vsync_p, vsync_s and vsync_e
> sources?
No idea, unfortunately. They are gpioN or just mdp_vsync all over the
place. For the reference, in case of the SDM845 and Pixel3 the signal
is routed through SoC GPIO12.
> In that case wouldnt it be better to name it like that?
>
> > + - timer0
> > + - timer1
> > + - timer2
> > + - timer3
> > + - timer4
> > +
>
> These are indicating watchdog timer sources right?
Yes.
>
> > required:
> > - port@0
> > - port@1
> > @@ -452,6 +467,7 @@ examples:
> > dsi0_out: endpoint {
> > remote-endpoint = <_in>;
> > data-lanes = <0 1 2 3>;
> > + qcom,te-source = "mdp_gpio2";
>
> I have a basic doubt on this. Should te-source should be in the input
> port or the output one for the controller? Because TE is an input to the
> DSI. And if the source is watchdog timer then it aligns even more as a
> property of the input endpoint.
I don't really want to split this. Both data-lanes and te-source are
properties of the link between the DSI and panel. You can not really
say which side has which property.
> > };
> > };
> > };
> >
--
With best wishes
Dmitry
Re: [PATCH 2/7] drm/msm/dpu: convert vsync source defines to the enum
On Wed, 22 May 2024 at 21:41, Abhinav Kumar wrote:
>
>
>
> On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
> > Add enum dpu_vsync_source instead of a series of defines. Use this enum
> > to pass vsync information.
> >
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 26
> > ++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 2 +-
> > 5 files changed, 18 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> > index 66759623fc42..a2eff36a2224 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> > @@ -54,18 +54,20 @@
> > #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12)
> > #define DPU_BLEND_BG_TRANSP_EN (1 << 13)
> >
> > -#define DPU_VSYNC0_SOURCE_GPIO 0
> > -#define DPU_VSYNC1_SOURCE_GPIO 1
> > -#define DPU_VSYNC2_SOURCE_GPIO 2
> > -#define DPU_VSYNC_SOURCE_INTF_0 3
> > -#define DPU_VSYNC_SOURCE_INTF_1 4
> > -#define DPU_VSYNC_SOURCE_INTF_2 5
> > -#define DPU_VSYNC_SOURCE_INTF_3 6
> > -#define DPU_VSYNC_SOURCE_WD_TIMER_4 11
> > -#define DPU_VSYNC_SOURCE_WD_TIMER_3 12
> > -#define DPU_VSYNC_SOURCE_WD_TIMER_2 13
> > -#define DPU_VSYNC_SOURCE_WD_TIMER_1 14
> > -#define DPU_VSYNC_SOURCE_WD_TIMER_0 15
> > +enum dpu_vsync_source {
> > + DPU_VSYNC_SOURCE_GPIO_0,
> > + DPU_VSYNC_SOURCE_GPIO_1,
> > + DPU_VSYNC_SOURCE_GPIO_2,
> > + DPU_VSYNC_SOURCE_INTF_0 = 3,
>
> Do we need this assignment to 3?
It is redundant, but it points out that if at some point another GPIO
is added, it should go to the end (or to some other place, having the
proper value).
>
> Rest LGTM,
>
> Reviewed-by: Abhinav Kumar
--
With best wishes
Dmitry
Re: [PATCH 0/7] drm/msm/dpu: handle non-default TE source pins
On Wed, 22 May 2024 at 21:39, Abhinav Kumar wrote: > > > > On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote: > > Command-mode DSI panels need to signal the display controlller when > > vsync happens, so that the device can start sending the next frame. Some > > devices (Google Pixel 3) use a non-default pin, so additional > > configuration is required. Add a way to specify this information in DT > > and handle it in the DSI and DPU drivers. > > > > Which pin is the pixel 3 using? Just wanted to know .. is it gpio0 or gpio1? gpio2. If it was gpio0 then there were no issues at all. > > > Signed-off-by: Dmitry Baryshkov > > --- > > Dmitry Baryshkov (7): > >dt-bindings: display/msm/dsi: allow specifying TE source > >drm/msm/dpu: convert vsync source defines to the enum > >drm/msm/dsi: drop unused GPIOs handling > >drm/msm/dpu: pull the is_cmd_mode out of > > _dpu_encoder_update_vsync_source() > >drm/msm/dpu: rework vsync_source handling > >drm/msm/dsi: parse vsync source from device tree > >drm/msm/dpu: support setting the TE source > > > > .../bindings/display/msm/dsi-controller-main.yaml | 16 > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 11 ++--- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 5 +-- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 2 +- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 2 +- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 26 ++-- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 2 +- > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 44 > > > > drivers/gpu/drm/msm/dsi/dsi.h | 1 + > > drivers/gpu/drm/msm/dsi/dsi_host.c | 48 > > +- > > drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +++ > > drivers/gpu/drm/msm/msm_drv.h | 6 +++ > > 12 files changed, 106 insertions(+), 62 deletions(-) > > --- > > base-commit: 75fa778d74b786a1608d55d655d42b480a6fa8bd > > change-id: 20240514-dpu-handle-te-signal-82663c0211bd > > > > Best regards, -- With best wishes Dmitry
[PATCH v2 13/14] drm/msm/hdmi: ensure that HDMI is one if HPD is requested
The HDMI block needs to be enabled to properly generate HPD events. Make
sure it is not turned off in the disable paths if HPD delivery is enabled.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h| 2 ++
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 8 +++-
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 9 -
4 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index a9437054c015..2890196857f8 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -409,6 +409,7 @@ static int msm_hdmi_dev_probe(struct platform_device *pdev)
hdmi->pdev = pdev;
hdmi->config = config;
spin_lock_init(>reg_lock);
+ mutex_init(>state_mutex);
ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, 1, 0, NULL,
>next_bridge);
if (ret && ret != -ENODEV)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 268ff8604423..7f0ca5252018 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -42,6 +42,8 @@ struct hdmi {
/* video state: */
bool power_on;
+ bool hpd_enabled;
+ struct mutex state_mutex; /* protects two booleans */
unsigned long int pixclock;
void __iomem *mmio;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index cddba640d292..104107ed47d0 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -117,11 +117,13 @@ static void msm_hdmi_bridge_atomic_pre_enable(struct
drm_bridge *bridge,
DBG("power up");
+ mutex_lock(>state_mutex);
if (!hdmi->power_on) {
msm_hdmi_phy_resource_enable(phy);
msm_hdmi_power_on(bridge);
hdmi->power_on = true;
}
+ mutex_unlock(>state_mutex);
if (hdmi->hdmi_mode) {
msm_hdmi_config_avi_infoframe(hdmi);
@@ -147,7 +149,10 @@ static void msm_hdmi_bridge_atomic_post_disable(struct
drm_bridge *bridge,
msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
DBG("power down");
- msm_hdmi_set_mode(hdmi, false);
+
+ /* Keep the HDMI enabled if the HPD is enabled */
+ mutex_lock(>state_mutex);
+ msm_hdmi_set_mode(hdmi, hdmi->hpd_enabled);
msm_hdmi_phy_powerdown(phy);
@@ -158,6 +163,7 @@ static void msm_hdmi_bridge_atomic_post_disable(struct
drm_bridge *bridge,
msm_hdmi_audio_update(hdmi);
msm_hdmi_phy_resource_disable(phy);
}
+ mutex_unlock(>state_mutex);
}
static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index d3353c6148ed..cb89e9e2c6ea 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -73,10 +73,14 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
if (ret)
return ret;
+ mutex_lock(>state_mutex);
msm_hdmi_set_mode(hdmi, false);
msm_hdmi_phy_reset(hdmi);
msm_hdmi_set_mode(hdmi, true);
+ hdmi->hpd_enabled = true;
+ mutex_unlock(>state_mutex);
+
hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b);
/* enable HPD events: */
@@ -106,7 +110,10 @@ void msm_hdmi_hpd_disable(struct hdmi *hdmi)
/* Disable HPD interrupt */
hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0);
- msm_hdmi_set_mode(hdmi, false);
+ mutex_lock(>state_mutex);
+ hdmi->hpd_enabled = false;
+ msm_hdmi_set_mode(hdmi, hdmi->power_on);
+ mutex_unlock(>state_mutex);
pm_runtime_put(dev);
}
--
2.39.2
[PATCH v2 11/14] drm/msm/hdmi: expand the HDMI_CFG macro
Expand the HDMI_CFG() macro in HDMI config description. It has no added
value other than hiding some boilerplate declarations.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 16
drivers/gpu/drm/msm/hdmi/hdmi.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c39a1f3a7505..e160a23e962e 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -223,24 +223,24 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
* The hdmi device:
*/
-#define HDMI_CFG(item, entry) \
- .item ## _names = item ##_names_ ## entry, \
- .item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry)
-
static const char *pwr_reg_names_8960[] = {"core-vdda"};
static const char *pwr_clk_names_8960[] = {"core", "master_iface",
"slave_iface"};
static const struct hdmi_platform_config hdmi_tx_8960_config = {
- HDMI_CFG(pwr_reg, 8960),
- HDMI_CFG(pwr_clk, 8960),
+ .pwr_reg_names = pwr_reg_names_8960,
+ .pwr_reg_cnt = ARRAY_SIZE(pwr_reg_names_8960),
+ .pwr_clk_names = pwr_clk_names_8960,
+ .pwr_clk_cnt = ARRAY_SIZE(pwr_clk_names_8960),
};
static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"};
static const char *pwr_clk_names_8x74[] = {"iface", "core", "mdp_core",
"alt_iface"};
static const struct hdmi_platform_config hdmi_tx_8974_config = {
- HDMI_CFG(pwr_reg, 8x74),
- HDMI_CFG(pwr_clk, 8x74),
+ .pwr_reg_names = pwr_reg_names_8x74,
+ .pwr_reg_cnt = ARRAY_SIZE(pwr_reg_names_8x74),
+ .pwr_clk_names = pwr_clk_names_8x74,
+ .pwr_clk_cnt = ARRAY_SIZE(pwr_clk_names_8x74),
};
/*
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 1e346e697f8e..2a98efa8b6bd 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -89,7 +89,7 @@ struct hdmi_platform_config {
const char **pwr_reg_names;
int pwr_reg_cnt;
- /* clks that need to be on for hpd: */
+ /* clks that need to be on: */
const char **pwr_clk_names;
int pwr_clk_cnt;
};
--
2.39.2
[PATCH v2 14/14] drm/msm/hdmi: wire in hpd_enable/hpd_disable bridge ops
The HDMI driver already has msm_hdmi_hpd_enable() and
msm_hdmi_hpd_disable() functions. Wire them into the
msm_hdmi_bridge_funcs, so that HPD can be enabled and disabled
dynamically rather than always having HPD events generation enabled.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 9 -
drivers/gpu/drm/msm/hdmi/hdmi.h| 4 ++--
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 3 +++
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 12 ++--
4 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 2890196857f8..06adcf4a6544 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -202,12 +202,6 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
goto fail;
}
- ret = msm_hdmi_hpd_enable(hdmi->bridge);
- if (ret < 0) {
- DRM_DEV_ERROR(>pdev->dev, "failed to enable HPD: %d\n",
ret);
- goto fail;
- }
-
return 0;
fail:
@@ -377,9 +371,6 @@ static void msm_hdmi_unbind(struct device *dev, struct
device *master,
if (priv->hdmi->audio_pdev)
platform_device_unregister(priv->hdmi->audio_pdev);
- if (priv->hdmi->bridge)
- msm_hdmi_hpd_disable(priv->hdmi);
-
msm_hdmi_destroy(priv->hdmi);
priv->hdmi = NULL;
}
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 7f0ca5252018..c6519e6f7f2c 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -219,8 +219,8 @@ int msm_hdmi_bridge_init(struct hdmi *hdmi);
void msm_hdmi_hpd_irq(struct drm_bridge *bridge);
enum drm_connector_status msm_hdmi_bridge_detect(
struct drm_bridge *bridge);
-int msm_hdmi_hpd_enable(struct drm_bridge *bridge);
-void msm_hdmi_hpd_disable(struct hdmi *hdmi);
+void msm_hdmi_hpd_enable(struct drm_bridge *bridge);
+void msm_hdmi_hpd_disable(struct drm_bridge *bridge);
/*
* i2c adapter for ddc:
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 104107ed47d0..41722b2e6b44 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -300,6 +300,9 @@ static const struct drm_bridge_funcs msm_hdmi_bridge_funcs
= {
.mode_valid = msm_hdmi_bridge_mode_valid,
.edid_read = msm_hdmi_bridge_edid_read,
.detect = msm_hdmi_bridge_detect,
+
+ .hpd_enable = msm_hdmi_hpd_enable,
+ .hpd_disable = msm_hdmi_hpd_disable,
};
static void
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index cb89e9e2c6ea..04d00b6f36fd 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -60,7 +60,7 @@ static void msm_hdmi_phy_reset(struct hdmi *hdmi)
}
}
-int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
+void msm_hdmi_hpd_enable(struct drm_bridge *bridge)
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;
@@ -70,8 +70,8 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
unsigned long flags;
ret = pm_runtime_resume_and_get(dev);
- if (ret)
- return ret;
+ if (WARN_ON(ret))
+ return;
mutex_lock(>state_mutex);
msm_hdmi_set_mode(hdmi, false);
@@ -99,12 +99,12 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
hdmi_write(hdmi, REG_HDMI_HPD_CTRL,
HDMI_HPD_CTRL_ENABLE | hpd_ctrl);
spin_unlock_irqrestore(>reg_lock, flags);
-
- return 0;
}
-void msm_hdmi_hpd_disable(struct hdmi *hdmi)
+void msm_hdmi_hpd_disable(struct drm_bridge *bridge)
{
+ struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
+ struct hdmi *hdmi = hdmi_bridge->hdmi;
struct device *dev = >pdev->dev;
/* Disable HPD interrupt */
--
2.39.2
[PATCH v2 12/14] drm/msm/hdmi: drop hpd-gpios support
Supporting simultaneous check of native HPD and the external GPIO proved
to be less stable than just native HPD. Drop the hpd-gpios support,
leaving just the native HPD support. In case the native HPD doesn't work
the user is urged to switch to specifying the HPD property to the
hdmi-connector device.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 14 +++---
drivers/gpu/drm/msm/hdmi/hdmi.h | 2 --
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 53 +++--
3 files changed, 7 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index e160a23e962e..a9437054c015 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -468,17 +468,9 @@ static int msm_hdmi_dev_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(hdmi->extp_clk),
"failed to get extp clock\n");
- hdmi->hpd_gpiod = devm_gpiod_get_optional(>dev, "hpd", GPIOD_IN);
- /* This will catch e.g. -EPROBE_DEFER */
- if (IS_ERR(hdmi->hpd_gpiod))
- return dev_err_probe(dev, PTR_ERR(hdmi->hpd_gpiod),
-"failed to get hpd gpio\n");
-
- if (!hdmi->hpd_gpiod)
- DBG("failed to get HPD gpio");
-
- if (hdmi->hpd_gpiod)
- gpiod_set_consumer_name(hdmi->hpd_gpiod, "HDMI_HPD");
+ if (of_find_property(dev->of_node, "hpd-gpios", NULL) ||
+ of_find_property(dev->of_node, "hpd-gpio", NULL))
+ dev_warn(dev, "hpd-gpios is not supported anymore, please
migrate to the hdmi-connector\n");
ret = msm_hdmi_get_phy(hdmi);
if (ret) {
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 2a98efa8b6bd..268ff8604423 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -52,8 +52,6 @@ struct hdmi {
struct clk_bulk_data *pwr_clks;
struct clk *extp_clk;
- struct gpio_desc *hpd_gpiod;
-
struct hdmi_phy *phy;
struct device *phy_dev;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index 32e447267e3b..d3353c6148ed 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -69,9 +69,6 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
int ret;
unsigned long flags;
- if (hdmi->hpd_gpiod)
- gpiod_set_value_cansleep(hdmi->hpd_gpiod, 1);
-
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
@@ -144,8 +141,11 @@ void msm_hdmi_hpd_irq(struct drm_bridge *bridge)
}
}
-static enum drm_connector_status detect_reg(struct hdmi *hdmi)
+enum drm_connector_status msm_hdmi_bridge_detect(
+ struct drm_bridge *bridge)
{
+ struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
+ struct hdmi *hdmi = hdmi_bridge->hdmi;
uint32_t hpd_int_status = 0;
int ret;
@@ -161,48 +161,3 @@ static enum drm_connector_status detect_reg(struct hdmi
*hdmi)
return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ?
connector_status_connected :
connector_status_disconnected;
}
-
-#define HPD_GPIO_INDEX 2
-static enum drm_connector_status detect_gpio(struct hdmi *hdmi)
-{
- return gpiod_get_value(hdmi->hpd_gpiod) ?
- connector_status_connected :
- connector_status_disconnected;
-}
-
-enum drm_connector_status msm_hdmi_bridge_detect(
- struct drm_bridge *bridge)
-{
- struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
- struct hdmi *hdmi = hdmi_bridge->hdmi;
- enum drm_connector_status stat_gpio, stat_reg;
- int retry = 20;
-
- /*
-* some platforms may not have hpd gpio. Rely only on the status
-* provided by REG_HDMI_HPD_INT_STATUS in this case.
-*/
- if (!hdmi->hpd_gpiod)
- return detect_reg(hdmi);
-
- do {
- stat_gpio = detect_gpio(hdmi);
- stat_reg = detect_reg(hdmi);
-
- if (stat_gpio == stat_reg)
- break;
-
- mdelay(10);
- } while (--retry);
-
- /* the status we get from reading gpio seems to be more reliable,
-* so trust that one the most if we didn't manage to get hdmi and
-* gpio status to agree:
-*/
- if (stat_gpio != stat_reg) {
- DBG("HDMI_HPD_INT_STATUS tells us: %d", stat_reg);
- DBG("hpd gpio tells us: %d", stat_gpio);
- }
-
- return stat_gpio;
-}
--
2.39.2
[PATCH v2 10/14] drm/msm/hdmi: rename hpd_clks to pwr_clks
As these clocks are now used in the runtime PM callbacks, they have no
connection to 'HPD'. Rename corresponding fields to follow clocks
purpose, to power up the HDMI controller.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 26 +-
drivers/gpu/drm/msm/hdmi/hdmi.h | 6 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index cc671baad87b..c39a1f3a7505 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -228,19 +228,19 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
.item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry)
static const char *pwr_reg_names_8960[] = {"core-vdda"};
-static const char *hpd_clk_names_8960[] = {"core", "master_iface",
"slave_iface"};
+static const char *pwr_clk_names_8960[] = {"core", "master_iface",
"slave_iface"};
static const struct hdmi_platform_config hdmi_tx_8960_config = {
HDMI_CFG(pwr_reg, 8960),
- HDMI_CFG(hpd_clk, 8960),
+ HDMI_CFG(pwr_clk, 8960),
};
static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"};
-static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core",
"alt_iface"};
+static const char *pwr_clk_names_8x74[] = {"iface", "core", "mdp_core",
"alt_iface"};
static const struct hdmi_platform_config hdmi_tx_8974_config = {
HDMI_CFG(pwr_reg, 8x74),
- HDMI_CFG(hpd_clk, 8x74),
+ HDMI_CFG(pwr_clk, 8x74),
};
/*
@@ -449,17 +449,17 @@ static int msm_hdmi_dev_probe(struct platform_device
*pdev)
if (ret)
return dev_err_probe(dev, ret, "failed to get pwr
regulators\n");
- hdmi->hpd_clks = devm_kcalloc(>dev,
- config->hpd_clk_cnt,
- sizeof(hdmi->hpd_clks[0]),
+ hdmi->pwr_clks = devm_kcalloc(>dev,
+ config->pwr_clk_cnt,
+ sizeof(hdmi->pwr_clks[0]),
GFP_KERNEL);
- if (!hdmi->hpd_clks)
+ if (!hdmi->pwr_clks)
return -ENOMEM;
- for (i = 0; i < config->hpd_clk_cnt; i++)
- hdmi->hpd_clks[i].id = config->hpd_clk_names[i];
+ for (i = 0; i < config->pwr_clk_cnt; i++)
+ hdmi->pwr_clks[i].id = config->pwr_clk_names[i];
- ret = devm_clk_bulk_get(>dev, config->hpd_clk_cnt,
hdmi->hpd_clks);
+ ret = devm_clk_bulk_get(>dev, config->pwr_clk_cnt,
hdmi->pwr_clks);
if (ret)
return ret;
@@ -517,7 +517,7 @@ static int msm_hdmi_runtime_suspend(struct device *dev)
struct hdmi *hdmi = dev_get_drvdata(dev);
const struct hdmi_platform_config *config = hdmi->config;
- clk_bulk_disable_unprepare(config->hpd_clk_cnt, hdmi->hpd_clks);
+ clk_bulk_disable_unprepare(config->pwr_clk_cnt, hdmi->pwr_clks);
pinctrl_pm_select_sleep_state(dev);
@@ -540,7 +540,7 @@ static int msm_hdmi_runtime_resume(struct device *dev)
if (ret)
goto fail;
- ret = clk_bulk_prepare_enable(config->hpd_clk_cnt, hdmi->hpd_clks);
+ ret = clk_bulk_prepare_enable(config->pwr_clk_cnt, hdmi->pwr_clks);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index ee5463eb41b6..1e346e697f8e 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -49,7 +49,7 @@ struct hdmi {
phys_addr_t mmio_phy_addr;
struct regulator_bulk_data *pwr_regs;
- struct clk_bulk_data *hpd_clks;
+ struct clk_bulk_data *pwr_clks;
struct clk *extp_clk;
struct gpio_desc *hpd_gpiod;
@@ -90,8 +90,8 @@ struct hdmi_platform_config {
int pwr_reg_cnt;
/* clks that need to be on for hpd: */
- const char **hpd_clk_names;
- int hpd_clk_cnt;
+ const char **pwr_clk_names;
+ int pwr_clk_cnt;
};
struct hdmi_bridge {
--
2.39.2
[PATCH v2 06/14] drm/msm/hdmi: switch to clk_bulk API
The last platform using legacy clock names for HDMI block (APQ8064)
switched to new clock names in 5.16. It's time to stop caring about old
DT, drop hand-coded helpers and switch to clk_bulk_* API.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 15 +-
drivers/gpu/drm/msm/hdmi/hdmi.h | 2 +-
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 39 +
3 files changed, 19 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c14e009f38b1..7ec4ca3b7597 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -469,17 +469,12 @@ static int msm_hdmi_dev_probe(struct platform_device
*pdev)
if (!hdmi->hpd_clks)
return -ENOMEM;
- for (i = 0; i < config->hpd_clk_cnt; i++) {
- struct clk *clk;
+ for (i = 0; i < config->hpd_clk_cnt; i++)
+ hdmi->hpd_clks[i].id = config->hpd_clk_names[i];
- clk = msm_clk_get(pdev, config->hpd_clk_names[i]);
- if (IS_ERR(clk))
- return dev_err_probe(dev, PTR_ERR(clk),
-"failed to get hpd clk: %s\n",
-config->hpd_clk_names[i]);
-
- hdmi->hpd_clks[i] = clk;
- }
+ ret = devm_clk_bulk_get(>dev, config->hpd_clk_cnt,
hdmi->hpd_clks);
+ if (ret)
+ return ret;
hdmi->extp_clk = devm_clk_get_optional(>dev, "extp");
if (IS_ERR(hdmi->extp_clk))
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index c0d60ed23b75..eeba85ffef09 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -50,7 +50,7 @@ struct hdmi {
struct regulator_bulk_data *hpd_regs;
struct regulator_bulk_data *pwr_regs;
- struct clk **hpd_clks;
+ struct clk_bulk_data *hpd_clks;
struct clk *extp_clk;
struct gpio_desc *hpd_gpiod;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index 7ae69b14e953..36266aa626dc 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -60,27 +60,6 @@ static void msm_hdmi_phy_reset(struct hdmi *hdmi)
}
}
-static void enable_hpd_clocks(struct hdmi *hdmi, bool enable)
-{
- const struct hdmi_platform_config *config = hdmi->config;
- struct device *dev = >pdev->dev;
- int i, ret;
-
- if (enable) {
- for (i = 0; i < config->hpd_clk_cnt; i++) {
- ret = clk_prepare_enable(hdmi->hpd_clks[i]);
- if (ret) {
- DRM_DEV_ERROR(dev,
- "failed to enable hpd clk: %s (%d)\n",
- config->hpd_clk_names[i], ret);
- }
- }
- } else {
- for (i = config->hpd_clk_cnt - 1; i >= 0; i--)
- clk_disable_unprepare(hdmi->hpd_clks[i]);
- }
-}
-
int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
@@ -107,7 +86,9 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
gpiod_set_value_cansleep(hdmi->hpd_gpiod, 1);
pm_runtime_get_sync(dev);
- enable_hpd_clocks(hdmi, true);
+ ret = clk_bulk_prepare_enable(config->hpd_clk_cnt, hdmi->hpd_clks);
+ if (ret)
+ goto fail;
msm_hdmi_set_mode(hdmi, false);
msm_hdmi_phy_reset(hdmi);
@@ -149,7 +130,7 @@ void msm_hdmi_hpd_disable(struct hdmi *hdmi)
msm_hdmi_set_mode(hdmi, false);
- enable_hpd_clocks(hdmi, false);
+ clk_bulk_disable_unprepare(config->hpd_clk_cnt, hdmi->hpd_clks);
pm_runtime_put(dev);
ret = pinctrl_pm_select_sleep_state(dev);
@@ -193,14 +174,20 @@ void msm_hdmi_hpd_irq(struct drm_bridge *bridge)
static enum drm_connector_status detect_reg(struct hdmi *hdmi)
{
- uint32_t hpd_int_status;
+ const struct hdmi_platform_config *config = hdmi->config;
+ uint32_t hpd_int_status = 0;
+ int ret;
pm_runtime_get_sync(>pdev->dev);
- enable_hpd_clocks(hdmi, true);
+ ret = clk_bulk_prepare_enable(config->hpd_clk_cnt, hdmi->hpd_clks);
+ if (ret)
+ goto out;
hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS);
- enable_hpd_clocks(hdmi, false);
+ clk_bulk_disable_unprepare(config->hpd_clk_cnt, hdmi->hpd_clks);
+
+out:
pm_runtime_put(>pdev->dev);
return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ?
--
2.39.2
[PATCH v2 01/14] drm/msm/hdmi: move the alt_iface clock to the hpd list
According to the vendor kernel [1] , the alt_iface clock should be
enabled together with the rest of HPD clocks, to make HPD to work
properly.
[1]
https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 24abcb7254cc..108c86925780 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -235,9 +235,9 @@ static const struct hdmi_platform_config
hdmi_tx_8960_config = {
};
static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"};
-static const char *pwr_clk_names_8x74[] = {"extp", "alt_iface"};
-static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core"};
-static unsigned long hpd_clk_freq_8x74[] = {0, 1920, 0};
+static const char *pwr_clk_names_8x74[] = {"extp"};
+static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core",
"alt_iface"};
+static unsigned long hpd_clk_freq_8x74[] = {0, 1920, 0, 0};
static const struct hdmi_platform_config hdmi_tx_8974_config = {
HDMI_CFG(pwr_reg, 8x74),
--
2.39.2
[PATCH v2 09/14] drm/msm/hdmi: implement proper runtime PM handling
It is completely not obvious, but the so-called 'hpd' clocks and
regulators are required for the HDMI host to function properly. Merge
pwr and hpd regulators. Use regulators, clocks and pinctrl to implement
proper runtime PM callbacks.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 62 +-
drivers/gpu/drm/msm/hdmi/hdmi.h| 7 +---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 12 ---
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 42 +--
4 files changed, 48 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 7ec4ca3b7597..cc671baad87b 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
@@ -226,11 +227,11 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
.item ## _names = item ##_names_ ## entry, \
.item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry)
-static const char *hpd_reg_names_8960[] = {"core-vdda"};
+static const char *pwr_reg_names_8960[] = {"core-vdda"};
static const char *hpd_clk_names_8960[] = {"core", "master_iface",
"slave_iface"};
static const struct hdmi_platform_config hdmi_tx_8960_config = {
- HDMI_CFG(hpd_reg, 8960),
+ HDMI_CFG(pwr_reg, 8960),
HDMI_CFG(hpd_clk, 8960),
};
@@ -434,20 +435,6 @@ static int msm_hdmi_dev_probe(struct platform_device *pdev)
if (hdmi->irq < 0)
return hdmi->irq;
- hdmi->hpd_regs = devm_kcalloc(>dev,
- config->hpd_reg_cnt,
- sizeof(hdmi->hpd_regs[0]),
- GFP_KERNEL);
- if (!hdmi->hpd_regs)
- return -ENOMEM;
-
- for (i = 0; i < config->hpd_reg_cnt; i++)
- hdmi->hpd_regs[i].supply = config->hpd_reg_names[i];
-
- ret = devm_regulator_bulk_get(>dev, config->hpd_reg_cnt,
hdmi->hpd_regs);
- if (ret)
- return dev_err_probe(dev, ret, "failed to get hpd
regulators\n");
-
hdmi->pwr_regs = devm_kcalloc(>dev,
config->pwr_reg_cnt,
sizeof(hdmi->pwr_regs[0]),
@@ -525,6 +512,48 @@ static void msm_hdmi_dev_remove(struct platform_device
*pdev)
msm_hdmi_put_phy(hdmi);
}
+static int msm_hdmi_runtime_suspend(struct device *dev)
+{
+ struct hdmi *hdmi = dev_get_drvdata(dev);
+ const struct hdmi_platform_config *config = hdmi->config;
+
+ clk_bulk_disable_unprepare(config->hpd_clk_cnt, hdmi->hpd_clks);
+
+ pinctrl_pm_select_sleep_state(dev);
+
+ regulator_bulk_disable(config->pwr_reg_cnt, hdmi->pwr_regs);
+
+ return 0;
+}
+
+static int msm_hdmi_runtime_resume(struct device *dev)
+{
+ struct hdmi *hdmi = dev_get_drvdata(dev);
+ const struct hdmi_platform_config *config = hdmi->config;
+ int ret;
+
+ ret = regulator_bulk_enable(config->pwr_reg_cnt, hdmi->pwr_regs);
+ if (ret)
+ return ret;
+
+ ret = pinctrl_pm_select_default_state(dev);
+ if (ret)
+ goto fail;
+
+ ret = clk_bulk_prepare_enable(config->hpd_clk_cnt, hdmi->hpd_clks);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ pinctrl_pm_select_sleep_state(dev);
+
+ return ret;
+}
+
+DEFINE_RUNTIME_DEV_PM_OPS(msm_hdmi_pm_ops, msm_hdmi_runtime_suspend,
msm_hdmi_runtime_resume, NULL);
+
static const struct of_device_id msm_hdmi_dt_match[] = {
{ .compatible = "qcom,hdmi-tx-8996", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8994", .data = _tx_8974_config },
@@ -541,6 +570,7 @@ static struct platform_driver msm_hdmi_driver = {
.driver = {
.name = "hdmi_msm",
.of_match_table = msm_hdmi_dt_match,
+ .pm = _hdmi_pm_ops,
},
};
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index eeba85ffef09..ee5463eb41b6 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -48,7 +48,6 @@ struct hdmi {
void __iomem *qfprom_mmio;
phys_addr_t mmio_phy_addr;
- struct regulator_bulk_data *hpd_regs;
struct regulator_bulk_data *pwr_regs;
struct clk_bulk_data *hpd_clks;
struct clk *extp_clk;
@@ -86,11 +85,7 @@ struct hdmi {
/* platform config data (ie. from DT, or pdata) */
struct hdmi_platform_config {
- /* regulators that need to be on for hpd: */
- const char **hpd_reg_names;
- int hpd_reg_cnt;
-
- /* regulators that need to be on for screen pwr: */
+ /* regulators that nee
[PATCH v2 08/14] drm/msm/hdmi: add runtime PM calls to DDC transfer function
We must be sure that the HDMI controller is powered on, while performing
the DDC transfer. Add corresponding runtime PM calls to
msm_hdmi_i2c_xfer().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_i2c.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c
b/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c
index 7aa500d24240..ebefea4fb408 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c
@@ -107,11 +107,15 @@ static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
if (num == 0)
return num;
+ ret = pm_runtime_resume_and_get(>pdev->dev);
+ if (ret)
+ return ret;
+
init_ddc(hdmi_i2c);
ret = ddc_clear_irq(hdmi_i2c);
if (ret)
- return ret;
+ goto fail;
for (i = 0; i < num; i++) {
struct i2c_msg *p = [i];
@@ -169,7 +173,7 @@ static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS),
hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS),
hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL));
- return ret;
+ goto fail;
}
ddc_status = hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS);
@@ -202,7 +206,13 @@ static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
}
}
+ pm_runtime_put(>pdev->dev);
+
return i;
+
+fail:
+ pm_runtime_put(>pdev->dev);
+ return ret;
}
static u32 msm_hdmi_i2c_func(struct i2c_adapter *adapter)
--
2.39.2
[PATCH v2 05/14] drm/msm/hdmi: drop clock frequency assignment
The only clock which has frequency being set through hpd_freqs is the
"core" aka MDSS_HDMI_CLK clock. It always has the specified frequency,
so we can drop corresponding clk_set_rate() call together with the
hpd_freq infrastructure.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 2 --
drivers/gpu/drm/msm/hdmi/hdmi.h | 1 -
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 9 -
3 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 681265e29aa0..c14e009f38b1 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -236,12 +236,10 @@ static const struct hdmi_platform_config
hdmi_tx_8960_config = {
static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"};
static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core",
"alt_iface"};
-static unsigned long hpd_clk_freq_8x74[] = {0, 1920, 0, 0};
static const struct hdmi_platform_config hdmi_tx_8974_config = {
HDMI_CFG(pwr_reg, 8x74),
HDMI_CFG(hpd_clk, 8x74),
- .hpd_freq = hpd_clk_freq_8x74,
};
/*
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index abdbe4779cf9..c0d60ed23b75 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -96,7 +96,6 @@ struct hdmi_platform_config {
/* clks that need to be on for hpd: */
const char **hpd_clk_names;
- const long unsigned *hpd_freq;
int hpd_clk_cnt;
};
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index 9ce0ffa35417..7ae69b14e953 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -68,15 +68,6 @@ static void enable_hpd_clocks(struct hdmi *hdmi, bool enable)
if (enable) {
for (i = 0; i < config->hpd_clk_cnt; i++) {
- if (config->hpd_freq && config->hpd_freq[i]) {
- ret = clk_set_rate(hdmi->hpd_clks[i],
- config->hpd_freq[i]);
- if (ret)
- dev_warn(dev,
-"failed to set clk %s (%d)\n",
-config->hpd_clk_names[i], ret);
- }
-
ret = clk_prepare_enable(hdmi->hpd_clks[i]);
if (ret) {
DRM_DEV_ERROR(dev,
--
2.39.2
[PATCH v2 07/14] drm/msm/hdmi: switch to pm_runtime_resume_and_get()
The pm_runtime_get_sync() function is a bad choise for runtime power
management. Switch HDMI driver to pm_runtime_resume_and_get() and add
proper error handling, while we are at it.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 +-
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 12 ++--
drivers/gpu/drm/msm/hdmi/hdmi_phy.c| 6 +-
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index fb99328107dd..d1b35328b6e8 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -19,7 +19,7 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge)
const struct hdmi_platform_config *config = hdmi->config;
int ret;
- pm_runtime_get_sync(>pdev->dev);
+ pm_runtime_resume_and_get(>pdev->dev);
ret = regulator_bulk_enable(config->pwr_reg_cnt, hdmi->pwr_regs);
if (ret)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index 36266aa626dc..fc21ad3b01dc 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -85,7 +85,12 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
if (hdmi->hpd_gpiod)
gpiod_set_value_cansleep(hdmi->hpd_gpiod, 1);
- pm_runtime_get_sync(dev);
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "runtime resume failed: %d\n", ret);
+ goto fail;
+ }
+
ret = clk_bulk_prepare_enable(config->hpd_clk_cnt, hdmi->hpd_clks);
if (ret)
goto fail;
@@ -178,7 +183,10 @@ static enum drm_connector_status detect_reg(struct hdmi
*hdmi)
uint32_t hpd_int_status = 0;
int ret;
- pm_runtime_get_sync(>pdev->dev);
+ ret = pm_runtime_resume_and_get(>pdev->dev);
+ if (ret)
+ goto out;
+
ret = clk_bulk_prepare_enable(config->hpd_clk_cnt, hdmi->hpd_clks);
if (ret)
goto out;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
index 88a3423b7f24..d5acae752300 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
@@ -58,7 +58,11 @@ int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy)
struct device *dev = >pdev->dev;
int i, ret = 0;
- pm_runtime_get_sync(dev);
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "runtime resume failed: %d\n", ret);
+ return ret;
+ }
ret = regulator_bulk_enable(cfg->num_regs, phy->regs);
if (ret) {
--
2.39.2
[PATCH v2 04/14] drm/msm/hdmi: set infoframes on all pre_enable calls
In consequent modeset calls, the atomic_pre_enable() will be called
several times without calling atomic_post_disable() inbetween. Thus
iframes will not be updated for the next mode. Fix this by setting the
iframe outside of the !power_on check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 3c6121c57b01..fb99328107dd 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -133,10 +133,11 @@ static void msm_hdmi_bridge_atomic_pre_enable(struct
drm_bridge *bridge,
msm_hdmi_phy_resource_enable(phy);
msm_hdmi_power_on(bridge);
hdmi->power_on = true;
- if (hdmi->hdmi_mode) {
- msm_hdmi_config_avi_infoframe(hdmi);
- msm_hdmi_audio_update(hdmi);
- }
+ }
+
+ if (hdmi->hdmi_mode) {
+ msm_hdmi_config_avi_infoframe(hdmi);
+ msm_hdmi_audio_update(hdmi);
}
msm_hdmi_phy_powerup(phy, hdmi->pixclock);
--
2.39.2
[PATCH v2 03/14] drm/msm/hdmi: switch to atomic_pre_enable/post_disable
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 9eb4d06bdc0e..3c6121c57b01 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -120,7 +120,8 @@ static void msm_hdmi_config_avi_infoframe(struct hdmi *hdmi)
hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
}
-static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
+static void msm_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state
*old_bridge_state)
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;
@@ -146,7 +147,8 @@ static void msm_hdmi_bridge_pre_enable(struct drm_bridge
*bridge)
msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
}
-static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
+static void msm_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state
*old_bridge_state)
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;
@@ -292,8 +294,13 @@ static enum drm_mode_status
msm_hdmi_bridge_mode_valid(struct drm_bridge *bridge
}
static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
- .pre_enable = msm_hdmi_bridge_pre_enable,
- .post_disable = msm_hdmi_bridge_post_disable,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+
+ .atomic_pre_enable = msm_hdmi_bridge_atomic_pre_enable,
+ .atomic_post_disable = msm_hdmi_bridge_atomic_post_disable,
+
.mode_set = msm_hdmi_bridge_mode_set,
.mode_valid = msm_hdmi_bridge_mode_valid,
.edid_read = msm_hdmi_bridge_edid_read,
--
2.39.2
[PATCH v2 02/14] drm/msm/hdmi: simplify extp clock handling
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 24
drivers/gpu/drm/msm/hdmi/hdmi.h| 6 +-
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 33 +
3 files changed, 18 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 108c86925780..681265e29aa0 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -235,13 +235,11 @@ static const struct hdmi_platform_config
hdmi_tx_8960_config = {
};
static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"};
-static const char *pwr_clk_names_8x74[] = {"extp"};
static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core",
"alt_iface"};
static unsigned long hpd_clk_freq_8x74[] = {0, 1920, 0, 0};
static const struct hdmi_platform_config hdmi_tx_8974_config = {
HDMI_CFG(pwr_reg, 8x74),
- HDMI_CFG(pwr_clk, 8x74),
HDMI_CFG(hpd_clk, 8x74),
.hpd_freq = hpd_clk_freq_8x74,
};
@@ -485,24 +483,10 @@ static int msm_hdmi_dev_probe(struct platform_device
*pdev)
hdmi->hpd_clks[i] = clk;
}
- hdmi->pwr_clks = devm_kcalloc(>dev,
- config->pwr_clk_cnt,
- sizeof(hdmi->pwr_clks[0]),
- GFP_KERNEL);
- if (!hdmi->pwr_clks)
- return -ENOMEM;
-
- for (i = 0; i < config->pwr_clk_cnt; i++) {
- struct clk *clk;
-
- clk = msm_clk_get(pdev, config->pwr_clk_names[i]);
- if (IS_ERR(clk))
- return dev_err_probe(dev, PTR_ERR(clk),
-"failed to get pwr clk: %s\n",
-config->pwr_clk_names[i]);
-
- hdmi->pwr_clks[i] = clk;
- }
+ hdmi->extp_clk = devm_clk_get_optional(>dev, "extp");
+ if (IS_ERR(hdmi->extp_clk))
+ return dev_err_probe(dev, PTR_ERR(hdmi->extp_clk),
+"failed to get extp clock\n");
hdmi->hpd_gpiod = devm_gpiod_get_optional(>dev, "hpd", GPIOD_IN);
/* This will catch e.g. -EPROBE_DEFER */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 4586baf36415..abdbe4779cf9 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -51,7 +51,7 @@ struct hdmi {
struct regulator_bulk_data *hpd_regs;
struct regulator_bulk_data *pwr_regs;
struct clk **hpd_clks;
- struct clk **pwr_clks;
+ struct clk *extp_clk;
struct gpio_desc *hpd_gpiod;
@@ -98,10 +98,6 @@ struct hdmi_platform_config {
const char **hpd_clk_names;
const long unsigned *hpd_freq;
int hpd_clk_cnt;
-
- /* clks that need to be on for screen pwr (ie pixel clk): */
- const char **pwr_clk_names;
- int pwr_clk_cnt;
};
struct hdmi_bridge {
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 4a5b5112227f..9eb4d06bdc0e 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -17,7 +17,7 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge)
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;
const struct hdmi_platform_config *config = hdmi->config;
- int i, ret;
+ int ret;
pm_runtime_get_sync(>pdev->dev);
@@ -25,21 +25,15 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge)
if (ret)
DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %d\n",
ret);
- if (config->pwr_clk_cnt > 0) {
+ if (hdmi->extp_clk) {
DBG("pixclock: %lu", hdmi->pixclock);
- ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
- if (ret) {
- DRM_DEV_ERROR(dev->dev, "failed to set pixel clk: %s
(%d)\n",
- config->pwr_clk_names[0], ret);
- }
- }
+ ret = clk_set_rate(hdmi->extp_clk, hdmi->pixclock);
+ if (ret)
+ DRM_DEV_ERROR(dev->dev, "failed to set extp clk rate:
%d\n", ret);
- for (i = 0; i < config->pwr_clk_cnt; i++) {
- ret = clk_prepare_enable(hdmi->pwr_clks[i]);
- if (ret) {
- DRM_DEV_ERROR(d
[PATCH v2 00/14] drm/msm/hdmi: rework and fix the HPD even generation
The MSM HDMI driver is plagued with the long-standing bug. If HDMI cable is disconnected, in most of the cases cable reconnection will not be detected properly. We have been carrying the patch from [1] in our integration tree for ages. The time has come to fix the long-standing bug and implement proper HPD handling. This series was tested on msm8996 and apq8064 boards. Previously HPD handling sometimes could trigger in the CRTC event handling, however I can no longer reproduce it now. [1] https://lore.kernel.org/linux-arm-msm/20171027105732.19235-2-arch...@codeaurora.org/ --- Dmitry Baryshkov (14): drm/msm/hdmi: move the alt_iface clock to the hpd list drm/msm/hdmi: simplify extp clock handling drm/msm/hdmi: switch to atomic_pre_enable/post_disable drm/msm/hdmi: set infoframes on all pre_enable calls drm/msm/hdmi: drop clock frequency assignment drm/msm/hdmi: switch to clk_bulk API drm/msm/hdmi: switch to pm_runtime_resume_and_get() drm/msm/hdmi: add runtime PM calls to DDC transfer function drm/msm/hdmi: implement proper runtime PM handling drm/msm/hdmi: rename hpd_clks to pwr_clks drm/msm/hdmi: expand the HDMI_CFG macro drm/msm/hdmi: drop hpd-gpios support drm/msm/hdmi: ensure that HDMI is one if HPD is requested drm/msm/hdmi: wire in hpd_enable/hpd_disable bridge ops drivers/gpu/drm/msm/hdmi/hdmi.c| 145 - drivers/gpu/drm/msm/hdmi/hdmi.h| 26 ++ drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 80 +- drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 142 ++-- drivers/gpu/drm/msm/hdmi/hdmi_i2c.c| 14 +++- drivers/gpu/drm/msm/hdmi/hdmi_phy.c| 6 +- 6 files changed, 157 insertions(+), 256 deletions(-) --- base-commit: 8314289a8d50a4e05d8ece1ae0445a3b57bb4d3b change-id: 20240522-fd-hdmi-hpd-e3868deb6ae0 Best regards, -- Dmitry Baryshkov
[PATCH v2] Revert "drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set"
In the DPU driver blank IRQ handling is called from a vblank worker and
can happen outside of the irq_enable / irq_disable pair. Using the
worker makes that completely asynchronous with the rest of the code.
Revert commit d13f638c9b88 ("drm/msm/dpu: drop
dpu_encoder_phys_ops.atomic_mode_set") to fix vblank IRQ assignment for
CMD DSI panels.
Call trace:
dpu_encoder_phys_cmd_control_vblank_irq+0x218/0x294
dpu_encoder_toggle_vblank_for_crtc+0x160/0x194
dpu_crtc_vblank+0xbc/0x228
dpu_kms_enable_vblank+0x18/0x24
vblank_ctrl_worker+0x34/0x6c
process_one_work+0x218/0x620
worker_thread+0x1ac/0x37c
kthread+0x114/0x118
ret_from_fork+0x10/0x20
Fixes: d13f638c9b88 ("drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set")
Signed-off-by: Dmitry Baryshkov
---
Changes in v2:
- Expanded commit message to describe the reason for revert and added a
call trace (Abhinav)
- Link to v1:
https://lore.kernel.org/r/20240514-dpu-revert-ams-v1-1-b13623d6c...@linaro.org
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 32 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 +++--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 11 +++-
5 files changed, 46 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..a7d8ecf3f5be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1200,6 +1200,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct
drm_encoder *drm_enc,
phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
phys->cached_mode = crtc_state->adjusted_mode;
+ if (phys->ops.atomic_mode_set)
+ phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 002e89cc1705..30470cd15a48 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -69,6 +69,8 @@ struct dpu_encoder_phys;
* @is_master: Whether this phys_enc is the current master
* encoder. Can be switched at enable time. Based
* on split_role and current mode (CMD/VID).
+ * @atomic_mode_set: DRM Call. Set a DRM mode.
+ * This likely caches the mode, for use at enable.
* @enable:DRM Call. Enable a DRM mode.
* @disable: DRM Call. Disable mode.
* @control_vblank_irq Register/Deregister for VBLANK IRQ
@@ -93,6 +95,9 @@ struct dpu_encoder_phys;
struct dpu_encoder_phys_ops {
void (*prepare_commit)(struct dpu_encoder_phys *encoder);
bool (*is_master)(struct dpu_encoder_phys *encoder);
+ void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state);
void (*enable)(struct dpu_encoder_phys *encoder);
void (*disable)(struct dpu_encoder_phys *encoder);
int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 489be1c0c704..95cd39b49668 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -142,6 +142,23 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg)
dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
}
+static void dpu_encoder_phys_cmd_atomic_mode_set(
+ struct dpu_encoder_phys *phys_enc,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
+
+ phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
+
+ if (phys_enc->has_intf_te)
+ phys_enc->irq[INTR_IDX_RDPTR] =
phys_enc->hw_intf->cap->intr_tear_rd_ptr;
+ else
+ phys_enc->irq[INTR_IDX_RDPTR] =
phys_enc->hw_pp->caps->intr_rdptr;
+
+ phys_enc->irq[INTR_IDX_UNDERRUN] =
phys_enc->hw_intf->cap->intr_underrun;
+}
+
static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
struct dpu_encoder_phys *phys_enc)
{
@@ -280,14 +297,6 @@ static void dpu_encoder_phys_cmd_irq_enable(struct
dpu_encoder_phys *phys_enc)
phys_enc->hw_pp->idx - PINGPONG_0,
phys_enc->vblank
[PATCH v3 3/3] drm/panel/lg-sw43408: mark sw43408_backlight_ops as static
Fix sparse warning regarding symbol 'sw43408_backlight_ops' not being
declared.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202404200739.hbwzvohr-...@intel.com/
Reviewed-by: Neil Armstrong
Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/panel/panel-lg-sw43408.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c
b/drivers/gpu/drm/panel/panel-lg-sw43408.c
index 115f4702d59f..2b3a73696dce 100644
--- a/drivers/gpu/drm/panel/panel-lg-sw43408.c
+++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c
@@ -182,7 +182,7 @@ static int sw43408_backlight_update_status(struct
backlight_device *bl)
return mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
}
-const struct backlight_ops sw43408_backlight_ops = {
+static const struct backlight_ops sw43408_backlight_ops = {
.update_status = sw43408_backlight_update_status,
};
--
2.39.2
[PATCH v3 1/3] drm/display: split DSC helpers from DP helpers
Currently the DRM DSC functions are selected by the DRM_DISPLAY_DP_HELPER Kconfig symbol. This is not optimal, since the DSI code (both panel and host drivers) end up selecting the seemingly irrelevant DP helpers. Split the DSC code to be guarded by the separate DRM_DISPLAY_DSC_HELPER Kconfig symbol. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/amd/amdgpu/Kconfig | 1 + drivers/gpu/drm/display/Kconfig| 6 ++ drivers/gpu/drm/display/Makefile | 3 ++- drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/msm/Kconfig| 1 + drivers/gpu/drm/panel/Kconfig | 4 ++-- 6 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 22d88f8ef527..b69d5c4a5367 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -6,6 +6,7 @@ config DRM_AMDGPU depends on !UML select FW_LOADER select DRM_DISPLAY_DP_HELPER + select DRM_DISPLAY_DSC_HELPER select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDCP_HELPER select DRM_DISPLAY_HELPER diff --git a/drivers/gpu/drm/display/Kconfig b/drivers/gpu/drm/display/Kconfig index 864a6488bfdf..f524cf95dec3 100644 --- a/drivers/gpu/drm/display/Kconfig +++ b/drivers/gpu/drm/display/Kconfig @@ -59,6 +59,12 @@ config DRM_DISPLAY_DP_TUNNEL_STATE_DEBUG If in doubt, say "N". +config DRM_DISPLAY_DSC_HELPER + bool + depends on DRM_DISPLAY_HELPER + help + DRM display helpers for VESA DSC (used by DSI and DisplayPort). + config DRM_DISPLAY_HDCP_HELPER bool depends on DRM_DISPLAY_HELPER diff --git a/drivers/gpu/drm/display/Makefile b/drivers/gpu/drm/display/Makefile index 17d2cc73ff56..2ec71e15c3cb 100644 --- a/drivers/gpu/drm/display/Makefile +++ b/drivers/gpu/drm/display/Makefile @@ -6,7 +6,8 @@ drm_display_helper-y := drm_display_helper_mod.o drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_HELPER) += \ drm_dp_dual_mode_helper.o \ drm_dp_helper.o \ - drm_dp_mst_topology.o \ + drm_dp_mst_topology.o +drm_display_helper-$(CONFIG_DRM_DISPLAY_DSC_HELPER) += \ drm_dsc_helper.o drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_TUNNEL) += \ drm_dp_tunnel.o diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 5932024f8f95..117b84260b1c 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -11,6 +11,7 @@ config DRM_I915 select SHMEM select TMPFS select DRM_DISPLAY_DP_HELPER + select DRM_DISPLAY_DSC_HELPER select DRM_DISPLAY_HDCP_HELPER select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HELPER diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 1931ecf73e32..6dcd26180611 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -111,6 +111,7 @@ config DRM_MSM_DSI depends on DRM_MSM select DRM_PANEL select DRM_MIPI_DSI + select DRM_DISPLAY_DSC_HELPER default y help Choose this option if you have a need for MIPI DSI connector diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 982324ef5a41..4a2f621433ef 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -547,7 +547,7 @@ config DRM_PANEL_RAYDIUM_RM692E5 depends on OF depends on DRM_MIPI_DSI depends on BACKLIGHT_CLASS_DEVICE - select DRM_DISPLAY_DP_HELPER + select DRM_DISPLAY_DSC_HELPER select DRM_DISPLAY_HELPER help Say Y here if you want to enable support for Raydium RM692E5-based @@ -905,7 +905,7 @@ config DRM_PANEL_VISIONOX_R66451 depends on OF depends on DRM_MIPI_DSI depends on BACKLIGHT_CLASS_DEVICE - select DRM_DISPLAY_DP_HELPER + select DRM_DISPLAY_DSC_HELPER select DRM_DISPLAY_HELPER help Say Y here if you want to enable support for Visionox -- 2.39.2
[PATCH v3 2/3] drm/panel/lg-sw43408: select CONFIG_DRM_DISPLAY_DP_HELPER
This panel driver uses DSC PPS functions and as such depends on the
DRM_DISPLAY_DP_HELPER. Select this symbol to make required functions
available to the driver.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202404200800.kysryyli-...@intel.com/
Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/panel/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4a2f621433ef..3e3f63479544 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -340,6 +340,8 @@ config DRM_PANEL_LG_SW43408
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_DISPLAY_DSC_HELPER
+ select DRM_DISPLAY_HELPER
help
Say Y here if you want to enable support for LG sw43408 panel.
The panel has a 1080x2160@60Hz resolution and uses 24 bit RGB per
--
2.39.2
[PATCH v3 0/3] drm/panel: two fixes for lg-sw43408
Fix two issues with the panel-lg-sw43408 driver reported by the kernel test robot. To: Neil Armstrong To: Jessica Zhang To: Sam Ravnborg To: Maarten Lankhorst To: Maxime Ripard To: Thomas Zimmermann To: David Airlie To: Daniel Vetter To: Sumit Semwal To: Caleb Connolly To: Alex Deucher To: Christian König To: Pan, Xinhui To: Jani Nikula To: Joonas Lahtinen To: Rodrigo Vivi To: Tvrtko Ursulin To: Rob Clark To: Abhinav Kumar To: Sean Paul To: Marijn Suijten To: Vinod Koul To: Caleb Connolly Cc: dri-de...@lists.freedesktop.org Cc: linux-ker...@vger.kernel.org Cc: amd-...@lists.freedesktop.org Cc: intel-...@lists.freedesktop.org Cc: linux-arm-...@vger.kernel.org Cc: freedreno@lists.freedesktop.org Signed-off-by: Dmitry Baryshkov Changes in v3: - Split DRM_DISPLAY_DSC_HELPER from DRM_DISPLAY_DP_HELPER - Added missing Fixes tags - Link to v2: https://lore.kernel.org/r/20240510-panel-sw43408-fix-v2-0-d1ef91ee1...@linaro.org Changes in v2: - use SELECT instead of DEPEND to follow the reverted Kconfig changes - Link to v1: https://lore.kernel.org/r/20240420-panel-sw43408-fix-v1-0-b282ff725...@linaro.org --- Dmitry Baryshkov (3): drm/display: split DSC helpers from DP helpers drm/panel/lg-sw43408: select CONFIG_DRM_DISPLAY_DP_HELPER drm/panel/lg-sw43408: mark sw43408_backlight_ops as static drivers/gpu/drm/amd/amdgpu/Kconfig | 1 + drivers/gpu/drm/display/Kconfig | 6 ++ drivers/gpu/drm/display/Makefile | 3 ++- drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/panel/Kconfig| 6 -- drivers/gpu/drm/panel/panel-lg-sw43408.c | 2 +- 7 files changed, 16 insertions(+), 4 deletions(-) --- base-commit: 8314289a8d50a4e05d8ece1ae0445a3b57bb4d3b change-id: 20240420-panel-sw43408-fix-ff6549c121be Best regards, -- Dmitry Baryshkov
Re: [PATCH 08/11] drm/msm/dp: switch to struct drm_edid
On Mon, 20 May 2024 at 15:25, Jani Nikula wrote:
>
> On Sun, 19 May 2024, Dmitry Baryshkov wrote:
> > On Tue, May 14, 2024 at 03:55:14PM +0300, Jani Nikula wrote:
> >> Prefer the struct drm_edid based functions for reading the EDID and
> >> updating the connector.
> >>
> >> Simplify the flow by updating the EDID property when the EDID is read
> >> instead of at .get_modes.
> >>
> >> Signed-off-by: Jani Nikula
> >>
> >> ---
> >
> > The patch looks good to me, I'd like to hear an opinion from Doug (added
> > to CC).
> >
> > Reviewed-by: Dmitry Baryshkov
>
> Thanks!
>
> > What is the merge strategy for the series? Do you plan to pick up all
> > the patches to drm-misc or should we pick up individual patches into
> > driver trees?
>
> I think all of the patches here are connected in theme, but
> independent. Either way is fine by me.
>
> >
> >
> >>
> >> Cc: Rob Clark
> >> Cc: Abhinav Kumar
> >> Cc: Dmitry Baryshkov
> >> Cc: Sean Paul
> >> Cc: Marijn Suijten
> >> Cc: linux-arm-...@vger.kernel.org
> >> Cc: freedreno@lists.freedesktop.org
> >> ---
> >> drivers/gpu/drm/msm/dp/dp_display.c | 11 +++
> >> drivers/gpu/drm/msm/dp/dp_panel.c | 47 +
> >> drivers/gpu/drm/msm/dp/dp_panel.h | 2 +-
> >> 3 files changed, 20 insertions(+), 40 deletions(-)
> >
> > [skipped]
> >
> >> @@ -249,10 +228,12 @@ void dp_panel_handle_sink_request(struct dp_panel
> >> *dp_panel)
> >> panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
> >>
> >> if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) {
> >> +/* FIXME: get rid of drm_edid_raw() */
> >
> > The code here can get use of something like drm_edid_smth_checksum().
> > 'Something', because I could not come up with the word that would make
> > it clear that it is the declared checksum instead of the actual /
> > computed one.
>
> This is an annoying one, to be honest, and linked to the historical fact
> that we filter some EDID blocks that have an incorrect checksum.
It is a part of the DP test suite if I remember correctly.
>
> (Some blocks, yes. We don't filter all blocks, because there are some
> nasty docks out there that modify the CTA block but fail to update the
> checksum, and filtering the CTA blocks would render the display
> useless. So we accept CTA blocks with incorrect checksums. But reject
> others. Yay.)
>
> IMO the real fix would be to stop mucking with the EDID, and just expose
> it to userspace, warts and all. We could still ignore the EDID blocks
> with incorrect checksum while using it ourselves if we want to. And with
> that, we could just have a function that checks the last EDID block's
> checksum, and stop using this ->real_edid_checksum thing.
>
> Anyway, yes, we could add the function already.
>
> BR,
> Jani.
>
> >
> >> +const struct edid *edid = drm_edid_raw(dp_panel->drm_edid);
> >> u8 checksum;
> >>
> >> -if (dp_panel->edid)
> >> -checksum = dp_panel_get_edid_checksum(dp_panel->edid);
> >> +if (edid)
> >> +checksum = dp_panel_get_edid_checksum(edid);
> >> else
> >> checksum = dp_panel->connector->real_edid_checksum;
> >>
>
> --
> Jani Nikula, Intel
--
With best wishes
Dmitry
[PATCH 7/7] drm/msm/dpu: support setting the TE source
Make the DPU driver use the TE source specified in the DT. If none is
specified, the driver defaults to the first GPIO (mdp_vsync0).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 44 -
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e9991f3756d4..932d0bb41d7e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -505,6 +505,44 @@ static void dpu_kms_wait_flush(struct msm_kms *kms,
unsigned crtc_mask)
dpu_kms_wait_for_commit_done(kms, crtc);
}
+static const char *dpu_vsync_sources[] = {
+ [DPU_VSYNC_SOURCE_GPIO_0] = "mdp_gpio0",
+ [DPU_VSYNC_SOURCE_GPIO_1] = "mdp_gpio1",
+ [DPU_VSYNC_SOURCE_GPIO_2] = "mdp_gpio2",
+ [DPU_VSYNC_SOURCE_INTF_0] = "mdp_intf0",
+ [DPU_VSYNC_SOURCE_INTF_1] = "mdp_intf1",
+ [DPU_VSYNC_SOURCE_INTF_2] = "mdp_intf2",
+ [DPU_VSYNC_SOURCE_INTF_3] = "mdp_intf3",
+ [DPU_VSYNC_SOURCE_WD_TIMER_0] = "timer0",
+ [DPU_VSYNC_SOURCE_WD_TIMER_1] = "timer1",
+ [DPU_VSYNC_SOURCE_WD_TIMER_2] = "timer2",
+ [DPU_VSYNC_SOURCE_WD_TIMER_3] = "timer3",
+ [DPU_VSYNC_SOURCE_WD_TIMER_4] = "timer4",
+};
+
+static int dpu_kms_dsi_set_te_source(struct msm_display_info *info,
+struct msm_dsi *dsi)
+{
+ const char *te_source = msm_dsi_get_te_source(dsi);
+ int i;
+
+ if (!te_source) {
+ info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
+ return 0;
+ }
+
+ /* we can not use match_string since dpu_vsync_sources is a sparse
array */
+ for (i = 0; i < ARRAY_SIZE(dpu_vsync_sources); i++) {
+ if (dpu_vsync_sources[i] &&
+ !strcmp(dpu_vsync_sources[i], te_source)) {
+ info->vsync_source = i;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
static int _dpu_kms_initialize_dsi(struct drm_device *dev,
struct msm_drm_private *priv,
struct dpu_kms *dpu_kms)
@@ -543,7 +581,11 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
- info.vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
+ rc = dpu_kms_dsi_set_te_source(, priv->dsi[i]);
+ if (rc) {
+ DPU_ERROR("failed to identify TE source for dsi
display\n");
+ return rc;
+ }
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, );
if (IS_ERR(encoder)) {
--
2.39.2
[PATCH 6/7] drm/msm/dsi: parse vsync source from device tree
Allow board's device tree to specify the vsync source (aka TE source).
If the property is omitted, the display controller driver will use the
default setting.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c| 11 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
drivers/gpu/drm/msm/msm_drv.h | 6 ++
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index afc290408ba4..87496db203d6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -37,6 +37,7 @@ struct msm_dsi {
struct mipi_dsi_host *host;
struct msm_dsi_phy *phy;
+ const char *te_source;
struct drm_bridge *next_bridge;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index c4d72562c95a..c26ad0fed54d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1786,9 +1786,11 @@ static int dsi_populate_dsc_params(struct msm_dsi_host
*msm_host, struct drm_dsc
static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
{
+ struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev);
struct device *dev = _host->pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *endpoint;
+ const char *te_source;
int ret = 0;
/*
@@ -1811,6 +1813,15 @@ static int dsi_host_parse_dt(struct msm_dsi_host
*msm_host)
goto err;
}
+ ret = of_property_read_string(endpoint, "qcom,te-source", _source);
+ if (ret && ret != -EINVAL) {
+ DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n",
+ __func__, ret);
+ goto err;
+ }
+ if (!ret)
+ msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL);
+
if (of_property_read_bool(np, "syscon-sfpb")) {
msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
"syscon-sfpb");
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 5b3f3068fd92..a210b7c9e5ca 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -603,3 +603,8 @@ bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
{
return IS_MASTER_DSI_LINK(msm_dsi->id);
}
+
+const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi)
+{
+ return msm_dsi->te_source;
+}
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 912ebaa5df84..afd98dffea99 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -330,6 +330,7 @@ bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi);
struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
+const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi);
#else
static inline void __init msm_dsi_register(void)
{
@@ -367,6 +368,11 @@ static inline struct drm_dsc_config
*msm_dsi_get_dsc_config(struct msm_dsi *msm_
{
return NULL;
}
+
+static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi)
+{
+ return NULL;
+}
#endif
#ifdef CONFIG_DRM_MSM_DP
--
2.39.2
[PATCH 3/7] drm/msm/dsi: drop unused GPIOs handling
Neither disp-enable-gpios nor disp-te-gpios are defined in the schema.
None of the board DT files use those GPIO pins. Drop them from the
driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 37 -
1 file changed, 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a50f4dda5941..c4d72562c95a 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -7,7 +7,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -130,9 +129,6 @@ struct msm_dsi_host {
unsigned long src_clk_rate;
- struct gpio_desc *disp_en_gpio;
- struct gpio_desc *te_gpio;
-
const struct msm_dsi_cfg_handler *cfg_hnd;
struct completion dma_comp;
@@ -1613,28 +1609,6 @@ static irqreturn_t dsi_host_irq(int irq, void *ptr)
return IRQ_HANDLED;
}
-static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
- struct device *panel_device)
-{
- msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
-"disp-enable",
-GPIOD_OUT_LOW);
- if (IS_ERR(msm_host->disp_en_gpio)) {
- DBG("cannot get disp-enable-gpios %ld",
- PTR_ERR(msm_host->disp_en_gpio));
- return PTR_ERR(msm_host->disp_en_gpio);
- }
-
- msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
- GPIOD_IN);
- if (IS_ERR(msm_host->te_gpio)) {
- DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
- return PTR_ERR(msm_host->te_gpio);
- }
-
- return 0;
-}
-
static int dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *dsi)
{
@@ -1651,11 +1625,6 @@ static int dsi_host_attach(struct mipi_dsi_host *host,
if (dsi->dsc)
msm_host->dsc = dsi->dsc;
- /* Some gpios defined in panel DT need to be controlled by host */
- ret = dsi_host_init_panel_gpios(msm_host, >dev);
- if (ret)
- return ret;
-
ret = dsi_dev_attach(msm_host->pdev);
if (ret)
return ret;
@@ -2422,9 +2391,6 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
dsi_sw_reset(msm_host);
dsi_ctrl_enable(msm_host, phy_shared_timings, phy);
- if (msm_host->disp_en_gpio)
- gpiod_set_value(msm_host->disp_en_gpio, 1);
-
msm_host->power_on = true;
mutex_unlock(_host->dev_mutex);
@@ -2454,9 +2420,6 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host)
dsi_ctrl_disable(msm_host);
- if (msm_host->disp_en_gpio)
- gpiod_set_value(msm_host->disp_en_gpio, 0);
-
pinctrl_pm_select_sleep_state(_host->pdev->dev);
cfg_hnd->ops->link_clk_disable(msm_host);
--
2.39.2
[PATCH 5/7] drm/msm/dpu: rework vsync_source handling
The struct msm_display_info has is_te_using_watchdog_timer field which
is neither used anywhere nor is flexible enough to specify different
sources. Replace it with the field specifying the vsync source using
enum dpu_vsync_source.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
3 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index bd37a56b4d03..b147f8814a18 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -743,10 +743,7 @@ static void _dpu_encoder_update_vsync_source(struct
dpu_encoder_virt *dpu_enc,
vsync_cfg.pp_count = dpu_enc->num_phys_encs;
vsync_cfg.frame_rate =
drm_mode_vrefresh(_enc->base.crtc->state->adjusted_mode);
- if (disp_info->is_te_using_watchdog_timer)
- vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
- else
- vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
+ vsync_cfg.vsync_source = disp_info->vsync_source;
hw_mdptop->ops.setup_vsync_source(hw_mdptop, _cfg);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 76be77e30954..cb59bd4436f4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -26,15 +26,14 @@
* @h_tile_instance:Controller instance used per tile. Number of elements
is
* based on num_of_h_tiles
* @is_cmd_modeBoolean to indicate if the CMD mode is requested
- * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
- * used instead of panel TE in cmd mode panels
+ * @vsync_source: Source of the TE signal for DSI CMD devices
*/
struct msm_display_info {
enum dpu_intf_type intf_type;
uint32_t num_of_h_tiles;
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
- bool is_te_using_watchdog_timer;
+ enum dpu_vsync_source vsync_source;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 1955848b1b78..e9991f3756d4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -543,6 +543,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
+ info.vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
+
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, );
if (IS_ERR(encoder)) {
DPU_ERROR("encoder init failed for dsi display\n");
--
2.39.2
[PATCH 4/7] drm/msm/dpu: pull the is_cmd_mode out of _dpu_encoder_update_vsync_source()
Setting vsync source makes sense only for DSI CMD panels. Pull the
is_cmd_mode condition out of the function into the calling code, so that
it becomes more explicit.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 4988a1029431..bd37a56b4d03 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -736,8 +736,7 @@ static void _dpu_encoder_update_vsync_source(struct
dpu_encoder_virt *dpu_enc,
return;
}
- if (hw_mdptop->ops.setup_vsync_source &&
- disp_info->is_cmd_mode) {
+ if (hw_mdptop->ops.setup_vsync_source) {
for (i = 0; i < dpu_enc->num_phys_encs; i++)
vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
@@ -1226,7 +1225,8 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
dpu_enc->cur_master->hw_mdptop);
- _dpu_encoder_update_vsync_source(dpu_enc, _enc->disp_info);
+ if (dpu_enc->disp_info.is_cmd_mode)
+ _dpu_encoder_update_vsync_source(dpu_enc, _enc->disp_info);
if (dpu_enc->disp_info.intf_type == INTF_DSI &&
!WARN_ON(dpu_enc->num_phys_encs == 0)) {
--
2.39.2
[PATCH 2/7] drm/msm/dpu: convert vsync source defines to the enum
Add enum dpu_vsync_source instead of a series of defines. Use this enum
to pass vsync information.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 26 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 2 +-
5 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..4988a1029431 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -747,7 +747,7 @@ static void _dpu_encoder_update_vsync_source(struct
dpu_encoder_virt *dpu_enc,
if (disp_info->is_te_using_watchdog_timer)
vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
else
- vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
+ vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
hw_mdptop->ops.setup_vsync_source(hw_mdptop, _cfg);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 225c1c7768ff..96f6160cf607 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -462,7 +462,7 @@ static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf
*intf,
}
static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf,
- u32 vsync_source)
+ enum dpu_vsync_source vsync_source)
{
struct dpu_hw_blk_reg_map *c;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index f9015c67a574..ac244f0b33fb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -107,7 +107,7 @@ struct dpu_hw_intf_ops {
int (*connect_external_te)(struct dpu_hw_intf *intf, bool
enable_external_te);
- void (*vsync_sel)(struct dpu_hw_intf *intf, u32 vsync_source);
+ void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source
vsync_source);
/**
* Disable autorefresh if enabled
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 66759623fc42..a2eff36a2224 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -54,18 +54,20 @@
#define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12)
#define DPU_BLEND_BG_TRANSP_EN (1 << 13)
-#define DPU_VSYNC0_SOURCE_GPIO 0
-#define DPU_VSYNC1_SOURCE_GPIO 1
-#define DPU_VSYNC2_SOURCE_GPIO 2
-#define DPU_VSYNC_SOURCE_INTF_03
-#define DPU_VSYNC_SOURCE_INTF_14
-#define DPU_VSYNC_SOURCE_INTF_25
-#define DPU_VSYNC_SOURCE_INTF_36
-#define DPU_VSYNC_SOURCE_WD_TIMER_411
-#define DPU_VSYNC_SOURCE_WD_TIMER_312
-#define DPU_VSYNC_SOURCE_WD_TIMER_213
-#define DPU_VSYNC_SOURCE_WD_TIMER_114
-#define DPU_VSYNC_SOURCE_WD_TIMER_015
+enum dpu_vsync_source {
+ DPU_VSYNC_SOURCE_GPIO_0,
+ DPU_VSYNC_SOURCE_GPIO_1,
+ DPU_VSYNC_SOURCE_GPIO_2,
+ DPU_VSYNC_SOURCE_INTF_0 = 3,
+ DPU_VSYNC_SOURCE_INTF_1,
+ DPU_VSYNC_SOURCE_INTF_2,
+ DPU_VSYNC_SOURCE_INTF_3,
+ DPU_VSYNC_SOURCE_WD_TIMER_4 = 11,
+ DPU_VSYNC_SOURCE_WD_TIMER_3,
+ DPU_VSYNC_SOURCE_WD_TIMER_2,
+ DPU_VSYNC_SOURCE_WD_TIMER_1,
+ DPU_VSYNC_SOURCE_WD_TIMER_0,
+};
enum dpu_hw_blk_type {
DPU_HW_BLK_TOP = 0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index 6f3dc98087df..5c9a7ede991e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -64,7 +64,7 @@ struct dpu_vsync_source_cfg {
u32 pp_count;
u32 frame_rate;
u32 ppnumber[PINGPONG_MAX];
- u32 vsync_source;
+ enum dpu_vsync_source vsync_source;
};
/**
--
2.39.2
[PATCH 1/7] dt-bindings: display/msm/dsi: allow specifying TE source
Command mode panels provide TE signal back to the DSI host to signal
that the frame display has completed and update of the image will not
cause tearing. Usually it is connected to the first GPIO with the
mdp_vsync function, which is the default. In such case the property can
be skipped.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dsi-controller-main.yaml| 16
1 file changed, 16 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 1fa28e976559..c1771c69b247 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -162,6 +162,21 @@ properties:
items:
enum: [ 0, 1, 2, 3 ]
+ qcom,te-source:
+$ref: /schemas/types.yaml#/definitions/string
+description:
+ Specifies the source of vsync signal from the panel used for
+ tearing elimination. The default is mdp_gpio0.
+enum:
+ - mdp_gpio0
+ - mdp_gpio1
+ - mdp_gpio2
+ - timer0
+ - timer1
+ - timer2
+ - timer3
+ - timer4
+
required:
- port@0
- port@1
@@ -452,6 +467,7 @@ examples:
dsi0_out: endpoint {
remote-endpoint = <_in>;
data-lanes = <0 1 2 3>;
+ qcom,te-source = "mdp_gpio2";
};
};
};
--
2.39.2
[PATCH 0/7] drm/msm/dpu: handle non-default TE source pins
Command-mode DSI panels need to signal the display controlller when vsync happens, so that the device can start sending the next frame. Some devices (Google Pixel 3) use a non-default pin, so additional configuration is required. Add a way to specify this information in DT and handle it in the DSI and DPU drivers. Signed-off-by: Dmitry Baryshkov --- Dmitry Baryshkov (7): dt-bindings: display/msm/dsi: allow specifying TE source drm/msm/dpu: convert vsync source defines to the enum drm/msm/dsi: drop unused GPIOs handling drm/msm/dpu: pull the is_cmd_mode out of _dpu_encoder_update_vsync_source() drm/msm/dpu: rework vsync_source handling drm/msm/dsi: parse vsync source from device tree drm/msm/dpu: support setting the TE source .../bindings/display/msm/dsi-controller-main.yaml | 16 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 11 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 5 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 26 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 44 drivers/gpu/drm/msm/dsi/dsi.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 48 +- drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +++ drivers/gpu/drm/msm/msm_drv.h | 6 +++ 12 files changed, 106 insertions(+), 62 deletions(-) --- base-commit: 75fa778d74b786a1608d55d655d42b480a6fa8bd change-id: 20240514-dpu-handle-te-signal-82663c0211bd Best regards, -- Dmitry Baryshkov
Re: [PATCH] drm/msm/adreno: Check for zap node availability
On Fri, May 17, 2024 at 12:50:19PM -0700, Rob Clark wrote: > From: Rob Clark > > This should allow disabling the zap node via an overlay, for slbounce. > > Suggested-by: Nikita Travkin > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH 08/11] drm/msm/dp: switch to struct drm_edid
On Tue, May 14, 2024 at 03:55:14PM +0300, Jani Nikula wrote:
> Prefer the struct drm_edid based functions for reading the EDID and
> updating the connector.
>
> Simplify the flow by updating the EDID property when the EDID is read
> instead of at .get_modes.
>
> Signed-off-by: Jani Nikula
>
> ---
The patch looks good to me, I'd like to hear an opinion from Doug (added
to CC).
Reviewed-by: Dmitry Baryshkov
What is the merge strategy for the series? Do you plan to pick up all
the patches to drm-misc or should we pick up individual patches into
driver trees?
>
> Cc: Rob Clark
> Cc: Abhinav Kumar
> Cc: Dmitry Baryshkov
> Cc: Sean Paul
> Cc: Marijn Suijten
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedreno@lists.freedesktop.org
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 11 +++
> drivers/gpu/drm/msm/dp/dp_panel.c | 47 +
> drivers/gpu/drm/msm/dp/dp_panel.h | 2 +-
> 3 files changed, 20 insertions(+), 40 deletions(-)
[skipped]
> @@ -249,10 +228,12 @@ void dp_panel_handle_sink_request(struct dp_panel
> *dp_panel)
> panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
>
> if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) {
> + /* FIXME: get rid of drm_edid_raw() */
The code here can get use of something like drm_edid_smth_checksum().
'Something', because I could not come up with the word that would make
it clear that it is the declared checksum instead of the actual /
computed one.
> + const struct edid *edid = drm_edid_raw(dp_panel->drm_edid);
> u8 checksum;
>
> - if (dp_panel->edid)
> - checksum = dp_panel_get_edid_checksum(dp_panel->edid);
> + if (edid)
> + checksum = dp_panel_get_edid_checksum(edid);
> else
> checksum = dp_panel->connector->real_edid_checksum;
>
--
With best wishes
Dmitry
Re: [PATCH] drm/msm: Add obj flags to gpu devcoredump
On Mon, May 13, 2024 at 08:51:47AM -0700, Rob Clark wrote: > From: Rob Clark > > When debugging faults, it is useful to know how the BO is mapped (cached > vs WC, gpu readonly, etc). > > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 + > drivers/gpu/drm/msm/msm_gpu.c | 6 -- > drivers/gpu/drm/msm/msm_gpu.h | 1 + > 3 files changed, 6 insertions(+), 2 deletions(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [RFC PATCH 4/4] drm/msm: switch msm_kms to use msm_iommu_disp_new()
On Fri, May 17, 2024 at 04:37:59PM -0700, Abhinav Kumar wrote: > Switch msm_kms to use msm_iommu_disp_new() so that the newly > registered fault handler will kick-in during any mmu faults. > > Signed-off-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/msm_kms.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c > index 62c8e6163e81..1859efbbff1d 100644 > --- a/drivers/gpu/drm/msm/msm_kms.c > +++ b/drivers/gpu/drm/msm/msm_kms.c > @@ -181,7 +181,7 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct > drm_device *dev) > else > iommu_dev = mdss_dev; > > - mmu = msm_iommu_new(iommu_dev, 0); > + mmu = msm_iommu_disp_new(iommu_dev, 0); > if (IS_ERR(mmu)) > return ERR_CAST(mmu); Reviewed-by: Dmitry Baryshkov Note to myself: make mdp4 use msm_kms_init_aspace(). -- With best wishes Dmitry
Re: [RFC PATCH 1/4] drm/msm: register a fault handler for display mmu faults
On Fri, May 17, 2024 at 04:37:56PM -0700, Abhinav Kumar wrote:
> In preparation to register a iommu fault handler for display
> related modules, register a fault handler for the backing
> mmu object of msm_kms.
>
> Currently, the fault handler only captures the display snapshot
> but we can expand this later if more information needs to be
> added to debug display mmu faults.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/msm_kms.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
> index af6a6fcb1173..62c8e6163e81 100644
> --- a/drivers/gpu/drm/msm/msm_kms.c
> +++ b/drivers/gpu/drm/msm/msm_kms.c
> @@ -200,6 +200,28 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct
> drm_device *dev)
> return aspace;
> }
>
> +static int msm_kms_fault_handler(void *arg, unsigned long iova, int flags,
> void *data)
> +{
> + struct msm_kms *kms = arg;
> + struct msm_disp_state *state;
> + int ret;
> +
> + ret = mutex_lock_interruptible(>dump_mutex);
> + if (ret)
> + return ret;
> +
> + state = msm_disp_snapshot_state_sync(kms);
> +
> + mutex_unlock(>dump_mutex);
> +
> + if (IS_ERR(state)) {
> + DRM_DEV_ERROR(kms->dev->dev, "failed to capture snapshot\n");
> + return PTR_ERR(state);
> + }
> +
> + return 0;
Hmm, after reading the rest of the code, this means that we won't get
the error on the console. Could you please change this to -ENOSYS?
> +}
> +
> void msm_drm_kms_uninit(struct device *dev)
> {
> struct platform_device *pdev = to_platform_device(dev);
> @@ -261,6 +283,9 @@ int msm_drm_kms_init(struct device *dev, const struct
> drm_driver *drv)
> goto err_msm_uninit;
> }
>
> + if (kms->aspace)
> + msm_mmu_set_fault_handler(kms->aspace->mmu, kms,
> msm_kms_fault_handler);
> +
> drm_helper_move_panel_connectors_to_head(ddev);
>
> drm_for_each_crtc(crtc, ddev) {
> --
> 2.44.0
>
--
With best wishes
Dmitry
Re: [RFC PATCH 3/4] drm/msm/iommu: introduce msm_iommu_disp_new() for msm_kms
On Fri, May 17, 2024 at 04:37:58PM -0700, Abhinav Kumar wrote:
> Introduce a new API msm_iommu_disp_new() for display use-cases.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/msm_iommu.c | 28
> drivers/gpu/drm/msm/msm_mmu.h | 1 +
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
> index a79cd18bc4c9..3d5c1bb4c013 100644
> --- a/drivers/gpu/drm/msm/msm_iommu.c
> +++ b/drivers/gpu/drm/msm/msm_iommu.c
> @@ -343,6 +343,19 @@ static int msm_gpu_fault_handler(struct iommu_domain
> *domain, struct device *dev
> return 0;
> }
>
> +static int msm_disp_fault_handler(struct iommu_domain *domain, struct device
> *dev,
> + unsigned long iova, int flags, void *arg)
> +{
> + struct msm_iommu *iommu = arg;
> +
> + if (iommu->base.handler)
> + return iommu->base.handler(iommu->base.arg, iova, flags, NULL);
> +
> + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
> +
> + return 0;
I'd say, drop pr_warn and return -ENOSYS, letting the
arm_smmu_context_fault() report the error.
> +}
> +
> static void msm_iommu_resume_translation(struct msm_mmu *mmu)
> {
> struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev);
> @@ -434,6 +447,21 @@ struct msm_mmu *msm_iommu_new(struct device *dev,
> unsigned long quirks)
> return >base;
> }
>
> +struct msm_mmu *msm_iommu_disp_new(struct device *dev, unsigned long quirks)
> +{
> + struct msm_iommu *iommu;
> + struct msm_mmu *mmu;
> +
> + mmu = msm_iommu_new(dev, quirks);
> + if (IS_ERR_OR_NULL(mmu))
> + return mmu;
> +
> + iommu = to_msm_iommu(mmu);
> + iommu_set_fault_handler(iommu->domain, msm_disp_fault_handler, iommu);
> +
> + return mmu;
> +}
> +
> struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu,
> unsigned long quirks)
> {
> struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
> diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
> index 88af4f490881..730458d08d6b 100644
> --- a/drivers/gpu/drm/msm/msm_mmu.h
> +++ b/drivers/gpu/drm/msm/msm_mmu.h
> @@ -42,6 +42,7 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct
> device *dev,
>
> struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks);
> struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu,
> unsigned long quirks);
> +struct msm_mmu *msm_iommu_disp_new(struct device *dev, unsigned long quirks);
>
> static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
> int (*handler)(void *arg, unsigned long iova, int flags, void
> *data))
> --
> 2.44.0
>
--
With best wishes
Dmitry
Re: [RFC PATCH 2/4] drm/msm/iommu: rename msm_fault_handler to msm_gpu_fault_handler
On Fri, May 17, 2024 at 04:37:57PM -0700, Abhinav Kumar wrote: > In preparation of registering a separate fault handler for > display, lets rename the existing msm_fault_handler to > msm_gpu_fault_handler. > > Signed-off-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/msm_iommu.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [RFC PATCH 1/4] drm/msm: register a fault handler for display mmu faults
On Fri, May 17, 2024 at 04:37:56PM -0700, Abhinav Kumar wrote:
> In preparation to register a iommu fault handler for display
> related modules, register a fault handler for the backing
> mmu object of msm_kms.
>
> Currently, the fault handler only captures the display snapshot
> but we can expand this later if more information needs to be
> added to debug display mmu faults.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/msm_kms.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
> index af6a6fcb1173..62c8e6163e81 100644
> --- a/drivers/gpu/drm/msm/msm_kms.c
> +++ b/drivers/gpu/drm/msm/msm_kms.c
> @@ -200,6 +200,28 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct
> drm_device *dev)
> return aspace;
> }
>
> +static int msm_kms_fault_handler(void *arg, unsigned long iova, int flags,
> void *data)
> +{
> + struct msm_kms *kms = arg;
> + struct msm_disp_state *state;
> + int ret;
> +
> + ret = mutex_lock_interruptible(>dump_mutex);
> + if (ret)
> + return ret;
> +
> + state = msm_disp_snapshot_state_sync(kms);
> +
> + mutex_unlock(>dump_mutex);
> +
> + if (IS_ERR(state)) {
> + DRM_DEV_ERROR(kms->dev->dev, "failed to capture snapshot\n");
> + return PTR_ERR(state);
> + }
> +
> + return 0;
> +}
> +
> void msm_drm_kms_uninit(struct device *dev)
> {
> struct platform_device *pdev = to_platform_device(dev);
> @@ -261,6 +283,9 @@ int msm_drm_kms_init(struct device *dev, const struct
> drm_driver *drv)
> goto err_msm_uninit;
> }
>
> + if (kms->aspace)
> + msm_mmu_set_fault_handler(kms->aspace->mmu, kms,
> msm_kms_fault_handler);
> +
Can we move this to msm_kms_init_aspace() instead of checking for
kms->aspace?
> drm_helper_move_panel_connectors_to_head(ddev);
>
> drm_for_each_crtc(crtc, ddev) {
> --
> 2.44.0
>
--
With best wishes
Dmitry
Re: [RFC PATCH 0/4] drm/msm: add a display mmu fault handler
On Fri, May 17, 2024 at 04:37:55PM -0700, Abhinav Kumar wrote: > To debug display mmu faults, this series introduces a display fault > handler similar to the gpu one. > > This is only compile tested at the moment, till a suitable method > to trigger the fault is found and see if this handler does the needful > on the device. You should always be able to trigger the issue by programming wrong values to the SSPP. > > Abhinav Kumar (4): > drm/msm: register a fault handler for display mmu faults > drm/msm/iommu: rename msm_fault_handler to msm_gpu_fault_handler > drm/msm/iommu: introduce msm_iommu_disp_new() for msm_kms > drm/msm: switch msm_kms to use msm_iommu_disp_new() > > drivers/gpu/drm/msm/msm_iommu.c | 34 ++--- > drivers/gpu/drm/msm/msm_kms.c | 27 +- > drivers/gpu/drm/msm/msm_mmu.h | 1 + > 3 files changed, 58 insertions(+), 4 deletions(-) > > -- > 2.44.0 > -- With best wishes Dmitry
Re: [PATCH v4] drm/msm/a6xx: request memory region
On Sun, May 12, 2024 at 05:03:53AM -0400, Kiarash Hajian wrote:
> The driver's memory regions are currently just ioremap()ed, but not
> reserved through a request. That's not a bug, but having the request is
> a little more robust.
>
> Implement the region-request through the corresponding managed
> devres-function.
>
> Signed-off-by: Kiarash Hajian
> ---
> Changes in v4:
> - Combine v3 commits into a singel commit
> - Link to v3:
> https://lore.kernel.org/r/20240512-msm-adreno-memory-region-v3-0-0a728ad45...@gmail.com
>
> Changes in v3:
> - Remove redundant devm_iounmap calls, relying on devres for automatic
> resource cleanup.
>
> Changes in v2:
> - update the subject prefix to "drm/msm/a6xx:", to match the majority of
> other changes to this file.
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 22 +-
> 1 file changed, 1 insertion(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 8bea8ef26f77..cf0b3b3d8f34 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -524,9 +524,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
> uint32_t pdc_address_offset;
> bool pdc_in_aop = false;
>
> - if (IS_ERR(pdcptr))
> - goto err;
So, if there is an error, we just continue through? What about the code
that accesses the region afterwards?
If error handling becomes void, then there should be an early return
instead of dropping the error check completely.
> -
> if (adreno_is_a650(adreno_gpu) ||
> adreno_is_a660_family(adreno_gpu) ||
> adreno_is_a7xx(adreno_gpu))
> @@ -540,8 +537,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
>
> if (!pdc_in_aop) {
> seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
> - if (IS_ERR(seqptr))
> - goto err;
Same question.
> }
>
> /* Disable SDE clock gating */
> @@ -633,12 +628,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
> wmb();
>
> a6xx_rpmh_stop(gmu);
> -
> -err:
> - if (!IS_ERR_OR_NULL(pdcptr))
> - iounmap(pdcptr);
> - if (!IS_ERR_OR_NULL(seqptr))
> - iounmap(seqptr);
> }
>
> /*
> @@ -1503,7 +1492,7 @@ static void __iomem *a6xx_gmu_get_mmio(struct
> platform_device *pdev,
> return ERR_PTR(-EINVAL);
> }
>
> - ret = ioremap(res->start, resource_size(res));
> + ret = devm_ioremap_resource(>dev, res);
> if (!ret) {
> DRM_DEV_ERROR(>dev, "Unable to map the %s registers\n",
> name);
> return ERR_PTR(-EINVAL);
> @@ -1613,13 +1602,11 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu,
> struct device_node *node)
> gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
> if (IS_ERR(gmu->mmio)) {
> ret = PTR_ERR(gmu->mmio);
> - goto err_mmio;
And this is even worse. See the comment below.
> }
>
> gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
> if (IS_ERR(gmu->cxpd)) {
> ret = PTR_ERR(gmu->cxpd);
> - goto err_mmio;
> }
>
> if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) {
> @@ -1635,7 +1622,6 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu,
> struct device_node *node)
> gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
> if (IS_ERR(gmu->gxpd)) {
> ret = PTR_ERR(gmu->gxpd);
> - goto err_mmio;
> }
>
> gmu->initialized = true;
> @@ -1645,9 +1631,6 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu,
> struct device_node *node)
> detach_cxpd:
> dev_pm_domain_detach(gmu->cxpd, false);
>
> -err_mmio:
> - iounmap(gmu->mmio);
> -
You have dropped the iounmap(). However now the error path should
remain. The put_device() must be called. So fix the label name and just
drop the iounmap().
> /* Drop reference taken in of_find_device_by_node */
> put_device(gmu->dev);
>
> @@ -1825,9 +1808,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
> dev_pm_domain_detach(gmu->cxpd, false);
>
> err_mmio:
> - iounmap(gmu->mmio);
> - if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
> - iounmap(gmu->rscc);
Same comment here.
> free_irq(gmu->gmu_irq, gmu);
> free_irq(gmu->hfi_irq, gmu);
>
>
> ---
> base-commit: cf87f46fd34d6c19283d9625a7822f20d90b64a4
> change-id: 20240511-msm-adreno-memory-region-2bcb1c958621
>
> Best regards,
> --
> Kiarash Hajian
>
--
With best wishes
Dmitry
[PATCH] Revert "drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set"
In the DPU driver blank IRQ handling is called from a vblank worker and
can happen outside of the irq_enable / irq_disable pair. Revert commit
d13f638c9b88 ("drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set")
to fix vblank IRQ assignment for CMD DSI panels.
Fixes: d13f638c9b88 ("drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 32 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 +++--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 11 +++-
5 files changed, 46 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..a7d8ecf3f5be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1200,6 +1200,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct
drm_encoder *drm_enc,
phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
phys->cached_mode = crtc_state->adjusted_mode;
+ if (phys->ops.atomic_mode_set)
+ phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 002e89cc1705..30470cd15a48 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -69,6 +69,8 @@ struct dpu_encoder_phys;
* @is_master: Whether this phys_enc is the current master
* encoder. Can be switched at enable time. Based
* on split_role and current mode (CMD/VID).
+ * @atomic_mode_set: DRM Call. Set a DRM mode.
+ * This likely caches the mode, for use at enable.
* @enable:DRM Call. Enable a DRM mode.
* @disable: DRM Call. Disable mode.
* @control_vblank_irq Register/Deregister for VBLANK IRQ
@@ -93,6 +95,9 @@ struct dpu_encoder_phys;
struct dpu_encoder_phys_ops {
void (*prepare_commit)(struct dpu_encoder_phys *encoder);
bool (*is_master)(struct dpu_encoder_phys *encoder);
+ void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state);
void (*enable)(struct dpu_encoder_phys *encoder);
void (*disable)(struct dpu_encoder_phys *encoder);
int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 489be1c0c704..95cd39b49668 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -142,6 +142,23 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg)
dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
}
+static void dpu_encoder_phys_cmd_atomic_mode_set(
+ struct dpu_encoder_phys *phys_enc,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
+
+ phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
+
+ if (phys_enc->has_intf_te)
+ phys_enc->irq[INTR_IDX_RDPTR] =
phys_enc->hw_intf->cap->intr_tear_rd_ptr;
+ else
+ phys_enc->irq[INTR_IDX_RDPTR] =
phys_enc->hw_pp->caps->intr_rdptr;
+
+ phys_enc->irq[INTR_IDX_UNDERRUN] =
phys_enc->hw_intf->cap->intr_underrun;
+}
+
static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
struct dpu_encoder_phys *phys_enc)
{
@@ -280,14 +297,6 @@ static void dpu_encoder_phys_cmd_irq_enable(struct
dpu_encoder_phys *phys_enc)
phys_enc->hw_pp->idx - PINGPONG_0,
phys_enc->vblank_refcount);
- phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
- phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
-
- if (phys_enc->has_intf_te)
- phys_enc->irq[INTR_IDX_RDPTR] =
phys_enc->hw_intf->cap->intr_tear_rd_ptr;
- else
- phys_enc->irq[INTR_IDX_RDPTR] =
phys_enc->hw_pp->caps->intr_rdptr;
-
dpu_core_irq_register_callback(phys_enc->dpu_kms,
phys_enc->irq[INTR_IDX_PINGPONG],
Re: [PATCH v3 2/2] drm/msm/a6xx: request memory region
On Sun, May 12, 2024 at 01:49:39AM -0400, Kiarash Hajian wrote: > The devm_iounmap function is being used unnecessarily, > managed resource mechanisms (devres) are handling resource cleanup > automatically > > This commit removes the calls to devm_iounmap and relies on devres > > Signed-off-by: Kiarash Hajian > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 -- > 1 file changed, 18 deletions(-) In my opinion, this patch is better be squashed into the first patch. Though I'd leave a final word here to Rob and Konrad. BTW: for some reason your patches don't appear on freedreno's patchwork, although they definitely hit the list and appear on lore.kernel.org. -- With best wishes Dmitry
[PATCH v2] docs: document python version used for compilation
The drm/msm driver had adopted using Python3 script to generate register header files instead of shipping pre-generated header files. Document the minimal Python version supported by the script. Per request by Jon Hunter, the script is required to be compatible with Python 3.5. Python is documented as an optional dependency, as it is required only in a limited set of kernel configurations (following the example of other optional dependencies). Cc: Jon Hunter Signed-off-by: Dmitry Baryshkov --- Depends: https://lore.kernel.org/dri-devel/20240507230440.3384949-1-quic_abhin...@quicinc.com/ --- Changes in v2: - Expanded documentation for the Python usage. - Link to v1: https://lore.kernel.org/r/20240509-python-version-v1-1-a7dda3a95...@linaro.org --- Documentation/process/changes.rst | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst index 5685d7bfe4d0..30f17e3f954f 100644 --- a/Documentation/process/changes.rst +++ b/Documentation/process/changes.rst @@ -63,6 +63,7 @@ cpio any cpio --version GNU tar1.28 tar --version gtags (optional) 6.6.5gtags --version mkimage (optional) 2017.01 mkimage --version +Python (optional) 3.5.xpython3 --version == === .. [#f1] Sphinx is needed only to build the Kernel documentation @@ -198,6 +199,13 @@ platforms. The tool is available via the ``u-boot-tools`` package or can be built from the U-Boot source code. See the instructions at https://docs.u-boot.org/en/latest/build/tools.html#building-tools-for-linux +Python +-- + +Python is required to generate register headers for the drm/msm driver or to +build the linker script if the kernel is built using Clang compiler if LTO +(Link Time Optimisation) is enabled. + System utilities --- base-commit: e8bd80985f8ed4c04e36209228163fcf06496763 change-id: 20240509-python-version-a8b6ca2125ff Best regards, -- Dmitry Baryshkov
Re: [PATCH v2] drm/msm/a6xx: request memory region
On Sat, 11 May 2024 at 22:56, Kiarash Hajian
wrote:
>
> The driver's memory regions are currently just ioremap()ed, but not
> reserved through a request. That's not a bug, but having the request is
> a little more robust.
>
> Implement the region-request through the corresponding managed
> devres-function.
>
> Signed-off-by: Kiarash Hajian
> ---
> Changes in v2:
> - update the subject prefix to "drm/msm/a6xx:", to match the majority of
> other changes to this file.
Same comment as I posted for v1 of the patch.
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 8bea8ef26f77..aa83cb461a75 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -636,9 +636,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
>
> err:
> if (!IS_ERR_OR_NULL(pdcptr))
> - iounmap(pdcptr);
> + devm_iounmap(>dev,pdcptr);
> if (!IS_ERR_OR_NULL(seqptr))
> - iounmap(seqptr);
> + devm_iounmap(>dev,seqptr);
> }
>
> /*
> @@ -1503,7 +1503,7 @@ static void __iomem *a6xx_gmu_get_mmio(struct
> platform_device *pdev,
> return ERR_PTR(-EINVAL);
> }
>
> - ret = ioremap(res->start, resource_size(res));
> + ret = devm_ioremap_resource(>dev, res);
> if (!ret) {
> DRM_DEV_ERROR(>dev, "Unable to map the %s registers\n",
> name);
> return ERR_PTR(-EINVAL);
> @@ -1646,7 +1646,7 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu,
> struct device_node *node)
> dev_pm_domain_detach(gmu->cxpd, false);
>
> err_mmio:
> - iounmap(gmu->mmio);
> + devm_iounmap(gmu->dev ,gmu->mmio);
>
> /* Drop reference taken in of_find_device_by_node */
> put_device(gmu->dev);
> @@ -1825,9 +1825,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
> dev_pm_domain_detach(gmu->cxpd, false);
>
> err_mmio:
> - iounmap(gmu->mmio);
> + devm_iounmap(gmu->dev ,gmu->mmio);
> if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
> - iounmap(gmu->rscc);
> + devm_iounmap(gmu->dev ,gmu->rscc);
> free_irq(gmu->gmu_irq, gmu);
> free_irq(gmu->hfi_irq, gmu);
>
>
> ---
> base-commit: cf87f46fd34d6c19283d9625a7822f20d90b64a4
> change-id: 20240511-msm-adreno-memory-region-2bcb1c958621
>
> Best regards,
> --
> Kiarash Hajian
>
--
With best wishes
Dmitry
Re: [PATCH] drm/msm/adreno: request memory region
On Sat, 11 May 2024 at 22:35, Kiarash Hajian
wrote:
>
> The driver's memory regions are currently just ioremap()ed, but not
> reserved through a request. That's not a bug, but having the request is
> a little more robust.
>
> Implement the region-request through the corresponding managed
> devres-function.
>
> Signed-off-by: Kiarash Hajian
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 8bea8ef26f77..aa83cb461a75 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -636,9 +636,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
>
> err:
> if (!IS_ERR_OR_NULL(pdcptr))
> - iounmap(pdcptr);
> + devm_iounmap(>dev,pdcptr);
> if (!IS_ERR_OR_NULL(seqptr))
> - iounmap(seqptr);
> + devm_iounmap(>dev,seqptr);
Is there any reason to keep devm_iounmap calls? IMO with the devres
management in place, there should be no need to unmap them manually.
> }
>
> /*
> @@ -1503,7 +1503,7 @@ static void __iomem *a6xx_gmu_get_mmio(struct
> platform_device *pdev,
> return ERR_PTR(-EINVAL);
> }
>
> - ret = ioremap(res->start, resource_size(res));
> + ret = devm_ioremap_resource(>dev, res);
> if (!ret) {
> DRM_DEV_ERROR(>dev, "Unable to map the %s registers\n",
> name);
> return ERR_PTR(-EINVAL);
> @@ -1646,7 +1646,7 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu,
> struct device_node *node)
> dev_pm_domain_detach(gmu->cxpd, false);
>
> err_mmio:
> - iounmap(gmu->mmio);
> + devm_iounmap(gmu->dev ,gmu->mmio);
>
> /* Drop reference taken in of_find_device_by_node */
> put_device(gmu->dev);
> @@ -1825,9 +1825,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
> dev_pm_domain_detach(gmu->cxpd, false);
>
> err_mmio:
> - iounmap(gmu->mmio);
> + devm_iounmap(gmu->dev ,gmu->mmio);
> if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
> - iounmap(gmu->rscc);
> + devm_iounmap(gmu->dev ,gmu->rscc);
> free_irq(gmu->gmu_irq, gmu);
> free_irq(gmu->hfi_irq, gmu);
>
>
> ---
> base-commit: cf87f46fd34d6c19283d9625a7822f20d90b64a4
> change-id: 20240511-msm-adreno-memory-region-2bcb1c958621
>
> Best regards,
> --
> Kiarash Hajian
>
--
With best wishes
Dmitry
Re: [PATCH] docs: document python version used for compilation
On Fri, 10 May 2024 at 13:09, Jani Nikula wrote: > > On Fri, 10 May 2024, Mauro Carvalho Chehab wrote: > > Em Fri, 10 May 2024 11:08:38 +0300 > > Jani Nikula escreveu: > > > >> On Thu, 09 May 2024, Dmitry Baryshkov wrote: > >> > The drm/msm driver had adopted using Python3 script to generate register > >> > header files instead of shipping pre-generated header files. Document > >> > the minimal Python version supported by the script. > >> > > >> > Signed-off-by: Dmitry Baryshkov > >> > --- > >> > Documentation/process/changes.rst | 1 + > >> > 1 file changed, 1 insertion(+) > >> > > >> > diff --git a/Documentation/process/changes.rst > >> > b/Documentation/process/changes.rst > >> > index 5685d7bfe4d0..8d225a9f65a2 100644 > >> > --- a/Documentation/process/changes.rst > >> > +++ b/Documentation/process/changes.rst > >> > @@ -63,6 +63,7 @@ cpio any cpio --version > >> > GNU tar1.28 tar --version > >> > gtags (optional) 6.6.5gtags --version > >> > mkimage (optional) 2017.01 mkimage --version > >> > +Python (optional) 3.5.xpython3 --version > >> > >> Python 3.5 reached end-of-life 3½ years ago [1]. What's the point in > >> using anything older than the oldest supported version of Python, > >> i.e. 3.8 at this time? > > > > What's the point of breaking compilation with on older distros? > > The idea of minimal versions here is to specify the absolute minimum > > version that it is required for the build to happen. If 3.5 is > > the minimal one, then be it. > > AFAICT 3.5 was an arbitrary rather than a deliberate choice. We should > at least be aware *why* we'd be sticking to old versions. >From my side, the 3.5 was chosen basing on the previous feedback from Jon Hunter: https://lore.kernel.org/dri-devel/20240412165407.42163-1-jonath...@nvidia.com/ After checking distros that I can easily use, I don't think I will be able to test the script with Python versions earlier than 3.7.3 (Debian oldoldstable). I can try setting up Debian stretch (old-old-old-stable), which has Python 3.5 and so cover the needs of Jon. > > Minimum versions here also means sticking to features available in said > versions, for Python just as well as for GCC or any other tool. That's > not zero cost. > > I guess there are two angles here too. The absolute minimum version > currently required, and the, uh, maximum the minimum version can be > safely bumped to. Say, you want to use a feature not available in the > current minimum, how far up can you bump the version to? > > Could we define and document the criteria (e.g. based on distros as you > suggest below) so we don't have to repeat the discussion? > > > BR, > Jani. > > > > > - > > > > Now, a criteria is needed to raise the minimal version. IMO, the > > minimal version shall be at least the minimal one present on most > > used LTS distros that are not EOL. > > > > I would look for at least 4 such distros: > > > > - Debian > > > > Looking at https://wiki.debian.org/LTS, Debian 10 EOL will be on > > June, 2024. > > > > Looking at: > > > > https://distrowatch.com/table.php?distribution=debian > > > > Debian 10 uses python 3.7.3. > > > > - Looking at Distrowatch for openSUSE Leap 15.5, it uses Python > > 3.6.15 and has an EOL schedule for Dec, 2024. > > > > - RHEL 8.9 uses a bigger version than those two - 3.11.5 - again > > looking at Distrowatch to check it. > > > > - SLES 15 SP4 and above uses Python 3.11, according with: > > https://www.suse.com/c/python-3-11-stack-for-suse-linux-enterprise-15/ > > > > From the above, IMO kernel shall support building with Python 3.6 > > at least until the end of this year. > > > > Regards, > > Mauro > > -- > Jani Nikula, Intel -- With best wishes Dmitry
Re: [PATCH v2] drm/msm/dpu: fix encoder irq wait skip
On Thu, 9 May 2024 at 22:40, Barnabás Czémán wrote:
>
> The irq_idx is unsigned so it cannot be lower than zero, better
> to change the condition to check if it is equal with zero.
> It could not cause any issue because a valid irq index starts from one.
>
> Fixes: 5a9d50150c2c ("drm/msm/dpu: shift IRQ indices by 1")
> Signed-off-by: Barnabás Czémán
In the previous revision you have got the Reviewed-by tag, which you
didn't include here for some reason.
This revision is:
Reviewed-by: Dmitry Baryshkov
Note, there is no need to send a next iteration just for these tags.
They usually get picked up by the patch management software (including
the Fixes tag).
> ---
> Changes in v2:
> - Add Fixes in commit message.
> - Link to v1:
> https://lore.kernel.org/r/20240509-irq_wait-v1-1-41d653e37...@gmail.com
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 119f3ea50a7c..cf7d769ab3b9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -428,7 +428,7 @@ int dpu_encoder_helper_wait_for_irq(struct
> dpu_encoder_phys *phys_enc,
> return -EWOULDBLOCK;
> }
>
> - if (irq_idx < 0) {
> + if (irq_idx == 0) {
> DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
> DRMID(phys_enc->parent), func);
> return 0;
>
> ---
> base-commit: 704ba27ac55579704ba1289392448b0c66b56258
> change-id: 20240509-irq_wait-49444cea77e2
>
> Best regards,
> --
> Barnabás Czémán
>
--
With best wishes
Dmitry
[PATCH] docs: document python version used for compilation
The drm/msm driver had adopted using Python3 script to generate register header files instead of shipping pre-generated header files. Document the minimal Python version supported by the script. Signed-off-by: Dmitry Baryshkov --- Documentation/process/changes.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst index 5685d7bfe4d0..8d225a9f65a2 100644 --- a/Documentation/process/changes.rst +++ b/Documentation/process/changes.rst @@ -63,6 +63,7 @@ cpio any cpio --version GNU tar1.28 tar --version gtags (optional) 6.6.5gtags --version mkimage (optional) 2017.01 mkimage --version +Python (optional) 3.5.xpython3 --version == === .. [#f1] Sphinx is needed only to build the Kernel documentation --- base-commit: 704ba27ac55579704ba1289392448b0c66b56258 change-id: 20240509-python-version-a8b6ca2125ff Best regards, -- Dmitry Baryshkov
Re: [PATCH] drm/msm: remove python 3.9 dependency for compiling msm
On Wed, 8 May 2024 at 02:05, Abhinav Kumar wrote:
>
> Since commit 5acf49119630 ("drm/msm: import gen_header.py script from Mesa"),
> compilation is broken on machines having python versions older than 3.9
> due to dependency on argparse.BooleanOptionalAction.
>
> Switch to use simple bool for the validate flag to remove the dependency.
>
> Fixes: 5acf49119630 ("drm/msm: import gen_header.py script from Mesa")
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/registers/gen_header.py | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH v2 2/2] drm/ci: validate drm/msm XML register files against schema
On Sat, 4 May 2024 at 01:38, Abhinav Kumar wrote: > > > > On 5/3/2024 1:20 PM, Dmitry Baryshkov wrote: > > On Fri, 3 May 2024 at 22:42, Abhinav Kumar > > wrote: > >> > >> > >> > >> On 5/3/2024 11:15 AM, Dmitry Baryshkov wrote: > >>> In order to validate drm/msm register definition files against schema, > >>> reuse the nodebugfs build step. The validation entry is guarded by > >>> the EXPERT Kconfig option and we don't want to enable that option for > >>> all the builds. > >>> > >>> Signed-off-by: Dmitry Baryshkov > >>> --- > >>>drivers/gpu/drm/ci/build.sh | 3 +++ > >>>drivers/gpu/drm/ci/build.yml | 1 + > >>>2 files changed, 4 insertions(+) > >>> > >>> diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh > >>> index 106f2d40d222..28a495c0c39c 100644 > >>> --- a/drivers/gpu/drm/ci/build.sh > >>> +++ b/drivers/gpu/drm/ci/build.sh > >>> @@ -12,6 +12,9 @@ rm -rf .git/rebase-apply > >>>apt-get update > >>>apt-get install -y libssl-dev > >>> > >>> +# for msm header validation > >>> +apt-get install -y python3-lxml > >>> + > >>>if [[ "$KERNEL_ARCH" = "arm64" ]]; then > >>>GCC_ARCH="aarch64-linux-gnu" > >>>DEBIAN_ARCH="arm64" > >>> diff --git a/drivers/gpu/drm/ci/build.yml b/drivers/gpu/drm/ci/build.yml > >>> index 17ab38304885..9c198239033d 100644 > >>> --- a/drivers/gpu/drm/ci/build.yml > >>> +++ b/drivers/gpu/drm/ci/build.yml > >>> @@ -106,6 +106,7 @@ build-nodebugfs:arm64: > >>> extends: .build:arm64 > >>> variables: > >>>DISABLE_KCONFIGS: "DEBUG_FS" > >>> +ENABLE_KCONFIGS: "EXPERT DRM_MSM_VALIDATE_XML" > >>> > >> > >> Wouldnt this end up enabling DRM_MSM_VALIDATE_XML for any arm64 device. > >> > >> Cant we make this build rule msm specific? > > > > No need to. We just need to validate the files at least once during > > the whole pipeline build. > > > > ah okay, today the arm64 config anyway sets all arm64 vendor drm configs > to y. > > A couple of more questions: > > 1) Why is this enabled only for no-debugfs option? > 2) Will there be any concerns from other vendors to enable CONFIG_EXPERT > in their CI runs as the arm64 config is shared across all arm64 vendors. I don't get the second question. This option is only enabled for no-debugfs, which isn't used for execution. I didn't want to add an extra build stage, just for the sake of validating regs against the schema, nor did I want EXPERT to find its way into the actual running kernels. -- With best wishes Dmitry
Re: [PATCH] drm/msm/dpu: fix vblank IRQ handling for command panels
On Fri, May 03, 2024 at 11:18:52AM +0200, Luca Weiss wrote: > On Sun Apr 7, 2024 at 5:15 AM CEST, Dmitry Baryshkov wrote: > > On Sat, 30 Mar 2024 at 18:49, Marijn Suijten > > wrote: > > > > > > On 2024-03-30 05:52:29, Dmitry Baryshkov wrote: > > > > In case of CMD DSI panels, the vblank IRQ can be used outside of > > > > irq_enable/irq_disable pair. This results in the following kind of > > > > > > Can you clarify when exactly that is? Is it via ops.control_vblank_irq in > > > dpu_encoder_toggle_vblank_for_crtc()? > > > > Call trace: > > dpu_encoder_phys_cmd_control_vblank_irq+0x218/0x294 > > dpu_encoder_toggle_vblank_for_crtc+0x160/0x194 > > dpu_crtc_vblank+0xbc/0x228 > > dpu_kms_enable_vblank+0x18/0x24 > > vblank_ctrl_worker+0x34/0x6c > > process_one_work+0x218/0x620 > > worker_thread+0x1ac/0x37c > > kthread+0x114/0x118 > > ret_from_fork+0x10/0x20 > > > > The vblank_ctrl_work happens when the framework attempts to trigger > > the vblank on the CRTC. > > > > > > > > > messages. Move assignment of IRQ indices to atomic_enable / > > > > atomic_disable callbacks. > > > > > > > > [dpu error]invalid IRQ=[134217727, 31] > > > > [drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err > > > > id:31 pp:0 ret:-22, enable true/0 > > > > [drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err > > > > id:31 pp:0 ret:-22, enable false/0 > > > > > > You are right that such messages are common, both at random but also > > > seemingly > > > around toggling the `ACTIVE` property on the CRTC: > > > > > > [ 45.878300] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_disable > > > [ 45.909941] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_unprepare > > > [ 46.093234] [drm:dpu_encoder_helper_wait_for_irq] *ERROR* > > > encoder is disabled id=31, callback=dpu_encoder_phys_cmd_ctl_start_irq, > > > IRQ=[134217727, 31] > > > [ 46.130421] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_prepare > > > [ 46.340457] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_enable > > > [ 65.520323] [dpu error]invalid IRQ=[134217727, 31] > > > irq_cb:dpu_encoder_phys_cmd_te_rd_ptr_irq > > > [ 65.520463] [drm:dpu_encoder_phys_cmd_control_vblank_irq] > > > *ERROR* vblank irq err id:31 pp:0 ret:-22, enable true/0 > > > [ 65.630199] [drm:dpu_encoder_phys_cmd_control_vblank_irq] > > > *ERROR* vblank irq err id:31 pp:0 ret:-22, enable false/0 > > > [ 166.576465] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_disable > > > [ 166.609674] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_unprepare > > > [ 166.781967] [drm:dpu_encoder_helper_wait_for_irq] *ERROR* > > > encoder is disabled id=31, callback=dpu_encoder_phys_cmd_ctl_start_irq, > > > IRQ=[134217727, 31] > > > [ 166.829805] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_prepare > > > [ 167.040476] panel-samsung-souxp ae94000.dsi.0: > > > samsung_souxp00_enable > > > [ 337.449827] [dpu error]invalid IRQ=[134217727, 31] > > > irq_cb:dpu_encoder_phys_cmd_te_rd_ptr_irq > > > [ 337.450434] [drm:dpu_encoder_phys_cmd_control_vblank_irq] > > > *ERROR* vblank irq err id:31 pp:0 ret:-22, enable true/0 > > > [ 337.569526] [drm:dpu_encoder_phys_cmd_control_vblank_irq] > > > *ERROR* vblank irq err id:31 pp:0 ret:-22, enable false/0 > > > [ 354.980357] [dpu error]invalid IRQ=[134217727, 31] > > > irq_cb:dpu_encoder_phys_cmd_te_rd_ptr_irq > > > [ 354.980495] [drm:dpu_encoder_phys_cmd_control_vblank_irq] > > > *ERROR* vblank irq err id:31 pp:0 ret:-22, enable true/0 > > > [ 355.090460] [drm:dpu_encoder_phys_cmd_control_vblank_irq] > > > *ERROR* vblank irq err id:31 pp:0 ret:-22, enable false/0 > > > > > > Unfortunately with this patch, turning the CRTC off via ./modetest -M msm > > > -a > > > -w 81:ACTIVE:0 immediately triggers a bunch of WARNs (note that the CRTC > > > turns > > > on immediately again when the command returns, that's probably the > > > framebuffer > > > console taking over again). Running it a few times in succession this > > > ma
Re: [PATCH] drm/msm/gen_header: allow skipping the validation
On Fri, May 03, 2024 at 09:48:12AM -0700, Nathan Chancellor wrote: > Hi Dmitry, > > On Tue, Apr 09, 2024 at 05:22:54PM +0300, Dmitry Baryshkov wrote: > > We don't need to run the validation of the XML files if we are just > > compiling the kernel. Skip the validation unless the user enables > > corresponding Kconfig option. This removes a warning from gen_header.py > > about lxml being not installed. > > > > Reported-by: Stephen Rothwell > > Closes: > > https://lore.kernel.org/all/20240409120108.2303d...@canb.auug.org.au/ > > Signed-off-by: Dmitry Baryshkov > > --- > > drivers/gpu/drm/msm/Kconfig | 8 > > drivers/gpu/drm/msm/Makefile| 9 - > > drivers/gpu/drm/msm/registers/gen_header.py | 14 +++--- > > 3 files changed, 27 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > > index f202f26adab2..4c9bf237d4a2 100644 > > --- a/drivers/gpu/drm/msm/Kconfig > > +++ b/drivers/gpu/drm/msm/Kconfig > > @@ -54,6 +54,14 @@ config DRM_MSM_GPU_SUDO > > Only use this if you are a driver developer. This should *not* > > be enabled for production kernels. If unsure, say N. > > > > +config DRM_MSM_VALIDATE_XML > > + bool "Validate XML register files against schema" > > + depends on DRM_MSM && EXPERT > > + depends on $(success,$(PYTHON3) -c "import lxml") > > + help > > + Validate XML files with register definitions against rules-fd schema. > > + This option is mostly targeting DRM MSM developers. If unsure, say N. > > Is this change going to be applied? I have gotten a little tired of > seeing "lxml not found, skipping validation" in all of my builds :) > I've posted v2, including CI changes. The plan is to get it merged before the drm/msm pull request. -- With best wishes Dmitry
Re: [PATCH v2 0/2] drm/msm/gen_header: allow skipping the validation
On Fri, 3 May 2024 at 21:15, Dmitry Baryshkov wrote: > > In order to remove pointless messages regarding missing lxml, skip > validation of MSM register files against the schema. Only the driver > developers really care and/or can fix the files. > > Keep the validation enabled during one of DRM CI stages, so that we > still catch errors, introduced by mistake. Helen, could you please ack merging the second patch through drm/msm tree? > --- > Dmitry Baryshkov (2): > drm/msm/gen_header: allow skipping the validation > drm/ci: validate drm/msm XML register files against schema -- With best wishes Dmitry
Re: [PATCH v2 2/2] drm/ci: validate drm/msm XML register files against schema
On Fri, 3 May 2024 at 22:42, Abhinav Kumar wrote: > > > > On 5/3/2024 11:15 AM, Dmitry Baryshkov wrote: > > In order to validate drm/msm register definition files against schema, > > reuse the nodebugfs build step. The validation entry is guarded by > > the EXPERT Kconfig option and we don't want to enable that option for > > all the builds. > > > > Signed-off-by: Dmitry Baryshkov > > --- > > drivers/gpu/drm/ci/build.sh | 3 +++ > > drivers/gpu/drm/ci/build.yml | 1 + > > 2 files changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh > > index 106f2d40d222..28a495c0c39c 100644 > > --- a/drivers/gpu/drm/ci/build.sh > > +++ b/drivers/gpu/drm/ci/build.sh > > @@ -12,6 +12,9 @@ rm -rf .git/rebase-apply > > apt-get update > > apt-get install -y libssl-dev > > > > +# for msm header validation > > +apt-get install -y python3-lxml > > + > > if [[ "$KERNEL_ARCH" = "arm64" ]]; then > > GCC_ARCH="aarch64-linux-gnu" > > DEBIAN_ARCH="arm64" > > diff --git a/drivers/gpu/drm/ci/build.yml b/drivers/gpu/drm/ci/build.yml > > index 17ab38304885..9c198239033d 100644 > > --- a/drivers/gpu/drm/ci/build.yml > > +++ b/drivers/gpu/drm/ci/build.yml > > @@ -106,6 +106,7 @@ build-nodebugfs:arm64: > > extends: .build:arm64 > > variables: > > DISABLE_KCONFIGS: "DEBUG_FS" > > +ENABLE_KCONFIGS: "EXPERT DRM_MSM_VALIDATE_XML" > > > > Wouldnt this end up enabling DRM_MSM_VALIDATE_XML for any arm64 device. > > Cant we make this build rule msm specific? No need to. We just need to validate the files at least once during the whole pipeline build. -- With best wishes Dmitry
[PATCH v2 2/2] drm/ci: validate drm/msm XML register files against schema
In order to validate drm/msm register definition files against schema, reuse the nodebugfs build step. The validation entry is guarded by the EXPERT Kconfig option and we don't want to enable that option for all the builds. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/ci/build.sh | 3 +++ drivers/gpu/drm/ci/build.yml | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh index 106f2d40d222..28a495c0c39c 100644 --- a/drivers/gpu/drm/ci/build.sh +++ b/drivers/gpu/drm/ci/build.sh @@ -12,6 +12,9 @@ rm -rf .git/rebase-apply apt-get update apt-get install -y libssl-dev +# for msm header validation +apt-get install -y python3-lxml + if [[ "$KERNEL_ARCH" = "arm64" ]]; then GCC_ARCH="aarch64-linux-gnu" DEBIAN_ARCH="arm64" diff --git a/drivers/gpu/drm/ci/build.yml b/drivers/gpu/drm/ci/build.yml index 17ab38304885..9c198239033d 100644 --- a/drivers/gpu/drm/ci/build.yml +++ b/drivers/gpu/drm/ci/build.yml @@ -106,6 +106,7 @@ build-nodebugfs:arm64: extends: .build:arm64 variables: DISABLE_KCONFIGS: "DEBUG_FS" +ENABLE_KCONFIGS: "EXPERT DRM_MSM_VALIDATE_XML" build:x86_64: extends: .build:x86_64 -- 2.39.2
[PATCH v2 1/2] drm/msm/gen_header: allow skipping the validation
We don't need to run the validation of the XML files if we are just
compiling the kernel. Skip the validation unless the user enables
corresponding Kconfig option. This removes a warning from gen_header.py
about lxml being not installed.
Reported-by: Stephen Rothwell
Closes: https://lore.kernel.org/all/20240409120108.2303d...@canb.auug.org.au/
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 8
drivers/gpu/drm/msm/Makefile| 9 -
drivers/gpu/drm/msm/registers/gen_header.py | 14 +++---
3 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index f202f26adab2..4c9bf237d4a2 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -54,6 +54,14 @@ config DRM_MSM_GPU_SUDO
Only use this if you are a driver developer. This should *not*
be enabled for production kernels. If unsure, say N.
+config DRM_MSM_VALIDATE_XML
+ bool "Validate XML register files against schema"
+ depends on DRM_MSM && EXPERT
+ depends on $(success,$(PYTHON3) -c "import lxml")
+ help
+ Validate XML files with register definitions against rules-fd schema.
+ This option is mostly targeting DRM MSM developers. If unsure, say N.
+
config DRM_MSM_MDSS
bool
depends on DRM_MSM
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index c861de58286c..718968717ad5 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -156,8 +156,15 @@ msm-y += $(adreno-y) $(msm-display-y)
obj-$(CONFIG_DRM_MSM) += msm.o
+ifeq (y,$(CONFIG_DRM_MSM_VALIDATE_XML))
+ headergen-opts += --validate
+else
+ headergen-opts += --no-validate
+endif
+
quiet_cmd_headergen = GENHDR $@
- cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3)
$(srctree)/$(src)/registers/gen_header.py --rnn $(srctree)/$(src)/registers
--xml $< c-defines > $@
+ cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3)
$(srctree)/$(src)/registers/gen_header.py \
+ $(headergen-opts) --rnn $(srctree)/$(src)/registers --xml
$< c-defines > $@
$(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
$(src)/registers/adreno/adreno_common.xml \
diff --git a/drivers/gpu/drm/msm/registers/gen_header.py
b/drivers/gpu/drm/msm/registers/gen_header.py
index 90d5c2991d05..fc3bfdc991d2 100644
--- a/drivers/gpu/drm/msm/registers/gen_header.py
+++ b/drivers/gpu/drm/msm/registers/gen_header.py
@@ -538,6 +538,9 @@ class Parser(object):
self.variants.add(reg.domain)
def do_validate(self, schemafile):
+ if self.validate == False:
+ return
+
try:
from lxml import etree
@@ -567,7 +570,10 @@ class Parser(object):
if not xmlschema.validate(xml_doc):
error_str =
str(xmlschema.error_log.filter_from_errors()[0])
raise self.error("Schema validation failed for:
" + filename + "\n" + error_str)
- except ImportError:
+ except ImportError as e:
+ if self.validate:
+ raise e
+
print("lxml not found, skipping validation",
file=sys.stderr)
def do_parse(self, filename):
@@ -586,9 +592,10 @@ class Parser(object):
self.stack.pop()
file.close()
- def parse(self, rnn_path, filename):
+ def parse(self, rnn_path, filename, validate):
self.path = rnn_path
self.stack = []
+ self.validate = validate
self.do_parse(filename)
def parse_reg(self, attrs, bit_size):
@@ -853,7 +860,7 @@ def dump_c(args, guard, func):
p = Parser()
try:
- p.parse(args.rnn, args.xml)
+ p.parse(args.rnn, args.xml, args.validate)
except Error as e:
print(e, file=sys.stderr)
exit(1)
@@ -941,6 +948,7 @@ def main():
parser = argparse.ArgumentParser()
parser.add_argument('--rnn', type=str, required=True)
parser.add_argument('--xml', type=str, required=True)
+ parser.add_argument('--validate', action=argparse.BooleanOptionalAction)
subparsers = parser.add_subparsers()
subparsers.required = True
--
2.39.2
[PATCH v2 0/2] drm/msm/gen_header: allow skipping the validation
In order to remove pointless messages regarding missing lxml, skip validation of MSM register files against the schema. Only the driver developers really care and/or can fix the files. Keep the validation enabled during one of DRM CI stages, so that we still catch errors, introduced by mistake. To: Rob Clark To: Abhinav Kumar To: Sean Paul To: Marijn Suijten To: David Airlie To: Daniel Vetter To: Helen Koike To: Maarten Lankhorst To: Maxime Ripard To: Thomas Zimmermann Cc: linux-arm-...@vger.kernel.org Cc: dri-de...@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Cc: linux-ker...@vger.kernel.org Signed-off-by: Dmitry Baryshkov Changes in v2: - added validation of XML files agains schema in in DRM CI - Link to v1: https://lore.kernel.org/r/20240409-fd-fix-lxml-v1-1-e5c300d6c...@linaro.org --- Dmitry Baryshkov (2): drm/msm/gen_header: allow skipping the validation drm/ci: validate drm/msm XML register files against schema drivers/gpu/drm/ci/build.sh | 3 +++ drivers/gpu/drm/ci/build.yml| 1 + drivers/gpu/drm/msm/Kconfig | 8 drivers/gpu/drm/msm/Makefile| 9 - drivers/gpu/drm/msm/registers/gen_header.py | 14 +++--- 5 files changed, 31 insertions(+), 4 deletions(-) --- base-commit: 104e548a7c97da24224b375632fca0fc8b64c0db change-id: 20240409-fd-fix-lxml-eecc6949f64e Best regards, -- Dmitry Baryshkov
Re: [PATCH v2 5/6] drm/msm: Add MSM_PARAM_RAYTRACING uapi
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote: > > Expose the value of the software fuse to userspace. > > Signed-off-by: Connor Abbott > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ > include/uapi/drm/msm_drm.h | 1 + > 2 files changed, 4 insertions(+) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v2 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote: > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to > initialize cx_mem. Copy this from downstream (minus BCL which we > currently don't support). On a750, this includes a new "fuse" register > which can be used by qcom_scm to fuse off certain features like > raytracing in software. The fuse is default off, and is initialized by > calling the method. Afterwards we have to read it to find out which > features were enabled. > > Signed-off-by: Connor Abbott > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 88 > - > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 + > 2 files changed, 89 insertions(+), 1 deletion(-) > I didn't check the register bits, but the rest looks fine Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v2 3/6] drm/msm: Update a6xx registers
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote:
>
> Update to mesa commit ff155f46a33 ("freedreno/a7xx: Register updates
> from kgsl").
>
> Signed-off-by: Connor Abbott
> ---
> drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28
> ---
> 1 file changed, 25 insertions(+), 3 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH v2 2/6] firmware: qcom_scm: Add gpu_init_regs call
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote: > > This will used by drm/msm. Can we have some description please? > > Signed-off-by: Connor Abbott > --- > drivers/firmware/qcom/qcom_scm.c | 14 ++ > drivers/firmware/qcom/qcom_scm.h | 3 +++ > include/linux/firmware/qcom/qcom_scm.h | 23 +++ > 3 files changed, 40 insertions(+) > With the commit message improved: Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v2 1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote:
>
> This is doubled compared to previous GPUs. We can't access the new
> SW_FUSE_VALUE register without this.
>
> Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes")
> Signed-off-by: Connor Abbott
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 18:36, Connor Abbott wrote: > > On Fri, Apr 26, 2024 at 4:24 PM Dmitry Baryshkov > wrote: > > > > On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote: > > > > > > On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov > > > wrote: > > > > > > > > On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote: > > > > > > > > > > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov > > > > > wrote: > > > > > > > > > > > > On Fri, 26 Apr 2024 at 15:35, Connor Abbott > > > > > > wrote: > > > > > > > > > > > > > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov > > > > > > > wrote: > > > > > > > > > > > > > > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a > > > > > > > > > method to > > > > > > > > > initialize cx_mem. Copy this from downstream (minus BCL which > > > > > > > > > we > > > > > > > > > currently don't support). On a750, this includes a new "fuse" > > > > > > > > > register > > > > > > > > > which can be used by qcom_scm to fuse off certain features > > > > > > > > > like > > > > > > > > > raytracing in software. The fuse is default off, and is > > > > > > > > > initialized by > > > > > > > > > calling the method. Afterwards we have to read it to find out > > > > > > > > > which > > > > > > > > > features were enabled. > > > > > > > > > > > > > > > > > > Signed-off-by: Connor Abbott > > > > > > > > > --- > > > > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 > > > > > > > > > - > > > > > > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 + > > > > > > > > > 2 files changed, 90 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > > > > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > > > > > > > index cf0b1de1c071..fb2722574ae5 100644 > > > > > > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > > > > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > > > > > > > @@ -10,6 +10,7 @@ > > > > > > > > > > > > > > > > > > #include > > > > > > > > > #include > > > > > > > > > +#include > > > > > > > > > #include > > > > > > > > > #include > > > > > > > > > > > > > > > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct > > > > > > > > > msm_gpu *gpu) > > > > > > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT > > > > > > > > > | \ > > > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | > > > > > > > > > \ > > > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ > > > > > > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR) > > > > > > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ > > > > > > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) > > > > > > > > > > > > > > > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ > > > > > > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \ > > > > > > > > > @@ -2356,6 +2358,26 @@ static void > > > > > > > > > a6xx_fault_detect_irq(struct msm_gpu *gpu) > > > > > > > > > kthread_queue_work(gpu->worker, >recover_work); > >
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
> > > > >
> > > > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > > > wrote:
> > > > > >
> > > > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott
> > > > > > wrote:
> > > > > > >
> > > > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a
> > > > > > > method to
> > > > > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > > > > currently don't support). On a750, this includes a new "fuse"
> > > > > > > register
> > > > > > > which can be used by qcom_scm to fuse off certain features like
> > > > > > > raytracing in software. The fuse is default off, and is
> > > > > > > initialized by
> > > > > > > calling the method. Afterwards we have to read it to find out
> > > > > > > which
> > > > > > > features were enabled.
> > > > > > >
> > > > > > > Signed-off-by: Connor Abbott
> > > > > > > ---
> > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > > > -
> > > > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > @@ -10,6 +10,7 @@
> > > > > > >
> > > > > > > #include
> > > > > > > #include
> > > > > > > +#include
> > > > > > > #include
> > > > > > > #include
> > > > > > >
> > > > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct
> > > > > > > msm_gpu *gpu)
> > > > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > >
> > > > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct
> > > > > > > msm_gpu *gpu)
> > > > > > > kthread_queue_work(gpu->worker, >recover_work);
> > > > > > > }
> > > > > > >
> > > > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > > > +{
> > > > > > > + u32 status;
> > > > > > > +
> > > > > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > > > +
> > > > > > > + dev_err_ratelimited(>pdev->dev, "SW fuse violation
> > > > > > > status=%8.8x\n", status);
> > > > > > > +
> > > > > > > + /* Ignore FASTBLEND violations, because the HW will
> > > > > > > silently fall back
> > > > > > > +* to legacy blending.
> > > > > > > +*/
> > > &
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > > > >
> > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method
> > > > > to
> > > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > > currently don't support). On a750, this includes a new "fuse" register
> > > > > which can be used by qcom_scm to fuse off certain features like
> > > > > raytracing in software. The fuse is default off, and is initialized by
> > > > > calling the method. Afterwards we have to read it to find out which
> > > > > features were enabled.
> > > > >
> > > > > Signed-off-by: Connor Abbott
> > > > > ---
> > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > -
> > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > @@ -10,6 +10,7 @@
> > > > >
> > > > > #include
> > > > > #include
> > > > > +#include
> > > > > #include
> > > > > #include
> > > > >
> > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu
> > > > > *gpu)
> > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > >
> > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct
> > > > > msm_gpu *gpu)
> > > > > kthread_queue_work(gpu->worker, >recover_work);
> > > > > }
> > > > >
> > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > +{
> > > > > + u32 status;
> > > > > +
> > > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > +
> > > > > + dev_err_ratelimited(>pdev->dev, "SW fuse violation
> > > > > status=%8.8x\n", status);
> > > > > +
> > > > > + /* Ignore FASTBLEND violations, because the HW will silently
> > > > > fall back
> > > > > +* to legacy blending.
> > > > > +*/
> > > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > > + del_timer(>hangcheck_timer);
> > > > > +
> > > > > + kthread_queue_work(gpu->worker, >recover_work);
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > {
> > > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > > dev_err_ratelimited(>pdev->dev, "UCHE | Out of
> > > > > bounds access\n");
> > > >
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 15:54, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 1:35 PM Connor Abbott wrote:
> >
> > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > > >
> > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > currently don't support). On a750, this includes a new "fuse" register
> > > > which can be used by qcom_scm to fuse off certain features like
> > > > raytracing in software. The fuse is default off, and is initialized by
> > > > calling the method. Afterwards we have to read it to find out which
> > > > features were enabled.
> > > >
> > > > Signed-off-by: Connor Abbott
> > > > ---
> > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > @@ -10,6 +10,7 @@
> > > >
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu
> > > > *gpu)
> > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > >
> > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > > > *gpu)
> > > > kthread_queue_work(gpu->worker, >recover_work);
> > > > }
> > > >
> > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > +{
> > > > + u32 status;
> > > > +
> > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > +
> > > > + dev_err_ratelimited(>pdev->dev, "SW fuse violation
> > > > status=%8.8x\n", status);
> > > > +
> > > > + /* Ignore FASTBLEND violations, because the HW will silently
> > > > fall back
> > > > +* to legacy blending.
> > > > +*/
> > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > + del_timer(>hangcheck_timer);
> > > > +
> > > > + kthread_queue_work(gpu->worker, >recover_work);
> > > > + }
> > > > +}
> > > > +
> > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > {
> > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > dev_err_ratelimited(>pdev->dev, "UCHE | Out of
> > > > bounds access\n");
> > > >
> > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > +
> > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > msm_gpu_retire(gpu);
> > > >
> > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > platform_device *pdev,
> > > >
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> wrote:
> >
> > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > >
> > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > currently don't support). On a750, this includes a new "fuse" register
> > > which can be used by qcom_scm to fuse off certain features like
> > > raytracing in software. The fuse is default off, and is initialized by
> > > calling the method. Afterwards we have to read it to find out which
> > > features were enabled.
> > >
> > > Signed-off-by: Connor Abbott
> > > ---
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index cf0b1de1c071..fb2722574ae5 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -10,6 +10,7 @@
> > >
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > >
> > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
> > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > >
> > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > > *gpu)
> > > kthread_queue_work(gpu->worker, >recover_work);
> > > }
> > >
> > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > +{
> > > + u32 status;
> > > +
> > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > +
> > > + dev_err_ratelimited(>pdev->dev, "SW fuse violation
> > > status=%8.8x\n", status);
> > > +
> > > + /* Ignore FASTBLEND violations, because the HW will silently fall
> > > back
> > > +* to legacy blending.
> > > +*/
> > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > + del_timer(>hangcheck_timer);
> > > +
> > > + kthread_queue_work(gpu->worker, >recover_work);
> > > + }
> > > +}
> > > +
> > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > {
> > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > dev_err_ratelimited(>pdev->dev, "UCHE | Out of
> > > bounds access\n");
> > >
> > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > + a7xx_sw_fuse_violation_irq(gpu);
> > > +
> > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > msm_gpu_retire(gpu);
> > >
> > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > platform_device *pdev,
> > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > }
> > >
> > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > +{
> > > + struct adreno_gpu *adreno_gpu = _gpu->base;
> > > + struct msm_gpu *gpu = _gpu->base;
> > > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > > + u32 fuse_val;
> > > + int ret;
> > > +
> > > + if (adreno_is_a740(adreno_gpu)) {
> > > + /* R
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 15:46, Rob Clark wrote:
>
> On Thu, Apr 25, 2024 at 4:02 PM Dmitry Baryshkov
> wrote:
> >
> > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > >
> > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > currently don't support). On a750, this includes a new "fuse" register
> > > which can be used by qcom_scm to fuse off certain features like
> > > raytracing in software. The fuse is default off, and is initialized by
> > > calling the method. Afterwards we have to read it to find out which
> > > features were enabled.
> > >
> > > Signed-off-by: Connor Abbott
> > > ---
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > >
[...]
> > > + gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
> > > +
> > > + ret = qcom_scm_gpu_init_regs(gpu_req);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + /* On a750 raytracing may be disabled by the firmware, find out
> > > whether
> > > +* that's the case. The scm call above sets the fuse register.
> > > +*/
> > > + if (adreno_is_a750(adreno_gpu)) {
> > > + fuse_val = a6xx_llc_read(a6xx_gpu,
> > > REG_A7XX_CX_MISC_SW_FUSE_VALUE);
> >
> > This register isn't accessible with the current sm8650.dtsi. Since DT
> > and driver are going through different trees, please add safety guards
> > here, so that the driver doesn't crash if used with older dtsi
> > (not to mention that dts is considered to be an ABI and newer kernels
> > are supposed not to break with older DT files).
>
> I'd be happy if older kernels consistently worked with newer dtb, the
> other direction is too much to ask.
Well, we guarantee that newer kernels work with older dts.
> If necessary we can ask for ack
> to land the dts fix thru msm-next somehow, but since the gpu is newly
> enabled device landing in the same merge window I think that is not
> necessary.
This might work too.
--
With best wishes
Dmitry
Re: [PATCH 5/6] drm/msm: Add MSM_PARAM_RAYTRACING uapi
On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote: > > Expose the value of the software fuse to userspace. > > Signed-off-by: Connor Abbott > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ > include/uapi/drm/msm_drm.h | 1 + > 2 files changed, 4 insertions(+) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
>
> On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> initialize cx_mem. Copy this from downstream (minus BCL which we
> currently don't support). On a750, this includes a new "fuse" register
> which can be used by qcom_scm to fuse off certain features like
> raytracing in software. The fuse is default off, and is initialized by
> calling the method. Afterwards we have to read it to find out which
> features were enabled.
>
> Signed-off-by: Connor Abbott
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> 2 files changed, 90 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index cf0b1de1c071..fb2722574ae5 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -10,6 +10,7 @@
>
> #include
> #include
> +#include
> #include
> #include
>
> @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
>A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
>A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
>A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
>
> #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> A6XX_CP_APRIV_CNTL_RBFETCH | \
> @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
> kthread_queue_work(gpu->worker, >recover_work);
> }
>
> +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> +{
> + u32 status;
> +
> + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> +
> + dev_err_ratelimited(>pdev->dev, "SW fuse violation
> status=%8.8x\n", status);
> +
> + /* Ignore FASTBLEND violations, because the HW will silently fall back
> +* to legacy blending.
> +*/
> + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> + del_timer(>hangcheck_timer);
> +
> + kthread_queue_work(gpu->worker, >recover_work);
> + }
> +}
> +
> static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> {
> struct msm_drm_private *priv = gpu->dev->dev_private;
> @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> dev_err_ratelimited(>pdev->dev, "UCHE | Out of bounds
> access\n");
>
> + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> + a7xx_sw_fuse_violation_irq(gpu);
> +
> if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> msm_gpu_retire(gpu);
>
> @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> platform_device *pdev,
> a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> }
>
> +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> +{
> + struct adreno_gpu *adreno_gpu = _gpu->base;
> + struct msm_gpu *gpu = _gpu->base;
> + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> + u32 fuse_val;
> + int ret;
> +
> + if (adreno_is_a740(adreno_gpu)) {
> + /* Raytracing is always enabled on a740 */
> + adreno_gpu->has_ray_tracing = true;
> + }
> +
> + if (!qcom_scm_is_available()) {
> + /* Assume that if qcom scm isn't available, that whatever
> +* replacement allows writing the fuse register ourselves.
> +* Users of alternative firmware need to make sure this
> +* register is writeable or indicate that it's not somehow.
> +* Print a warning because if you mess this up you're about to
> +* crash horribly.
> +*/
> + if (adreno_is_a750(adreno_gpu)) {
> + dev_warn_once(gpu->dev->dev,
> + "SCM is not available, poking fuse
> register\n");
> + a6xx_llc_write(a6xx_gpu,
> REG_A7XX_CX_MISC_SW_FUSE_VALUE,
> + A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> + A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
> + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
> + adreno_gpu->has_ray_tracing = true;
> + }
> +
> + return 0;
> + }
> +
> + if (adreno_is_a750(adreno_gpu))
Most of the function is under the if (adreno_is_a750) conditions. Can
we invert the logic and add a single block of if(adreno_is_a750) and
then place all the code underneath?
> + gpu_req |=
Re: [PATCH 0/6] drm/msm: Support a750 "software fuse" for raytracing
On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote: > > On a750, Qualcomm decided to gate support for certain features behind a > "software fuse." This consists of a register in the cx_mem zone, which > is normally only writeable by the TrustZone firmware. On bootup it is > 0, and we must call an SCM method to initialize it. Then we communicate > its value to userspace. This implements all of this, copying the SCM > call from the downstream kernel and kgsl. > > So far the only optional feature we use is ray tracing (i.e. the > "ray_intersection" instruction) in a pending Mesa MR [1], so that's what > we expose to userspace. There's one extra patch to write some missing > registers, which depends on the register XML bump but is otherwise > unrelated, I just included it to make things easier on myself. > > The drm/msm part of this series depends on [2] to avoid conflicts. > > [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28447 > [2] > https://lore.kernel.org/all/20240324095222.ldnwumjkxk6uy...@hu-akhilpo-hyd.qualcomm.com/T/ > > Connor Abbott (6): > arm64: dts: qcom: sm8650: Fix GPU cx_mem size > firmware: qcom_scm: Add gpu_init_regs call I don't see patch 2 at all. Granted that patches 1 and 3-6 have different cc lists, might it be that it went to some blackhole? > drm/msm: Update a6xx registers > drm/msm/a7xx: Initialize a750 "software fuse" > drm/msm: Add MSM_PARAM_RAYTRACING uapi > drm/msm/a7xx: Add missing register writes from downstream -- With best wishes Dmitry
Re: [PATCH v5 09/18] drm/msm: import A6xx XML display registers database
On Wed, 24 Apr 2024 at 15:21, Connor Abbott wrote:
>
> On Mon, Apr 1, 2024 at 3:52 AM Dmitry Baryshkov
> wrote:
> >
> > Import Adreno registers database for A6xx from the Mesa, commit
> > 639488f924d9 ("freedreno/registers: limit the rules schema").
> >
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4970
> > +
> > drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 228 +
> > 2 files changed, 5198 insertions(+)
> >
>
> FYI, this will conflict with a series I will send out soon based on
> the register updates in [1]. Is there any chance to update this before
> it lands in msm-next?
I'd suggest updating the XML file as a part of your series. I've
already opened a MR for the display changes to be picked up by Rob.
> Best regards,
>
> Connor
>
> [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28883.
--
With best wishes
Dmitry
Re: [PATCH 2/2] drm/msm/dsi: Remove dsi_phy_write_[un]delay()
On Tue, Apr 23, 2024 at 12:37:00AM +0200, Konrad Dybcio wrote: > These are dummy wrappers that do literally nothing interesting. > Remove them. > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 -- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 81 > +++--- > 3 files changed, 54 insertions(+), 33 deletions(-) > Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH 1/2] drm/msm/dsi: Remove dsi_phy_read/write()
On Tue, Apr 23, 2024 at 12:36:59AM +0200, Konrad Dybcio wrote: > These are dummy wrappers that do literally nothing interesting. > Remove them. > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 - > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 273 +--- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 215 > drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 109 > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 224 - > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 205 +++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 320 > > 7 files changed, 645 insertions(+), 703 deletions(-) > Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH 2/3] drm/msm/mdp4: don't destroy mdp4_kms in mdp4_kms_init error path
On Mon, Apr 22, 2024 at 11:17:15AM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 7:33 PM, Dmitry Baryshkov wrote:
> > Since commit 3c74682637e6 ("drm/msm/mdp4: move resource allocation to
> > the _probe function") the mdp4_kms data is allocated during probe. It is
> > an error to destroy it during mdp4_kms_init(), as the data is still
> > referenced by the drivers's data and can be used later in case of probe
> > deferral.
> >
>
> mdp4_destroy() currently detaches mmu, calls msm_kms_destroy() which
> destroys pending timers and releases refcount on the aspace.
>
> It does not touch the mdp4_kms as that one is devm managed.
>
> In the comment
> https://patchwork.freedesktop.org/patch/590411/?series=132664=1#comment_1074306,
> we had discussed that the last component's reprobe attempt is affected
> (which is not dpu or mdp4 or mdp5 right? )
>
> If it was an interface (such as DSI OR DP), is it the aspace detach which is
> causing the crash?
I should have retained the trace log. I'll trigger the issue and post the trace.
>
> Another note is, mdp5 needs the same fix in that case.
>
> dpu_kms_init() looks fine.
>
> > Fixes: 3c74682637e6 ("drm/msm/mdp4: move resource allocation to the _probe
> > function")
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 28 +---
> > 1 file changed, 9 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
> > b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
> > index 4ba1cb74ad76..4c5f72b7e0e5 100644
> > --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
> > @@ -392,7 +392,7 @@ static int mdp4_kms_init(struct drm_device *dev)
> > ret = mdp_kms_init(_kms->base, _funcs);
> > if (ret) {
> > DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
> > - goto fail;
> > + return ret;
> > }
> > kms = priv->kms;
> > @@ -403,7 +403,7 @@ static int mdp4_kms_init(struct drm_device *dev)
> > ret = regulator_enable(mdp4_kms->vdd);
> > if (ret) {
> > DRM_DEV_ERROR(dev->dev, "failed to enable regulator
> > vdd: %d\n", ret);
> > - goto fail;
> > + return ret;
> > }
> > }
> > @@ -414,8 +414,7 @@ static int mdp4_kms_init(struct drm_device *dev)
> > if (major != 4) {
> > DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
> > major, minor);
> > - ret = -ENXIO;
> > - goto fail;
> > + return -ENXIO;
> > }
> > mdp4_kms->rev = minor;
> > @@ -423,8 +422,7 @@ static int mdp4_kms_init(struct drm_device *dev)
> > if (mdp4_kms->rev >= 2) {
> > if (!mdp4_kms->lut_clk) {
> > DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
> > - ret = -ENODEV;
> > - goto fail;
> > + return -ENODEV;
> > }
> > clk_set_rate(mdp4_kms->lut_clk, max_clk);
> > }
> > @@ -445,8 +443,7 @@ static int mdp4_kms_init(struct drm_device *dev)
> > mmu = msm_iommu_new(>dev, 0);
> > if (IS_ERR(mmu)) {
> > - ret = PTR_ERR(mmu);
> > - goto fail;
> > + return PTR_ERR(mmu);
> > } else if (!mmu) {
> > DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
> > "contig buffers for scanout\n");
> > @@ -458,8 +455,7 @@ static int mdp4_kms_init(struct drm_device *dev)
> > if (IS_ERR(aspace)) {
> > if (!IS_ERR(mmu))
> > mmu->funcs->destroy(mmu);
> > - ret = PTR_ERR(aspace);
> > - goto fail;
> > + return PTR_ERR(aspace);
> > }
> > kms->aspace = aspace;
> > @@ -468,7 +464,7 @@ static int mdp4_kms_init(struct drm_device *dev)
> > ret = modeset_init(mdp4_kms);
> > if (ret) {
> > DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
> > - goto fail;
> > + return ret;
> > }
> > mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC |
> > MSM_BO_SCANOUT);
> > @@ -476,14 +472,14 @@ static int mdp
Re: [PATCH 1/3] drm/msm: don't clean up priv->kms prematurely
On Mon, Apr 22, 2024 at 09:12:20AM -0700, Abhinav Kumar wrote: > > > On 4/21/2024 3:35 PM, Dmitry Baryshkov wrote: > > On Sat, Apr 20, 2024 at 04:02:00PM -0700, Abhinav Kumar wrote: > > > > > > > > > On 4/19/2024 7:33 PM, Dmitry Baryshkov wrote: > > > > MSM display drivers provide kms structure allocated during probe(). > > > > Don't clean up priv->kms field in case of an error. Otherwise probe > > > > functions might fail after KMS probe deferral. > > > > > > > > > > So just to understand this more, this will happen when master component > > > probe (dpu) succeeded but other sub-component probe (dsi) deferred? > > > > > > Because if master component probe itself deferred it will allocate > > > priv->kms > > > again isnt it and we will not even hit here. > > > > Master probing succeeds (so priv->kms is set), then kms_init fails at > > runtime, during binding of the master device. This results in probe > > deferral from the last component's component_add() function and reprobe > > attempt when possible (once the next device is added or probed). However > > as priv->kms is NULL, probe crashes. > > > > Got it, a better commit text would have helped here. Either way, I'll update the commit text with the text above. > > Reviewed-by: Abhinav Kumar -- With best wishes Dmitry
Re: [PATCH 1/3] drm/msm: don't clean up priv->kms prematurely
On Mon, Apr 22, 2024 at 10:23:18AM -0700, Abhinav Kumar wrote:
>
>
> On 4/21/2024 3:35 PM, Dmitry Baryshkov wrote:
> > On Sat, Apr 20, 2024 at 04:02:00PM -0700, Abhinav Kumar wrote:
> > >
> > >
> > > On 4/19/2024 7:33 PM, Dmitry Baryshkov wrote:
> > > > MSM display drivers provide kms structure allocated during probe().
> > > > Don't clean up priv->kms field in case of an error. Otherwise probe
> > > > functions might fail after KMS probe deferral.
> > > >
> > >
> > > So just to understand this more, this will happen when master component
> > > probe (dpu) succeeded but other sub-component probe (dsi) deferred?
> > >
> > > Because if master component probe itself deferred it will allocate
> > > priv->kms
> > > again isnt it and we will not even hit here.
> >
> > Master probing succeeds (so priv->kms is set), then kms_init fails at
> > runtime, during binding of the master device. This results in probe
> > deferral from the last component's component_add() function and reprobe
> > attempt when possible (once the next device is added or probed). However
> > as priv->kms is NULL, probe crashes.
> >
> > >
> > > > Fixes: a2ab5d5bb6b1 ("drm/msm: allow passing struct msm_kms to
> > > > msm_drv_probe()")
>
> Actually, Is this Fixes tag correct?
>
> OR is this one better
>
> Fixes: 506efcba3129 ("drm/msm: carve out KMS code from msm_drv.c")
No. The issue existed even before the carve-out.
>
>
> > > > Signed-off-by: Dmitry Baryshkov
> > > > ---
> > > >drivers/gpu/drm/msm/msm_kms.c | 1 -
> > > >1 file changed, 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/msm_kms.c
> > > > b/drivers/gpu/drm/msm/msm_kms.c
> > > > index af6a6fcb1173..6749f0fbca96 100644
> > > > --- a/drivers/gpu/drm/msm/msm_kms.c
> > > > +++ b/drivers/gpu/drm/msm/msm_kms.c
> > > > @@ -244,7 +244,6 @@ int msm_drm_kms_init(struct device *dev, const
> > > > struct drm_driver *drv)
> > > > ret = priv->kms_init(ddev);
> > > > if (ret) {
> > > > DRM_DEV_ERROR(dev, "failed to load kms\n");
> > > > - priv->kms = NULL;
> > > > return ret;
> > > > }
> > > >
> >
--
With best wishes
Dmitry
Re: [PATCH 1/2] drm/print: drop include debugfs.h and include where needed
On Mon, Apr 22, 2024 at 03:10:10PM +0300, Jani Nikula wrote: > Surprisingly many places depend on debugfs.h to be included via > drm_print.h. Fix them. > > v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe > > v2: Also fix ivpu and vmwgfx > > Reviewed-by: Andrzej Hajda > Acked-by: Maxime Ripard > Link: > https://patchwork.freedesktop.org/patch/msgid/20240410141434.157908-1-jani.nik...@intel.com > Signed-off-by: Jani Nikula > > --- > > Cc: Jacek Lawrynowicz > Cc: Stanislaw Gruszka > Cc: Oded Gabbay > Cc: Russell King > Cc: David Airlie > Cc: Daniel Vetter > Cc: Andrzej Hajda > Cc: Neil Armstrong > Cc: Robert Foss > Cc: Laurent Pinchart > Cc: Jonas Karlman > Cc: Jernej Skrabec > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Thomas Zimmermann > Cc: Jani Nikula > Cc: Rodrigo Vivi > Cc: Joonas Lahtinen > Cc: Tvrtko Ursulin > Cc: Frank Binns > Cc: Matt Coster > Cc: Rob Clark > Cc: Abhinav Kumar > Cc: Dmitry Baryshkov > Cc: Sean Paul > Cc: Marijn Suijten > Cc: Karol Herbst > Cc: Lyude Paul > Cc: Danilo Krummrich > Cc: Alex Deucher > Cc: "Christian König" > Cc: "Pan, Xinhui" > Cc: Alain Volmat > Cc: Huang Rui > Cc: Zack Rusin > Cc: Broadcom internal kernel review list > > Cc: Lucas De Marchi > Cc: "Thomas Hellström" > Cc: dri-de...@lists.freedesktop.org > Cc: intel-...@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org > Cc: linux-arm-...@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Cc: nouv...@lists.freedesktop.org > Cc: amd-...@lists.freedesktop.org > --- > drivers/accel/ivpu/ivpu_debugfs.c | 2 ++ > drivers/gpu/drm/armada/armada_debugfs.c | 1 + > drivers/gpu/drm/bridge/ite-it6505.c | 1 + > drivers/gpu/drm/bridge/panel.c | 2 ++ > drivers/gpu/drm/drm_print.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_dmc.c| 1 + > drivers/gpu/drm/imagination/pvr_fw_trace.c | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 ++ Acked-by: Dmitry Baryshkov # drm/msm > drivers/gpu/drm/nouveau/dispnv50/crc.c | 2 ++ > drivers/gpu/drm/radeon/r100.c | 1 + > drivers/gpu/drm/radeon/r300.c | 1 + > drivers/gpu/drm/radeon/r420.c | 1 + > drivers/gpu/drm/radeon/r600.c | 3 ++- > drivers/gpu/drm/radeon/radeon_fence.c | 1 + > drivers/gpu/drm/radeon/radeon_gem.c | 1 + > drivers/gpu/drm/radeon/radeon_ib.c | 2 ++ > drivers/gpu/drm/radeon/radeon_pm.c | 1 + > drivers/gpu/drm/radeon/radeon_ring.c| 2 ++ > drivers/gpu/drm/radeon/radeon_ttm.c | 1 + > drivers/gpu/drm/radeon/rs400.c | 1 + > drivers/gpu/drm/radeon/rv515.c | 1 + > drivers/gpu/drm/sti/sti_drv.c | 1 + > drivers/gpu/drm/ttm/ttm_device.c| 1 + > drivers/gpu/drm/ttm/ttm_resource.c | 3 ++- > drivers/gpu/drm/ttm/ttm_tt.c| 5 +++-- > drivers/gpu/drm/vc4/vc4_drv.h | 1 + > drivers/gpu/drm/vmwgfx/vmwgfx_gem.c | 2 ++ > drivers/gpu/drm/xe/xe_debugfs.c | 1 + > drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 ++ > drivers/gpu/drm/xe/xe_uc_debugfs.c | 2 ++ > include/drm/drm_print.h | 2 +- > 31 files changed, 46 insertions(+), 8 deletions(-) -- With best wishes Dmitry
Re: [PATCH 4/9] drm/msm/dpu: move dpu_format_populate_plane_sizes to atomic_check
On Fri, Apr 19, 2024 at 07:37:44PM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 6:34 PM, Dmitry Baryshkov wrote:
> > On Fri, Apr 19, 2024 at 05:14:01PM -0700, Abhinav Kumar wrote:
> > >
> > >
> > > On 3/19/2024 6:22 AM, Dmitry Baryshkov wrote:
> > > > Move a call to dpu_format_populate_plane_sizes() to the atomic_check
> > > > step, so that any issues with the FB layout can be reported as early as
> > > > possible.
> > > >
> > > > Signed-off-by: Dmitry Baryshkov
> > > > ---
> > > >drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 ++--
> > > >1 file changed, 6 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > > index d9631fe90228..a9de1fbd0df3 100644
> > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > > @@ -673,12 +673,6 @@ static int dpu_plane_prepare_fb(struct drm_plane
> > > > *plane,
> > > > }
> > > > }
> > > > - ret = dpu_format_populate_plane_sizes(new_state->fb,
> > > > >layout);
> > > > - if (ret) {
> > > > - DPU_ERROR_PLANE(pdpu, "failed to get format plane
> > > > sizes, %d\n", ret);
> > > > - return ret;
> > > > - }
> > > > -
> > > > /* validate framebuffer layout before commit */
> > > > ret = dpu_format_populate_addrs(pstate->aspace,
> > > > new_state->fb,
> > > > @@ -864,6 +858,12 @@ static int dpu_plane_atomic_check(struct drm_plane
> > > > *plane,
> > > > return -E2BIG;
> > > > }
> > > > + ret = dpu_format_populate_plane_sizes(new_plane_state->fb,
> > > > >layout);
> > > > + if (ret) {
> > > > + DPU_ERROR_PLANE(pdpu, "failed to get format plane
> > > > sizes, %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > >
> > > I think we need another function to do the check. It seems incorrect to
> > > populate the layout to the plane state knowing it can potentially fail.
> >
> > why? The state is interim object, which is subject to checks. In other
> > parts of the atomic_check we also fill parts of the state, perform
> > checks and then destroy it if the check fails.
> >
>
> Yes, the same thing you wrote.
>
> I felt we can perform the validation and reject it before populating it in
> the state as it seems thats doable here rather than populating it without
> knowing whether it can be discarded.
But populate function does the check. It seems like an overkill to add
another function. Also I still don't see the point. It was fine to call
this function from .prepare_fb, but it's not fine to call it from
.atomic_check?
>
> > Maybe I'm missing your point here. Could you please explain what is the
> > problem from your point of view?
> >
> > >
> > > Can we move the validation part of dpu_format_populate_plane_sizes() out
> > > to
> > > another helper dpu_format_validate_plane_sizes() and use that?
> > >
> > > And then make the remaining dpu_format_populate_plane_sizes() just a void
> > > API to fill the layout?
> >
--
With best wishes
Dmitry
Re: [PATCH 1/9] drm/msm/dpu: drop dpu_format_check_modified_format
On Fri, Apr 19, 2024 at 07:32:35PM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 6:26 PM, Dmitry Baryshkov wrote:
> > On Fri, Apr 19, 2024 at 04:43:20PM -0700, Abhinav Kumar wrote:
> > >
> > >
> > > On 3/19/2024 6:21 AM, Dmitry Baryshkov wrote:
> > > > The msm_kms_funcs::check_modified_format() callback is not used by the
> > > > driver. Drop it completely.
> > > >
> > > > Signed-off-by: Dmitry Baryshkov
> > > > ---
> > > >drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 45
> > > > -
> > > >drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 15 --
> > > >drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
> > > >drivers/gpu/drm/msm/msm_kms.h | 5
> > > >4 files changed, 66 deletions(-)
> > > >
> > >
> > > I think in this case, I am leaning towards completing the implementation
> > > rather than dropping it as usual.
> > >
> > > It seems its easier to just add the support to call this like the attached
> > > patch?
> >
> > Please don't attach patches to the email. It makes it impossible to
> > respond to them.
> >
>
> I attached it because it was too much to paste over here.
>
> Please review msm_framebuffer_init() in the downstream sources.
>
> The only missing piece I can see is the handling of DRM_MODE_FB_MODIFIERS
> flags.
I checked and I don't like this approach.
With the generic formats database in place, there should be no
driver-specific code that handles formats. Moreover, I think this should
be handled by the generic code in framebuffer_check() if msm driver
implements a proper get_format_info() callback. Please consider sending
a patch that does it. For now I can only consider the function in
question to be a dead code which should be dropped.
>
> I am unable to trace back why this support was not present.
>
> > Anyway, what are we missing with the current codebase? Why wasn't the
> > callback / function used in the first place?
> >
> > >
> > > WDYT?
> > >
> > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > > > index e366ab134249..ff0df478c958 100644
> > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > > > @@ -960,51 +960,6 @@ int dpu_format_populate_layout(
> > > > return ret;
> > > >}
> > > > -int dpu_format_check_modified_format(
> > > > - const struct msm_kms *kms,
> > > > - const struct msm_format *msm_fmt,
> > > > - const struct drm_mode_fb_cmd2 *cmd,
> > > > - struct drm_gem_object **bos)
> > > > -{
> > > > - const struct drm_format_info *info;
> > > > - const struct dpu_format *fmt;
> > > > - struct dpu_hw_fmt_layout layout;
> > > > - uint32_t bos_total_size = 0;
> > > > - int ret, i;
> > > > -
> > > > - if (!msm_fmt || !cmd || !bos) {
> > > > - DRM_ERROR("invalid arguments\n");
> > > > - return -EINVAL;
> > > > - }
> > > > -
> > > > - fmt = to_dpu_format(msm_fmt);
> > > > - info = drm_format_info(fmt->base.pixel_format);
> > > > - if (!info)
> > > > - return -EINVAL;
> > > > -
> > > > - ret = dpu_format_get_plane_sizes(fmt, cmd->width, cmd->height,
> > > > - , cmd->pitches);
> > > > - if (ret)
> > > > - return ret;
> > > > -
> > > > - for (i = 0; i < info->num_planes; i++) {
> > > > - if (!bos[i]) {
> > > > - DRM_ERROR("invalid handle for plane %d\n", i);
> > > > - return -EINVAL;
> > > > - }
> > > > - if ((i == 0) || (bos[i] != bos[0]))
> > > > - bos_total_size += bos[i]->size;
> > > > - }
> > > > -
> > > > - if (bos_total_size < layout.total_size) {
> > > > - DRM_ERROR("buffers total size too small %u expected
> > > > %u\n",
> > > > -
Re: [PATCH 1/3] drm/msm: don't clean up priv->kms prematurely
On Sat, Apr 20, 2024 at 04:02:00PM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 7:33 PM, Dmitry Baryshkov wrote:
> > MSM display drivers provide kms structure allocated during probe().
> > Don't clean up priv->kms field in case of an error. Otherwise probe
> > functions might fail after KMS probe deferral.
> >
>
> So just to understand this more, this will happen when master component
> probe (dpu) succeeded but other sub-component probe (dsi) deferred?
>
> Because if master component probe itself deferred it will allocate priv->kms
> again isnt it and we will not even hit here.
Master probing succeeds (so priv->kms is set), then kms_init fails at
runtime, during binding of the master device. This results in probe
deferral from the last component's component_add() function and reprobe
attempt when possible (once the next device is added or probed). However
as priv->kms is NULL, probe crashes.
>
> > Fixes: a2ab5d5bb6b1 ("drm/msm: allow passing struct msm_kms to
> > msm_drv_probe()")
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > drivers/gpu/drm/msm/msm_kms.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
> > index af6a6fcb1173..6749f0fbca96 100644
> > --- a/drivers/gpu/drm/msm/msm_kms.c
> > +++ b/drivers/gpu/drm/msm/msm_kms.c
> > @@ -244,7 +244,6 @@ int msm_drm_kms_init(struct device *dev, const struct
> > drm_driver *drv)
> > ret = priv->kms_init(ddev);
> > if (ret) {
> > DRM_DEV_ERROR(dev, "failed to load kms\n");
> > - priv->kms = NULL;
> > return ret;
> > }
> >
--
With best wishes
Dmitry
[PATCH v2 9/9] drm/msm: drop msm_kms_funcs::get_format() callback
Now as all subdrivers were converted to use common database of formats,
drop the get_format() callback and use mdp_get_format() directly.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c| 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 -
drivers/gpu/drm/msm/msm_fb.c | 2 +-
drivers/gpu/drm/msm/msm_kms.h| 4
8 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b966c44ec835..ef69c2f408c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -274,7 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, , _params);
- fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base, fmt_fourcc,
0);
+ fmt = mdp_get_format(_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
if (phys_enc->hw_cdm)
@@ -414,7 +414,7 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
ctl = phys_enc->hw_ctl;
fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
- fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base, fmt_fourcc,
0);
+ fmt = mdp_get_format(_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index de17bcbb8492..d3ea91c1d7d2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -326,8 +326,7 @@ static void dpu_encoder_phys_wb_setup(
wb_job = wb_enc->wb_job;
format = msm_framebuffer_format(wb_enc->wb_job->fb);
- dpu_fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base,
-
format->pixel_format, wb_job->fb->modifier);
+ dpu_fmt = mdp_get_format(_enc->dpu_kms->base,
format->pixel_format, wb_job->fb->modifier);
DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
hw_wb->idx - WB_0, mode.name,
@@ -577,7 +576,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct
dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base,
+ wb_cfg->dest.format = mdp_get_format(_enc->dpu_kms->base,
format->pixel_format,
job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index cb30137443e8..1955848b1b78 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -982,7 +982,6 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .get_format = mdp_get_format,
.destroy = dpu_kms_destroy,
.snapshot= dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b92a13cc9b36..1c3a2657450c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -627,7 +627,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
- fmt = priv->kms->funcs->get_format(priv->kms, DRM_FORMAT_ABGR, 0);
+ fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR, 0);
/* should not happen ever */
if (!fmt)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 4ba1cb74ad76..6e4e74f9d63d 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -151,7 +151,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.flush_commit= mdp4_flush_c
[PATCH v2 5/9] drm/msm: merge dpu_format and mdp_format in struct msm_format
Structures dpu_format and mdp_format are largely the same structures.
In order to remove duplication between format databases, merge these two
stucture definitions into the global struct msm_format.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 184 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h| 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 41 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 30 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h| 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c| 14 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 18 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 74 -
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 26 +--
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 54 +++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ++--
drivers/gpu/drm/msm/disp/mdp_format.h | 28
drivers/gpu/drm/msm/disp/mdp_kms.h | 13 --
28 files changed, 296 insertions(+), 305 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 88c2e51ab166..9f2164782844 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -320,7 +320,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc
*crtc,
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate, struct dpu_format *format)
+ struct dpu_plane_state *pstate, const struct msm_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
uint32_t blend_op;
@@ -363,7 +363,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer
*mixer,
fg_alpha, bg_alpha, blend_op);
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
- >base.pixel_format, format->alpha_enable, blend_op);
+ >pixel_format, format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -395,7 +395,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc
*crtc,
struct dpu_crtc_mixer *mixer,
u32 num_mixers,
enum dpu_stage stage,
- struct dpu_format *format,
+ const struct msm_format *format,
uint64_t modifier,
struct dpu_sw_pipe *pipe,
unsigned int stage_idx,
@@ -412,7 +412,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc
*crtc,
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, to_dpu_plane_state(state), stage_idx,
- format->base.pixel_format,
+ format->pixel_format,
modifier);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d
multirect_idx %d\n",
@@ -440,7 +440,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
- struct dpu_format *format;
+ const struct msm_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
uint32_t lm_idx;
@@ -459,7 +459,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
+ format = msm_framebuffer_format(pstate->base.fb);
if
[PATCH v2 8/9] drm/msm: merge dpu format database to MDP formats
Finally remove duplication between DPU and generic MDP code by merging
DPU format lists to the MDP format database.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 7 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 602
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h| 23 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 10 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 614 ++---
drivers/gpu/drm/msm/disp/mdp_format.h | 10 +
drivers/gpu/drm/msm/disp/mdp_kms.h | 2 -
drivers/gpu/drm/msm/msm_drv.h | 2 +
11 files changed, 571 insertions(+), 708 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index deb2f6b446d3..b966c44ec835 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -274,7 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, , _params);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base, fmt_fourcc,
0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
if (phys_enc->hw_cdm)
@@ -414,7 +414,7 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
ctl = phys_enc->hw_ctl;
fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base, fmt_fourcc,
0);
DPU_DEBUG_VIDENC(phys_enc, "\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 8b5a4a1c239e..de17bcbb8492 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -326,7 +326,8 @@ static void dpu_encoder_phys_wb_setup(
wb_job = wb_enc->wb_job;
format = msm_framebuffer_format(wb_enc->wb_job->fb);
- dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format,
wb_job->fb->modifier);
+ dpu_fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base,
+
format->pixel_format, wb_job->fb->modifier);
DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
hw_wb->idx - WB_0, mode.name,
@@ -576,8 +577,8 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct
dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format = dpu_get_dpu_format_ext(
- format->pixel_format, job->fb->modifier);
+ wb_cfg->dest.format =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base,
+format->pixel_format,
job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
DPU_ERROR("failed to get format %p4cc\n",
>pixel_format);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 2bb1584920c6..6b1e9a617da3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -11,186 +11,11 @@
#include "dpu_kms.h"
#include "dpu_formats.h"
-#define DPU_UBWC_META_MACRO_W_H16
-#define DPU_UBWC_META_BLOCK_SIZE 256
#define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096
-#define DPU_TILE_HEIGHT_DEFAULT1
-#define DPU_TILE_HEIGHT_TILED 4
-#define DPU_TILE_HEIGHT_UBWC 4
-#define DPU_TILE_HEIGHT_NV12 8
-
#define DPU_MAX_IMG_WIDTH 0x3FFF
#define DPU_MAX_IMG_HEIGHT 0x3FFF
-/*
- * DPU supported format packing, bpp, and other format
- * information.
- * DPU currently only supports interleaved RGB formats
- * UBWC support for a pixel format is indicated by the flag,
- * there is additional meta data plane for such formats
- */
-
-#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
-bp, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha,
[PATCH v2 7/9] drm/msm: convert msm_format::unpack_align_msb to the flag
Instead of having a u8 or bool field unpack_align_msb, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 12 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +- drivers/gpu/drm/msm/disp/mdp_format.h | 4 ++-- 4 files changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 705b91582b0f..2bb1584920c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -43,7 +43,6 @@ bp, flg, fm, np) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ - .unpack_align_msb = 0,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ @@ -64,7 +63,6 @@ alpha, bp, flg, fm, np, th) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ - .unpack_align_msb = 0,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ @@ -86,7 +84,6 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 0,\ .unpack_count = count,\ .bpp = bp,\ .fetch_mode = fm, \ @@ -106,7 +103,6 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 0,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ @@ -127,7 +123,6 @@ flg, fm, np, th) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 0,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ @@ -147,11 +142,10 @@ flg, fm, np, th) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 1,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -168,11 +162,10 @@ flg, fm, np, th) \ .bpc_r_cr = r
[PATCH v2 6/9] drm/msm: convert msm_format::unpack_tight to the flag
Instead of having a u8 or bool field unpack_tight, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 22 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 +- drivers/gpu/drm/msm/disp/mdp_format.c | 52 ++--- drivers/gpu/drm/msm/disp/mdp_format.h | 4 +-- 7 files changed, 41 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 855f0d29c387..705b91582b0f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -44,11 +44,10 @@ bp, flg, fm, np) \ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -66,11 +65,10 @@ alpha, bp, flg, fm, np, th) \ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = th \ } @@ -89,11 +87,10 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_a = a, \ .chroma_sample = chroma, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = count,\ .bpp = bp,\ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -110,11 +107,10 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_a = a, \ .chroma_sample = chroma, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -132,11 +128,10 @@ flg, fm, np, th) \ .bpc_a = a, \ .chroma_sample = chroma, \ .unpack_align_msb = 0
[PATCH v2 4/9] drm/msm/dpu: pull format flag definitions to mdp_format.h
In preparation to merger of formats databases, pull format flag definitions to mdp_format.h header, so that they are visibile to both dpu and mdp drivers. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 31 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 8 +-- drivers/gpu/drm/msm/disp/mdp_format.c | 6 +- drivers/gpu/drm/msm/disp/mdp_format.h | 39 drivers/gpu/drm/msm/disp/mdp_kms.h | 4 +- drivers/gpu/drm/msm/msm_drv.h | 4 -- 9 files changed, 109 insertions(+), 89 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index caf536788ece..0c2afded0e56 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -44,8 +44,8 @@ bp, flg, fm, np) \ .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -63,8 +63,8 @@ alpha, bp, flg, fm, np, th) \ .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = th \ } @@ -83,8 +83,8 @@ alpha, chroma, count, bp, flg, fm, np) \ .unpack_tight = 1,\ .unpack_count = count,\ .bpp = bp,\ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -101,8 +101,8 @@ alpha, chroma, count, bp, flg, fm, np) \ .unpack_tight = 1,\ .unpack_count = 2,\ .bpp = 2, \ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -120,8 +120,8 @@ flg, fm, np, th) \ .unpack_tight = 1,\ .unpack_count = 2,\ .bpp = 2, \ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = th \ } @@ -138,8 +138,8 @@ flg, fm, np, th
[PATCH v2 3/9] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field
Using bitmap for the flags results in a clumsy syntax on test_bit,
replace it with unsigned long type and simple binary ops.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 18 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 16 +++-
2 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 87fa14fc5dd0..caf536788ece 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -45,7 +45,7 @@ bp, flg, fm, np)
\
.unpack_count = uc, \
.bpp = bp,\
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -64,7 +64,7 @@ alpha, bp, flg, fm, np, th)
\
.unpack_count = uc, \
.bpp = bp,\
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -84,7 +84,7 @@ alpha, chroma, count, bp, flg, fm, np)
\
.unpack_count = count,\
.bpp = bp,\
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -102,7 +102,7 @@ alpha, chroma, count, bp, flg, fm, np)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -121,7 +121,7 @@ flg, fm, np, th)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -139,7 +139,7 @@ flg, fm, np, th)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -158,7 +158,7 @@ flg, fm, np, th)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th
[PATCH v2 2/9] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
MDP4 and MDP5 drivers enumerate supported formats each time the plane is
created. In preparation to merger of MDP DPU format databases, define
precise formats list, so that changes to the database do not cause the
driver to add unsupported format to the list.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 +++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 ++-
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ---
drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
4 files changed, 80 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index b689b618da78..cebe20c82a54 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -371,6 +371,47 @@ static const uint64_t supported_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+const uint32_t mdp4_rgb_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+};
+
+const uint32_t mdp4_rgb_yuv_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
enum mdp4_pipe pipe_id, bool private_plane)
@@ -379,6 +420,8 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
struct mdp4_plane *mdp4_plane;
int ret;
enum drm_plane_type type;
+ const uint32_t *formats;
+ unsigned int nformats;
mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
if (!mdp4_plane) {
@@ -392,13 +435,17 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
mdp4_plane->name = pipe_names[pipe_id];
mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
- mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
- ARRAY_SIZE(mdp4_plane->formats),
- !pipe_supports_yuv(mdp4_plane->caps));
-
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
+
+ if (pipe_supports_yuv(mdp4_plane->caps)) {
+ formats = mdp4_rgb_yuv_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
+ } else {
+ formats = mdp4_rgb_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_formats);
+ }
ret = drm_universal_plane_init(dev, plane, 0xff, _plane_funcs,
-mdp4_plane->formats, mdp4_plane->nformats,
+formats, nformats,
supported_format_modifiers, type, NULL);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 0d5ff03cb091..aa8342d93393 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -17,9 +17,6 @@
struct mdp5_plane {
struct drm_plane base;
-
- uint32_t nformats;
- uint32_t formats[32];
};
#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
@@ -1007,6 +1004,32 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
return mask;
}
+const uint32_t mdp5_plane_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp5_plane_init(struct drm_device *dev,
enum drm_plane_type type)
@@ -1023,12 +1046,9 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
[PATCH v2 1/9] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
Instead of having DPU-specific defines, switch to the definitions from
the mdp_common.xml.h file. This is the preparation for merged of DPU and
MDP format tables.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 290 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 64 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
8 files changed, 169 insertions(+), 219 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index aa1e68379d9f..43431cb55421 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2223,19 +2223,19 @@ void dpu_encoder_helper_phys_setup_cdm(struct
dpu_encoder_phys *phys_enc,
/* enable 10 bit logic */
switch (cdm_cfg->output_fmt->chroma_sample) {
- case DPU_CHROMA_RGB:
+ case CHROMA_FULL:
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
- case DPU_CHROMA_H2V1:
+ case CHROMA_H2V1:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
- case DPU_CHROMA_420:
+ case CHROMA_420:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
break;
- case DPU_CHROMA_H1V2:
+ case CHROMA_H1V2:
default:
DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
DRMID(phys_enc->parent));
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 9dbb8ddcddec..ff41493147ab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -594,7 +594,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct
dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
- if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
+ if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 95e6e58b1a21..87fa14fc5dd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -35,11 +35,11 @@
bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED,\
+ .fetch_planes = MDP_PLANE_INTERLEAVED,\
.alpha_enable = alpha,\
.element = { (e0), (e1), (e2), (e3) },\
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0,\
.unpack_tight = 1,\
.unpack_count = uc, \
@@ -54,11 +54,11 @@ bp, flg, fm, np)
\
alpha, bp, flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED,\
+ .fetch_planes = MDP_PLANE_INTERLEAVED,\
.alpha_enable = alpha,\
.element = { (e0), (e1), (e2), (e3) },\
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
[PATCH v2 0/9] drm/msm: fold dpu_format into mdp_formats database
During the review of [1] Abhinav pointed out that mdp_rgb_formats and mdp_rgb_yuv_formats arrays from patch 1 are directly based on the struct mdp_format formats array. This was true, because MDP4 / MDP5 drivers used their own (small) list of supported formats. The DPU driver, supporting more formats, had larger database of the formats and their properties. While we don't have plans to expand MDP5 formats support, it make sense to merge these two databases into a common dataset. [1] https://patchwork.freedesktop.org/series/120377/ -- Changes in v2: - Rebased on top of msm-next - Moved all formats data to the new header mdp_formats.h (Abhinav) - Dropped the alpha_enable flag changes (Abhinav) - Link to v1: https://lore.kernel.org/r/20231202214016.1257621-1-dmitry.barysh...@linaro.org --- Dmitry Baryshkov (9): drm/msm/dpu: use format-related definitions from mdp_common.xml.h drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware drm/msm/dpu: in dpu_format replace bitmap with unsigned long field drm/msm/dpu: pull format flag definitions to mdp_format.h drm/msm: merge dpu_format and mdp_format in struct msm_format drm/msm: convert msm_format::unpack_tight to the flag drm/msm: convert msm_format::unpack_align_msb to the flag drm/msm: merge dpu format database to MDP formats drm/msm: drop msm_kms_funcs::get_format() callback drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 20 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 658 + drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h| 27 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 124 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 40 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h| 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c| 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h| 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 22 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 75 +-- drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 - drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 86 ++- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 - drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 95 +-- drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +- drivers/gpu/drm/msm/disp/mdp_format.c | 630 +--- drivers/gpu/drm/msm/disp/mdp_format.h | 77 +++ drivers/gpu/drm/msm/disp/mdp_kms.h | 18 +- drivers/gpu/drm/msm/msm_drv.h | 4 +- drivers/gpu/drm/msm/msm_fb.c | 2 +- drivers/gpu/drm/msm/msm_kms.h | 4 - 34 files changed, 913 insertions(+), 1075 deletions(-) --- base-commit: a35e92ef04c07bd473404b9b73d489aea19a60a8 change-id: 20240420-dpu-format-d655c60875df Best regards, -- Dmitry Baryshkov
Re: [PATCH 9/9] drm/msm/dpu: sync mode_config limits to the FB limits in dpu_plane.c
On Sat, 20 Apr 2024 at 06:05, Abhinav Kumar wrote: > > > > On 3/19/2024 6:22 AM, Dmitry Baryshkov wrote: > > Lift mode_config limits set by the DPU driver to the actual FB limits as > > handled by the dpu_plane.c. > > > > Signed-off-by: Dmitry Baryshkov > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 ++--- > > 1 file changed, 2 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > > index 7257ac4020d8..e7dda9eca466 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > > @@ -1136,13 +1136,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) > > dev->mode_config.min_width = 0; > > dev->mode_config.min_height = 0; > > > > - /* > > - * max crtc width is equal to the max mixer width * 2 and max height > > is > > - * is 4K > > - */ > > - dev->mode_config.max_width = > > - dpu_kms->catalog->caps->max_mixer_width * 2; > > - dev->mode_config.max_height = 4096; > > + dev->mode_config.max_width = DPU_MAX_IMG_WIDTH; > > + dev->mode_config.max_height = DPU_MAX_IMG_HEIGHT; > > > > Can you please explain a little more about why the previous limits did > not work in the multi-monitor case? > > We support at the most using 2 LMs per display today. Quad pipe support > is not there yet. So by bounding to 2 * mixer_width should have been > same as rejecting the mixer width in atomic_check. This is the framebuffer limit, not a CRTC size limit. > > > dev->max_vblank_count = 0x; > > /* Disable vblank irqs aggressively for power-saving */ > > -- With best wishes Dmitry
[PATCH 2/3] drm/msm/mdp4: don't destroy mdp4_kms in mdp4_kms_init error path
Since commit 3c74682637e6 ("drm/msm/mdp4: move resource allocation to
the _probe function") the mdp4_kms data is allocated during probe. It is
an error to destroy it during mdp4_kms_init(), as the data is still
referenced by the drivers's data and can be used later in case of probe
deferral.
Fixes: 3c74682637e6 ("drm/msm/mdp4: move resource allocation to the _probe
function")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 4ba1cb74ad76..4c5f72b7e0e5 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -392,7 +392,7 @@ static int mdp4_kms_init(struct drm_device *dev)
ret = mdp_kms_init(_kms->base, _funcs);
if (ret) {
DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
- goto fail;
+ return ret;
}
kms = priv->kms;
@@ -403,7 +403,7 @@ static int mdp4_kms_init(struct drm_device *dev)
ret = regulator_enable(mdp4_kms->vdd);
if (ret) {
DRM_DEV_ERROR(dev->dev, "failed to enable regulator
vdd: %d\n", ret);
- goto fail;
+ return ret;
}
}
@@ -414,8 +414,7 @@ static int mdp4_kms_init(struct drm_device *dev)
if (major != 4) {
DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
major, minor);
- ret = -ENXIO;
- goto fail;
+ return -ENXIO;
}
mdp4_kms->rev = minor;
@@ -423,8 +422,7 @@ static int mdp4_kms_init(struct drm_device *dev)
if (mdp4_kms->rev >= 2) {
if (!mdp4_kms->lut_clk) {
DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
- ret = -ENODEV;
- goto fail;
+ return -ENODEV;
}
clk_set_rate(mdp4_kms->lut_clk, max_clk);
}
@@ -445,8 +443,7 @@ static int mdp4_kms_init(struct drm_device *dev)
mmu = msm_iommu_new(>dev, 0);
if (IS_ERR(mmu)) {
- ret = PTR_ERR(mmu);
- goto fail;
+ return PTR_ERR(mmu);
} else if (!mmu) {
DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
"contig buffers for scanout\n");
@@ -458,8 +455,7 @@ static int mdp4_kms_init(struct drm_device *dev)
if (IS_ERR(aspace)) {
if (!IS_ERR(mmu))
mmu->funcs->destroy(mmu);
- ret = PTR_ERR(aspace);
- goto fail;
+ return PTR_ERR(aspace);
}
kms->aspace = aspace;
@@ -468,7 +464,7 @@ static int mdp4_kms_init(struct drm_device *dev)
ret = modeset_init(mdp4_kms);
if (ret) {
DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
- goto fail;
+ return ret;
}
mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC |
MSM_BO_SCANOUT);
@@ -476,14 +472,14 @@ static int mdp4_kms_init(struct drm_device *dev)
ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo:
%d\n", ret);
mdp4_kms->blank_cursor_bo = NULL;
- goto fail;
+ return ret;
}
ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
_kms->blank_cursor_iova);
if (ret) {
DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n",
ret);
- goto fail;
+ return ret;
}
dev->mode_config.min_width = 0;
@@ -492,12 +488,6 @@ static int mdp4_kms_init(struct drm_device *dev)
dev->mode_config.max_height = 2048;
return 0;
-
-fail:
- if (kms)
- mdp4_destroy(kms);
-
- return ret;
}
static const struct dev_pm_ops mdp4_pm_ops = {
--
2.39.2
[PATCH 1/3] drm/msm: don't clean up priv->kms prematurely
MSM display drivers provide kms structure allocated during probe().
Don't clean up priv->kms field in case of an error. Otherwise probe
functions might fail after KMS probe deferral.
Fixes: a2ab5d5bb6b1 ("drm/msm: allow passing struct msm_kms to msm_drv_probe()")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_kms.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
index af6a6fcb1173..6749f0fbca96 100644
--- a/drivers/gpu/drm/msm/msm_kms.c
+++ b/drivers/gpu/drm/msm/msm_kms.c
@@ -244,7 +244,6 @@ int msm_drm_kms_init(struct device *dev, const struct
drm_driver *drv)
ret = priv->kms_init(ddev);
if (ret) {
DRM_DEV_ERROR(dev, "failed to load kms\n");
- priv->kms = NULL;
return ret;
}
--
2.39.2
