Re: [Freedreno] [PATCH v2 2/4] arm64: dts: qcom: sc7280: Add support for eDP panel on CRD
On Tue, Feb 08, 2022 at 08:48:43PM +0530, Sankeerth Billakanti wrote:
> Enable the eDP display panel support without HPD on sc7280 platform.
>
> Signed-off-by: Sankeerth Billakanti
> ---
>
> Changes in v2:
> - sort node references alphabetically
> - improve readability
> - move the pwm pinctrl to pwm node
> - move the regulators to root
> - define backlight power
> - remove dummy regulator node
> - cleanup pinctrl definitions
>
> arch/arm64/boot/dts/qcom/sc7280-crd.dts | 122
>
> arch/arm64/boot/dts/qcom/sc7280.dtsi| 2 -
> 2 files changed, 122 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts
> b/arch/arm64/boot/dts/qcom/sc7280-crd.dts
> index e2efbdd..bff2707 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts
> @@ -21,6 +21,34 @@
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + backlight_power: backlight-power {
nit: the other fixed regulator in sc7280-idp.dtsi is called
'nvme_3v3_regulator', if you wanted to be consistent you
could call this backlight_3v3_regulator.
> + compatible = "regulator-fixed";
> + regulator-name = "backlight_power";
> +
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> +
> + gpio = <_gpios 7 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_bl_power>;
> + };
> +
> + edp_power: edp-power {
nit: see above
> + compatible = "regulator-fixed";
> + regulator-name = "edp_power";
> +
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> +
> + gpio = < 80 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_panel_power>;
> + };
> };
>
> _rsc {
> @@ -76,6 +104,42 @@ ap_ts_pen_1v8: {
> };
> };
>
> +_out {
> + remote-endpoint = <_panel_in>;
> +};
> +
> + {
> + status = "okay";
> +};
> +
> +_edp {
> + status = "okay";
> +
> + vdda-1p2-supply = <_l6b_1p2>;
> + vdda-0p9-supply = <_l10c_0p8>;
> +};
> +
> +_edp_phy {
> + status = "okay";
> +
> + vdda-1p2-supply = <_l6b_1p2>;
> + vdda-0p9-supply = <_l10c_0p8>;
> +};
> +
> +_dp {
should be before 'mdss_edp'.
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_hot_plug_det>;
> + data-lanes = <0 1>;
> + vdda-1p2-supply = <_l6b_1p2>;
> + vdda-0p9-supply = <_l1b_0p8>;
> +};
> +
> +_mdp {
> + status = "okay";
> +};
> +
> _3v3_regulator {
> gpio = < 51 GPIO_ACTIVE_HIGH>;
> };
> @@ -84,7 +148,65 @@ ap_ts_pen_1v8: {
> pins = "gpio51";
> };
>
> +_pwm {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_bl_pwm>;
> +};
> +
> +_gpios {
should be before 'pm8350c_pwm'
> + edp_bl_power: edp-bl-power {
> + pins = "gpio7";
> + function = "normal";
> + qcom,drive-strength = ;
> + bias-disable;
> + output-low;
> + };
> +
> + edp_bl_pwm: edp-bl-pwm {
> + pins = "gpio8";
> + function = "func1";
> + qcom,drive-strength = ;
> + bias-disable;
> + output-low;
> + };
> +};
> +
> + {
> + edp_backlight: edp-backlight {
> + compatible = "pwm-backlight";
> +
> + power-supply = <_power>;
> + pwms = <_pwm 3 65535>;
> + };
> +
> + edp_panel: edp_panel {
in difference to labels node names should use dashes as separator, not
underscores (i.e. 'edp-panel')
> + compatible = "sharp,lq140m1jw46";
> +
> + power-supply = <_power>;
> + backlight = <_backlight>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + edp_panel_in: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> + };
> + };
> +};
> +
> {
> + edp_panel_power: edp-panel-power {
> + pins = "gpio80";
> + function = "gpio";
> + bias-pull-down;
> + };
> +
> tp_int_odl: tp-int-odl {
> pins = "gpio7";
> function = "gpio";
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 3572399..f8fa716 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3012,8 +3012,6 @@
>
> mdss_edp: edp@aea {
> compatible = "qcom,sc7280-edp";
Re: [Freedreno] [PATCH v1 3/4] arm64: dts: qcom: sc7280: Add DSI display nodes
<3>;
> + required-opps =
> <_opp_svs>;
> + };
> +
> + opp-35800 {
> + opp-hz = /bits/ 64 <35800>;
> + required-opps =
> <_opp_svs_l1>;
> + };
> + };
> + };
> +
> + dsi_phy: dsi-phy@ae94400 {
> + compatible = "qcom,sc7280-dsi-phy-7nm";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x280>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
I'm not an expect, but this looks sane to me and it's very similar to the
SC7180 config.
Reviewed-by: Matthias Kaehlcke
Re: [Freedreno] [PATCH v1 4/4] arm64: dts: qcom: sc7280: add edp display dt nodes
On Wed, Aug 18, 2021 at 03:57:04PM +0530, Krishna Manikandan wrote:
> From: Sankeerth Billakanti
>
> Add edp controller and phy DT nodes for sc7280.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 127
> ++-
> 1 file changed, 126 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index aadf55d..5be318e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1412,7 +1412,7 @@
> reg = <0 0xaf0 0 0x2>;
> clocks = < RPMH_CXO_CLK>,
>< GCC_DISP_GPLL0_CLK_SRC>,
> - <0>, <0>, <0>, <0>, <0>, <0>;
> + <0>, <0>, <0>, <0>, <_phy 0>, <_phy 1>;
> clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
> "dsi0_phy_pll_out_byteclk",
> "dsi0_phy_pll_out_dsiclk",
> @@ -1493,6 +1493,12 @@
> remote-endpoint =
> <_in>;
> };
> };
> + port@1 {
> + reg = <1>;
> + dpu_intf5_out: endpoint {
> + remote-endpoint =
> <_in>;
> + };
> + };
> };
>
> mdp_opp_table: mdp-opp-table {
> @@ -1608,6 +1614,101 @@
>
> status = "disabled";
> };
> +
> + msm_edp: edp@aea {
> + status = "disabled";
> + compatible = "qcom,sc7280-edp";
> + reg = <0 0xaea 0 0x200>,
> + <0 0xaea0200 0 0x200>,
> + <0 0xaea0400 0 0xc00>,
> + <0 0xaea1000 0 0x400>;
> +
> + interrupt-parent = <>;
> + interrupts = <14 IRQ_TYPE_NONE>;
> +
> + clocks = < RPMH_CXO_CLK>,
> + < GCC_EDP_CLKREF_EN>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_EDP_AUX_CLK>,
> + < DISP_CC_MDSS_EDP_LINK_CLK>,
> + <
> DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
> + < DISP_CC_MDSS_EDP_PIXEL_CLK>;
> + clock-names = "core_xo", "core_ref",
> + "core_iface", "core_aux",
> "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + #clock-cells = <1>;
> + assigned-clocks = <
> DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
> + <
> DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <_phy 0>,
> <_phy 1>;
> +
> + phys = <_phy>;
> + phy-names = "dp";
> +
> + vdda-1p2-supply = <_l6b_1p2>;
> + vdda-0p9-supply = <_l10c_0p8>;
These regulators are defined in the board .dts (sc7280-idp.dts), hence the SoC
.dtsi shouldn't depend on them. My impression is that pm7325.dtsi and
pm8350c.dtsi
should include definitions for regulators that supply basic SoC blocks. If the
configuration can vary depending on the SoC there could be SoC specific includes
for each PMIC. If a board uses a different configuration it could overwrite the
PMIC .dtsi settings.
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_hot_plug_det>,
> <_panel_power_on>;
> +
> + panel-bklt-gpio = <_gpios 7
> GPIO_ACTIVE_HIGH>;
> + panel-pwm-gpio = <_gpios 8
> GPIO_ACTIVE_HIGH>;
The pins are board specific, hence they shouldn't be configured in the .dtsi of
the SoC.
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + edp_in: endpoint {
> +
Re: [Freedreno] [PATCH v1 2/2] dt-bindings: Add SC7280 compatible string
On Thu, Aug 12, 2021 at 05:38:02AM +0530, Sankeerth Billakanti wrote: > The Qualcomm SC7280 platform supports an eDP controller, add > compatible string for it to msm/binding. > > Signed-off-by: Sankeerth Billakanti > --- > Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index 64d8d9e..23b78ac 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -17,6 +17,9 @@ properties: >compatible: > enum: >- qcom,sc7180-dp > + - qcom,sc8180x-dp > + - qcom,sc8180x-edp > + - qcom,sc7280-edp This adds compatible strings for sc8180x and sc7280 (e)DP, however the commit message only mentions sc7280. So either the commit message needs and update or the sc8180x compatibles should be removed. The driver change (https://patchwork.kernel.org/project/linux-arm-msm/patch/1628726882-27841-2-git-send-email-sbill...@codeaurora.org/) adds some (currently unused) 'io_start' addresses which are hardcoded, I wonder if these should be in the device tree instead (and 'num_dp' too?), if they are needed at all.
Re: [Freedreno] [PATCH v1 1/2] drm/msm/dp: Add support for SC7280 eDP
On Thu, Aug 12, 2021 at 05:38:01AM +0530, Sankeerth Billakanti wrote:
> The eDP controller on SC7280 is similar to the eDP/DP controllers
> supported by the current driver implementation.
>
> SC7280 supports one EDP and one DP controller which can operate
> concurrently.
>
> The following are some required changes for the sc7280 sink:
> 1. Additional gpio configuration for backlight and pwm via pmic.
> 2. ASSR support programming on the sink.
> 3. SSC support programming on the sink.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 +++
> drivers/gpu/drm/msm/dp/dp_display.c| 32
> --
> drivers/gpu/drm/msm/dp/dp_parser.c | 31 +
> drivers/gpu/drm/msm/dp/dp_parser.h | 5
> 5 files changed, 87 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b131fd37..1096c44 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -856,9 +856,9 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
> };
>
> static const struct dpu_intf_cfg sc7280_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK,
> MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 1, 24, INTF_SC7280_MASK,
> MDP_SSPP_TOP0_INTR, 24, 25),
> INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK,
> MDP_SSPP_TOP0_INTR, 22, 23),
> + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, 0, 24, INTF_SC7280_MASK,
> MDP_SSPP_TOP0_INTR, 22, 23),
> };
>
> /*
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index d2569da..06d5a2d 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -1244,7 +1244,9 @@ static int dp_ctrl_link_train(struct dp_ctrl_private
> *ctrl,
> struct dp_cr_status *cr, int *training_step)
> {
> int ret = 0;
> + u8 *dpcd = ctrl->panel->dpcd;
> u8 encoding = DP_SET_ANSI_8B10B;
> + u8 ssc = 0, assr = 0;
> struct dp_link_info link_info = {0};
>
> dp_ctrl_config_ctrl(ctrl);
> @@ -1254,9 +1256,21 @@ static int dp_ctrl_link_train(struct dp_ctrl_private
> *ctrl,
> link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
>
> dp_aux_link_configure(ctrl->aux, _info);
> +
> + if (dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
> + ssc = DP_SPREAD_AMP_0_5;
> + drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, , 1);
> + }
> +
> drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
> , 1);
>
> + if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) {
> + assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
> + drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
> + , 1);
> + }
> +
> ret = dp_ctrl_link_train_1(ctrl, cr, training_step);
> if (ret) {
> DRM_ERROR("link training #1 failed. ret=%d\n", ret);
> @@ -1328,9 +1342,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct
> dp_ctrl_private *ctrl)
> struct dp_io *dp_io = >parser->io;
> struct phy *phy = dp_io->phy;
> struct phy_configure_opts_dp *opts_dp = _io->phy_opts.dp;
> + u8 *dpcd = ctrl->panel->dpcd;
>
> opts_dp->lanes = ctrl->link->link_params.num_lanes;
> opts_dp->link_rate = ctrl->link->link_params.rate / 100;
> + opts_dp->ssc = dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
> dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
> ctrl->link->link_params.rate * 1000);
>
> @@ -1760,6 +1776,9 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
> ctrl->link->link_params.num_lanes = ctrl->panel->link_info.num_lanes;
> ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
>
> + if (ctrl->dp_ctrl.pixel_rate == 0)
> + return -EINVAL;
> +
> DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
> ctrl->link->link_params.rate,
> ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index ee5bf64..a772290 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -117,8 +117,36 @@ struct dp_display_private {
> struct dp_audio *audio;
> };
>
> +struct msm_dp_config {
> + phys_addr_t io_start[3];
> + size_t num_dp;
> +};
> +
> +static const
Re: [Freedreno] [v1] drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume
On Mon, Mar 22, 2021 at 02:17:12AM -0700, Kalyan Thota wrote: > From: Kalyan Thota > > DPU runtime resume will request for a min vote on the AXI bus as > it is a necessary step before turning ON the AXI clock. > > The change does below > 1) Move the icc path set before requesting runtime get_sync. > 2) remove the dependency of hw catalog for min ib vote > as it is initialized at a later point. > > Signed-off-by: Kalyan Thota Confirmed that this fixes a bunch of warnings at boot on SC7180 when (out-of-tree) camera support is enabled: [1.832228] gcc_disp_hf_axi_clk status stuck at 'off' [2.118292] gcc_disp_hf_axi_clk status stuck at 'off' [2.442383] gcc_disp_hf_axi_clk already disabled [2.750054] gcc_disp_hf_axi_clk already unprepared [3.154835] gcc_disp_hf_axi_clk already disabled [3.421835] gcc_disp_hf_axi_clk already unprepared Tested-by: Matthias Kaehlcke ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 1/2] arm64: dts: qcom: sc7180: Add gpu cooling support
Hi,
On Thu, Oct 15, 2020 at 12:07:01AM +0530, man...@codeaurora.org wrote:
> On 2020-10-14 18:59, Akhil P Oommen wrote:
> > On 10/9/2020 10:27 PM, Matthias Kaehlcke wrote:
> > > On Fri, Oct 09, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
> > > > Hi,
> > > >
> > > > On Thu, Oct 8, 2020 at 10:10 AM Akhil P Oommen
> > > > wrote:
> > > > >
> > > > > Add cooling-cells property and the cooling maps for the gpu tzones
> > > > > to support GPU cooling.
> > > > >
> > > > > Signed-off-by: Akhil P Oommen
> > > > > ---
> > > > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 29
> > > > > ++---
> > > > > 1 file changed, 22 insertions(+), 7 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > > > > b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > > > > index d46b383..40d6a28 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > > > > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > > > > @@ -2,7 +2,7 @@
> > > > > /*
> > > > >* SC7180 SoC device tree source
> > > > >*
> > > > > - * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> > > > > + * Copyright (c) 2019-20, The Linux Foundation. All rights
> > > > > reserved.
> > > > >*/
> > > > >
> > > > > #include
> > > > > @@ -1885,6 +1885,7 @@
> > > > > iommus = <_smmu 0>;
> > > > > operating-points-v2 = <_opp_table>;
> > > > > qcom,gmu = <>;
> > > > > + #cooling-cells = <2>;
> > > >
> > > > Presumably we should add this to the devicetree bindings, too?
> > Yes, thanks for catching this. Will update in the next patch.
> >
> > > >
> > > >
> > > > > interconnects = <_noc
> > > > > MASTER_GFX3D _virt SLAVE_EBI1>;
> > > > > interconnect-names = "gfx-mem";
> > > > > @@ -3825,16 +3826,16 @@
> > > > > };
> > > > >
> > > > > gpuss0-thermal {
> > > > > - polling-delay-passive = <0>;
> > > > > + polling-delay-passive = <100>;
> > > >
> > > > Why did you make this change? I'm pretty sure that we _don't_ want
> > > > this since we're using interrupts for the thermal sensor. See commit
> > > > 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in
> > > > Thermal-zones node").
> > >
> > > I was going to ask the same, this shouldn't be needed.
> As per our understanding unlike "polling-delay", this delay property is
> intended to activate polling thread on post trip threshold violation and it
> is irrespective of sensor is capable for trip interrupt or not.
> This polling is more of governor related. Below are the few references from
> Documentation/code which tells polling-delay-passive is needed for IPA for
> better IPA performance.
>
> As per Power allocator documentations
>
> 1.
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/driver-api/thermal/power_allocator.rst?h=v5.4.71#n264
>
> "The power allocator governor's PID controller works best if there is a
> periodic tick. If you have a driver that calls
> `thermal_zone_device_update()` (or anything that ends up calling the
> governor's `throttle()` function) repetitively, the governor response
> won't be very good. Note that this is not particular to this
> governor, step-wise will also misbehave if you call its throttle()
> faster than the normal thermal framework tick (due to interrupts for
> example) as it will overreact"
>
> 2. In Power allocator code, when switch_on/control trip temp violation, it
> is enabling passive counter to activate passive polling @
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/thermal/power_allocator.c?h=v5.4.71#n634
>
> 3. while calculating derivative term, it is using passive_delay @
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/thermal/power_allocator.c?h=v5.4.71#n243
>
> 4. Sensor interrupt will work if te
Re: [Freedreno] [PATCH 1/2] arm64: dts: qcom: sc7180: Add gpu cooling support
On Fri, Oct 09, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
> Hi,
>
> On Thu, Oct 8, 2020 at 10:10 AM Akhil P Oommen wrote:
> >
> > Add cooling-cells property and the cooling maps for the gpu tzones
> > to support GPU cooling.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> > arch/arm64/boot/dts/qcom/sc7180.dtsi | 29 ++---
> > 1 file changed, 22 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > index d46b383..40d6a28 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > @@ -2,7 +2,7 @@
> > /*
> > * SC7180 SoC device tree source
> > *
> > - * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2019-20, The Linux Foundation. All rights reserved.
> > */
> >
> > #include
> > @@ -1885,6 +1885,7 @@
> > iommus = <_smmu 0>;
> > operating-points-v2 = <_opp_table>;
> > qcom,gmu = <>;
> > + #cooling-cells = <2>;
>
> Presumably we should add this to the devicetree bindings, too?
>
>
> > interconnects = <_noc MASTER_GFX3D _virt
> > SLAVE_EBI1>;
> > interconnect-names = "gfx-mem";
> > @@ -3825,16 +3826,16 @@
> > };
> >
> > gpuss0-thermal {
> > - polling-delay-passive = <0>;
> > + polling-delay-passive = <100>;
>
> Why did you make this change? I'm pretty sure that we _don't_ want
> this since we're using interrupts for the thermal sensor. See commit
> 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in
> Thermal-zones node").
I was going to ask the same, this shouldn't be needed.
> > polling-delay = <0>;
> >
> > thermal-sensors = < 13>;
> >
> > trips {
> > gpuss0_alert0: trip-point0 {
> > - temperature = <9>;
> > + temperature = <95000>;
> > hysteresis = <2000>;
> > - type = "hot";
> > + type = "passive";
>
> Matthias probably knows better, but I wonder if we should be making
> two passive trip levels like we do with CPU. IIRC this is important
> if someone wants to be able to use this with IPA.
Yes, please introduce a second trip point and make both of them
'passive'.
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Re: [Freedreno] [PATCH] drm: msm: a6xx: fix gpu failure after system resume
On Tue, Jul 14, 2020 at 06:55:30PM +0530, Akhil P Oommen wrote: > On targets where GMU is available, GMU takes over the ownership of GX GDSC > during its initialization. So, take a refcount on the GX PD on behalf of > GMU before we initialize it. This makes sure that nobody can collapse the > GX GDSC once GMU owns the GX GDSC. This patch fixes some weird failures > during GPU wake up during system resume. > > Signed-off-by: Akhil P Oommen I went through a few dozen suspend/resume cycles on SC7180 and didn't run into the kernel panic that typically occurs after a few iterations without this patch. Reported-by: Matthias Kaehlcke Tested-by: Matthias Kaehlcke On which tree is this patch based on? I had to apply it manually because 'git am' is unhappy when I try to apply it: error: sha1 information is lacking or useless (drivers/gpu/drm/msm/adreno/a6xx_gmu.c). error: could not build fake ancestor Both upstream and drm-msm are in my remotes and synced, so I suspect it's some private tree. Please make sure to base patches on the corresponding maintainer tree or upstream, whichs makes life easier for maintainers, testers and reviewers. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [v1] drm/msm/dpu: add support for clk and bw scaling for display
On Tue, Jul 14, 2020 at 04:39:47PM +0530, kalya...@codeaurora.org wrote: > On 2020-07-14 06:42, Matthias Kaehlcke wrote: > > On Thu, Jun 18, 2020 at 07:38:41PM +0530, Kalyan Thota wrote: > > > This change adds support to scale src clk and bandwidth as > > > per composition requirements. > > > > > > Interconnect registration for bw has been moved to mdp > > > device node from mdss to facilitate the scaling. > > > > > > Changes in v1: > > > - Address armv7 compilation issues with the patch (Rob) > > > > > > Signed-off-by: Kalyan Thota > > > > It seems this is an evolution of this series: > > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=265351 > > > > Are the DT bits of the series still valid? If so please include them in > > the > > series, otherwise please add DT patches to allow folks to test and > > review, > > and get them landed in Bjorn's tree after the driver changes have > > landed. > > Hi, > > Yes the patch is dependent on the DT changes, should i add them with depends > tag in the commit text ? > https://patchwork.kernel.org/patch/11470785/ > https://patchwork.kernel.org/patch/11470789/ This patch doesn't really depend on the DT changes. I would suggest to make this a series of 3 patches, just like the original series linked above. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [v1] drm/msm/dpu: add support for clk and bw scaling for display
On Thu, Jun 18, 2020 at 07:38:41PM +0530, Kalyan Thota wrote: > This change adds support to scale src clk and bandwidth as > per composition requirements. > > Interconnect registration for bw has been moved to mdp > device node from mdss to facilitate the scaling. > > Changes in v1: > - Address armv7 compilation issues with the patch (Rob) > > Signed-off-by: Kalyan Thota It seems this is an evolution of this series: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=265351 Are the DT bits of the series still valid? If so please include them in the series, otherwise please add DT patches to allow folks to test and review, and get them landed in Bjorn's tree after the driver changes have landed. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH] drm/msm: handle for EPROBE_DEFER for of_icc_get
On Wed, Jul 01, 2020 at 01:13:34PM -0400, Jonathan Marek wrote: > On 7/1/20 1:12 PM, Matthias Kaehlcke wrote: > > Hi Jonathan, > > > > On Tue, Jun 30, 2020 at 11:08:41PM -0400, Jonathan Marek wrote: > > > Check for EPROBE_DEFER instead of silently not using icc if the msm driver > > > probes before the interconnect driver. > > > > Agreed with supporting deferred ICC probing. > > > > > Only check for EPROBE_DEFER because of_icc_get can return other errors > > > that > > > we want to ignore (ENODATA). > > > > What would be the -ENODATA case? > > > > The of_icc_get for the ocmem_icc_path can return -ENODATA when the ocmem > path is not specified (it is optional and only relevant for a3xx/a4xx). Thanks for the clarification! In this case it seems reasonable to me to return any error for the 'gfx-mem' path and all errors except -ENODATA for 'ocmem'. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH] drm/msm: handle for EPROBE_DEFER for of_icc_get
Hi Jonathan, On Tue, Jun 30, 2020 at 11:08:41PM -0400, Jonathan Marek wrote: > Check for EPROBE_DEFER instead of silently not using icc if the msm driver > probes before the interconnect driver. Agreed with supporting deferred ICC probing. > Only check for EPROBE_DEFER because of_icc_get can return other errors that > we want to ignore (ENODATA). What would be the -ENODATA case? If the 'interconnects' property is not specified of_icc_get() returns NULL, shouldn't all (or most) errors be propagated rather than staying silent? Thanks Matthias ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v3 2/6] drm: msm: a6xx: send opp instead of a frequency
Hi,
On Thu, Jun 18, 2020 at 10:52:09AM -0700, Rob Clark wrote:
> On Fri, Jun 5, 2020 at 9:26 PM Sharat Masetty wrote:
> >
> > This patch changes the plumbing to send the devfreq recommended opp rather
> > than the frequency. Also consolidate and rearrange the code in a6xx to set
> > the GPU frequency and the icc vote in preparation for the upcoming
> > changes for GPU->DDR scaling votes.
> >
> > Signed-off-by: Sharat Masetty
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 62
> > +++
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +-
> > drivers/gpu/drm/msm/msm_gpu.c | 3 +-
> > drivers/gpu/drm/msm/msm_gpu.h | 3 +-
> > 4 files changed, 38 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > index 748cd37..2d8124b 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > @@ -100,17 +100,30 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
> > A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
> > }
> >
> > -static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
> > +void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
> > {
> > - struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
> > - struct adreno_gpu *adreno_gpu = _gpu->base;
> > - struct msm_gpu *gpu = _gpu->base;
> > - int ret;
> > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> > + struct a6xx_gmu *gmu = _gpu->gmu;
> > + u32 perf_index;
> > + unsigned long gpu_freq;
> > + int ret = 0;
> > +
> > + gpu_freq = dev_pm_opp_get_freq(opp);
> > +
> > + if (gpu_freq == gmu->freq)
> > + return;
> > +
> > + for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1;
> > perf_index++)
> > + if (gpu_freq == gmu->gpu_freqs[perf_index])
> > + break;
> > +
> > + gmu->current_perf_index = perf_index;
> >
> > gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
> >
> > gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
> > - ((3 & 0xf) << 28) | index);
> > + ((3 & 0xf) << 28) | perf_index);
> >
> > /*
> > * Send an invalid index as a vote for the bus bandwidth and let the
> > @@ -126,7 +139,7 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu,
> > int index)
> > if (ret)
> > dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
> >
> > - gmu->freq = gmu->gpu_freqs[index];
> > + gmu->freq = gmu->gpu_freqs[perf_index];
> >
> > /*
> > * Eventually we will want to scale the path vote with the
> > frequency but
> > @@ -135,25 +148,6 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu,
> > int index)
> > icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
> > }
> >
> > -void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq)
> > -{
> > - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> > - struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> > - struct a6xx_gmu *gmu = _gpu->gmu;
> > - u32 perf_index = 0;
> > -
> > - if (freq == gmu->freq)
> > - return;
> > -
> > - for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1;
> > perf_index++)
> > - if (freq == gmu->gpu_freqs[perf_index])
> > - break;
> > -
> > - gmu->current_perf_index = perf_index;
> > -
> > - __a6xx_gmu_set_freq(gmu, perf_index);
> > -}
>
> this does end up conflicting a bit with some of the newer stuff that
> landed this cycle, in particular "drm/msm/a6xx: HFI v2 for A640 and
> A650"
>
> Adding Jonathan on CC since I think he will want to test this on
> a650/a640 as well..
Sharat, please send an updated version that is rebased on the latest drm-msm.
Thanks
Matthias
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Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth
On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote: > This patches replaces the previously used static DDR vote and uses > dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling > GPU frequency. > > Signed-off-by: Sharat Masetty > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 2d8124b..79433d3 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct > dev_pm_opp *opp) > > gmu->freq = gmu->gpu_freqs[perf_index]; > > - /* > - * Eventually we will want to scale the path vote with the frequency but > - * for now leave it at max so that the performance is nominal. > - */ > - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); > + dev_pm_opp_set_bw(>pdev->dev, opp); Is there a particular reason to keep this one liner in a separate patch? I think it would make sense to squash it into "drm: msm: a6xx: send opp instead of a frequency" and change the subject of the combined patch to something like "drm: msm: a6xx: Scale the DDR bandwidth dynamically". ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 4/6] drm: msm: a6xx: send opp instead of a frequency
On Thu, May 14, 2020 at 05:39:57PM -0700, Matthias Kaehlcke wrote: > On Thu, May 14, 2020 at 04:24:17PM +0530, Sharat Masetty wrote: > > This patch changes the plumbing to send the devfreq recommended opp rather > > than the frequency. Also consolidate and rearrange the code in a6xx to set > > the GPU frequency and the icc vote in preparation for the upcoming > > changes for GPU->DDR scaling votes. > > Could this be relatively easily split in two patches, one passing the OPP > instead of the frequency, and another doing the consolidation? It typically > makes reviewing easier when logically unrelated changes are done in separate > patches. After looking at the "upcoming changes for GPU->DDR scaling votes", which is essentially one line I'm doubting if the splitting would actually make sense. I'm now rather inclined to see "drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth" squashed into this patch. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 4/6] drm: msm: a6xx: send opp instead of a frequency
On Thu, May 14, 2020 at 04:24:17PM +0530, Sharat Masetty wrote: > This patch changes the plumbing to send the devfreq recommended opp rather > than the frequency. Also consolidate and rearrange the code in a6xx to set > the GPU frequency and the icc vote in preparation for the upcoming > changes for GPU->DDR scaling votes. Could this be relatively easily split in two patches, one passing the OPP instead of the frequency, and another doing the consolidation? It typically makes reviewing easier when logically unrelated changes are done in separate patches. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 3/6] OPP: Add and export helper to set bandwidth
On Thu, May 14, 2020 at 04:24:16PM +0530, Sharat Masetty wrote: > From: Sibi Sankar > > Add and export 'dev_pm_opp_set_bw' to set the bandwidth > levels associated with an OPP for a given frequency. Wait, this looks very much like Sibi's patch from v4 of the "DDR/L3 Scaling support on SDM845 and SC7180 SoCs" series (https://patchwork.kernel.org/patch/11527571/). Please don't repost patches from other series (unless the series/patch was clearly abandonded, which isn't the case here). Instead mention the patch as a dependency. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 0/6] Add support for GPU DDR BW scaling
On Thu, May 14, 2020 at 04:24:13PM +0530, Sharat Masetty wrote: > Subject: [PATCH 0/6] Add support for GPU DDR BW scaling For anything but the first version the subject (for all patches) should include the version (i.e. [v2, 0/6], etc for this series). > This is a rework of my previous series [1], but this time based on the > bindings > from Georgi [2] + a few fixes which look to be fixed in v8 of Georgi's series > [3]. The work is based on the chromeOS tip. Chrome OS is irrelevant here, the series should be based on Linus' or one of the relevant maintainer trees (+ the patches it depends on). If it is actually based on the Chrome OS kernel tree (v5.4 I imagine) there will likely be conflicts which will make maintainers unhappy. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 2/6] arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp
On Thu, May 14, 2020 at 04:24:15PM +0530, Sharat Masetty wrote:
> Subject: arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp
nit: s/opp/OPPs/
>
> Add opp-peak-kBps bindings to the GPU opp table, listing the peak
> GPU -> DDR bandwidth requirement for each opp level. This will be
> used to scale the DDR bandwidth along with the GPU frequency dynamically.
>
> Signed-off-by: Sharat Masetty
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 0ce9921..89f7767 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1392,36 +1392,43 @@
> opp-8 {
> opp-hz = /bits/ 64 <8>;
> opp-level =
> ;
> + opp-peak-kBps = <8532000>;
> };
>
> opp-65000 {
> opp-hz = /bits/ 64 <65000>;
> opp-level =
> ;
> + opp-peak-kBps = <7216000>;
> };
>
> opp-56500 {
> opp-hz = /bits/ 64 <56500>;
> opp-level = ;
> + opp-peak-kBps = <5412000>;
> };
>
> opp-43000 {
> opp-hz = /bits/ 64 <43000>;
> opp-level =
> ;
> + opp-peak-kBps = <5412000>;
I suppose it's intentional that the bandwidth is the same as for opp-56500,
just want to mention it for if it's a C error.
> };
>
> opp-35500 {
> opp-hz = /bits/ 64 <35500>;
> opp-level = ;
> + opp-peak-kBps = <3072000>;
> };
>
> opp-26700 {
> opp-hz = /bits/ 64 <26700>;
> opp-level =
> ;
> + opp-peak-kBps = <3072000>;
> };
ditto
> opp-18000 {
> opp-hz = /bits/ 64 <18000>;
> opp-level =
> ;
> + opp-peak-kBps = <1804000>;
> };
> };
> };
assuming the repeated bandwidths are indeed intentional:
Reviewed-by: Matthias Kaehlcke
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Re: [Freedreno] [PATCH 1/6] arm64: dts: qcom: sc7180: Add interconnect bindings for GPU
Hi Sharat,
On Thu, May 14, 2020 at 04:24:14PM +0530, Sharat Masetty wrote:
> Subject: arm64: dts: qcom: sc7180: Add interconnect bindings for GPU
>
> This patch adds the interconnect bindings to the GPU node. This enables
> the GPU->DDR path bandwidth voting.
This patch doesn't add any bindings, it adds the interconnects/interconnect
configuration for the GPU
The order of the patches in this series is a bit odd. Typically you would
start with the binding changes ("dt-bindings: drm/msm/gpu: Document gpu
opp table" in this case), then the code needed to support these changes,
and finally the DT bits for the specific devices/platforms making use
of the new 'feature'.
It doesn't really matter once the series has landed since the end result
is exactly the same, however it's the logical order in which most
reviewers read your patches, and typically also the order in which the
patches land (especially when multiple trees are involved).
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Re: [Freedreno] [v2] arm64: dts: sc7180: add dsi controller and phy entries for idp dts
On Fri, Feb 14, 2020 at 10:49:37AM -0800, Matthias Kaehlcke wrote:
> On Tue, Feb 11, 2020 at 05:07:35PM +0530, Harigovindan P wrote:
>
> > subject: arm64: dts: sc7180: add dsi controller and phy entries for idp dts
>
> nit: 'dts' at the end is redundant, the prefixes make it clear that this
> is about DT entries.
>
> Also the message isn't really concise. The main entries for the DSI
> controller and the PHY are in sc7180.dtsi. I would suggest to drop
> any mentions of DSI controller and PHYs, and just say something like
> 'Add nodes for IDP display'. In the body you could mention that the
> display is the Visionox RM69299.
>
> > Adding dsi controller and phy entries for idp dt.
> >
> > Signed-off-by: Harigovindan P
> > ---
> >
> > Changes in v1:
> > - Added dsi controller and dsi phy entries for idp dts
>
> Changes in v1 is pointless, it's the first patch
>
> > Changes in v2:
> > - Adding dependency patchwork series
> > - Removing suspend configuration
> > - Adding blank before curly brace
> >
> > This patch depends on following patchwork series:
> >
> > https://patchwork.kernel.org/patch/11364687/
> > https://patchwork.kernel.org/patch/11366303/
> >
> > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 55 +
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> > b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> > index 388f50ad4fde..6ccf8c3603ab 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> > @@ -7,6 +7,7 @@
> >
> > /dts-v1/;
> >
> > +#include
> > #include
> > #include "sc7180.dtsi"
> > #include "pm6150.dtsi"
> > @@ -232,6 +233,49 @@ vreg_bob: bob {
> > };
> > };
> >
> > + {
> > + status = "okay";
> > +
> > + vdda-supply = <_l3c_1p2>;
> > +
> > + panel@0 {
> > + compatible = "visionox,rm69299-1080p-display";
> > + reg = <0>;
> > +
> > + vdda-supply = <_l8c_1p8>;
> > + vdd3p3-supply = <_l18a_2p8>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_pins>;
> > +
> > + reset-gpios = <_gpio 3 GPIO_ACTIVE_HIGH>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + port@0 {
> > + reg = <0>;
> > + panel0_in: endpoint {
> > + remote-endpoint = <_out>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + ports {
> > + port@1 {
> > + endpoint {
> > + remote-endpoint = <_in>;
> > + data-lanes = <0 1 2 3>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +_phy {
> > + status = "okay";
> > +};
> > +
> > {
> > status = "okay";
> > pinctrl-names = "default";
> > @@ -289,6 +333,17 @@ _1_qmpphy {
> >
> > /* PINCTRL - additions to nodes defined in sc7180.dtsi */
> >
> > +_gpio {
> > + disp_pins: disp-pins {
> > + pins = "gpio3";
> > + function = "func1";
> > + qcom,drive-strength = <2>;
> > + power-source = <0>;
> > + bias-disable;
> > + output-low;
> > + };
> > +};
> > +
> > _clk {
> > pinconf {
> > pins = "gpio63";
>
> To get the display actually to work you also need this:
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> index 88919da1510b03..fdbcb56dfa81f9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> @@ -276,6 +276,14 @@
> status = "okay";
> };
>
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> +};
> +
> {
> status = "okay";
> pinctrl-names = "default";
>
> Maybe just add this to this patch?
ping
the display driver landed in drm-misc, but this patch still needs a
respin.
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Re: [Freedreno] [PATCH v11 1/2] drm/panel: add support for rm69299 visionox panel driver
Hi,
On Tue, Apr 21, 2020 at 10:25:07AM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
Please keep tags from previous versions (like my Reviewed-by from v7)
when making minimal changes.
Also there is no need to keep sending the bindings patch, it already
landed in drm-misc.
> diff --git a/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> new file mode 100644
> index ..3ef4cc80044a
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
...
> +MODULE_DESCRIPTION("Visionox RM69299 DSI Panel Driver");
> --
> 2.25.1
The last two lines break the patch:
git am
/tmp/v11-1-2-drm-panel-add-support-for-rm69299-visionox-panel-driver.patch
Applying: drm/panel: add support for rm69299 visionox panel driver
error: corrupt patch at line 379
Patch failed at 0001 drm/panel: add support for rm69299 visionox panel driver
Besides the broken format:
Reviewed-by: Matthias Kaehlcke
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Re: [Freedreno] [PATCH v7 2/2] drm/panel: add support for rm69299 visionox panel driver
Hi,
checkpatch finds multiple errors with this patch, as Sam reported on
https://patchwork.kernel.org/cover/11461945/. Please fix those and
send a new version (not sure which version number this should be (v11?),
this series is a bit confusing in this aspect).
Please also double check if there is any outstanding feedback that still
needs to be addressed (not from my side AFAIK).
Thanks
Matthias
On Mon, Mar 16, 2020 at 09:46:47AM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v2:
> - Dropping redundant space in Kconfig(Sam Ravnborg).
> - Changing structure for include files(Sam Ravnborg).
> - Removing backlight related code and functions(Sam Ravnborg).
> - Removing repeated printing of error message(Sam Ravnborg).
> - Adding drm_connector as an argument for get_modes function.
> Changes in v3:
> - Adding arguments for drm_panel_init to support against mainline.
> Changes in v4:
> - Removing error messages from regulator_set_load.
> - Removing dev struct entry.
> - Removing checks.
> - Dropping empty comment lines.
> Changes in v5:
> - Removing unused struct member variables.
> - Removing blank lines.
> - Fixed indentation.
> - Invoking dsi_detach and panel_remove while early exiting from probe.
> Changes in v6:
> - Changed "35597" to "rm69299" for power_on function.
> - Removing rm69299_config since it supports single type of panel for
> now.
> - Fixed alignment.
> - Using goto statements when regulator_set_load fails.
> Changes in v7:
> - Added new goto statement when regulator_set_load fails.
>
> drivers/gpu/drm/panel/Kconfig | 8 +
> drivers/gpu/drm/panel/Makefile| 1 +
> .../gpu/drm/panel/panel-visionox-rm69299.c| 295 ++
> 3 files changed, 304 insertions(+)
> create mode 100644 drivers/gpu/drm/panel/panel-visionox-rm69299.c
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index ae44ac2ec106..7b696f304a99 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -389,6 +389,14 @@ config DRM_PANEL_TRULY_NT35597_WQXGA
> Say Y here if you want to enable support for Truly NT35597 WQXGA Dual
> DSI
> Video Mode panel
>
> +config DRM_PANEL_VISIONOX_RM69299
> + tristate "Visionox RM69299"
> + depends on OF
> + depends on DRM_MIPI_DSI
> + help
> + Say Y here if you want to enable support for Visionox
> + RM69299 DSI Video Mode panel.
> +
> config DRM_PANEL_XINPENG_XPP055C272
> tristate "Xinpeng XPP055C272 panel driver"
> depends on OF
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index 7c4d3c581fd4..9f11d067a6b2 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -41,4 +41,5 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD028TTEC1) +=
> panel-tpo-td028ttec1.o
> obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o
> obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
> obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
> +obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
> obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
> diff --git a/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> new file mode 100644
> index ..0f877d21fdf2
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> @@ -0,0 +1,295 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +
> +struct visionox_rm69299 {
> + struct drm_panel panel;
> + struct regulator_bulk_data supplies[2];
> + struct gpio_desc *reset_gpio;
> + struct mipi_dsi_device *dsi;
> + bool prepared;
> + bool enabled;
> +};
> +
> +static inline struct visionox_rm69299 *panel_to_ctx(struct drm_panel *panel)
> +{
> + return container_of(panel, struct visionox_rm69299, panel);
> +}
> +
> +static int visionox_rm69299_power_on(struct visionox_rm69299 *ctx)
> +{
> + int ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> + if (ret < 0)
> + return ret;
> +
> + /*
> + * Reset sequence of visionox panel requires the panel to be
> + * out of reset for 10ms, followed by being held in reset
> + * for 10ms and then out again
> + */
> + gpiod_set_value(ctx->reset_gpio, 1);
> + usleep_range(1, 2);
> + gpiod_set_value(ctx->reset_gpio, 0);
> + usleep_range(1, 2);
> + gpiod_set_value(ctx->reset_gpio, 1);
> + usleep_range(1, 2);
> +
> +
Re: [Freedreno] [v1 3/3] arm64: dts: sc7180: define interconnects for sc7180 target
On Wed, Apr 01, 2020 at 02:47:45PM +0530, Krishna Manikandan wrote: > Subject: arm64: dts: sc7180: define interconnects for sc7180 target Please be more specific about which interconnect entries are added. Also no need to repeat 'sc7180', it is already clear from the prefix. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v10 0/2] Add support for rm69299 Visionox panel driver and add devicetree bindings for visionox panel
On Mon, Mar 30, 2020 at 09:25:11PM +0200, Sam Ravnborg wrote: > Hi Matthias. > > On Sun, Mar 29, 2020 at 10:44:17AM -0700, Matthias Kaehlcke wrote: > > Hi Sam, > > > > On Sat, Mar 28, 2020 at 09:40:47PM +0100, Sam Ravnborg wrote: > > > Hi Harigovindan > > > > > > On Fri, Mar 27, 2020 at 01:06:34PM +0530, Harigovindan P wrote: > > > > Adding support for visionox rm69299 panel driver and adding bindings > > > > for the same panel. > > > > > > > > Harigovindan P (2): > > > > dt-bindings: display: add visionox rm69299 panel variant > > > > drm/panel: add support for rm69299 visionox panel driver > > > > > > I have only the first patch, which is now applied. > > > Please resend second patch as it is lost somewhere. > > > > Yes, it seems for v8, v9 and v10 only the bindings were sent, even > > though the cover letter and subject say it's a series of two patches. > > > > To my knowledge the latest version of the driver patch is this: > > > > https://patchwork.kernel.org/patch/11439689/ > > I did not go back and check, but I recall there was > review feedback that is not yet addressed. > > I applied the patch here and checkpatch was not happy: > total: 14 errors, 22 warnings, 11 checks, 314 lines checked > > Many of these are trivial indent or spaces used where tabs should be > used. > These needs to be fixed before the driver will be applied. > > And there was too much that I just did it while applying. Oh, I totally missed these, sure this needs to be addressed. Harigovindan, please also double check if there is any outstanding feedback that still needs to be addressed. Thanks Matthias ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v10 0/2] Add support for rm69299 Visionox panel driver and add devicetree bindings for visionox panel
Hi Sam, On Sat, Mar 28, 2020 at 09:40:47PM +0100, Sam Ravnborg wrote: > Hi Harigovindan > > On Fri, Mar 27, 2020 at 01:06:34PM +0530, Harigovindan P wrote: > > Adding support for visionox rm69299 panel driver and adding bindings for > > the same panel. > > > > Harigovindan P (2): > > dt-bindings: display: add visionox rm69299 panel variant > > drm/panel: add support for rm69299 visionox panel driver > > I have only the first patch, which is now applied. > Please resend second patch as it is lost somewhere. Yes, it seems for v8, v9 and v10 only the bindings were sent, even though the cover letter and subject say it's a series of two patches. To my knowledge the latest version of the driver patch is this: https://patchwork.kernel.org/patch/11439689/ ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v7 2/2] drm/panel: add support for rm69299 visionox panel driver
On Mon, Mar 16, 2020 at 09:46:47AM +0530, Harigovindan P wrote: > Add support for Visionox panel driver. > > Signed-off-by: Harigovindan P Reviewed-by: Matthias Kaehlcke ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v6 2/2] drm/panel: add support for rm69299 visionox panel driver
Hi,
thanks for re-spinning!
One more comment inline.
On Wed, Mar 11, 2020 at 02:28:07PM +0530, Harigovindan P wrote:
> diff --git a/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> new file mode 100644
> index ..b226723a7543
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
>
> ...
>
> +static int visionox_rm69299_probe(struct mipi_dsi_device *dsi)
> +{
> + struct device *dev = >dev;
> + struct visionox_rm69299 *ctx;
> + int ret;
> +
> + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> + if (!ctx)
> + return -ENOMEM;
> +
> + mipi_dsi_set_drvdata(dsi, ctx);
> +
> + ctx->supplies[0].supply = "vdda";
> + ctx->supplies[1].supply = "vdd3p3";
> +
> + ret = devm_regulator_bulk_get(ctx->panel.dev, ARRAY_SIZE(ctx->supplies),
> + ctx->supplies);
> + if (ret < 0)
> + return ret;
> +
> + ctx->reset_gpio = devm_gpiod_get(ctx->panel.dev, "reset",
> GPIOD_OUT_LOW);
> + if (IS_ERR(ctx->reset_gpio)) {
> + DRM_DEV_ERROR(dev, "cannot get reset gpio %ld\n",
> + PTR_ERR(ctx->reset_gpio));
> + return PTR_ERR(ctx->reset_gpio);
> + }
> +
> + drm_panel_init(>panel, dev, _rm69299_drm_funcs,
> +DRM_MODE_CONNECTOR_DSI);
> + ctx->panel.dev = dev;
> + ctx->panel.funcs = _rm69299_drm_funcs;
> + drm_panel_add(>panel);
> +
> + dsi->lanes = 4;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM |
> + MIPI_DSI_CLOCK_NON_CONTINUOUS;
> + ret = mipi_dsi_attach(dsi);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "dsi attach failed ret = %d\n", ret);
> + goto err_dsi_attach;
> + }
> +
> + ret = regulator_set_load(ctx->supplies[0].consumer, 32000);
> + if (ret) {
> + mipi_dsi_detach(dsi);
> + goto err_dsi_attach;
> + }
the common way to do this kind of unwinding in the kernel would be to add
something like this before 'err_dsi_attach':
err_set_load:
mipi_dsi_detach(dsi);
and then just do 'goto err_set_load' in the error paths.
> +
> + ret = regulator_set_load(ctx->supplies[1].consumer, 13200);
> + if (ret) {
> + mipi_dsi_detach(dsi);
> + goto err_dsi_attach;
> + }
> +
> + return 0;
> +
> +err_dsi_attach:
> + drm_panel_remove(>panel);
> + return ret;
> +}
Reviewed-by: Matthias Kaehlcke
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Re: [Freedreno] [PATCH v5 2/2] drm/panel: add support for rm69299 visionox panel driver
Hi,
On Mon, Mar 09, 2020 at 10:53:04AM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v2:
> - Dropping redundant space in Kconfig(Sam Ravnborg).
> - Changing structure for include files(Sam Ravnborg).
> - Removing backlight related code and functions(Sam Ravnborg).
> - Removing repeated printing of error message(Sam Ravnborg).
> - Adding drm_connector as an argument for get_modes function.
> Changes in v3:
> - Adding arguments for drm_panel_init to support against mainline.
> Changes in v4:
> - Removing error messages from regulator_set_load.
> - Removing dev struct entry.
> - Removing checks.
> - Dropping empty comment lines.
> Changes in v5:
> - Removing unused struct member variables.
> - Removing blank lines.
> - Fixed indentation.
> - Invoking dsi_detach and panel_remove while early exiting from probe.
>
> drivers/gpu/drm/panel/Kconfig | 8 +
> drivers/gpu/drm/panel/Makefile| 1 +
> .../gpu/drm/panel/panel-visionox-rm69299.c| 315 ++
> 3 files changed, 324 insertions(+)
> create mode 100644 drivers/gpu/drm/panel/panel-visionox-rm69299.c
>
> ...
>
> diff --git a/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> new file mode 100644
> index ..2bd3af46d933
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
>
> ...
>
> +static int visionox_35597_power_on(struct visionox_rm69299 *ctx)
> +{
s/35597/rm69299/ ?
> +static const struct rm69299_config rm69299_dir = {
> + .width_mm = 74,
> + .height_mm = 131,
> + .dm = _rm69299_1080x2248_60hz,
> +};
Are there actually variants of the panel with different sizes? So far the
driver supports a single type of panel, so I would say struct rm69299_config
is not needed. It can be added later if the driver ever gets support for
other panel variants. For now just assign the values directly in
'visionox_rm69299_get_modes'.
> +static int visionox_rm69299_probe(struct mipi_dsi_device *dsi)
> +{
> + struct device *dev = >dev;
> + struct visionox_rm69299 *ctx;
> + int ret;
> +
> + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> + if (!ctx)
> + return -ENOMEM;
> +
> + mipi_dsi_set_drvdata(dsi, ctx);
> +
> + ctx->supplies[0].supply = "vdda";
> + ctx->supplies[1].supply = "vdd3p3";
> +
> + ret = devm_regulator_bulk_get(ctx->panel.dev, ARRAY_SIZE(ctx->supplies),
> + ctx->supplies);
nit: alignment is odd, either align with a tab after 'devm_regulator_bulk_get'
or with 'ctx->panel.dev'.
> + if (ret < 0)
> + return ret;
> +
> + ctx->reset_gpio = devm_gpiod_get(ctx->panel.dev, "reset",
> GPIOD_OUT_LOW);
> + if (IS_ERR(ctx->reset_gpio)) {
> + DRM_DEV_ERROR(dev, "cannot get reset gpio %ld\n",
> + PTR_ERR(ctx->reset_gpio));
> + return PTR_ERR(ctx->reset_gpio);
> + }
> +
> + drm_panel_init(>panel, dev, _rm69299_drm_funcs,
> +DRM_MODE_CONNECTOR_DSI);
> + ctx->panel.dev = dev;
> + ctx->panel.funcs = _rm69299_drm_funcs;
> + drm_panel_add(>panel);
> +
> + dsi->lanes = 4;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM |
> + MIPI_DSI_CLOCK_NON_CONTINUOUS;
> + ret = mipi_dsi_attach(dsi);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "dsi attach failed ret = %d\n", ret);
> + goto err_dsi_attach;
> + }
> +
> + ret = regulator_set_load(ctx->supplies[0].consumer, 32000);
> + if (ret) {
> + mipi_dsi_detach(dsi);
> + drm_panel_remove(>panel);
that's technically correct, but since you have the 'goto' above and do the
same unwinding for the other 'regulator_set_load' call below it would be
better to use a 'goto' here (and below) too. Actually the 'goto' above only
makes sense if 'goto' is also used for the other cases.
> + return ret;
> + }
> +
> + ret = regulator_set_load(ctx->supplies[1].consumer, 13200);
> + if (ret) {
> + mipi_dsi_detach(dsi);
> + drm_panel_remove(>panel);
> + return ret;
> + }
> +
> + return 0;
> +
> +err_dsi_attach:
> + drm_panel_remove(>panel);
> + return ret;
> +}
> +
> +static int visionox_rm69299_remove(struct mipi_dsi_device *dsi)
> +{
> + struct visionox_rm69299 *ctx = mipi_dsi_get_drvdata(dsi);
> +
> + mipi_dsi_detach(ctx->dsi);
> + mipi_dsi_device_unregister(ctx->dsi);
> +
> + drm_panel_remove(>panel);
> + return 0;
> +}
> +
> +static const struct of_device_id visionox_rm69299_of_match[] = {
> + {
> + .compatible = "visionox,rm69299-1080p-display",
> + .data = _dir,
> +
Re: [Freedreno] [PATCH v4 2/2] drm/panel: add support for rm69299 visionox panel driver
Hi,
On Fri, Mar 06, 2020 at 04:06:28PM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v2:
> - Dropping redundant space in Kconfig(Sam Ravnborg).
> - Changing structure for include files(Sam Ravnborg).
> - Removing backlight related code and functions(Sam Ravnborg).
> - Removing repeated printing of error message(Sam Ravnborg).
> - Adding drm_connector as an argument for get_modes function.
> Changes in v3:
> - Adding arguments for drm_panel_init to support against mainline.
> Changes in v4:
> - Removing error messages from regulator_set_load.
> - Removing dev struct entry.
> - Removing checks.
> - Dropping empty comment lines.
>
> drivers/gpu/drm/panel/Kconfig | 8 +
> drivers/gpu/drm/panel/Makefile| 1 +
> .../gpu/drm/panel/panel-visionox-rm69299.c| 322 ++
> 3 files changed, 331 insertions(+)
> create mode 100644 drivers/gpu/drm/panel/panel-visionox-rm69299.c
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index ae44ac2ec106..7b696f304a99 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -389,6 +389,14 @@ config DRM_PANEL_TRULY_NT35597_WQXGA
> Say Y here if you want to enable support for Truly NT35597 WQXGA Dual
> DSI
> Video Mode panel
>
> +config DRM_PANEL_VISIONOX_RM69299
> + tristate "Visionox RM69299"
> + depends on OF
> + depends on DRM_MIPI_DSI
> + help
> + Say Y here if you want to enable support for Visionox
> + RM69299 DSI Video Mode panel.
> +
> config DRM_PANEL_XINPENG_XPP055C272
> tristate "Xinpeng XPP055C272 panel driver"
> depends on OF
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index 7c4d3c581fd4..9f11d067a6b2 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -41,4 +41,5 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD028TTEC1) +=
> panel-tpo-td028ttec1.o
> obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o
> obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
> obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
> +obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
> obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
> diff --git a/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> new file mode 100644
> index ..eb15dca15398
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-visionox-rm69299.c
> @@ -0,0 +1,322 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +
> +struct rm69299_config {
> + unsigned long width_mm;
> + unsigned long height_mm;
> + const char *panel_name;
> + u32 num_on_cmds;
not used, remove
> + const struct drm_display_mode *dm;
> +};
> +
> +struct visionox_rm69299 {
> + struct drm_panel panel;
> +
> + struct regulator_bulk_data supplies[2];
> +
> + struct gpio_desc *reset_gpio;
> +
> + struct mipi_dsi_device *dsi;
nit: the use of blank lines in this struct seems a bit arbitrary,
just remove them?
> + const struct rm69299_config *config;
> + bool prepared;
> + bool enabled;
> +};
> +
> +static inline struct visionox_rm69299 *panel_to_ctx(struct drm_panel *panel)
> +{
> + return container_of(panel, struct visionox_rm69299, panel);
> +}
> +
> +static int visionox_35597_power_on(struct visionox_rm69299 *ctx)
> +{
> + int ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> + if (ret < 0)
> + return ret;
> +
> + /*
> + * Reset sequence of visionox panel requires the panel to be
> + * out of reset for 10ms, followed by being held in reset
> + * for 10ms and then out again
> + */
> + gpiod_set_value(ctx->reset_gpio, 1);
> + usleep_range(1, 2);
> + gpiod_set_value(ctx->reset_gpio, 0);
> + usleep_range(1, 2);
> + gpiod_set_value(ctx->reset_gpio, 1);
> + usleep_range(1, 2);
> +
> + return 0;
> +}
> +
> +static int visionox_rm69299_power_off(struct visionox_rm69299 *ctx)
> +{
> + gpiod_set_value(ctx->reset_gpio, 0);
> +
> + return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> +}
> +
> +static int visionox_rm69299_unprepare(struct drm_panel *panel)
> +{
> + struct visionox_rm69299 *ctx = panel_to_ctx(panel);
> + int ret;
> +
> + ctx->dsi->mode_flags = 0;
> +
> + ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
> + if (ret < 0)
> + DRM_DEV_ERROR(ctx->panel.dev,
Re: [Freedreno] [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support
On Thu, Feb 27, 2020 at 01:54:33PM -0800, Matthias Kaehlcke wrote:
> On Mon, Dec 02, 2019 at 01:48:57PM +, Chandan Uddaraju wrote:
> > Add the needed displayPort files to enable DP driver
> > on msm target.
> >
> > "dp_display" module is the main module that calls into
> > other sub-modules. "dp_drm" file represents the interface
> > between DRM framework and DP driver.
> >
> > changes in v2:
> > -- Update copyright markings on all relevant files.
> > -- Change pr_err() to DRM_ERROR()
> > -- Use APIs directly instead of function pointers.
> > -- Use drm_display_mode structure to store link parameters in the driver.
> > -- Use macros for register definitions instead of hardcoded values.
> > -- Replace writel_relaxed/readl_relaxed with writel/readl
> >and remove memory barriers.
> > -- Remove unnecessary NULL checks.
> > -- Use drm helper functions for dpcd read/write.
> > -- Use DRM_DEBUG_DP for debug msgs.
> >
> > changes in V3:
> > -- Removed changes in dpu_io_util.[ch]
> > -- Added locking around "is_connected" flag and removed atomic_set()
> > -- Removed the argument validation checks in all the static functions
> >except initialization functions and few API calls across msm/dp files
> > -- Removed hardcoded values for register reads/writes
> > -- Removed vreg related generic structures.
> > -- Added return values where ever necessary.
> > -- Updated dp_ctrl_on function.
> > -- Calling the ctrl specific catalog functions directly instead of
> >function pointers.
> > -- Added seperate change that adds standard value in drm_dp_helper file.
> > -- Added separate change in this list that is used to initialize
> >displayport in DPU driver.
> > -- Added change to use drm_dp_get_adjust_request_voltage() function.
> >
> > Signed-off-by: Chandan Uddaraju
> > ---
> > +++ b/drivers/gpu/drm/msm/dp/dp_power.c
> >
> > ...
> >
> > +int dp_power_init(struct dp_power *dp_power, bool flip)
> > +{
> > + int rc = 0;
> > + struct dp_power_private *power;
> > +
> > + if (!dp_power) {
> > + DRM_ERROR("invalid power data\n");
> > + rc = -EINVAL;
> > + goto exit;
> > + }
>
> drive-by comment:
>
> this would lead to calling 'pm_runtime_put_sync(>pdev->dev)'
> below with 'power' being NULL, which doesn't seem a good idea.
correction: with 'power' being uninitialized, which isn't a good idea
either.
> It is probably sane to expect that 'dp_power' is not NULL, if that's
> the case the check can be removed. Otherwise the function should just
> return -EINVAL instead of jumping to 'exit'.
>
> > +
> > + power = container_of(dp_power, struct dp_power_private, dp_power);
> > +
> > + pm_runtime_get_sync(>pdev->dev);
> > + rc = dp_power_regulator_enable(power);
> > + if (rc) {
> > + DRM_ERROR("failed to enable regulators, %d\n", rc);
> > + goto exit;
> > + }
> > +
> > + rc = dp_power_pinctrl_set(power, true);
> > + if (rc) {
> > + DRM_ERROR("failed to set pinctrl state, %d\n", rc);
> > + goto err_pinctrl;
> > + }
> > +
> > + rc = dp_power_config_gpios(power, flip);
> > + if (rc) {
> > + DRM_ERROR("failed to enable gpios, %d\n", rc);
> > + goto err_gpio;
> > + }
> > +
> > + rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
> > + if (rc) {
> > + DRM_ERROR("failed to enable DP core clocks, %d\n", rc);
> > + goto err_clk;
> > + }
> > +
> > + return 0;
> > +
> > +err_clk:
> > + dp_power_disable_gpios(power);
> > +err_gpio:
> > + dp_power_pinctrl_set(power, false);
> > +err_pinctrl:
> > + dp_power_regulator_disable(power);
> > +exit:
> > + pm_runtime_put_sync(>pdev->dev);
> > + return rc;
> > +}
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Re: [Freedreno] [DPU PATCH v3 4/5] drm/msm/dp: add support for DP PLL driver
On Mon, Dec 02, 2019 at 01:48:27PM +, Chandan Uddaraju wrote:
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
>
> The DP driver calls the DP PLL driver registration.
> The DP driver sets the link and pixel clock sources.
>
> Changes in v2:
> -- Update copyright markings on all relevant files.
> -- Use DRM_DEBUG_DP for debug msgs.
>
> Signed-off-by: Chandan Uddaraju
> ---
> diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
> b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
> new file mode 100644
> index 000..6ef2492
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
>
> ...
>
> +static u8 dp_mux_get_parent_10nm(struct clk_hw *hw)
> +{
> + u32 auxclk_div = 0;
> + struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw);
> + struct dp_pll_10nm *dp_res = pclksel->pll;
> + u8 val = 0;
> +
> + DRM_ERROR("clk_hw->init->name = %s\n", hw->init->name);
drive-by comment: DRM_ERROR doesn't seem the right level, DRM_DEBUG_DP
would probably be more adequate.
Also I found this line triggers a NULL pointer dereference on a SC7180
system, where clk_hw->init is NULL.
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Re: [Freedreno] [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support
On Mon, Dec 02, 2019 at 01:48:57PM +, Chandan Uddaraju wrote:
> Add the needed displayPort files to enable DP driver
> on msm target.
>
> "dp_display" module is the main module that calls into
> other sub-modules. "dp_drm" file represents the interface
> between DRM framework and DP driver.
>
> changes in v2:
> -- Update copyright markings on all relevant files.
> -- Change pr_err() to DRM_ERROR()
> -- Use APIs directly instead of function pointers.
> -- Use drm_display_mode structure to store link parameters in the driver.
> -- Use macros for register definitions instead of hardcoded values.
> -- Replace writel_relaxed/readl_relaxed with writel/readl
>and remove memory barriers.
> -- Remove unnecessary NULL checks.
> -- Use drm helper functions for dpcd read/write.
> -- Use DRM_DEBUG_DP for debug msgs.
>
> changes in V3:
> -- Removed changes in dpu_io_util.[ch]
> -- Added locking around "is_connected" flag and removed atomic_set()
> -- Removed the argument validation checks in all the static functions
>except initialization functions and few API calls across msm/dp files
> -- Removed hardcoded values for register reads/writes
> -- Removed vreg related generic structures.
> -- Added return values where ever necessary.
> -- Updated dp_ctrl_on function.
> -- Calling the ctrl specific catalog functions directly instead of
>function pointers.
> -- Added seperate change that adds standard value in drm_dp_helper file.
> -- Added separate change in this list that is used to initialize
>displayport in DPU driver.
> -- Added change to use drm_dp_get_adjust_request_voltage() function.
>
> Signed-off-by: Chandan Uddaraju
> ---
> +++ b/drivers/gpu/drm/msm/dp/dp_power.c
>
> ...
>
> +int dp_power_init(struct dp_power *dp_power, bool flip)
> +{
> + int rc = 0;
> + struct dp_power_private *power;
> +
> + if (!dp_power) {
> + DRM_ERROR("invalid power data\n");
> + rc = -EINVAL;
> + goto exit;
> + }
drive-by comment:
this would lead to calling 'pm_runtime_put_sync(>pdev->dev)'
below with 'power' being NULL, which doesn't seem a good idea.
It is probably sane to expect that 'dp_power' is not NULL, if that's
the case the check can be removed. Otherwise the function should just
return -EINVAL instead of jumping to 'exit'.
> +
> + power = container_of(dp_power, struct dp_power_private, dp_power);
> +
> + pm_runtime_get_sync(>pdev->dev);
> + rc = dp_power_regulator_enable(power);
> + if (rc) {
> + DRM_ERROR("failed to enable regulators, %d\n", rc);
> + goto exit;
> + }
> +
> + rc = dp_power_pinctrl_set(power, true);
> + if (rc) {
> + DRM_ERROR("failed to set pinctrl state, %d\n", rc);
> + goto err_pinctrl;
> + }
> +
> + rc = dp_power_config_gpios(power, flip);
> + if (rc) {
> + DRM_ERROR("failed to enable gpios, %d\n", rc);
> + goto err_gpio;
> + }
> +
> + rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
> + if (rc) {
> + DRM_ERROR("failed to enable DP core clocks, %d\n", rc);
> + goto err_clk;
> + }
> +
> + return 0;
> +
> +err_clk:
> + dp_power_disable_gpios(power);
> +err_gpio:
> + dp_power_pinctrl_set(power, false);
> +err_pinctrl:
> + dp_power_regulator_disable(power);
> +exit:
> + pm_runtime_put_sync(>pdev->dev);
> + return rc;
> +}
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Re: [Freedreno] [PATCH] dt-bindings: arm-smmu: update the list of clocks
On Thu, Feb 20, 2020 at 01:42:22PM +0530, Sharat Masetty wrote: > This patch adds a clock definition needed for powering on the GPU TBUs > and the GPU TCU. > > Signed-off-by: Sharat Masetty > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 6515dbe..235c0df 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -28,6 +28,7 @@ properties: >- enum: >- qcom,msm8996-smmu-v2 >- qcom,msm8998-smmu-v2 > + - qcom,sc7180-smmu-v2 The addition of the compatible string isn't (directly) related with $subject, this should be done in a separate patch. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [v2] arm64: dts: sc7180: add dsi controller and phy entries for idp dts
On Tue, Feb 11, 2020 at 05:07:35PM +0530, Harigovindan P wrote:
> subject: arm64: dts: sc7180: add dsi controller and phy entries for idp dts
nit: 'dts' at the end is redundant, the prefixes make it clear that this
is about DT entries.
Also the message isn't really concise. The main entries for the DSI
controller and the PHY are in sc7180.dtsi. I would suggest to drop
any mentions of DSI controller and PHYs, and just say something like
'Add nodes for IDP display'. In the body you could mention that the
display is the Visionox RM69299.
> Adding dsi controller and phy entries for idp dt.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v1:
> - Added dsi controller and dsi phy entries for idp dts
Changes in v1 is pointless, it's the first patch
> Changes in v2:
> - Adding dependency patchwork series
> - Removing suspend configuration
> - Adding blank before curly brace
>
> This patch depends on following patchwork series:
>
> https://patchwork.kernel.org/patch/11364687/
> https://patchwork.kernel.org/patch/11366303/
>
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 55 +
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> index 388f50ad4fde..6ccf8c3603ab 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> @@ -7,6 +7,7 @@
>
> /dts-v1/;
>
> +#include
> #include
> #include "sc7180.dtsi"
> #include "pm6150.dtsi"
> @@ -232,6 +233,49 @@ vreg_bob: bob {
> };
> };
>
> + {
> + status = "okay";
> +
> + vdda-supply = <_l3c_1p2>;
> +
> + panel@0 {
> + compatible = "visionox,rm69299-1080p-display";
> + reg = <0>;
> +
> + vdda-supply = <_l8c_1p8>;
> + vdd3p3-supply = <_l18a_2p8>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> +
> + reset-gpios = <_gpio 3 GPIO_ACTIVE_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + panel0_in: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> + };
> + };
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <_in>;
> + data-lanes = <0 1 2 3>;
> + };
> + };
> + };
> +};
> +
> +_phy {
> + status = "okay";
> +};
> +
> {
> status = "okay";
> pinctrl-names = "default";
> @@ -289,6 +333,17 @@ _1_qmpphy {
>
> /* PINCTRL - additions to nodes defined in sc7180.dtsi */
>
> +_gpio {
> + disp_pins: disp-pins {
> + pins = "gpio3";
> + function = "func1";
> + qcom,drive-strength = <2>;
> + power-source = <0>;
> + bias-disable;
> + output-low;
> + };
> +};
> +
> _clk {
> pinconf {
> pins = "gpio63";
To get the display actually to work you also need this:
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 88919da1510b03..fdbcb56dfa81f9 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -276,6 +276,14 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
pinctrl-names = "default";
Maybe just add this to this patch?
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Re: [Freedreno] [PATCH v2 1/7] iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context
Hi,
On Thu, Jan 02, 2020 at 04:32:07PM +0530, Sharat Masetty wrote:
> From: Jordan Crouse
>
> Pass the propposed io_pgtable_cfg to the implementation specific
> init_context() function to give the implementation an opportunity to
> to modify it before it gets passed to io-pgtable.
>
> Signed-off-by: Jordan Crouse
> Signed-off-by: Sai Prakash Ranjan
> ---
> drivers/iommu/arm-smmu-impl.c | 3 ++-
> drivers/iommu/arm-smmu.c | 11 ++-
> drivers/iommu/arm-smmu.h | 3 ++-
> 3 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c
> index b2fe72a..33ed682 100644
> --- a/drivers/iommu/arm-smmu-impl.c
> +++ b/drivers/iommu/arm-smmu-impl.c
> @@ -68,7 +68,8 @@ static int cavium_cfg_probe(struct arm_smmu_device *smmu)
> return 0;
> }
>
> -static int cavium_init_context(struct arm_smmu_domain *smmu_domain)
> +static int cavium_init_context(struct arm_smmu_domain *smmu_domain,
> + struct io_pgtable_cfg *pgtbl_cfg)
> {
> struct cavium_smmu *cs = container_of(smmu_domain->smmu,
> struct cavium_smmu, smmu);
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index eee48f9..4f7e0c0 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -758,11 +758,6 @@ static int arm_smmu_init_domain_context(struct
> iommu_domain *domain,
> cfg->asid = cfg->cbndx;
>
> smmu_domain->smmu = smmu;
> - if (smmu->impl && smmu->impl->init_context) {
> - ret = smmu->impl->init_context(smmu_domain);
> - if (ret)
> - goto out_unlock;
> - }
>
> smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) {
> .pgsize_bitmap = smmu->pgsize_bitmap,
> @@ -773,6 +768,12 @@ static int arm_smmu_init_domain_context(struct
> iommu_domain *domain,
> .iommu_dev = smmu->dev,
> };
>
> + if (smmu->impl && smmu->impl->init_context) {
> + ret = smmu->impl->init_context(smmu_domain,
> _domain->pgtbl_cfg);
Which patch adds 'pgtbl_cfg' to struct arm_smmu_domain? The field does
not exist in iommu/next.
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Re: [Freedreno] [v4] arm64: dts: sc7180: add display dt nodes
Hi,
On Tue, Jan 28, 2020 at 06:54:44PM +0530, Harigovindan P wrote:
> Add display, DSI hardware DT nodes for sc7180.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v1:
> -Added display DT nodes for sc7180
> Changes in v2:
> -Renamed node names
> -Corrected code alignments
> -Removed extra new line
> -Added DISP AHB clock for register access
> under display_subsystem node for global settings
> Changes in v3:
> -Modified node names
> -Modified hard coded values
> -Removed mdss reg entry
> Changes in v4:
> -Reverting mdp node name
> -Setting status to disabled in main SOC dtsi file
> -Replacing _ to - for node names
> -Adding clock dependency patch link
> -Splitting idp dt file to a separate patch
>
> This patch has dependency on the below series
> https://lkml.org/lkml/2019/12/27/73
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 128
> +++
> 1 file changed, 128 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 3bc3f64..c3883af 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1184,6 +1184,134 @@
> #power-domain-cells = <1>;
> };
>
> + mdss: mdss@ae0 {
> + compatible = "qcom,sc7180-mdss";
> + reg = <0 0x0ae0 0 0x1000>;
> + reg-names = "mdss";
> +
> + power-domains = < MDSS_GDSC>;
> +
> + clocks = < GCC_DISP_AHB_CLK>,
> + < GCC_DISP_HF_AXI_CLK>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "gcc_bus", "ahb", "core";
> +
> + assigned-clocks = < DISP_CC_MDSS_MDP_CLK>;
> + assigned-clock-rates = <3>;
> +
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <_smmu 0x800 0x2>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: mdp@ae01000 {
> + compatible = "qcom,sc7180-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb 0 0x2008>,
> + <0 0x0af03000 0 0x16>;
> + reg-names = "mdp", "vbif", "disp_cc";
> +
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_ROT_CLK>,
> + < DISP_CC_MDSS_MDP_LUT_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>,
> + < DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "iface", "rot", "lut", "core",
> + "vsync";
> + assigned-clocks = <
> DISP_CC_MDSS_MDP_CLK>,
> + <
> DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <3>,
> +<1920>;
The clock rate for DISP_CC_MDSS_MDP_CLK is already specified in the
parent node, do we really want/need to specify it twice?
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Re: [Freedreno] [v1] arm64: dts: sc7180: add dsi controller and phy entries for idp dts
Hi,
On Tue, Jan 28, 2020 at 07:06:57PM +0530, Harigovindan P wrote:
> Adding dsi controller and phy entries for idp dt.
>
> Signed-off-by: Harigovindan P
> ---
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 56
> +
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> index 388f50a..9f42367 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> @@ -7,6 +7,7 @@
>
> /dts-v1/;
>
> +#include
> #include
> #include "sc7180.dtsi"
> #include "pm6150.dtsi"
> @@ -232,6 +233,50 @@
> };
> };
>
> +_controller {
> + status = "okay";
> +
> + vdda-supply = <_l3c_1p2>;
> +
> + panel@0 {
> + compatible = "visionox,rm69299-1080p-display";
This depends on the series "Add support for rm69299 Visionox panel
driver and add devicetree bindings for visionox panel"
(https://patchwork.kernel.org/cover/11320773/) which hasn't landed
IIUC. This should be mentioned after '---'.
> + reg = <0>;
> +
> + vdda-supply = <_l8c_1p8>;
> + vdd3p3-supply = <_l18a_2p8>;
> +
> + pinctrl-names = "default", "suspend";
> + pinctrl-0 = <_pins_default>;
> + pinctrl-1 = <_pins_default>;
Is there a point for listing a suspend configuration if it is the same
as the default?
> + reset-gpios = <_gpio 3 GPIO_ACTIVE_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + panel0_in: endpoint {
> + remote-endpoint = <_out>;
The 'dsi0_out' node is added by 'arm64: dts: sc7180: add display dt nodes'
(https://patchwork.kernel.org/patch/11354253/), which has not landed. So
either you should list it as dependency below the commit message, or
(probably better) send the two patches in the same series.
> + };
> + };
> + };
> + };
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <_in>;
> + data-lanes = <0 1 2 3>;
> + };
> + };
> + };
> +};
> +
> +_phy {
Also this node does not exist yet, it also depends on the patch mentioned
above.
> + status = "okay";
> +};
> +
> {
> status = "okay";
> pinctrl-names = "default";
> @@ -289,6 +334,17 @@
>
> /* PINCTRL - additions to nodes defined in sc7180.dtsi */
>
> +_gpio {
> + disp_pins_default: disp-pins-default{
nit: missing blank before curly brace
If there is no suspend configuration you can get rid of the 'default'
suffix.
Since this is only a single pin I would suggest to use a name that
describes the function of the pin or the name used in the schematic
instead of 'disp-pins'.
Thanks
Matthias
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Re: [Freedreno] [PATCH] drm/msm: Fix a6xx GMU shutdown sequence
Hi Jordan,
On Thu, Jan 23, 2020 at 09:42:36AM -0700, Jordan Crouse wrote:
> Commit e812744c5f95 ("drm: msm: a6xx: Add support for A618") missed
> updating the VBIF flush in a6xx_gmu_shutdown and instead
> inserted the new sequence into a6xx_pm_suspend along with a redundant
> GMU idle.
>
> Move a6xx_bus_clear_pending_transactions to a6xx_gmu.c and use it in
> the appropriate place in the shutdown routine and remove the redundant
> idle call.
>
> Signed-off-by: Jordan Crouse
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 36 +
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43
> ---
> 2 files changed, 31 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 983afea..f371227 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>
> ...
>
> /* Gracefully try to shut down the GMU and by extension the GPU */
> static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
> {
> @@ -819,11 +849,7 @@ static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
> return;
> }
>
> - /* Clear the VBIF pipe before shutting down */
> - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
> - spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 0xf)
> - == 0xf);
> - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
> + a6xx_bus_clear_pending_transactions(adreno_gpu);
With this the variable 'gpu' isn't used anymore in a6xx_gmu_shutdown(),
please remove it.
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Re: [Freedreno] [PATCH v2 1/2] dt-bindings: display: add sc7180 panel variant
Hi,
On Tue, Jan 07, 2020 at 04:59:56PM +0530, Harigovindan P wrote:
> Subject: dt-bindings: display: add sc7180 panel variant
>
> Add a compatible string to support sc7180 panel version.
The sc7180 is a SoC, I suppose you are referring to the sc7180-idp, a
board based on this SoC. But even with the correct board name, this
isn't a good commit message. The board is irrelevant here, the display
could be used on dozens of other boards.
Apparently the panel is the Visionix RM69299, please use this instead
of 'sc7180'.
Thanks
Matthias
> Changes in v1:
> -Added a compatible string to support sc7180 panel version.
> Changes in v2:
> -Removed unwanted properties from description.
> -Creating source files without execute permissions(Rob Herring).
>
> Signed-off-by: Harigovindan P
> ---
> .../bindings/display/visionox,rm69299.txt | 48
> ++
> 1 file changed, 48 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/visionox,rm69299.txt
>
> diff --git a/Documentation/devicetree/bindings/display/visionox,rm69299.txt
> b/Documentation/devicetree/bindings/display/visionox,rm69299.txt
> new file mode 100644
> index 000..d7bbd5f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/visionox,rm69299.txt
> @@ -0,0 +1,48 @@
> +Visionox model RM69299 DSI display driver
> +
> +The Visionox RM69299 is a generic display driver, currently only configured
> +for use in the 1080p display on the Qualcomm SC7180 MTP board.
> +
> +Required properties:
> +- compatible: should be "visionox,rm69299-1080p-display"
> +- vdda-supply: phandle of the regulator that provides the supply voltage
> + Power IC supply
> +- vdd3p3-supply: phandle of the regulator that provides the supply voltage
> + Power IC supply
> +- reset-gpios: phandle of gpio for reset line
> + This should be 8mA, gpio can be configured using mux, pinctrl,
> pinctrl-names
> + (active low)
> +- ports: This device has one video port driven by one DSI. Their connections
> + are modeled using the OF graph bindings specified in
> + Documentation/devicetree/bindings/graph.txt.
> + - port@0: DSI input port driven by master DSI
> +
> +Example:
> +
> + dsi@ae94000 {
> + panel@0 {
> + compatible = "visionox,rm69299-1080p-display";
> + reg = <0>;
> +
> + vdda-supply = <_pp1800_l8c>;
> + vdd3p3-supply = <_pp2800_l18a>;
> +
> + pinctrl-names = "default", "suspend";
> + pinctrl-0 = <_pins_default>;
> + pinctrl-1 = <_pins_default>;
> +
> + reset-gpios = <_gpios 3 0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + panel0_in: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.7.4
>
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Re: [Freedreno] [PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob
Hi Sharat,
on which tree is this patch based on? It does not apply against
qcom/arm64-for-5.6-to-be-rebased.
In one of my repos which has a non-upstream Qualcomm tree as remote git can
make sense of the hashes in the index line, however the parent of your patch
looks quite different from the maintainer version.
Another thing that hints towards a custom tree:
> + interconnects = <_noc 35 _virt 512>;
To my knowledge no patches have been posted to add the referenced interconnect
nodes for SC7180.
Please base your patches on the appropriate maintainer tree(s).
Thanks
Matthias
On Tue, Dec 03, 2019 at 03:16:18PM +, Sharat Masetty wrote:
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
>
> Signed-off-by: Sharat Masetty
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 116
> +++
> 1 file changed, 116 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index c3db2e5..31223d0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -18,6 +18,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> / {
> interrupt-parent = <>;
> @@ -733,6 +735,120 @@
> #power-domain-cells = <1>;
> };
>
> + gpu: gpu@500 {
> + compatible = "qcom,adreno-618.0", "qcom,adreno";
> + #stream-id-cells = <16>;
> + reg = <0 0x500 0 0x4>, <0 0x509e000 0 0x1000>,
> + <0 0x5061000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
> +
> + interrupts = ;
> +
> + iommus = <_smmu 0>;
> +
> + operating-points-v2 = <_opp_table>;
> +
> + interconnects = <_noc 35 _virt 512>;
> +
> + qcom,gmu = <>;
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-8 {
> + opp-hz = /bits/ 64 <8>;
> + opp-level =
> ;
> + };
> +
> + opp-65000 {
> + opp-hz = /bits/ 64 <65000>;
> + opp-level =
> ;
> + };
> +
> + opp-56500 {
> + opp-hz = /bits/ 64 <56500>;
> + opp-level = ;
> + };
> +
> + opp-43000 {
> + opp-hz = /bits/ 64 <43000>;
> + opp-level =
> ;
> + };
> +
> +opp-35500 {
> + opp-hz = /bits/ 64 <35500>;
> + opp-level = ;
> + };
> +
> +opp-26700 {
> + opp-hz = /bits/ 64 <26700>;
> + opp-level =
> ;
> + };
> +
> + opp-18000 {
> + opp-hz = /bits/ 64 <18000>;
> + opp-level =
> ;
> + };
> + };
> + };
> +
> + adreno_smmu: iommu@504 {
> + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
> + reg = <0 0x504 0 0x1>;
> + #iommu-cells = <1>;
> + #global-interrupts = <2>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> + clocks = < GCC_GPU_MEMNOC_GFX_CLK>,
> + < GCC_GPU_CFG_AHB_CLK>,
> + < GCC_DDRSS_GPU_AXI_CLK>;
> +
> + clock-names = "bus", "iface", "mem_iface_clk";
> + power-domains = < CX_GDSC>;
> + };
> +
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu";
> +
> + reg = <0 0x506a000 0 0x31000>,
> + <0 0xb29 0 0x1>,
> + <0 0xb49 0 0x1>;
> +
Re: [Freedreno] [PATCH v1] drm/msm: add support for 2.4.1 DSI version for sc7180 soc
Hi,
On Fri, Nov 29, 2019 at 12:35:05PM +0530, Harigovindan P wrote:
> Changes in v1:
> -Modify commit text to indicate DSI version and SOC detail(Jeffrey
> Hugo).
> -Splitting visionox panel driver code out into a
>different patch(set), since panel drivers are merged into
>drm-next via a different tree(Rob Clark).
The change log shouldn't be part of the commit message, please place it
after the '---' separator.
I think at least a one line commit message besides the subject is
mandatory, so if you move the change log down you'll have to add
some short summary.
> Signed-off-by: Harigovindan P
> ---
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 21 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index b7b7c1a..7b967dd 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -133,6 +133,10 @@ static const char * const dsi_sdm845_bus_clk_names[] = {
> "iface", "bus",
> };
>
> +static const char * const dsi_sc7180_bus_clk_names[] = {
> + "iface", "bus",
> +};
> +
> static const struct msm_dsi_config sdm845_dsi_cfg = {
> .io_offset = DSI_6G_REG_SHIFT,
> .reg_cfg = {
> @@ -147,6 +151,20 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
> .num_dsi = 2,
> };
>
> +static const struct msm_dsi_config sc7180_dsi_cfg = {
> + .io_offset = DSI_6G_REG_SHIFT,
> + .reg_cfg = {
> + .num = 1,
> + .regs = {
> + {"vdda", 21800, 4 },/* 1.2 V */
> + },
> + },
> + .bus_clk_names = dsi_sc7180_bus_clk_names,
> + .num_bus_clks = ARRAY_SIZE(dsi_sc7180_bus_clk_names),
> + .io_start = { 0xae94000 },
> + .num_dsi = 1,
> +};
> +
> const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
> .link_clk_enable = dsi_link_clk_enable_v2,
> .link_clk_disable = dsi_link_clk_disable_v2,
> @@ -201,6 +219,9 @@ static const struct msm_dsi_cfg_handler
> dsi_cfg_handlers[] = {
> _dsi_cfg, _dsi_6g_v2_host_ops},
> {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
> _dsi_cfg, _dsi_6g_v2_host_ops},
> + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
> + _dsi_cfg, _dsi_6g_v2_host_ops},
> +
> };
>
> const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> index e2b7a7d..9919536 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> @@ -19,6 +19,7 @@
> #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
> #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x2000
> #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001
> +#define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
>
> #define MSM_DSI_V2_VER_MINOR_80640x0
>
> --
> 2.7.4
>
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Re: [Freedreno] [PATCH v5 0/8] drm/msm/dsi: Get PHY ref clocks from the DT
Hi, this series has gone through multiple rounds of review and there are no outstanding comments. It seems it should be ready to land, or is there anything left that needs to be addressed? Thanks Matthias On Wed, Dec 19, 2018 at 03:55:20PM -0800, Matthias Kaehlcke wrote: > The MSM DSI PHY drivers currently hardcode the name and the rate of > the PHY ref clock. Get the ref clock from the device tree instead. > > Note: testing of this series was limited to SDM845 and the 10nm PHY > > Major changes in v5: > - none (see per-patch change log for minor changes) > > Major changes in v4: > - always use parent rate for 28nm and 28nm 8960 PHYs > > Major changes in v3: > - keep supporting DTs without ref clock for the 28nm and the 28nm > 8960 PHYs > - added patch to add ref clock to qcom-apq8064.dtsi > > Major changes in v2: > - apply to all MSM DSI PHY drivers, not only 10nm > > Matthias Kaehlcke (8): > dt-bindings: msm/dsi: Add ref clock for PHYs > drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT > drm/msm/dsi: 28nm PHY: Get ref clock from the DT > drm/msm/dsi: 14nm PHY: Get ref clock from the DT > drm/msm/dsi: 10nm PHY: Get ref clock from the DT > arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY > arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs > ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY > > .../devicetree/bindings/display/msm/dsi.txt | 1 + > arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +-- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +-- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++--- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c| 20 +-- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c| 23 +--- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c| 36 +-- > .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 ++--- > 8 files changed, 92 insertions(+), 32 deletions(-) > ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v5:
- added "Reviewed-by: Stephen Boyd " tag
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
- updated commit message
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
.../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 +++
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 49008451085b8..76e5188169b91 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -47,7 +47,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 2700
#define VCO_MIN_RATE 6
#define VCO_MAX_RATE 12
@@ -125,7 +124,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
- val = VCO_REF_CLK_RATE / 10;
+ val = parent_rate / 10;
fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
fb_divider = fb_divider / 2 - 1;
pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
@@ -406,11 +405,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
pll_28nm->clks, pll_28nm->num_clks);
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+const char *ref_clk_name)
{
char *clk_name, *parent_name, *vco_name;
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "pxo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.flags = CLK_IGNORE_UNUSED,
.ops = _ops_dsi_pll_28nm_vco,
@@ -494,6 +494,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -506,6 +508,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id + 1;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ return ERR_PTR(ret);
+
+ dev_warn(>dev, "'ref' clock is not specified, using
default name\n");
+ vco_ref_clk_name = "pxo";
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(>dev, "%s: failed to map pll base\n", __func__);
@@ -524,7 +538,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll->en_seq_cnt = 1;
pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
- ret = pll_28nm_register(pll_28nm);
+ ret = pll_28nm_register(pll_28nm, vco_ref_clk_name);
if (ret) {
dev_err(>dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
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[Freedreno] [PATCH v5 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs
Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring --- Changes in v5: - added "Reviewed-by: Rob Herring " tag Changes in v4: - added "Reviewed-by" tags from Stephen and Doug Changes in v3: - added note that the ref clock is only required for new DTS files/entries Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd tag
---
Changes in v5:
- added missing return keyword in msm_dsi_pll_28nm_init()
- added "Reviewed-by: Stephen Boyd " tag
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate() and
dsi_pll_28nm_clk_recalc_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
- updated commit message
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
unsigned long
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 26e3a01a99c2b..c839464741927 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 35000
#define VCO_MAX_RATE 75000
@@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
- rem = rate % VCO_REF_CLK_RATE;
+ rem = rate % parent_rate;
if (rem) {
refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
frac_n_mode = 1;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
+ div_fbx1000 = rate / (parent_rate / 500);
+ gen_vco_clk = div_fbx1000 * (parent_rate / 500);
} else {
refclk_cfg = 0x0;
frac_n_mode = 0;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
+ div_fbx1000 = rate / (parent_rate / 1000);
+ gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
}
DBG("refclk_cfg = %d", refclk_cfg);
@@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
void __iomem *base = pll_28nm->mmio;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
- u32 ref_clk = VCO_REF_CLK_RATE;
+ u32 ref_clk = parent_rate;
unsigned long vco_rate;
VERB("parent_rate=%lu", parent_rate);
@@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
/* Check to see if the ref clk doubler is enabled */
doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
- ref_clk += (doubler * VCO_REF_CLK_RATE);
+ ref_clk += (doubler * ref_clk);
/* see if it is integer mode or sdm mode */
sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
@@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
pll_28nm->clk_data.clk_num = 0;
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+const char *ref_clk_name)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ return ERR_PTR(ret);
+
+ dev_warn(>dev, "'ref' clock is not specified, using
default name\n");
+ vco_ref_clk_name = "xo";
+ }
+
pll_28n
[Freedreno] [PATCH v5 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register() instead of storing a point
to the clk object in the PLL data structure
Changes in v4:
- none
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 23 +-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index 71fe60e5f01f1..9a647d93a7e0b 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 13UL
#define VCO_MAX_RATE 26UL
@@ -591,7 +590,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw,
unsigned long rate,
parent_rate);
pll_14nm->vco_current_rate = rate;
- pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
+ pll_14nm->vco_ref_clk_rate = parent_rate;
dsi_pll_14nm_input_init(pll_14nm);
@@ -947,11 +946,12 @@ static struct clk_hw *pll_14nm_postdiv_register(struct
dsi_pll_14nm *pll_14nm,
return _postdiv->hw;
}
-static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
+static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm,
+const char *ref_clk_name)
{
char clk_name[32], parent[32], vco_name[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -1050,6 +1050,8 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
{
struct dsi_pll_14nm *pll_14nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -1065,6 +1067,17 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
pll_14nm->id = id;
pll_14nm_list[id] = pll_14nm;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(vco_ref_clk)) {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+
pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
@@ -1094,7 +1107,7 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
pll->en_seq_cnt = 1;
pll->enable_seqs[0] = dsi_pll_14nm_enable_seq;
- ret = pll_14nm_register(pll_14nm);
+ ret = pll_14nm_register(pll_14nm, vco_ref_clk_name);
if (ret) {
dev_err(>dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
2.20.1.415.g653613c723-goog
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[Freedreno] [PATCH v5 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register() instead of storing a point
to the clk object in the PLL data structure
Changes in v4:
- none
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
- updated commit message
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..adbe5395f4f38 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -625,12 +625,14 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
* state to follow the master PLL's divider/mux state. Therefore, we don't
* require special clock ops that also configure the slave PLL registers
*/
-static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
+static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm,
+const char *ref_clk_name)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
+
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -771,6 +773,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
{
struct dsi_pll_10nm *pll_10nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -786,6 +790,16 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(vco_ref_clk)) {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
@@ -811,7 +825,7 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->vco_delay = 1;
- ret = pll_10nm_register(pll_10nm);
+ ret = pll_10nm_register(pll_10nm, vco_ref_clk_name);
if (ret) {
dev_err(>dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
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[Freedreno] [PATCH v5 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v5: - none Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = < GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = < GCC_MDSS_AHB_CLK>, +<_board>; + clock-names = "iface", "ref"; }; }; -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- Changes in v5: - none Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = < DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = < DSI_M_AHB_CLK>, +<_board>; }; -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 10nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- based on "[v6] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file" (https://patchwork.kernel.org/patch/10712827/) Changes in v5: - rebased on v6 of DPU DT patch Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 3e3ffe096f18a..f278f08906d21 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1378,8 +1378,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = < DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = < DISP_CC_MDSS_AHB_CLK>, +< RPMH_CXO_CLK>; + clock-names = "iface", "ref"; status = "disabled"; }; @@ -1444,8 +1445,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = < DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = < DISP_CC_MDSS_AHB_CLK>, +< RPMH_CXO_CLK>; + clock-names = "iface", "ref"; status = "disabled"; }; -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 0/8] drm/msm/dsi: Get PHY ref clocks from the DT
The MSM DSI PHY drivers currently hardcode the name and the rate of the PHY ref clock. Get the ref clock from the device tree instead. Note: testing of this series was limited to SDM845 and the 10nm PHY Major changes in v5: - none (see per-patch change log for minor changes) Major changes in v4: - always use parent rate for 28nm and 28nm 8960 PHYs Major changes in v3: - keep supporting DTs without ref clock for the 28nm and the 28nm 8960 PHYs - added patch to add ref clock to qcom-apq8064.dtsi Major changes in v2: - apply to all MSM DSI PHY drivers, not only 10nm Matthias Kaehlcke (8): dt-bindings: msm/dsi: Add ref clock for PHYs drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT drm/msm/dsi: 28nm PHY: Get ref clock from the DT drm/msm/dsi: 14nm PHY: Get ref clock from the DT drm/msm/dsi: 10nm PHY: Get ref clock from the DT arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY .../devicetree/bindings/display/msm/dsi.txt | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c| 20 +-- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c| 23 +--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c| 36 +-- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 ++--- 8 files changed, 92 insertions(+), 32 deletions(-) -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > index 71fe60e5f01f1..032bf3e8614bd 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > @@ -40,7 +40,6 @@
> >
> > #define NUM_PROVIDED_CLKS 2
> >
> > -#define VCO_REF_CLK_RATE 1920
> > #define VCO_MIN_RATE 13UL
> > #define VCO_MAX_RATE 26UL
> >
> > @@ -139,6 +138,7 @@ struct dsi_pll_14nm {
> > /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
> > spinlock_t postdiv_lock;
> >
> > + struct clk *vco_ref_clk;
>
> Is there any need to keep it in the struct? Or just get the clk, find
> the rate, and then put the clk and call pll_14nm_postdiv_register()?
I suppose you mean passing the clock name to pll_14nm_register()?
Is putting the clock really needed or preferable, or is it just fine
to auto-put it when the device is deleted?
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Re: [Freedreno] [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Hi Niklas,
On Wed, Dec 12, 2018 at 11:07:17PM +0100, Niklas Cassel wrote:
> On Tue, Dec 04, 2018 at 02:42:29PM -0800, Matthias Kaehlcke wrote:
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > Changes in v4:
> > - always use parent rate in dsi_pll_28nm_clk_set_rate() and
> >dsi_pll_28nm_clk_recalc_rate()
> > - pass name of VCO ref clock to pll_28nm_register() instead of
> > storing it in a struct field
> > - updated commit message
> >
> > Changes in v3:
> > - use default name and rate if the ref clock is not specified
> > in the DT
> > - store vco_ref_clk_name instead of vco_ref_clk
> > - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
> > unsigned long
> > - fixed check for EPROBE_DEFER
> > - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
> >
> > Changes in v2:
> > - patch added to the series
> > ---
> > drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++---
> > 1 file changed, 25 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > index 26e3a01a99c2b..340b03e8d 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > @@ -40,7 +40,6 @@
> >
> > #define NUM_PROVIDED_CLKS 2
> >
> > -#define VCO_REF_CLK_RATE 1920
> > #define VCO_MIN_RATE 35000
> > #define VCO_MAX_RATE 75000
> >
> > @@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> > *hw, unsigned long rate,
> > pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
> > pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
> >
> > - rem = rate % VCO_REF_CLK_RATE;
> > + rem = rate % parent_rate;
> > if (rem) {
> > refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> > frac_n_mode = 1;
> > - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
> > - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
> > + div_fbx1000 = rate / (parent_rate / 500);
> > + gen_vco_clk = div_fbx1000 * (parent_rate / 500);
> > } else {
> > refclk_cfg = 0x0;
> > frac_n_mode = 0;
> > - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
> > - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
> > + div_fbx1000 = rate / (parent_rate / 1000);
> > + gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
> > }
> >
> > DBG("refclk_cfg = %d", refclk_cfg);
> > @@ -265,7 +264,7 @@ static unsigned long
> > dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> > void __iomem *base = pll_28nm->mmio;
> > u32 sdm0, doubler, sdm_byp_div;
> > u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> > - u32 ref_clk = VCO_REF_CLK_RATE;
> > + u32 ref_clk = parent_rate;
> > unsigned long vco_rate;
> >
> > VERB("parent_rate=%lu", parent_rate);
> > @@ -273,7 +272,7 @@ static unsigned long
> > dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> > /* Check to see if the ref clk doubler is enabled */
> > doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
> > DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> > - ref_clk += (doubler * VCO_REF_CLK_RATE);
> > + ref_clk += (doubler * ref_clk);
> >
> > /* see if it is integer mode or sdm mode */
> > sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
> > @@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll
> > *pll)
> > pll_28nm->clk_data.clk_num = 0;
> > }
> >
> > -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> > +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
> > +const char *ref_clk_name)
> > {
> > char clk_name[32], parent1[32], parent2[32], vco_name[32];
> > struct clk_init_data vco_init = {
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_names = _clk_name,
> > .num_parents = 1,
> > .name = vco_name,
> > .flags = CLK_IGNORE_UNUSED,
> > @@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
> > platform_device *pdev,
> >
[Freedreno] [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate() and
dsi_pll_28nm_clk_recalc_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
- updated commit message
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
unsigned long
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 26e3a01a99c2b..340b03e8d 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 35000
#define VCO_MAX_RATE 75000
@@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
- rem = rate % VCO_REF_CLK_RATE;
+ rem = rate % parent_rate;
if (rem) {
refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
frac_n_mode = 1;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
+ div_fbx1000 = rate / (parent_rate / 500);
+ gen_vco_clk = div_fbx1000 * (parent_rate / 500);
} else {
refclk_cfg = 0x0;
frac_n_mode = 0;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
+ div_fbx1000 = rate / (parent_rate / 1000);
+ gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
}
DBG("refclk_cfg = %d", refclk_cfg);
@@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
void __iomem *base = pll_28nm->mmio;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
- u32 ref_clk = VCO_REF_CLK_RATE;
+ u32 ref_clk = parent_rate;
unsigned long vco_rate;
VERB("parent_rate=%lu", parent_rate);
@@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
/* Check to see if the ref clk doubler is enabled */
doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
- ref_clk += (doubler * VCO_REF_CLK_RATE);
+ ref_clk += (doubler * ref_clk);
/* see if it is integer mode or sdm mode */
sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
@@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
pll_28nm->clk_data.clk_num = 0;
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+const char *ref_clk_name)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ ERR_PTR(ret);
+
+ dev_warn(>dev, "'ref' clock is not specified, using
default name\n");
+ vco_ref_clk_name = "xo";
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(>dev, "%s: failed to map
[Freedreno] [PATCH v4 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
- updated commit message
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
.../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 +++
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 49008451085b8..76e5188169b91 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -47,7 +47,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 2700
#define VCO_MIN_RATE 6
#define VCO_MAX_RATE 12
@@ -125,7 +124,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
- val = VCO_REF_CLK_RATE / 10;
+ val = parent_rate / 10;
fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
fb_divider = fb_divider / 2 - 1;
pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
@@ -406,11 +405,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
pll_28nm->clks, pll_28nm->num_clks);
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+const char *ref_clk_name)
{
char *clk_name, *parent_name, *vco_name;
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "pxo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.flags = CLK_IGNORE_UNUSED,
.ops = _ops_dsi_pll_28nm_vco,
@@ -494,6 +494,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -506,6 +508,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id + 1;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ return ERR_PTR(ret);
+
+ dev_warn(>dev, "'ref' clock is not specified, using
default name\n");
+ vco_ref_clk_name = "pxo";
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(>dev, "%s: failed to map pll base\n", __func__);
@@ -524,7 +538,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll->en_seq_cnt = 1;
pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
- ret = pll_28nm_register(pll_28nm);
+ ret = pll_28nm_register(pll_28nm, vco_ref_clk_name);
if (ret) {
dev_err(>dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
2.20.0.rc1.387.gf8505762e3-goog
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[Freedreno] [PATCH v4 0/8] drm/msm/dsi: Get PHY ref clocks from the DT
The MSM DSI PHY drivers currently hardcode the name and the rate of the PHY ref clock. Get the ref clock from the device tree instead. Note: testing of this series was limited to SDM845 and the 10nm PHY Major changes in v4: - always use parent rate for 28nm and 28nm 8960 PHYs Major changes in v3: - keep supporting DTs without ref clock for the 28nm and the 28nm 8960 PHYs - added patch to add ref clock to qcom-apq8064.dtsi Major changes in v2: - apply to all MSM DSI PHY drivers, not only 10nm Matthias Kaehlcke (8): dt-bindings: msm/dsi: Add ref clock for PHYs drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT drm/msm/dsi: 28nm PHY: Get ref clock from the DT drm/msm/dsi: 14nm PHY: Get ref clock from the DT drm/msm/dsi: 10nm PHY: Get ref clock from the DT arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY .../devicetree/bindings/display/msm/dsi.txt | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c| 13 ++- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c| 16 +++-- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c| 36 +-- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 ++--- 8 files changed, 82 insertions(+), 28 deletions(-) -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v4 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v4:
- none
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
- updated commit message
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..2d23372acd20d 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -91,6 +91,7 @@ struct dsi_pll_10nm {
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
+ struct clk *vco_ref_clk;
u64 vco_ref_clk_rate;
u64 vco_current_rate;
@@ -629,8 +630,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
+ const char *ref_clk_name = __clk_get_name(pll_10nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -786,6 +788,15 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
+ pll_10nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_10nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_10nm->vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
--
2.20.0.rc1.387.gf8505762e3-goog
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[Freedreno] [PATCH v4 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
(https://patchwork.kernel.org/patch/10666253/)
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes in v3:
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5728b4cfae269..cdb5a9bb23e69 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1372,8 +1372,9 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = < DISP_CC_MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
};
dsi1: dsi@ae96000 {
@@ -1434,8 +1435,9 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = < DISP_CC_MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
};
};
--
2.20.0.rc1.387.gf8505762e3-goog
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[Freedreno] [PATCH v4 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = < DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = < DSI_M_AHB_CLK>, +<_board>; }; -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v4 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs
Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson --- Chnages in v4: - added "Reviewed-by" tags from Stephen and Doug Changes in v3: - added note that the ref clock is only required for new DTS files/entries Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v4:
- none
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index 71fe60e5f01f1..032bf3e8614bd 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 13UL
#define VCO_MAX_RATE 26UL
@@ -139,6 +138,7 @@ struct dsi_pll_14nm {
/* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
+ struct clk *vco_ref_clk;
u64 vco_current_rate;
u64 vco_ref_clk_rate;
@@ -591,7 +591,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw,
unsigned long rate,
parent_rate);
pll_14nm->vco_current_rate = rate;
- pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
+ pll_14nm->vco_ref_clk_rate = parent_rate;
dsi_pll_14nm_input_init(pll_14nm);
@@ -950,8 +950,9 @@ static struct clk_hw *pll_14nm_postdiv_register(struct
dsi_pll_14nm *pll_14nm,
static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
{
char clk_name[32], parent[32], vco_name[32];
+ const char *ref_clk_name = __clk_get_name(pll_14nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -1065,6 +1066,15 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
pll_14nm->id = id;
pll_14nm_list[id] = pll_14nm;
+ pll_14nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_14nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_14nm->vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
--
2.20.0.rc1.387.gf8505762e3-goog
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[Freedreno] [PATCH v4 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = < GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = < GCC_MDSS_AHB_CLK>, +<_board>; + clock-names = "iface", "ref"; }; }; -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v3 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate. Use default values if the ref
> > clock is not specified.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > Changes in v3:
> > - use default name and rate if the ref clock is not specified
> > in the DT
> > - store vco_ref_clk_name instead of vco_ref_clk
> > - fixed check for EPROBE_DEFER
> > - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
> >
> > Changes in v2:
> > - patch added to the series
> > ---
> > .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 +++
> > 1 file changed, 23 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
> > index 49008451085b8..3af678d3317f6 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
> > @@ -47,9 +47,9 @@
> >
> > #define NUM_PROVIDED_CLKS 2
> >
> > -#define VCO_REF_CLK_RATE 2700
> > -#define VCO_MIN_RATE 6
> > -#define VCO_MAX_RATE 12
> > +#define VCO_REF_CLK_DEFAULT_RATE 2700
> > +#define VCO_MIN_RATE 6
> > +#define VCO_MAX_RATE 12
> >
> > #define DSI_BYTE_PLL_CLK 0
> > #define DSI_PIXEL_PLL_CLK 1
> > @@ -75,6 +75,8 @@ struct dsi_pll_28nm {
> > struct platform_device *pdev;
> > void __iomem *mmio;
> >
> > + const char *vco_ref_clk_name;
>
> Can this be passed around during clk registration so we don't have to
> store it away in the structure?
makes sense, will do
> > +
> > /* custom byte clock divider */
> > struct clk_bytediv *bytediv;
> >
> > @@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> > *hw, unsigned long rate,
> > DBG("rate=%lu, parent's=%lu", rate, parent_rate);
> >
> > temp = rate / 10;
> > - val = VCO_REF_CLK_RATE / 10;
> > + if (parent_rate)
> > + val = parent_rate / 10;
> > + else
> > + val = VCO_REF_CLK_DEFAULT_RATE / 10;
>
> Is the clk not properly hooked up to a parent sometimes so parent_rate
> is 0? That sounds odd given the fact that it used to be 'pxo' and that
> has always existed on the system as 27 MHz. So I'd remove this and just
> use parent_rate all the time.
I wondered about this, but since I don't have hardware for testing I
kept the previous hardcoded rate. If we know for sure that 'pxo'
always exists it should indeed be fine to use the parent rate.
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Re: [Freedreno] [PATCH v3 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY
On Tue, Dec 04, 2018 at 08:48:22AM -0800, Stephen Boyd wrote: > Quoting Matthias Kaehlcke (2018-11-30 16:52:54) > > Add 'xo_board' as ref clock for the DSI PHY, it was previously > > hardcoded in the PLL 'driver' for the 28nm 8960 PHY. > > Why is driver in quotes? It's not really a full fledged driver, but part of the 28nm 8960 PHY driver. > > > > Signed-off-by: Matthias Kaehlcke > > Reviewed-by: Stephen Boyd Thanks for the review! ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate. Use default values if the ref
clock is not specified.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
unsigned long
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 35 --
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 26e3a01a99c2b..4a84c69ca0b2b 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -40,7 +40,7 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
+#define VCO_REF_CLK_DEFAULT_RATE 1920
#define VCO_MIN_RATE 35000
#define VCO_MAX_RATE 75000
@@ -81,6 +81,7 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
+ const char *vco_ref_clk_name;
int vco_delay;
/* private clocks: */
@@ -139,6 +140,8 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = _28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
+ unsigned long ref_clk_rate = parent_rate ?
+ parent_rate : VCO_REF_CLK_DEFAULT_RATE;
unsigned long div_fbx1000, gen_vco_clk;
u32 refclk_cfg, frac_n_mode, frac_n_value;
u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
@@ -166,17 +169,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
- rem = rate % VCO_REF_CLK_RATE;
+ rem = rate % ref_clk_rate;
if (rem) {
refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
frac_n_mode = 1;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
+ div_fbx1000 = rate / (ref_clk_rate / 500);
+ gen_vco_clk = div_fbx1000 * (ref_clk_rate / 500);
} else {
refclk_cfg = 0x0;
frac_n_mode = 0;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
+ div_fbx1000 = rate / (ref_clk_rate / 1000);
+ gen_vco_clk = div_fbx1000 * (ref_clk_rate / 1000);
}
DBG("refclk_cfg = %d", refclk_cfg);
@@ -265,7 +268,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
void __iomem *base = pll_28nm->mmio;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
- u32 ref_clk = VCO_REF_CLK_RATE;
+ u32 ref_clk = parent_rate ?
+ parent_rate : VCO_REF_CLK_DEFAULT_RATE;
unsigned long vco_rate;
VERB("parent_rate=%lu", parent_rate);
@@ -273,7 +277,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
/* Check to see if the ref clk doubler is enabled */
doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
- ref_clk += (doubler * VCO_REF_CLK_RATE);
+ ref_clk += (doubler * ref_clk);
/* see if it is integer mode or sdm mode */
sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
@@ -518,7 +522,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _28nm->vco_ref_clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -593,6 +597,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
int ret;
if (!pdev)
@@ -605,6 +610,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ pll_28nm->vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+
[Freedreno] [PATCH v3 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index 71fe60e5f01f1..032bf3e8614bd 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 13UL
#define VCO_MAX_RATE 26UL
@@ -139,6 +138,7 @@ struct dsi_pll_14nm {
/* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
+ struct clk *vco_ref_clk;
u64 vco_current_rate;
u64 vco_ref_clk_rate;
@@ -591,7 +591,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw,
unsigned long rate,
parent_rate);
pll_14nm->vco_current_rate = rate;
- pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
+ pll_14nm->vco_ref_clk_rate = parent_rate;
dsi_pll_14nm_input_init(pll_14nm);
@@ -950,8 +950,9 @@ static struct clk_hw *pll_14nm_postdiv_register(struct
dsi_pll_14nm *pll_14nm,
static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
{
char clk_name[32], parent[32], vco_name[32];
+ const char *ref_clk_name = __clk_get_name(pll_14nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -1065,6 +1066,15 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
pll_14nm->id = id;
pll_14nm_list[id] = pll_14nm;
+ pll_14nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_14nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_14nm->vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
--
2.20.0.rc1.387.gf8505762e3-goog
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[Freedreno] [PATCH v3 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke --- Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = < DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = < DSI_M_AHB_CLK>, +<_board>; }; -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
- updated commit message
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..2d23372acd20d 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -91,6 +91,7 @@ struct dsi_pll_10nm {
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
+ struct clk *vco_ref_clk;
u64 vco_ref_clk_rate;
u64 vco_current_rate;
@@ -629,8 +630,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
+ const char *ref_clk_name = __clk_get_name(pll_10nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -786,6 +788,15 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
+ pll_10nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_10nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_10nm->vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
--
2.20.0.rc1.387.gf8505762e3-goog
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[Freedreno] [PATCH v3 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
(https://patchwork.kernel.org/patch/10666253/)
Changes in v3:
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5728b4cfae269..cdb5a9bb23e69 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1372,8 +1372,9 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = < DISP_CC_MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
};
dsi1: dsi@ae96000 {
@@ -1434,8 +1435,9 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = < DISP_CC_MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
};
};
--
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[Freedreno] [PATCH v3 0/8] drm/msm/dsi: Get PHY ref clocks from the DT
The MSM DSI PHY drivers currently hardcode the name and the rate of the PHY ref clock. Get the ref clock from the device tree instead. Note: testing of this series was limited to SDM845 and the 10nm PHY Major changes in v3: - keep supporting DTs without ref clock for the 28nm and the 28nm 8960 PHYs - added patch to add ref clock to qcom-apq8064.dtsi Major changes in v2: - apply to all MSM DSI PHY drivers, not only 10nm Matthias Kaehlcke (8): dt-bindings: msm/dsi: Add ref clock for PHYs drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT drm/msm/dsi: 28nm PHY: Get ref clock from the DT drm/msm/dsi: 14nm PHY: Get ref clock from the DT drm/msm/dsi: 10nm PHY: Get ref clock from the DT arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY .../devicetree/bindings/display/msm/dsi.txt | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c| 13 ++- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c| 16 +++-- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c| 35 ++- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 --- 8 files changed, 87 insertions(+), 26 deletions(-) -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson --- Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = < GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = < GCC_MDSS_AHB_CLK>, +<_board>; + clock-names = "iface", "ref"; }; }; -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate. Use default values if the ref
clock is not specified.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
.../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 +++
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 49008451085b8..3af678d3317f6 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -47,9 +47,9 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 2700
-#define VCO_MIN_RATE 6
-#define VCO_MAX_RATE 12
+#define VCO_REF_CLK_DEFAULT_RATE 2700
+#define VCO_MIN_RATE 6
+#define VCO_MAX_RATE 12
#define DSI_BYTE_PLL_CLK 0
#define DSI_PIXEL_PLL_CLK 1
@@ -75,6 +75,8 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
+ const char *vco_ref_clk_name;
+
/* custom byte clock divider */
struct clk_bytediv *bytediv;
@@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
- val = VCO_REF_CLK_RATE / 10;
+ if (parent_rate)
+ val = parent_rate / 10;
+ else
+ val = VCO_REF_CLK_DEFAULT_RATE / 10;
fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
fb_divider = fb_divider / 2 - 1;
pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
@@ -410,7 +415,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
{
char *clk_name, *parent_name, *vco_name;
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "pxo" },
+ .parent_names = _28nm->vco_ref_clk_name,
.num_parents = 1,
.flags = CLK_IGNORE_UNUSED,
.ops = _ops_dsi_pll_28nm_vco,
@@ -494,6 +499,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
int ret;
if (!pdev)
@@ -506,6 +512,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id + 1;
+ vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ pll_28nm->vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ return ERR_PTR(ret);
+
+ dev_warn(>dev, "'ref' clock is not specified, using
default name\n");
+ pll_28nm->vco_ref_clk_name = "pxo";
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(>dev, "%s: failed to map pll base\n", __func__);
--
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[Freedreno] [PATCH v3 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs
Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke --- Changes in V3: - added note that the ref clock is only required for new DTS files/entries Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: -- 2.20.0.rc1.387.gf8505762e3-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v2 3/7] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
On Tue, Nov 27, 2018 at 10:00:50PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> > @@ -409,8 +410,9 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll
> > *pll)
> > static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> > {
> > char *clk_name, *parent_name, *vco_name;
> > + const char *ref_clk_name = __clk_get_name(pll_28nm->vco_ref_clk);
>
> IMO for the 28nm PHY driver you should probably make things work OK
> even if the "ref" clock wasn't supplied. In the spirit of the stable
> device tree it would be nice (even if nobody actually ships device
> trees separate from kernels). ...and also it makes the whole thing
> easier to land. If you add compatibility here then the code and
> device tree patch can go in separately.
Ok, I'll make it fall back to the 'default' values if the ref clock is
not specified.
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Re: [Freedreno] [PATCH v2 2/7] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
On Tue, Nov 27, 2018 at 09:56:46PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> >
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
>
> In the case of the 14nm PHY I think it's OK that you break
> compatibility with old device tree files (as this patch does) since
> the 14nm support was added sorta recently and "git grep" shows no
> users in linuxnext. You should note that you're breaking
> compatibility with old DTS files in the commit message here so that if
> someone crawls out of the woodwork it will be easy for them to
> understand what happened.
ok, I'll add the note
> > + pll_14nm->vco_ref_clk = devm_clk_get(>dev, "ref");
> > + if (IS_ERR(pll_14nm->vco_ref_clk)) {
> > + ret = PTR_ERR(pll_14nm->vco_ref_clk);
> > + if (ret != EPROBE_DEFER)
>
> Shouldn't this check against -EPROBE_DEFER, not against EPROBE_DEFER?
> It's negative. Presumably this same feedback needs to be applied to
> the whole patch series.
You are right, will fix it throughout the series, thanks!
> Other than that this looks good to me and you can feel free to add my
> Reviewed-by tag FWIW.
Great, thanks for the review!
Matthias
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Re: [Freedreno] [PATCH v2 1/7] dt-bindings: msm/dsi: Add ref clock for PHYs
On Tue, Nov 27, 2018 at 09:41:39PM -0800, Doug Anderson wrote: > Hi, > > On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote: > > > > Allow the PHY drivers to get the ref clock from the DT. > > > > Signed-off-by: Matthias Kaehlcke > > --- > > Changes in v2: > > - add the ref clock for all PHYs, not only the 10nm one > > - updated commit message > > --- > > Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt > > b/Documentation/devicetree/bindings/display/msm/dsi.txt > > index dfc743219bd88..b0485559a719c 100644 > > --- a/Documentation/devicetree/bindings/display/msm/dsi.txt > > +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt > > @@ -106,6 +106,7 @@ Required properties: > > - clocks: Phandles to device clocks. See [1] for details on clock bindings. > > - clock-names: the following clocks are required: > >* "iface" > > + * "ref" > > We can't quite make ref "required" because there are some old device > tree files dating back to 2016 that would be broken. It could be > listed as optional, but I _think_ Rob is OK with it being listed as > "required" for all new device tree files with the footnote that if > it's not present then the code will still work. Ok, will update the code to keep supporting old DT files and update the description. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 6/7] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
(https://patchwork.kernel.org/patch/10666253/)
Changes in v2:
- patch added to the series
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5728b4cfae269..cdb5a9bb23e69 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1372,8 +1372,9 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = < DISP_CC_MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
};
dsi1: dsi@ae96000 {
@@ -1434,8 +1435,9 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = < DISP_CC_MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
};
};
--
2.20.0.rc0.387.gc7a69e6b6c-goog
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[Freedreno] [PATCH v2 1/7] dt-bindings: msm/dsi: Add ref clock for PHYs
Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke --- Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..b0485559a719c 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: -- 2.20.0.rc0.387.gc7a69e6b6c-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 7/7] drm/msm/dsi: 10nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
- updated commit message
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..32e31574e1432 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -91,6 +91,7 @@ struct dsi_pll_10nm {
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
+ struct clk *vco_ref_clk;
u64 vco_ref_clk_rate;
u64 vco_current_rate;
@@ -629,8 +630,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
+ const char *ref_clk_name = __clk_get_name(pll_10nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -786,6 +788,15 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
+ pll_10nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_10nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_10nm->vco_ref_clk);
+ if (ret != EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
--
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[Freedreno] [PATCH v2 4/7] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke --- Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = < GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = < GCC_MDSS_AHB_CLK>, +<_board>; + clock-names = "iface", "ref"; }; }; -- 2.20.0.rc0.387.gc7a69e6b6c-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 5/7] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 29 +++---
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 26e3a01a99c2b..a1ab5ecbf7c7d 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 35000
#define VCO_MAX_RATE 75000
@@ -81,6 +80,7 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
+ struct clk *vco_ref_clk;
int vco_delay;
/* private clocks: */
@@ -139,6 +139,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = _28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
+ u64 ref_clk_rate = parent_rate;
unsigned long div_fbx1000, gen_vco_clk;
u32 refclk_cfg, frac_n_mode, frac_n_value;
u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
@@ -166,17 +167,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
- rem = rate % VCO_REF_CLK_RATE;
+ rem = rate % ref_clk_rate;
if (rem) {
refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
frac_n_mode = 1;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
+ div_fbx1000 = rate / (ref_clk_rate / 500);
+ gen_vco_clk = div_fbx1000 * (ref_clk_rate / 500);
} else {
refclk_cfg = 0x0;
frac_n_mode = 0;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
+ div_fbx1000 = rate / (ref_clk_rate / 1000);
+ gen_vco_clk = div_fbx1000 * (ref_clk_rate / 1000);
}
DBG("refclk_cfg = %d", refclk_cfg);
@@ -265,7 +266,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
void __iomem *base = pll_28nm->mmio;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
- u32 ref_clk = VCO_REF_CLK_RATE;
+ u32 ref_clk = parent_rate;
unsigned long vco_rate;
VERB("parent_rate=%lu", parent_rate);
@@ -273,7 +274,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
/* Check to see if the ref clk doubler is enabled */
doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
- ref_clk += (doubler * VCO_REF_CLK_RATE);
+ ref_clk += (doubler * ref_clk);
/* see if it is integer mode or sdm mode */
sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
@@ -517,8 +518,9 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
+ const char *ref_clk_name = __clk_get_name(pll_28nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -605,6 +607,15 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id;
+ pll_28nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_28nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_28nm->vco_ref_clk);
+ if (ret != EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(>dev, "%s: failed to map pll base\n", __func__);
--
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[Freedreno] [PATCH v2 3/7] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 49008451085b8..461975c410fc4 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -47,7 +47,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 2700
#define VCO_MIN_RATE 6
#define VCO_MAX_RATE 12
@@ -75,6 +74,8 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
+ struct clk *vco_ref_clk;
+
/* custom byte clock divider */
struct clk_bytediv *bytediv;
@@ -125,7 +126,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
- val = VCO_REF_CLK_RATE / 10;
+ val = parent_rate / 10;
fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
fb_divider = fb_divider / 2 - 1;
pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
@@ -409,8 +410,9 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
{
char *clk_name, *parent_name, *vco_name;
+ const char *ref_clk_name = __clk_get_name(pll_28nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "pxo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.flags = CLK_IGNORE_UNUSED,
.ops = _ops_dsi_pll_28nm_vco,
@@ -506,6 +508,15 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id + 1;
+ pll_28nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_28nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_28nm->vco_ref_clk);
+ if (ret != EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(>dev, "%s: failed to map pll base\n", __func__);
--
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[Freedreno] [PATCH v2 0/7] drm/msm/dsi: Get PHY ref clocks from the DT
The MSM DSI PHY drivers currently hardcode the name and the rate of the PHY ref clock. Get the ref clock from the device tree instead. Note: testing of this series was limited to SDM845 and the 10nm PHY Major changes in v2: - apply to all MSM DSI PHY drivers, not only 10nm Matthias Kaehlcke (7): dt-bindings: msm/dsi: Add ref clock for PHYs drm/msm/dsi: 14nm PHY: Get ref clock from the DT drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY drm/msm/dsi: 28nm PHY: Get ref clock from the DT arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs drm/msm/dsi: 10nm PHY: Get ref clock from the DT .../devicetree/bindings/display/msm/dsi.txt | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 ++-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c| 13 - drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c| 16 -- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c| 29 +-- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 17 +-- 7 files changed, 69 insertions(+), 22 deletions(-) -- 2.20.0.rc0.387.gc7a69e6b6c-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 2/7] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index 71fe60e5f01f1..f58298bd6c423 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 13UL
#define VCO_MAX_RATE 26UL
@@ -139,6 +138,7 @@ struct dsi_pll_14nm {
/* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
+ struct clk *vco_ref_clk;
u64 vco_current_rate;
u64 vco_ref_clk_rate;
@@ -591,7 +591,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw,
unsigned long rate,
parent_rate);
pll_14nm->vco_current_rate = rate;
- pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
+ pll_14nm->vco_ref_clk_rate = parent_rate;
dsi_pll_14nm_input_init(pll_14nm);
@@ -950,8 +950,9 @@ static struct clk_hw *pll_14nm_postdiv_register(struct
dsi_pll_14nm *pll_14nm,
static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
{
char clk_name[32], parent[32], vco_name[32];
+ const char *ref_clk_name = __clk_get_name(pll_14nm->vco_ref_clk);
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = _clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -1065,6 +1066,15 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
pll_14nm->id = id;
pll_14nm_list[id] = pll_14nm;
+ pll_14nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_14nm->vco_ref_clk)) {
+ ret = PTR_ERR(pll_14nm->vco_ref_clk);
+ if (ret != EPROBE_DEFER)
+ dev_err(>dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
--
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Re: [Freedreno] [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT
On Thu, Nov 08, 2018 at 02:04:31PM -0800, Doug Anderson wrote:
> Hi,
>
> On Fri, Nov 2, 2018 at 2:45 PM Matthias Kaehlcke wrote:
> >
> > Get the PHY ref clock from the device tree instead of hardcoding
> > its name and rate.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 11 ++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > index 4c03f0b7343ed..1016eb50df8f5 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > @@ -91,6 +91,8 @@ struct dsi_pll_10nm {
> > void __iomem *phy_cmn_mmio;
> > void __iomem *mmio;
> >
> > + struct clk *vco_ref_clk;
> > +
> > u64 vco_ref_clk_rate;
> > u64 vco_current_rate;
> >
> > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> > *pll_10nm)
> > char clk_name[32], parent[32], vco_name[32];
> > char parent2[32], parent3[32], parent4[32];
> > struct clk_init_data vco_init = {
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_names = (const char *[]){
> > + __clk_get_name(pll_10nm->vco_ref_clk) },
> > .num_parents = 1,
> > .name = vco_name,
> > .flags = CLK_IGNORE_UNUSED,
> > @@ -786,6 +789,12 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
> > platform_device *pdev, int id)
> > pll_10nm->id = id;
> > pll_10nm_list[id] = pll_10nm;
> >
> > + pll_10nm->vco_ref_clk = devm_clk_get(>dev, "ref");
> > + if (IS_ERR(pll_10nm->vco_ref_clk)) {
> > + dev_err(>dev, "couldn't get 'ref' clock\n");
> > + return (void *)pll_10nm->vco_ref_clk;
> > + }
>
> So, u. Can you follow the same pattern for all the other clocks
> in this file too? All parents should get their name based on
> references in the device tree.
>
> It turns out that right now we have a mismatch because
> "drivers/clk/qcom/dispcc-sdm845.c" calls "dsi0pllbyte"
> "dsi0_phy_pll_out_byteclk" and calls "dsi0pll"
> "dsi0_phy_pll_out_dsiclk". We might want to change the names in
> dispcc-sdm845.c, but it wouldn't matter if we simply didn't hardcode
> them here.
Hm, I understand the problem, but not quite what you mean with 'follow
the same pattern'. The VCO ref clock is an 'external'/existing clock,
hence it can be specificed in the DT and obtained with
_clk_get(). However the clocks you mention above are 'created' by the
PHY driver, so we could only specify their names in the DT, not sure
if that's what you are suggesting. I guess 'clock-output-names' could
be used, though it isn't really useful to describe the names in a
clock tree. If you still think this should be done please share how
you envision the DT entries to look.
Cheers
Matthias
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Re: [Freedreno] [PATCH 1/2] dt-bindings: msm/dsi: Add ref clock for 10nm PHY
On Tue, Nov 06, 2018 at 03:09:40PM -0800, Stephen Boyd wrote: > Quoting Matthias Kaehlcke (2018-11-02 14:45:33) > > Allow the 10nm PHY driver to get the ref clock from the DT. > > > > Signed-off-by: Matthias Kaehlcke > > --- > > Documentation/devicetree/bindings/display/msm/dsi.txt | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt > > b/Documentation/devicetree/bindings/display/msm/dsi.txt > > index dfc743219bd88..d0d2046ceff69 100644 > > --- a/Documentation/devicetree/bindings/display/msm/dsi.txt > > +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt > > @@ -105,6 +105,10 @@ Required properties: > > - power-domains: Should be < MDSS_GDSC>. > > - clocks: Phandles to device clocks. See [1] for details on clock bindings. > > - clock-names: the following clocks are required: > > + For 10nm PHY: > > + * "iface" > > + * "ref" > > + For other PHYs: > >* "iface" > > Any reason we can't go back and do this for other phys too? They're all > the same with regards to this reference clk input. To avoid breaking existing users, at least the 28nm PHY is used by msm8916. Also I don't have the hardware to test changes for other PHYs. Cheers Matthias ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT
On Tue, Nov 06, 2018 at 03:11:48PM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-02 14:45:34)
> > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> > *pll_10nm)
> > char clk_name[32], parent[32], vco_name[32];
> > char parent2[32], parent3[32], parent4[32];
> > struct clk_init_data vco_init = {
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_names = (const char *[]){
> > + __clk_get_name(pll_10nm->vco_ref_clk) },
>
> I find this syntax odd, in addition to needing to check for NULL here as
> Sean pointed out. Preferably just have it be the address of the
> character pointer instead of making an anonymous array and then casting
> that inline, i.e
>
> .parent_names = _clk_name,
Ok
I'm not convinced the check for NULL is needed though, see my reply to Sean.
> > .num_parents = 1,
> > .name = vco_name,
> > .flags = CLK_IGNORE_UNUSED,
> > @@ -786,6 +789,12 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
> > platform_device *pdev, int id)
> > pll_10nm->id = id;
> > pll_10nm_list[id] = pll_10nm;
> >
> > + pll_10nm->vco_ref_clk = devm_clk_get(>dev, "ref");
> > + if (IS_ERR(pll_10nm->vco_ref_clk)) {
> > + dev_err(>dev, "couldn't get 'ref' clock\n");
>
> This might be because of probe defer, which may be annoying to see this
> failure many times.
Ok, will skip the logging for -EPROBE_DEFER
Cheers
Matthias
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Re: [Freedreno] [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT
On Mon, Nov 05, 2018 at 12:33:04PM -0500, Sean Paul wrote:
> On Fri, Nov 02, 2018 at 02:45:34PM -0700, Matthias Kaehlcke wrote:
> > Get the PHY ref clock from the device tree instead of hardcoding
> > its name and rate.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 11 ++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > index 4c03f0b7343ed..1016eb50df8f5 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > @@ -91,6 +91,8 @@ struct dsi_pll_10nm {
> > void __iomem *phy_cmn_mmio;
> > void __iomem *mmio;
> >
> > + struct clk *vco_ref_clk;
> > +
> > u64 vco_ref_clk_rate;
> > u64 vco_current_rate;
> >
> > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> > *pll_10nm)
> > char clk_name[32], parent[32], vco_name[32];
> > char parent2[32], parent3[32], parent4[32];
> > struct clk_init_data vco_init = {
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_names = (const char *[]){
> > + __clk_get_name(pll_10nm->vco_ref_clk) },
> > .num_parents = 1,
>
> You should check the return of __clk_get_name() since you're setting
> num_parents
> to 1.
Is that actually needed? __clk_get_name() only returns NULL if the
passed clock is NULL, and this can't happen here since _init() fails
if the clock can't be obtained, or am I missing something here?
> Also, you should revert the patch that hardcodes 19.2MHz as part of this
> set.
Ooops, this somehow got dropped when moving the patch from my working
tree to the repo I use for upstreaming.
> > .name = vco_name,
> > .flags = CLK_IGNORE_UNUSED,
> > @@ -786,6 +789,12 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
> > platform_device *pdev, int id)
> > pll_10nm->id = id;
> > pll_10nm_list[id] = pll_10nm;
> >
> > + pll_10nm->vco_ref_clk = devm_clk_get(>dev, "ref");
> > + if (IS_ERR(pll_10nm->vco_ref_clk)) {
> > + dev_err(>dev, "couldn't get 'ref' clock\n");
>
> Please print the error message
Ok, except for -EPROBE_DEFER as per Stephen's comment.
> > + return (void *)pll_10nm->vco_ref_clk;
>
> Use ERR_CAST here
Will do
Cheers
Matthias
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[Freedreno] [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT
Get the PHY ref clock from the device tree instead of hardcoding
its name and rate.
Signed-off-by: Matthias Kaehlcke
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..1016eb50df8f5 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -91,6 +91,8 @@ struct dsi_pll_10nm {
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
+ struct clk *vco_ref_clk;
+
u64 vco_ref_clk_rate;
u64 vco_current_rate;
@@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = (const char *[]){
+ __clk_get_name(pll_10nm->vco_ref_clk) },
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -786,6 +789,12 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
+ pll_10nm->vco_ref_clk = devm_clk_get(>dev, "ref");
+ if (IS_ERR(pll_10nm->vco_ref_clk)) {
+ dev_err(>dev, "couldn't get 'ref' clock\n");
+ return (void *)pll_10nm->vco_ref_clk;
+ }
+
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
dev_err(>dev, "failed to map CMN PHY base\n");
--
2.19.1.930.g4563a0d9d0-goog
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[Freedreno] [PATCH 1/2] dt-bindings: msm/dsi: Add ref clock for 10nm PHY
Allow the 10nm PHY driver to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke --- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..d0d2046ceff69 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -105,6 +105,10 @@ Required properties: - power-domains: Should be < MDSS_GDSC>. - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: + For 10nm PHY: + * "iface" + * "ref" + For other PHYs: * "iface" For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node -- 2.19.1.930.g4563a0d9d0-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v2 2/3] drm/msm/dpu: Integrate interconnect API in MDSS
Hi Sravanthi,
On Wed, Oct 10, 2018 at 02:54:33PM +0530, Sravanthi Kollukuduru wrote:
> The interconnect framework is designed to provide a
> standard kernel interface to control the settings of
> the interconnects on a SoC.
>
> The interconnect API uses a consumer/provider-based model,
> where the providers are the interconnect buses and the
> consumers could be various drivers.
>
> MDSS is one of the interconnect consumers which uses the
> interconnect APIs to get the path between endpoints and
> set its bandwidth/latency/QoS requirements for the given
> interconnected path.
>
> Changes in v2:
> - Remove error log and unnecessary check (Jordan Crouse)
>
> Signed-off-by: Sravanthi Kollukuduru
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 50
> +---
> 1 file changed, 46 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> index 2235ef8129f4..27c2594e5133 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> @@ -4,6 +4,7 @@
> */
>
> #include "dpu_kms.h"
> +#include
>
> #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
>
> @@ -16,8 +17,33 @@ struct dpu_mdss {
> u32 hwversion;
> struct dss_module_power mp;
> struct dpu_irq_controller irq_controller;
> + struct icc_path *path[2];
> + u32 num_paths;
> };
>
> +static int dpu_mdss_parse_data_bus_icc_path(
> + struct drm_device *dev, struct dpu_mdss *dpu_mdss)
> +{
> + struct icc_path *path0 = of_icc_get(dev->dev, "port0");
> + struct icc_path *path1 = of_icc_get(dev->dev, "port1");
> + int total_num_paths = 0;
initialization is not needed
nit: the 'total_' prefix doesn't add any value here, just 'num_paths'
would be easier to parse. Actually you could get rid of the variable
completely by just initializing and incrementing dpu_mdss->num_paths.
> static irqreturn_t dpu_mdss_irq(int irq, void *arg)
> {
> struct dpu_mdss *dpu_mdss = arg;
> @@ -127,7 +153,12 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
> {
> struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
> struct dss_module_power *mp = _mdss->mp;
> - int ret;
> + int ret, i;
> + u64 ab = (dpu_mdss->num_paths) ? 68/dpu_mdss->num_paths : 0;
parentheses are not needed
> + u64 ib = 68;
There should probably be a define for 68.
nit: names like avg_bw and peak_pw would be clearer than ab and ib,
without being excessively verbose.
Cheers
Matthias
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