Re: [Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845
Hi Chandan, I see some difference in DP and PLL base address between SD845 Android 4.9 kernel and [DPU,v3,1/5] dt-bindings. And also I find difference in reg format, why is that so? Is it possible to share your git tree of SD845 DP to check on DB845C? [DPU,v3,1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845Linux: --- reg = <1 0xea000 0x200>, <1 0xeaa00 0x200>, <1 0xea200 0x200>, <1 0xea600 0x200>, <2 0x03000 0x8>; reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; reg = <0 0x9 0x0dc>, <0 0x90200 0x0c0>, <0 0x90400 0x508>, <0 0x90a00 0x094>, <1 0xeaa00 0x200>, <1 0xea200 0x200>, <1 0xea600 0x200>, <2 0x02000 0x1a0>, <3 0x0 0x621c>, <1 0xea000 0x180>, <1 0xe8000 0x20>, <4 0xe1000 0x034>; reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_mmss_cc", "qfprom_physical", "dp_pll", "usb3_dp_com", "hdcp_physical"; SD845 Android kernel 4.9: -- reg = <0x088ea000 0x200>, <0x088eaa00 0x200>, <0x088ea200 0x200>, <0x088ea600 0x200>, <0xaf03000 0x8>; reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; reg = <0xae9 0x0dc>, <0xae90200 0x0c0>, <0xae90400 0x508>, <0xae90a00 0x094>, <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, <0xaf02000 0x1a0>, <0x78 0x621c>, <0x88ea030 0x10>, <0x88e8000 0x20>, <0x0aee1000 0x034>; /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_mmss_cc", "qfprom_physical", "dp_pll", "usb3_dp_com", "hdcp_physical"; Regards, Vadiraj On Sat, Dec 14, 2019 at 4:35 AM wrote: > > Send Freedreno mailing list submissions to > freedreno@lists.freedesktop.org > > To subscribe or unsubscribe via the World Wide Web, visit > https://lists.freedesktop.org/mailman/listinfo/freedreno > or, via email, send a message with subject or body 'help' to > freedreno-requ...@lists.freedesktop.org > > You can reach the person managing the list at > freedreno-ow...@lists.freedesktop.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of Freedreno digest..." > > > Today's Topics: > >1. Re: [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of > DP/DP-PLL driver for Snapdragon 845 (Rob Herring) >2. Re: [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of > DP/DP-PLL driver for Snapdragon 845 (Jeffrey Hugo) > > > -- > > Message: 1 > Date: Fri, 13 Dec 2019 16:58:00 -0600 > From: Rob Herring > To: Chandan Uddaraju > Cc: freedreno@lists.freedesktop.org, linux-arm-...@vger.kernel.org, > devicet...@vger.kernel.org, seanp...@chromium.org, > robdcl...@gmail.com, abhin...@codeaurora.org, nga...@codeaurora.org, > jsa...@codeaurora.org, hoegsb...@google.com, > dri-de...@lists.freedesktop.org > Subject: Re: [Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add > bindings of DP/DP-PLL driver for Snapdragon 845 > Message-ID: <20191213225800.GA21739@bogus> > Content-Type: text/plain; charset=us-ascii > > On Mon, Dec 02, 2019 at 01:47:45PM +, Chandan Uddaraju wrote: > > Add bindings for Snapdragon 845 DisplayPort and > > display-port PLL driver. >
Re: [Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845
On Mon, Dec 2, 2019 at 6:48 AM Chandan Uddaraju wrote: > > Add bindings for Snapdragon 845 DisplayPort and > display-port PLL driver. > > Changes in V2: > Provide details about sel-gpio > > Signed-off-by: Chandan Uddaraju > --- > .../devicetree/bindings/display/msm/dp.txt | 249 > + > .../devicetree/bindings/display/msm/dpu.txt| 16 +- > 2 files changed, 261 insertions(+), 4 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt > > diff --git a/Documentation/devicetree/bindings/display/msm/dp.txt > b/Documentation/devicetree/bindings/display/msm/dp.txt > new file mode 100644 > index 000..38be36d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dp.txt > @@ -0,0 +1,249 @@ > +Qualcomm Technologies, Inc. > +DP is the master Display Port device which supports DP host controllers that > are compatible with VESA Display Port interface specification. > +DP Controller: Required properties: > +- compatible: Should be "qcom,dp-display". > +- reg: Base address and length of DP hardware's memory > mapped regions. > +- cell-index: Specifies the controller instance. > +- reg-names:A list of strings that name the list of regs. > + "dp_ahb" - DP controller memory region. > + "dp_aux" - DP AUX memory region. > + "dp_link" - DP link layer memory region. > + "dp_p0" - DP pixel clock domain memory region. > + "dp_phy" - DP PHY memory region. > + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory > region. > + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory > region. > + "dp_mmss_cc" - Display Clock Control memory region. > + "qfprom_physical" - QFPROM Phys memory region. > + "dp_pll" - USB3 DP combo PLL memory region. > + "usb3_dp_com" - USB3 DP PHY combo memory region. > + "hdcp_physical" - DP HDCP memory region. > +- interrupt-parent phandle to the interrupt parent device node. > +- interrupts: The interrupt signal from the DP block. > +- clocks: Clocks required for Display Port operation. See [1] > for details on clock bindings. > +- clock-names: Names of the clocks corresponding to handles. > Following clocks are required: > + "core_aux_clk", > "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", > + "core_usb_pipe_clk", "ctrl_link_clk", > "ctrl_link_iface_clk", "ctrl_crypto_clk", > + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". > +- pll-node:phandle to DP PLL node. > +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. > +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. > +- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 > settings. The first > + entry in this array corresponds to >
Re: [Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845
On Mon, Dec 02, 2019 at 01:47:45PM +, Chandan Uddaraju wrote: > Add bindings for Snapdragon 845 DisplayPort and > display-port PLL driver. Is it just me, but I keep getting 2 copies of codeaurora emails? > > Changes in V2: > Provide details about sel-gpio This is V3, what changed in V3? > > Signed-off-by: Chandan Uddaraju > --- > .../devicetree/bindings/display/msm/dp.txt | 249 > + > .../devicetree/bindings/display/msm/dpu.txt| 16 +- > 2 files changed, 261 insertions(+), 4 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt New bindings should be in DT schema format. > diff --git a/Documentation/devicetree/bindings/display/msm/dp.txt > b/Documentation/devicetree/bindings/display/msm/dp.txt > new file mode 100644 > index 000..38be36d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dp.txt > @@ -0,0 +1,249 @@ > +Qualcomm Technologies, Inc. > +DP is the master Display Port device which supports DP host controllers that > are compatible with VESA Display Port interface specification. > +DP Controller: Required properties: > +- compatible: Should be "qcom,dp-display". Needs to be more specific like including the SoC name. > +- reg: Base address and length of DP hardware's memory > mapped regions. > +- cell-index: Specifies the controller instance. FDT doesn't use cell-index. > +- reg-names:A list of strings that name the list of regs. > + "dp_ahb" - DP controller memory region. > + "dp_aux" - DP AUX memory region. > + "dp_link" - DP link layer memory region. > + "dp_p0" - DP pixel clock domain memory region. > + "dp_phy" - DP PHY memory region. > + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. > + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. > + "dp_mmss_cc" - Display Clock Control memory region. Sounds like a separate clock controller node... > + "qfprom_physical" - QFPROM Phys memory region. > + "dp_pll" - USB3 DP combo PLL memory region. > + "usb3_dp_com" - USB3 DP PHY combo memory region. Should be a separate phy node? > + "hdcp_physical" - DP HDCP memory region. The 'dp_' part is redundant. What does 'physical' mean? Addresses in DT are always physical. > +- interrupt-parent phandle to the interrupt parent device node. Don't document interrupt-parent. It's not required either because it could be in a parent node. > +- interrupts:The interrupt signal from the DP block. > +- clocks: Clocks required for Display Port operation. See [1] > for details on clock bindings. > +- clock-names: Names of the clocks corresponding to handles. > Following clocks are required: > + "core_aux_clk", > "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", > + "core_usb_pipe_clk", "ctrl_link_clk", > "ctrl_link_iface_clk", "ctrl_crypto_clk", > + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". Clocks should be actual clock inputs to the module. If 'pixel_parent' is just some parent clock you want to assign, then use assigned-clocks. > +- pll-node: phandle to DP PLL node. But you have a DP PLL reg region defined. Is this something else? Needs a 'qcom' prefix if it stays. > +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. > +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. > +- qcom,aux-cfg0-settings:Specifies the DP AUX configuration 0 > settings. The first > + entry in this array corresponds to the > register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. Needs more details on what these are and why they must be in DT. We generally don't just stuff DT with raw values to initial registers with. Line lengths should be <80 char. > +- qcom,aux-cfg1-settings:Specifies the DP AUX configuration 1 > settings. The first > + entry in this array corresponds to the > register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg2-settings:Specifies the DP AUX configuration 2 > settings. The first > + entry in this array corresponds to the > register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg3-settings:
[Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845
Add bindings for Snapdragon 845 DisplayPort and display-port PLL driver. Changes in V2: Provide details about sel-gpio Signed-off-by: Chandan Uddaraju --- .../devicetree/bindings/display/msm/dp.txt | 249 + .../devicetree/bindings/display/msm/dpu.txt| 16 +- 2 files changed, 261 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt diff --git a/Documentation/devicetree/bindings/display/msm/dp.txt b/Documentation/devicetree/bindings/display/msm/dp.txt new file mode 100644 index 000..38be36d --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dp.txt @@ -0,0 +1,249 @@ +Qualcomm Technologies, Inc. +DP is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. +DP Controller: Required properties: +- compatible: Should be "qcom,dp-display". +- reg: Base address and length of DP hardware's memory mapped regions. +- cell-index: Specifies the controller instance. +- reg-names:A list of strings that name the list of regs. + "dp_ahb" - DP controller memory region. + "dp_aux" - DP AUX memory region. + "dp_link" - DP link layer memory region. + "dp_p0" - DP pixel clock domain memory region. + "dp_phy" - DP PHY memory region. + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. + "dp_mmss_cc" - Display Clock Control memory region. + "qfprom_physical" - QFPROM Phys memory region. + "dp_pll" - USB3 DP combo PLL memory region. + "usb3_dp_com" - USB3 DP PHY combo memory region. + "hdcp_physical" - DP HDCP memory region. +- interrupt-parent phandle to the interrupt parent device node. +- interrupts: The interrupt signal from the DP block. +- clocks: Clocks required for Display Port operation. See [1] for details on clock bindings. +- clock-names: Names of the clocks corresponding to handles. Following clocks are required: + "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", + "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". +- pll-node:phandle to DP PLL node. +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. +- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg6-settings: Specifies the DP AUX
