On Mon, Apr 20, 2020 at 10:03:11AM -0400, Jonathan Marek wrote:
> Signed-off-by: Jonathan Marek
I was wondering where this was. I don't think there is any reason to not squash
this into the previous patch since the GMU won't be operational without it.
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 3e51939eb867..b583bf6e293b 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -469,10 +469,18 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
> struct platform_device *pdev = to_platform_device(gmu->dev);
> void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
> void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
> + uint32_t pdc_address_offset;
>
> if (!pdcptr || !seqptr)
> goto err;
>
> + if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
> + pdc_address_offset = 0x30090;
> + else if (adreno_is_a650(adreno_gpu))
> + pdc_address_offset = 0x300a0;
> + else
> + pdc_address_offset = 0x30080;
> +
> /* Disable SDE clock gating */
> gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
>
> @@ -523,10 +531,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
>
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
> - if (adreno_is_a618(adreno_gpu))
> - pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090);
> - else
> - pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8,
> pdc_address_offset);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
>
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
> @@ -538,17 +543,12 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
>
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x3);
> - if (adreno_is_a618(adreno_gpu))
> + if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
> else
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
> -
> -
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
> - if (adreno_is_a618(adreno_gpu))
> - pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090);
> - else
> - pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8,
> pdc_address_offset);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
>
> /* Setup GPU PDC */
> --
> 2.26.1
>
--
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