Re: [Freedreno] [PATCH v1 3/4] drm/msm/dpu: merge base_off with blk_off in struct dpu_hw_blk_reg_map

2022-06-20 Thread Abhinav Kumar 




On 6/1/2022 9:13 AM, Dmitry Baryshkov wrote:

There is little point in keeping a separate MDP address and block offset
in this struct. Merge them to form a new blk_addr field used for all
register access.

Signed-off-by: Dmitry Baryshkov 

Reviewed-by: Abhinav Kumar 

---
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c| 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c   | 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c   | 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c| 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   | 5 ++---
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   | 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c   | 6 +++---
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   | 7 +++
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c   | 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 3 +--
  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 2 +-
  15 files changed, 20 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 1120ff408dae..e12b7fa48a7b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -58,8 +58,7 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
  
  	for (i = 0; i < m->ctl_count; i++) {

if (ctl == m->ctl[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->ctl[i].base;
+   b->blk_addr = addr + m->ctl[i].base;
b->log_mask = DPU_DBG_MASK_CTL;
return &m->ctl[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index dfe6e4c11917..411689ae6382 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -166,8 +166,7 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
  
  	for (i = 0; i < m->dsc_count; i++) {

if (dsc == m->dsc[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->dsc[i].base;
+   b->blk_addr = addr + m->dsc[i].base;
b->log_mask = DPU_DBG_MASK_DSC;
return &m->dsc[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 8196ae47dea8..8ab5ace34a2d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -80,8 +80,7 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp 
dspp,
  
  	for (i = 0; i < m->dspp_count; i++) {

if (dspp == m->dspp[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->dspp[i].base;
+   b->blk_addr = addr + m->dspp[i].base;
b->log_mask = DPU_DBG_MASK_DSPP;
return &m->dspp[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index d83503ea2419..cf1b6d84c18a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -401,8 +401,7 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
  static void __intr_offset(const struct dpu_mdss_cfg *m,
void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
  {
-   hw->base_off = addr;
-   hw->blk_off = m->mdp[0].base;
+   hw->blk_addr = addr + m->mdp[0].base;
  }
  
  struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index c7eb314f1d7a..d8aff0f459f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -77,8 +77,7 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf 
intf,
for (i = 0; i < m->intf_count; i++) {
if ((intf == m->intf[i].id) &&
(m->intf[i].type != INTF_NONE)) {
-   b->base_off = addr;
-   b->blk_off = m->intf[i].base;
+   b->blk_addr = addr + m->intf[i].base;
b->log_mask = DPU_DBG_MASK_INTF;
return &m->intf[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 87a4a5869b9b..75d55fd65f19 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -43,8 +43,7 @@ static const struct dpu_lm_cfg *_lm

[Freedreno] [PATCH v1 3/4] drm/msm/dpu: merge base_off with blk_off in struct dpu_hw_blk_reg_map

2022-06-01 Thread Dmitry Baryshkov 
There is little point in keeping a separate MDP address and block offset
in this struct. Merge them to form a new blk_addr field used for all
register access.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   | 5 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c   | 6 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   | 7 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 2 +-
 15 files changed, 20 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 1120ff408dae..e12b7fa48a7b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -58,8 +58,7 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
 
for (i = 0; i < m->ctl_count; i++) {
if (ctl == m->ctl[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->ctl[i].base;
+   b->blk_addr = addr + m->ctl[i].base;
b->log_mask = DPU_DBG_MASK_CTL;
return &m->ctl[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index dfe6e4c11917..411689ae6382 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -166,8 +166,7 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
 
for (i = 0; i < m->dsc_count; i++) {
if (dsc == m->dsc[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->dsc[i].base;
+   b->blk_addr = addr + m->dsc[i].base;
b->log_mask = DPU_DBG_MASK_DSC;
return &m->dsc[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 8196ae47dea8..8ab5ace34a2d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -80,8 +80,7 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp 
dspp,
 
for (i = 0; i < m->dspp_count; i++) {
if (dspp == m->dspp[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->dspp[i].base;
+   b->blk_addr = addr + m->dspp[i].base;
b->log_mask = DPU_DBG_MASK_DSPP;
return &m->dspp[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index d83503ea2419..cf1b6d84c18a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -401,8 +401,7 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
 static void __intr_offset(const struct dpu_mdss_cfg *m,
void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
 {
-   hw->base_off = addr;
-   hw->blk_off = m->mdp[0].base;
+   hw->blk_addr = addr + m->mdp[0].base;
 }
 
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index c7eb314f1d7a..d8aff0f459f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -77,8 +77,7 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf 
intf,
for (i = 0; i < m->intf_count; i++) {
if ((intf == m->intf[i].id) &&
(m->intf[i].type != INTF_NONE)) {
-   b->base_off = addr;
-   b->blk_off = m->intf[i].base;
+   b->blk_addr = addr + m->intf[i].base;
b->log_mask = DPU_DBG_MASK_INTF;
return &m->intf[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 87a4a5869b9b..75d55fd65f19 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -43,8 +43,7 @@ static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
 
for (i = 0; i < m->mixer_count; i++) {
i