Re: [Freedreno] [PATCH v2 04/11] drm/msm/dsi/phy: Reindent and reflow multiline function calls
On 2022-06-02 13:14:26, Dmitry Baryshkov wrote:
> On Thu, 2 Jun 2022 at 01:07, Marijn Suijten
> wrote:
> >
> > Patch 613cbd1da3c9 ("drm/msm/dsi: use devm_clk_*register to registe DSI
> > PHY clocks") introduced the devm_ prefix to clk_hw registration calls,
> > without updating the indentation of the arguments on the following
> > lines.
> >
> > Similarly e55b3fc8 ("drm/msm/dsi: drop PLL accessor functions")
> > moved from pll_write to dsi_phy_write without updating the indentation
> > of followup arguments either.
> >
> > Preparing for a series that heavily touches the clk calls, reflow and
> > reindent function calls that are adhering to an 80-char column limit by
> > spanning multiple lines. Where function names are very long the
> > arguments are indented with a fixed number of two tab characters instead
> > of aligning with the opening parenthesis of the function call.
> >
>
> I'm not a fan of reindenting the code, but let's do it.
I don't like it either, but it's better than trying to figure out how to
add and flow new arguments into the call-site while also leaving the
indentation in the same broken state. At the same time it seems more
consistent to fix up most faults rather than only touching clk calls.
It's unfortunate that there's no proper autoformatter for C, that is
consistently used across the kernel tree. Makes for a lot of mundane,
error-prone, manual work. But alas.
- Marijn
Re: [Freedreno] [PATCH v2 04/11] drm/msm/dsi/phy: Reindent and reflow multiline function calls
On Thu, 2 Jun 2022 at 01:07, Marijn Suijten
wrote:
>
> Patch 613cbd1da3c9 ("drm/msm/dsi: use devm_clk_*register to registe DSI
> PHY clocks") introduced the devm_ prefix to clk_hw registration calls,
> without updating the indentation of the arguments on the following
> lines.
>
> Similarly e55b3fc8 ("drm/msm/dsi: drop PLL accessor functions")
> moved from pll_write to dsi_phy_write without updating the indentation
> of followup arguments either.
>
> Preparing for a series that heavily touches the clk calls, reflow and
> reindent function calls that are adhering to an 80-char column limit by
> spanning multiple lines. Where function names are very long the
> arguments are indented with a fixed number of two tab characters instead
> of aligning with the opening parenthesis of the function call.
>
I'm not a fan of reindenting the code, but let's do it.
Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 96 +--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c| 9 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 73 +++---
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 63 ++--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 84
> 5 files changed, 161 insertions(+), 164 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 08b015ea1b1e..56892036e419 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -188,19 +188,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm
> *pll, struct dsi_pll_config *
> pr_debug("SSC is enabled\n");
>
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
> - config->ssc_stepsize & 0xff);
> + config->ssc_stepsize & 0xff);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
> - config->ssc_stepsize >> 8);
> + config->ssc_stepsize >> 8);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
> - config->ssc_div_per & 0xff);
> + config->ssc_div_per & 0xff);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
> - config->ssc_div_per >> 8);
> + config->ssc_div_per >> 8);
> dsi_phy_write(base +
> REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
> - config->ssc_adj_per & 0xff);
> + config->ssc_adj_per & 0xff);
> dsi_phy_write(base +
> REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
> - config->ssc_adj_per >> 8);
> + config->ssc_adj_per >> 8);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
> - SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
> + SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
> }
> }
>
> @@ -215,16 +215,19 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_10nm *pll)
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
> - 0xba);
> - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
> 0x0c);
> + 0xba);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
> + 0x0c);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
> - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,
> 0x08);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,
> + 0x08);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
> - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> 0xfa);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> + 0xfa);
> dsi_phy_write(base +
> REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
> - 0x4c);
> + 0x4c);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
> @@ -236,18 +239,18 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll,
> struct dsi_pll_config *conf
>
> dsi_phy_write(base +
[Freedreno] [PATCH v2 04/11] drm/msm/dsi/phy: Reindent and reflow multiline function calls
Patch 613cbd1da3c9 ("drm/msm/dsi: use devm_clk_*register to registe DSI
PHY clocks") introduced the devm_ prefix to clk_hw registration calls,
without updating the indentation of the arguments on the following
lines.
Similarly e55b3fc8 ("drm/msm/dsi: drop PLL accessor functions")
moved from pll_write to dsi_phy_write without updating the indentation
of followup arguments either.
Preparing for a series that heavily touches the clk calls, reflow and
reindent function calls that are adhering to an 80-char column limit by
spanning multiple lines. Where function names are very long the
arguments are indented with a fixed number of two tab characters instead
of aligning with the opening parenthesis of the function call.
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 96 +--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c| 9 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 73 +++---
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 63 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 84
5 files changed, 161 insertions(+), 164 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 08b015ea1b1e..56892036e419 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -188,19 +188,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll,
struct dsi_pll_config *
pr_debug("SSC is enabled\n");
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
- config->ssc_stepsize & 0xff);
+ config->ssc_stepsize & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
- config->ssc_stepsize >> 8);
+ config->ssc_stepsize >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
- config->ssc_div_per & 0xff);
+ config->ssc_div_per & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
- config->ssc_div_per >> 8);
+ config->ssc_div_per >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
- config->ssc_adj_per & 0xff);
+ config->ssc_adj_per & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
- config->ssc_adj_per >> 8);
+ config->ssc_adj_per >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
- SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
+ SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
}
}
@@ -215,16 +215,19 @@ static void dsi_pll_config_hzindep_reg(struct
dsi_pll_10nm *pll)
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
- 0xba);
- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
0x0c);
+ 0xba);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
+ 0x0c);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,
+ 0x08);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
0xfa);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
+ 0xfa);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
- 0x4c);
+ 0x4c);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
@@ -236,18 +239,18 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll,
struct dsi_pll_config *conf
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
- config->decimal_div_start);
+ config->decimal_div_start);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
- config->frac_div_start & 0xff);
+
