Re: [Freedreno] [PATCH v2 06/11] drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()

2022-06-02 Thread Dmitry Baryshkov 
On Thu, 2 Jun 2022 at 01:08, Marijn Suijten
 wrote:
>
> Now that the last DSI PHY PLL driver (dsi_phy_28nm_8960) has been
> converted to use a simple stack-local char-array instead of a
> devm_kzalloc heap allocation we can safely call sizeof() on every string
> variable (that's now a sized array instead of a pointer) passed into
> snprintf instead of hardcoding the size.
>
> Signed-off-by: Marijn Suijten 

Reviewed-by: Dmitry Baryshkov 

> ---
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 36 +--
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c| 18 +-
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 24 ++---
>  .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c   |  8 ++---
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 34 +-
>  5 files changed, 60 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 56892036e419..8bd7b97b1b9b 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -591,15 +591,15 @@ static int pll_10nm_register(struct dsi_pll_10nm 
> *pll_10nm, struct clk_hw **prov
>
> DBG("DSI%d", pll_10nm->phy->id);
>
> -   snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id);
> +   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", 
> pll_10nm->phy->id);
> pll_10nm->clk_hw.init = _init;
>
> ret = devm_clk_hw_register(dev, _10nm->clk_hw);
> if (ret)
> return ret;
>
> -   snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
> -   snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id);
> +   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", 
> pll_10nm->phy->id);
> +   snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_10nm->phy->id);
>
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> CLK_SET_RATE_PARENT, pll_10nm->phy->pll_base +
> @@ -610,8 +610,8 @@ static int pll_10nm_register(struct dsi_pll_10nm 
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> -   snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
> -   snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
> +   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", 
> pll_10nm->phy->id);
> +   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
> pll_10nm->phy->id);
>
> /* BIT CLK: DIV_CTRL_3_0 */
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> @@ -623,8 +623,8 @@ static int pll_10nm_register(struct dsi_pll_10nm 
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> -   snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", 
> pll_10nm->phy->id);
> -   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
> +   snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", 
> pll_10nm->phy->id);
> +   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
> pll_10nm->phy->id);
>
> /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> @@ -636,8 +636,8 @@ static int pll_10nm_register(struct dsi_pll_10nm 
> *pll_10nm, struct clk_hw **prov
>
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> -   snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
> -   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
> +   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", 
> pll_10nm->phy->id);
> +   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
> pll_10nm->phy->id);
>
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
>0, 1, 2);
> @@ -646,8 +646,8 @@ static int pll_10nm_register(struct dsi_pll_10nm 
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> -   snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", 
> pll_10nm->phy->id);
> -   snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
> +   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", 
> pll_10nm->phy->id);
> +   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
> pll_10nm->phy->id);
>
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
>0, 1, 4);
> @@ -656,11 +656,11 @@ static int pll_10nm_register(struct dsi_pll_10nm 
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> -   snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
> -   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
> -   snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
> -   snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
> -   snprintf(parent4, 32,

[Freedreno] [PATCH v2 06/11] drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()

2022-06-01 Thread Marijn Suijten 
Now that the last DSI PHY PLL driver (dsi_phy_28nm_8960) has been
converted to use a simple stack-local char-array instead of a
devm_kzalloc heap allocation we can safely call sizeof() on every string
variable (that's now a sized array instead of a pointer) passed into
snprintf instead of hardcoding the size.

Signed-off-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 36 +--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c| 18 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 24 ++---
 .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c   |  8 ++---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 34 +-
 5 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 56892036e419..8bd7b97b1b9b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -591,15 +591,15 @@ static int pll_10nm_register(struct dsi_pll_10nm 
*pll_10nm, struct clk_hw **prov
 
DBG("DSI%d", pll_10nm->phy->id);
 
-   snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id);
+   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_10nm->phy->id);
pll_10nm->clk_hw.init = _init;
 
ret = devm_clk_hw_register(dev, _10nm->clk_hw);
if (ret)
return ret;
 
-   snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_10nm->phy->id);
 
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
CLK_SET_RATE_PARENT, pll_10nm->phy->pll_base +
@@ -610,8 +610,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
 
/* BIT CLK: DIV_CTRL_3_0 */
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
@@ -623,8 +623,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
 
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
@@ -636,8 +636,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
 
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 
-   snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
 
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
   0, 1, 2);
@@ -646,8 +646,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
 
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
   0, 1, 4);
@@ -656,11 +656,11 @@ static int pll_10nm_register(struct dsi_pll_10nm 
*pll_10nm, struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
-   snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
-   snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
-   snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
+   snprintf(parent2, sizeof(parent2), "dsi%d_pll_by_2_bit_clk",