Re: [Freedreno] [PATCH v2 1/7] drm/msm/dpu: move hw_inf encoder baseclass
On Wed, Feb 13, 2019 at 05:19:10PM -0800, Jeykumar Sankaran wrote: > Both video and command physical encoders will have > a hw interface assigned to it. So there is really no > need to track the hw block in specific encoder subclass. > > Signed-off-by: Jeykumar Sankaran Reviewed-by: Sean Paul > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4 +- > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 125 > + > 2 files changed, 52 insertions(+), 77 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index 44e6f8b6..acd5956 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -201,6 +201,7 @@ struct dpu_encoder_irq { > * @hw_mdptop: Hardware interface to the top registers > * @hw_ctl: Hardware interface to the ctl registers > * @hw_pp: Hardware interface to the ping pong registers > + * @hw_intf: Hardware interface to the intf registers > * @dpu_kms: Pointer to the dpu_kms top level > * @cached_mode: DRM mode cached at mode_set time, acted on in enable > * @enabled: Whether the encoder has enabled and running a mode > @@ -229,6 +230,7 @@ struct dpu_encoder_phys { > struct dpu_hw_mdp *hw_mdptop; > struct dpu_hw_ctl *hw_ctl; > struct dpu_hw_pingpong *hw_pp; > + struct dpu_hw_intf *hw_intf; > struct dpu_kms *dpu_kms; > struct drm_display_mode cached_mode; > enum dpu_enc_split_role split_role; > @@ -255,12 +257,10 @@ static inline int dpu_encoder_phys_inc_pending(struct > dpu_encoder_phys *phys) > * struct dpu_encoder_phys_vid - sub-class of dpu_encoder_phys to handle > video > * mode specific operations > * @base:Baseclass physical encoder structure > - * @hw_intf: Hardware interface to the intf registers > * @timing_params: Current timing parameter > */ > struct dpu_encoder_phys_vid { > struct dpu_encoder_phys base; > - struct dpu_hw_intf *hw_intf; > struct intf_timing_params timing_params; > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index acdab5b0..e326395 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -18,14 +18,14 @@ > #include "dpu_trace.h" > > #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ > - (e) && (e)->base.parent ? \ > - (e)->base.parent->base.id : -1, \ > + (e) && (e)->parent ? \ > + (e)->parent->base.id : -1, \ > (e) && (e)->hw_intf ? \ > (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) > > #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \ > - (e) && (e)->base.parent ? \ > - (e)->base.parent->base.id : -1, \ > + (e) && (e)->parent ? \ > + (e)->parent->base.id : -1, \ > (e) && (e)->hw_intf ? \ > (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) > > @@ -44,7 +44,7 @@ static bool dpu_encoder_phys_vid_is_master( > } > > static void drm_mode_to_intf_timing_params( > - const struct dpu_encoder_phys_vid *vid_enc, > + const struct dpu_encoder_phys *phys_enc, > const struct drm_display_mode *mode, > struct intf_timing_params *timing) > { > @@ -92,7 +92,7 @@ static void drm_mode_to_intf_timing_params( > timing->hsync_skew = mode->hskew; > > /* DSI controller cannot handle active-low sync signals. */ > - if (vid_enc->hw_intf->cap->type == INTF_DSI) { > + if (phys_enc->hw_intf->cap->type == INTF_DSI) { > timing->hsync_polarity = 0; > timing->vsync_polarity = 0; > } > @@ -143,11 +143,11 @@ static u32 get_vertical_total(const struct > intf_timing_params *timing) > * lines based on the chip worst case latencies. > */ > static u32 programmable_fetch_get_num_lines( > - struct dpu_encoder_phys_vid *vid_enc, > + struct dpu_encoder_phys *phys_enc, > const struct intf_timing_params *timing) > { > u32 worst_case_needed_lines = > - vid_enc->hw_intf->cap->prog_fetch_lines_worst_case; > + phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; > u32 start_of_frame_lines = > timing->v_back_porch + timing->vsync_pulse_width; > u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines; > @@ -155,26 +155,26 @@ static u32 programmable_fetch_get_num_lines( > > /* Fetch must be outside active lines, otherwise undefined. */ > if (start_of_frame_lines >= worst_case_needed_lines) { > - DPU_DEBUG_VIDENC(vid_enc, > + DPU_DEBUG_VIDENC(phys_enc, >
[Freedreno] [PATCH v2 1/7] drm/msm/dpu: move hw_inf encoder baseclass
Both video and command physical encoders will have a hw interface assigned to it. So there is really no need to track the hw block in specific encoder subclass. Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 125 + 2 files changed, 52 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 44e6f8b6..acd5956 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -201,6 +201,7 @@ struct dpu_encoder_irq { * @hw_mdptop: Hardware interface to the top registers * @hw_ctl:Hardware interface to the ctl registers * @hw_pp: Hardware interface to the ping pong registers + * @hw_intf: Hardware interface to the intf registers * @dpu_kms: Pointer to the dpu_kms top level * @cached_mode: DRM mode cached at mode_set time, acted on in enable * @enabled: Whether the encoder has enabled and running a mode @@ -229,6 +230,7 @@ struct dpu_encoder_phys { struct dpu_hw_mdp *hw_mdptop; struct dpu_hw_ctl *hw_ctl; struct dpu_hw_pingpong *hw_pp; + struct dpu_hw_intf *hw_intf; struct dpu_kms *dpu_kms; struct drm_display_mode cached_mode; enum dpu_enc_split_role split_role; @@ -255,12 +257,10 @@ static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys) * struct dpu_encoder_phys_vid - sub-class of dpu_encoder_phys to handle video * mode specific operations * @base: Baseclass physical encoder structure - * @hw_intf: Hardware interface to the intf registers * @timing_params: Current timing parameter */ struct dpu_encoder_phys_vid { struct dpu_encoder_phys base; - struct dpu_hw_intf *hw_intf; struct intf_timing_params timing_params; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index acdab5b0..e326395 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -18,14 +18,14 @@ #include "dpu_trace.h" #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ - (e) && (e)->base.parent ? \ - (e)->base.parent->base.id : -1, \ + (e) && (e)->parent ? \ + (e)->parent->base.id : -1, \ (e) && (e)->hw_intf ? \ (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \ - (e) && (e)->base.parent ? \ - (e)->base.parent->base.id : -1, \ + (e) && (e)->parent ? \ + (e)->parent->base.id : -1, \ (e) && (e)->hw_intf ? \ (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) @@ -44,7 +44,7 @@ static bool dpu_encoder_phys_vid_is_master( } static void drm_mode_to_intf_timing_params( - const struct dpu_encoder_phys_vid *vid_enc, + const struct dpu_encoder_phys *phys_enc, const struct drm_display_mode *mode, struct intf_timing_params *timing) { @@ -92,7 +92,7 @@ static void drm_mode_to_intf_timing_params( timing->hsync_skew = mode->hskew; /* DSI controller cannot handle active-low sync signals. */ - if (vid_enc->hw_intf->cap->type == INTF_DSI) { + if (phys_enc->hw_intf->cap->type == INTF_DSI) { timing->hsync_polarity = 0; timing->vsync_polarity = 0; } @@ -143,11 +143,11 @@ static u32 get_vertical_total(const struct intf_timing_params *timing) * lines based on the chip worst case latencies. */ static u32 programmable_fetch_get_num_lines( - struct dpu_encoder_phys_vid *vid_enc, + struct dpu_encoder_phys *phys_enc, const struct intf_timing_params *timing) { u32 worst_case_needed_lines = - vid_enc->hw_intf->cap->prog_fetch_lines_worst_case; + phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; u32 start_of_frame_lines = timing->v_back_porch + timing->vsync_pulse_width; u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines; @@ -155,26 +155,26 @@ static u32 programmable_fetch_get_num_lines( /* Fetch must be outside active lines, otherwise undefined. */ if (start_of_frame_lines >= worst_case_needed_lines) { - DPU_DEBUG_VIDENC(vid_enc, + DPU_DEBUG_VIDENC(phys_enc, "prog fetch is not needed, large vbp+vsw\n"); actual_vfp_lines = 0; } else if (timing->v_front_porch < needed_vfp_lines) { /* Warn fetch needed, but not enough porch in p